Semiconductor device and method of manufacturing the same

Abstract

The application provides a semiconductor device and a preparation method thereof. In the preparation method of the semiconductor device, a self-alignment process is used to form a source and a lead-out area through the same mask, so that the process is simplified. The source is stacked on the lead-out area. That is, the source and the lead-out area are in a stacked structure in a direction perpendicular to the substrate, so that the lead-out area does not affect the size of the source; meanwhile, holes can directly enter the lead-out area through a body area without bypassing the source to enter the lead-out area, so that the current path is reduced, the on-resistance is reduced, the opening of a parasitic NPN is avoided, and the device performance is improved. In addition, the application also uses a conductive plug to penetrate the source and contact the lead-out area to realize the simultaneous lead-out of the source and the lead-out area. The region where the source is located is subjected to an amorphization treatment, which is beneficial to the growth of an adhesive layer in the conductive plug, so that the electrical contact effect is good. Therefore, the application not only realizes the simultaneous lead-out of the source and the lead-out area, but also reduces the process difficulty and the on-resistance and improves the performance of a slot type MOS.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device manufacturing technology, and in particular to a semiconductor device and its preparation method. Background Technology

[0002] In the field of semiconductor device manufacturing technology, laterally-diffused metal-oxide semiconductors (LDMOS) require a drift region to withstand the breakdown voltage, resulting in a large device size at higher voltage levels. In contrast, trench MOS with vertical channels adjusts the breakdown voltage by varying the trench depth, thus reducing device size. However, vertical channel trench MOS uses highly doped backside substrates to collect carriers, leading to poor compatibility with CMOS processes.

[0003] To achieve compatibility with CMOS processes, the source and drain of a vertical channel MOSFET need to be brought out on the substrate surface. However, deeper trenches present significant manufacturing challenges and can lead to increased on-resistance. Therefore, a new type of vertical channel MOSFET is needed to address these issues. Summary of the Invention

[0004] The purpose of this invention is to provide a semiconductor device and its fabrication method to solve at least one of the problems of how to reduce the process difficulty of source and lead-out terminals and how to improve the performance of vertical channel MOS.

[0005] To solve the above-mentioned technical problems, the present invention provides a method for fabricating a semiconductor device, comprising:

[0006] A substrate is provided in which a well region and a trench are formed extending downward from the upper surface of the substrate, and the trench penetrates the well region;

[0007] A gate structure is formed, the gate structure covering the sidewalls of the trench;

[0008] A body region is formed, which is located in the substrate below the well region and partially overlaps with the gate structure;

[0009] A source electrode and a lead-out region are formed, both of which are located in the body region below the trench. The trench exposes at least a portion of the source electrode, and the source electrode is stacked on the lead-out region.

[0010] A first dielectric layer is formed, and the first dielectric layer fills the trench;

[0011] A drain is formed, the drain being located in the well region on the outer periphery of the trench;

[0012] A contact hole is formed, which sequentially penetrates the first dielectric layer and the source electrode and extends into the lead-out area, and a conductive plug is formed in the contact hole.

[0013] Optionally, in the method for fabricating the semiconductor device, a doping process is used to form the body region, the source, the lead-out region, and the drain; the body region and the lead-out region have a first conductivity type, and the doping concentration of the lead-out region is higher than the doping concentration of the body region; the well region, the source, and the drain have a second conductivity type.

[0014] Optionally, in the semiconductor device fabrication method, the distance between the bottom of the source electrode and the bottom wall of the trench ranges from 0.15 micrometers to 0.25 micrometers; the distance between the bottom of the lead-out region and the bottom wall of the trench ranges from 0.35 micrometers to 0.45 micrometers.

[0015] Optionally, in the method for fabricating the semiconductor device, a substrate is provided, wherein a well region and a trench extending downward from the upper surface of the substrate are formed therein, and the trench penetrates the well region, comprising:

[0016] A well region extending downward from the surface of the substrate is formed in the substrate;

[0017] A patterned first mask layer is formed on the upper surface of the substrate;

[0018] Using the patterned first mask layer as a barrier, the substrate is etched to form the trench that sequentially penetrates the first mask layer and the well region, and the trench also extends into the substrate below the well region.

[0019] Optionally, in the method for fabricating the semiconductor device, after forming a well region extending downward from the surface of the substrate in the substrate, and before forming a patterned first mask layer on the upper surface of the substrate, the method includes: forming an isolation structure embedded in the well region.

[0020] The formation of a patterned first mask layer on the upper surface of the substrate includes: the patterned first mask layer exposing at least a portion of the isolation structure;

[0021] During the etching of the substrate using the patterned first mask layer as a barrier, the isolation structure is also etched to form the trench that sequentially penetrates the first mask layer, the isolation structure, and the well region.

[0022] Optionally, in the method for fabricating the semiconductor device, forming a gate structure that covers the sidewalls of the trench includes:

[0023] A gate dielectric layer is formed, which covers the surface of the first mask layer and the bottom and sidewalls of the trench;

[0024] The trench is filled with gate conductive material and the gate conductive material is etched back, while the gate conductive material at the bottom of the trench is retained;

[0025] A second dielectric layer is formed, which covers the gate conductive material at the bottom of the trench, the first mask layer, and the sidewalls of the trench;

[0026] The second dielectric layer is etched in part to expose the first mask layer and the gate conductive material at the bottom of part of the trench, while retaining the second dielectric layer covering the sidewalls of the trench.

[0027] Using the first mask layer and the second dielectric layer of the trench sidewall as barriers, the exposed portion of the gate conductive material at the bottom of the trench is etched until the etching stops at the gate dielectric layer at the bottom wall of the trench. The remaining gate conductive material at the bottom of the trench and the gate dielectric layer between the remaining gate conductive material at the bottom of the trench and the sidewall of the trench together constitute the gate structure.

[0028] Optionally, in the method for fabricating the semiconductor device, the formation of a contact hole, wherein the contact hole sequentially penetrates the first dielectric layer and the source electrode and extends into the lead-out region, and a conductive plug is formed in the contact hole, comprising:

[0029] A patterned second mask layer is formed, the patterned second mask layer covering the substrate surface and a portion of the first dielectric layer surface, and exposing a portion of the first dielectric layer surface;

[0030] Using the patterned second mask layer as a barrier, a contact hole is etched to form penetrating the first dielectric layer and the source electrode. The bottom of the contact hole exposes at least part of the lead-out area, and the sidewall of the contact hole located at the junction of the first dielectric layer and the source electrode protrudes toward the central axis of the contact hole.

[0031] An adhesive layer is formed, which covers the bottom of the contact hole;

[0032] The contact hole is filled with a conductive material to form the conductive plug.

[0033] Optionally, in the semiconductor device fabrication method, the aperture of the contact hole ranges from 0.3 micrometers to 0.4 micrometers, and the depth of the contact hole ranges from 2.8 micrometers to 2.9 micrometers.

[0034] Based on the same inventive concept, the present invention provides a semiconductor device, comprising:

[0035] A substrate having a well region extending downward from the surface of the substrate;

[0036] A body region located in the substrate below the well region;

[0037] A trench that opens from the surface of the well region, penetrates the well region, and extends into the body region;

[0038] A gate structure that covers the sidewalls of the trench and partially overlaps with the body region;

[0039] Source electrode, the source electrode being located in the body region below the trench;

[0040] The lead-out region is located in the body region below the source electrode;

[0041] Drain electrode, the drain electrode being located in the well region on the outer periphery of the trench;

[0042] A first dielectric layer fills the trench;

[0043] The contact hole passes through the first dielectric layer and the source electrode in sequence and extends into the lead-out area. The contact hole is filled with a conductive plug.

[0044] Optionally, in the semiconductor device, the source electrode is stacked on the lead-out region, and the distance between the bottom of the source electrode and the bottom wall of the trench ranges from 0.15 micrometers to 0.25 micrometers; the distance between the bottom of the lead-out region and the bottom wall of the trench ranges from 0.35 micrometers to 0.45 micrometers.

[0045] Optionally, in the semiconductor device, the aspect ratio of the trench is from 1.3:1 to 3:1.

[0046] Optionally, in the semiconductor device, the sidewall of the conductive plug located at the junction of the first dielectric layer and the source electrode is recessed toward the central axis of the conductive plug.

[0047] Optionally, in the semiconductor device, the aperture of the contact hole ranges from 0.3 micrometers to 0.4 micrometers; the depth of the contact hole ranges from 2.8 micrometers to 2.9 micrometers.

[0048] In summary, this invention provides a semiconductor device and its fabrication method. In the fabrication method of the semiconductor device, this invention uses the same mask and a self-aligned approach to form the source and lead-out regions separately, simplifying the process flow. The source is stacked on the lead-out region. That is, the source and the lead-out region are stacked in a direction perpendicular to the substrate, so the lead-out region does not affect the size of the source. Simultaneously, when the device is turned on, holes can directly enter the lead-out region through the body region without bypassing the source, reducing the current path, lowering the on-resistance, avoiding the activation of parasitic NPN, and improving device performance. Furthermore, this invention utilizes a conductive plug that penetrates the source to contact the lead-out region, achieving simultaneous lead-out of both the source and the lead-out region. The region where the source is located is amorphized, which facilitates the growth of the adhesion layer in the conductive plug, resulting in good electrical contact.

[0049] Therefore, the semiconductor device and its fabrication method provided by the present invention not only achieve simultaneous extraction of the source and extraction regions, but also simplify the process flow, reduce the process difficulty, reduce the on-resistance, and improve the performance of the vertical channel MOS. Attached Figure Description

[0050] Figure 1 This is a schematic diagram of an exemplary vertical trench MOS semiconductor structure;

[0051] Figure 2 This is a flowchart of a semiconductor device fabrication method in one embodiment;

[0052] Figure 3-18 This is a schematic diagram of the semiconductor structure in each step of the semiconductor device fabrication method in one embodiment;

[0053] The attached figures are labeled as follows:

[0054] 100-Substrate; 101-Body region; 102-Well region; 103-First dielectric layer; 104-Gate structure; 105-Source; 106-Lead-out terminal; 107-Conductive plug; 108-Drain;

[0055] 200-Substrate; 201-Well region; 202-Isolation structure; 203-First mask layer; 204-Gate dielectric layer; 205-Gate material layer; 206-Second dielectric layer; 207-Gate structure; 208-Bulk region; 209-Source; 210-Lead-out region; 211-First dielectric layer; 212-Third mask layer; 213-Drain; 214-Second mask layer; 215-Conductive plug;

[0056] T - Contact hole; L - Central axis. Detailed Implementation

[0057] To make the objectives, advantages, and features of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to facilitate and clearly illustrate the objectives of the embodiments of the present invention. Furthermore, the structures shown in the drawings are often part of the actual structures. In particular, different figures may emphasize different aspects and sometimes use different scales. It should also be understood that, unless specifically stated or indicated, the terms "first," "second," "third," etc., in the specification are only used to distinguish the various components, elements, steps, etc., in the specification, and are not used to indicate the logical or sequential relationships between the various components, elements, steps, etc.

[0058] Compared to LDMOS, which sacrifices device size to increase breakdown voltage, vertical channel MOSFETs can adjust the breakdown voltage by changing the trench depth without sacrificing device area. While vertical channel MOSFETs have a smaller device size, one of their electrodes needs to be brought out from the back of the substrate, making it difficult to accommodate CMOS processes. To achieve CMOS compatibility, the source, drain, and bulk terminals of the vertical channel MOSFET must all be brought out from the substrate surface.

[0059] One exemplary vertical channel trench MOS semiconductor structure involves forming a heavily doped buried layer in the drift region to collect charge carriers. A high-dose ion implantation is then used on the substrate surface to form a connection region that connects to the buried layer, thereby leading the charge carriers to the substrate surface. However, this process becomes more complex and increases on-resistance when the trench is deep. Another exemplary vertical channel trench MOS semiconductor structure involves directly leading out the source and drain via interconnects. However, the bulk and source terminals are typically separate, resulting in a longer charge carrier collection path, which may make parasitic NPN transistors easier to turn on.

[0060] Another exemplary longitudinal trench MOS semiconductor structure alternates between the body region, the lead-out terminal, and the source. For example... Figure 1 As shown, the lead-out terminal 106 and the source terminal 105 are disposed together, and the lead-out terminal 106 is inserted in the middle of the source terminal 105, so that the two are spaced apart from each other. However, Figure 1 The structure shown requires an additional masking step during fabrication; specifically, each doping step for the source 105 and the lead-out 106 requires a masking step to achieve the fabrication of the source 105 and the lead-out 106. Furthermore, photoresist cannot form patterns in the trenches, making process development more difficult. Simultaneously, this device structure not only reduces the area of ​​the source 105 but also forces holes to bypass the N-type ion doped region of the source to reach the P-type ion doped region of the lead-out (e.g., ...). Figure 1As shown by the arrow, the long current path and high resistance make it easy for a voltage drop to cause parasitic NPN to turn on, affecting device performance. If lead 106 is not provided, a voltage drop in the body region 101 can easily occur when the device is turned on, causing the NPN to turn on and affecting device performance.

[0061] Therefore, to solve at least one of the aforementioned technical problems, this embodiment provides a method for fabricating a semiconductor device. Please refer to [link to relevant documentation]. Figure 2 ,include:

[0062] Step 1 S10: Provide a substrate in which a well region and a trench extending downward from the upper surface of the substrate are formed, and the trench penetrates the well region;

[0063] Step 2 S20: Form a gate structure, the gate structure covering the sidewalls of the trench;

[0064] Step 3 S30: Form a body region, which is located in the substrate below the well region and partially overlaps with the gate structure;

[0065] Step 4S40: Form a source electrode and a lead-out region, wherein the source electrode and the lead-out region are both located in the body region under the trench, the trench exposes at least a portion of the source electrode, and the source electrode is stacked on the lead-out region;

[0066] Step 5 S50: Form a first dielectric layer, the first dielectric layer filling the trench;

[0067] Step 6 S60: Form a drain electrode, the drain electrode being located in the well region on the outer periphery of the trench;

[0068] Step 7 S70: Form a contact hole, which sequentially penetrates the first dielectric layer and the source electrode and extends into the lead-out area, and forms a conductive plug in the contact hole.

[0069] As can be seen, the semiconductor device fabrication method provided in this embodiment uses the same mask to form the source and lead-out regions separately using a self-aligned method, eliminating the need for separate masks to fabricate the source and lead-out regions, thus simplifying the process. The source is stacked on the lead-out region. That is, the source and lead-out region are stacked in a direction perpendicular to the substrate, so the lead-out region does not affect the size of the source. Simultaneously, when the device is turned on, holes can directly enter the lead-out region through the body region without bypassing the source, reducing the current path, lowering the on-resistance, avoiding the activation of parasitic NPN, and improving device performance. Furthermore, this embodiment utilizes a conductive plug that penetrates the source and contacts the lead-out region, allowing the conductive plug to be electrically connected to both the source and the lead-out region, achieving simultaneous lead-out of both the source and the lead-out region. The region where the source is located is treated with amorphization, which facilitates the growth of the adhesion layer in the conductive plug, resulting in good electrical contact.

[0070] The following is in conjunction with the appendix Figure 3-18 The following describes in detail the fabrication method of the semiconductor device provided in this embodiment:

[0071] Step 1 S10: Please refer to Figure 3-5 A substrate 200 is provided, wherein a well region 201 and a trench are formed in the substrate 200 extending downward from the upper surface of the substrate 200, and the trench penetrates the well region 201.

[0072] like Figure 3 As shown, the substrate 200 can provide an operating platform for subsequent processes. It can be any substrate known to those skilled in the art for carrying semiconductor integrated circuit components. It can be a bare die or a wafer processed by epitaxial growth. Further, the substrate 200 can be selected as a silicon-on-insulator (SOI) substrate, a bulk silicon substrate, a germanium substrate, a germanium-silicon substrate, an indium phosphide (InP) substrate, a gallium arsenide (GaAs) substrate, or a germanium-on-insulator substrate, etc.

[0073] Continue as Figure 3 As shown, the well region 201 has a second conductivity type. In this embodiment, the second conductivity type is N-type, and the first conductivity type is P-type. That is, N-type ions are doped into the substrate 200 through a doping process to form the well region 201, and the well region 201 extends downward from the surface of the substrate 200 by a predetermined thickness. In another embodiment, the first conductivity type may be N-type, and the second conductivity type may be P-type.

[0074] In one embodiment, step S10 further includes sub-steps S101 to S103.

[0075] Sub-step S101, such as Figure 4 As shown, after a well region 201 extending downward from the upper surface of the substrate 200 is formed in the substrate 200, and before the trench is formed, an isolation structure 202 embedded in the well region 201 is also formed to define the active region. In one embodiment, the filling material of the isolation structure 202 includes, but is not limited to, silicon dioxide.

[0076] Sub-step S102, such as Figure 5 As shown, a patterned first mask layer 203 is formed on the surface of the well region 202 to serve as a mask and barrier for subsequent processes. The first mask layer 203 covers the surface of the well region 202 and a portion of the surface of the isolation structure 202, with at least a portion of the isolation structure 202 exposed. In one embodiment, the first mask layer 203 is made of silicon nitride or silicon dioxide.

[0077] For sub-step S103, please refer to the following. Figure 5 Using the patterned first mask layer 203 as a barrier, the substrate is etched using a dry or wet etching process to form a trench that sequentially penetrates the first mask layer 203, the isolation structure 202, and the well region 201, and the trench extends into the substrate 200 below the well region 201. The trench penetrates the isolation structure 202, which is intended to make the trench-type MOS with the isolation structure 202 more compatible with CMOS processes. In one embodiment, the aspect ratio of the trench is 1.3:1 to 3:1, depending on the device requirements. In one embodiment, the depth of the trench ranges from 2.0 micrometers to 3.0 micrometers, preferably 2.5 micrometers; the diameter of the trench ranges from 1.0 micrometers to 1.5 micrometers, preferably 1.2 micrometers.

[0078] Step 2 S20: Please refer to Figure 6-10 A gate structure 207 is formed, which covers the sidewalls of the trench.

[0079] In one embodiment, step two S20 further includes sub-steps S201 to S205.

[0080] For sub-step S201, please refer to [link / reference]. Figure 6 After forming the trench, a gate dielectric layer 204 is formed, which covers the surface of the first mask layer 203 and the bottom and sidewalls of the trench. In one embodiment, the material of the gate dielectric layer 204 includes, but is not limited to, silicon dioxide.

[0081] Sub-step S202, such as Figure 7-8As shown, the trench is filled with gate conductive material 205 and the gate conductive material 205 is etched back, while the gate conductive material 205 at the bottom of the trench is retained (e.g., Figure 8 (As shown). Optionally, the gate conductive material 205 is made of polysilicon. During the etching of the gate conductive material 205, the gate dielectric layer 204 on the surface of the first mask layer 203 and the gate dielectric layer 204 covering the trench sidewalls may also be etched or not etched.

[0082] In one embodiment, during the process of etching back the gate conductive material 205 while retaining the gate conductive material 205 at the bottom of the trench, a thin layer of gate dielectric layer 204 remains on the exposed surface of the first mask layer 203, and a thin layer of gate dielectric layer 204 also remains on the surface of a portion of the exposed sidewalls of the trench. In another embodiment, during the process of etching back the gate conductive material 205 while retaining the gate conductive material 205 at the bottom of the trench, the gate dielectric layer 204 on the exposed surface of the first mask layer 203 is completely removed, and the gate dielectric layer 204 on the surface of a portion of the exposed sidewalls of the trench is also completely removed. In yet another embodiment, during the process of etching back the gate conductive material 205 while retaining the gate conductive material 205 at the bottom of the trench, the gate dielectric layer 204 on the exposed surface of the first mask layer 203 is not etched, and the gate dielectric layer 204 on the surface of a portion of the exposed sidewalls of the trench is also not etched.

[0083] Sub-step S203, such as Figure 9 As shown, a second dielectric layer 206 is formed, which covers the gate conductive material 205 at the bottom of the trench, the first mask layer 203, and the sidewalls of the trench. In one embodiment, the material of the second dielectric layer 206 includes, but is not limited to, silicon dioxide.

[0084] In one embodiment, the second dielectric layer 206 covers the first mask layer 203 and the sidewalls of the trench. In fact, the second dielectric layer 206 covers a thin layer of gate dielectric layer 204 remaining on the exposed surface of the first mask layer 203. The second dielectric layer 206 also covers a thin layer of gate dielectric layer 204 remaining on the surface of a portion of the exposed sidewalls of the trench.

[0085] In one embodiment, the second dielectric layer 206 covers the first mask layer 203 and the sidewalls of the trench. In fact, the second dielectric layer 206 directly covers the exposed surface of the first mask layer 203, and the second dielectric layer 206 also directly covers the surface of a portion of the exposed sidewalls of the trench.

[0086] In one embodiment, the second dielectric layer 206 covers the first mask layer 203 and the sidewalls of the trench. In fact, the second dielectric layer 206 covers the gate dielectric layer 204 exposed on the surface of the first mask layer 203, and the second dielectric layer 206 also covers the gate dielectric layer 204 on the surface of a portion of the exposed sidewalls of the trench.

[0087] In sub-step S204, the second dielectric layer 206 is etched to expose the first mask layer 203 and the gate conductive material 205 at the bottom of a portion of the trench, while retaining the second dielectric layer 206 covering the sidewalls of the trench. In one embodiment, if a thin layer of gate dielectric layer 204 or an unetched gate dielectric layer 204 remains on the surface of the first mask layer 203 exposed in sub-step S202, then in sub-step S204, after etching the second dielectric layer 203, the gate dielectric layer 204 is further etched to expose the surface of the first mask layer 203.

[0088] In one embodiment, the top of the remaining second dielectric layer 206 covering the sidewalls of the trench is flush with the surface of the first mask layer 203. In another embodiment, the top of the remaining second dielectric layer 206 covering the sidewalls of the trench is below the surface of the first mask layer 203.

[0089] For sub-step S205, please refer to [link / reference]. Figure 10 Using the first mask layer 203 and the second dielectric layer 206 of the trench sidewall as barriers, the exposed portion of the gate conductive material 205 at the bottom of the trench is etched until the gate dielectric layer 204 at the bottom wall of the trench is reached. The remaining gate conductive material 205 at the bottom of the trench and the gate dielectric layer 204 between the remaining gate conductive material 205 at the bottom of the trench and the sidewall of the trench together constitute the gate structure 207.

[0090] Step 3 S30: Please refer to Figure 11 A body region 208 is formed, which is located in the substrate 200 below the well region 201 and partially overlaps with the gate structure 207.

[0091] In one embodiment, the body region 208 has a first conductivity type. Specifically, under the obstruction of the first mask layer 203 and the second dielectric layer 204, ion doping is performed on the semiconductor structure using P-type ions, with the ions penetrating through the bottom of the trench into the substrate 200. After the doping process, a rapid thermal annealing process is performed to allow ion diffusion to form the body region 208. In one embodiment, the formed body region 208 is located below the well region 201, and the body region 208 and the well region 201 are adjacent, or the body region 208 and the well region 201 are spaced apart. In one embodiment, the morphology of the body region 208 can be... Figure 11 A thin layer as shown. In one embodiment, the morphology of the body region 208 may be a doped region, and the body region 208 surrounds the bottom of the trench.

[0092] In one embodiment, see further. Figure 11 The body region 208 and the gate structure 207 partially overlap in the direction of the trench sidewall. The purpose is to ensure that when the gate structure 207 acts on the body region 208, the body region 208 can form a sufficiently long conductive channel. However, the channel is not necessarily as long as possible; therefore, the partial overlap between the gate structure 207 and the body region 208 is sufficient.

[0093] Step 4 S40: Please refer to Figure 12 A source electrode 209 and a lead-out region 210 are formed, both of which are located in the body region 208 below the trench. The trench exposes at least a portion of the source electrode 209, and the source electrode 209 is stacked on the lead-out region 210. That is, the trench is disposed adjacent to at least a portion of the source electrode 209, and at least a portion of the source electrode 209 forms at least a portion of the bottom wall of the trench.

[0094] In one embodiment, both the source electrode 209 and the lead-out region 210 are formed using ion doping processes. This embodiment does not limit the order in which the source electrode 209 and the lead-out region 210 are formed; the lead-out region 210 can be formed first, followed by the source electrode 209, or vice versa. Furthermore, the source electrode 209 has a second conductivity type, and the lead-out region 210 has a first conductivity type.

[0095] In one embodiment, the source 209 is formed by performing an ion doping process on the bottom of the trench, under the protection of the first mask layer 203 and the second dielectric layer 206. The source 209 is doped with N-type ions, and the implantation dose can be selected as 1*102 ions. 20Atoms per square centimeter. In one embodiment, the formed source electrode 209 is connected to the bottom of the trench, and the distance d1 between the bottom of the source electrode 209 and the bottom wall of the trench ranges from 0.15 micrometers to 0.25 micrometers, preferably 0.2 micrometers.

[0096] In one embodiment, the method for forming the lead-out region 210 is as follows: An ion doping process is performed on the bottom of the trench under the obstruction of the first mask layer 203 and the second dielectric layer 206. The lead-out region 210 is doped with P-type ions, and the implanted dose is the same as the ion dose implanted when forming the source 209, optionally 1*102. 20 Atoms per square centimeter. This dosage setting not only helps improve undercutting but also facilitates the growth of the adhesion layer in the conductive plug formed by subsequent processes, resulting in good contact performance. If the concentration of N-type ions in the source 209 is insufficient or excessive, undercutting will occur during subsequent etching to form contact holes. This will prevent the side-hole portion from growing during subsequent adhesion layer deposition, affecting the connection effect of the source 209 and the lead-out region 210, and consequently impacting device performance. Therefore, when the doping ion dosage in the source 209 and the lead-out region 210 is the same, it is equivalent to amorphizing the substrate of the implanted region, affecting the etching rate. During subsequent etching of the implanted region, a morphology protruding into the trench can be formed, allowing for the growth of more adhesion layers and the formation of a good contact junction.

[0097] In one embodiment, the source 209 and the lead-out region 210 are stacked in a direction perpendicular to the substrate 200. Compared to Figure 1 The structure shown allows the lead-out region 210 to remain within the dimensions of the source electrode 209, ensuring the optimal size of the source electrode 209 and improving device performance. Simultaneously, when the device is turned on, hole current can be directly collected by the lead-out region 210 through the body region 208, without bypassing the source electrode 209. This shortened current path also reduces resistance, preventing the activation of parasitic NPN transistors and further improving device performance. Furthermore, the ion doping concentration of the lead-out region 210 is higher than that of the body region 208, facilitating carrier concentration in the lead-out region 210. In one embodiment, the distance d2 between the bottom of the lead-out region 210 and the bottom wall of the trench ranges from 0.35 micrometers to 0.45 micrometers, preferably 0.4 micrometers.

[0098] Step 5 S50: Please refer to Figure 13-14 A first dielectric layer 211 is formed, and the first dielectric layer 211 fills the trench.

[0099] In one embodiment, the first dielectric layer 211 is formed using a high-density plasma chemical vapor deposition process, and the material of the first dielectric layer 211, the second dielectric layer 206, and the gate dielectric layer 204 is the same, which is silicon dioxide, serving as an isolation and barrier.

[0100] In one embodiment, after the first dielectric layer 211 is formed, as Figure 14 As shown, a chemical mechanical masking process is used to remove the first dielectric layer 211 and the first mask layer 203 from the surface of the well region 201, leaving only the first dielectric layer 211 in the trench.

[0101] Step 6 S60: Please refer to Figure 15 A drain 213 is formed, which is located in the well region 201 on the outer periphery of the trench.

[0102] In one embodiment, the drain 213 has a second conductivity type. Further, a patterned third mask layer 212 is first formed on the surface of the well region 201. The patterned third mask layer 212 covers the surface of the well region 201 and a portion of the surface of the first dielectric layer 211, exposing a portion of the surface of the first dielectric layer 211. Then, using the third mask layer 212 as a barrier, an ion doping process is performed on the well region 201 around the trench using N-type ions to form the drain 213. Finally, a rapid thermal annealing process is performed to repair lattice damage in the drain 213, the source 209, and the lead-out region 210, activating impurities.

[0103] Step 7 S70: Please refer to Figure 16-18 A contact hole T is formed, which sequentially penetrates the first dielectric layer 211 and the source electrode 209 and extends into the lead-out area 210. A conductive plug 215 is formed in the contact hole T.

[0104] Further, the third mask layer 212 is removed, and a patterned second mask layer 214 is formed on the surface of the well region 201. The second mask layer covers a portion of the surface of the well region 201, a portion of the isolation structure 202, and a portion of the surface of the first dielectric layer 211, and exposes a portion of the surface of the first dielectric layer 211 to define the opening position of the contact hole. Then, using the second mask layer 214 as a mask, a dry or wet etching process is used to sequentially etch the first dielectric layer 211, the source electrode 209, up to or extending to the surface of the lead-out region 210, forming a contact hole T. The contact hole T penetrates the first dielectric layer 211 and the source electrode 209, and the bottom of the contact hole T exposes at least a portion of the lead-out region 210. Since the source electrode 209 is doped with ions, it can be understood that, after ion implantation, the bottom of the trench is equivalent to undergoing an amorphization process. Figure 17 The structure shown is a partial magnified structure of the contact hole T. Due to the different etching rates of amorphous silicon and single-crystal silicon, the etching at the junction of the gate dielectric layer 204 and the source 209 causes the sidewall of the contact hole T located at the junction of the gate dielectric layer 204 and the source 209 to bulge towards the central axis L of the contact hole, which is beneficial to the growth of the subsequent adhesion layer and improves the contact effect.

[0105] In one embodiment, depending on the device requirements, the diameter range of the contact hole T, i.e., the diameter range along the X direction, is 0.3 micrometers to 0.4 micrometers, optionally 0.35 micrometers. The depth range of the contact hole, i.e., the depth range along the Y direction, is 2.8 micrometers to 2.9 micrometers, optionally 2.85 micrometers. In one embodiment, in the three-dimensional structure of the device, the contact hole T is a long, narrow groove structure, which is convenient for fabrication. If the contact hole T adopts an intermittent contact hole structure, the opening of the hole is already small, and the depth-to-width ratio of the hole is too large, making it difficult to implement in the process.

[0106] In one embodiment, see Figure 18 An adhesion layer (not shown) is formed at the bottom of the contact hole T. This adhesion layer covers the exposed surfaces of the source electrode 209 and the exposed lead-out region 210. Further, the adhesion layer is made of titanium or titanium nitride, which facilitates the connection between the conductive plug and the silicon substrate, improving contact performance. After forming the adhesion layer, the contact hole T is filled with a conductive material to form a conductive plug 215. The sidewall of the conductive plug 215 located at the junction of the first dielectric layer 211 and the source electrode 209 is recessed towards the central axis of the conductive plug 215. Preferably, the conductive material is tungsten.

[0107] Based on the same inventive concept, please refer to Figure 12 ,16 In addition to 18, this embodiment also provides a semiconductor device. In this embodiment, the second conductivity type is N-type and the first conductivity type is P-type. In another embodiment, the first conductivity type may be N-type and the second conductivity type may be P-type. Then the semiconductor device is a trench NMOS, comprising:

[0108] A substrate 200 has a well region 201 formed therein, extending downward from the surface of the substrate 200 by a predetermined thickness. The well region 201 has a second conductivity type, which in this embodiment is N-type, and the well region 201 is doped with N-type ions. In one embodiment, an isolation structure 202 is also embedded in the well region 201 to define an active region. The isolation structure 202 extends downward from the top surface of the well region 201 by a predetermined thickness and does not exceed the bottom of the well region 201. In one embodiment, the filling material of the isolation structure 202 includes, but is not limited to, silicon dioxide.

[0109] A body region 208 is located in the substrate 200 below the well region 201. The body region 208 has a first conductivity type, which in this embodiment is P-type, and is doped with P-type ions. In one embodiment, the body region 208 is located below the well region 201, and the body region 208 and the well region 201 are adjacent, or the body region 208 and the well region 201 are spaced apart. In one embodiment, the morphology of the body region 208 can be... Figure 11 A thin layer as shown. In one embodiment, the morphology of the body region 208 can be a doped region.

[0110] A trench opens from and penetrates the surface of the well region 201, extending into the body region 208. In one embodiment, the trench sequentially penetrates the isolation structure 202 and the well region 201. The trench penetrates the isolation structure 202 to facilitate compatibility of the trench-type MOS with the isolation structure 202 with CMOS processes. Furthermore, the body region 208 partially encloses the trench. In one embodiment, the aspect ratio of the trench can be selected from 1.3:1 to 3:1, depending on the device setup requirements.

[0111] A gate structure 207 covers the sidewalls of the trench and partially overlaps with the body region 208. In one embodiment, the gate structure 207 covers a portion of the sidewalls of the trench near the bottom wall. In another embodiment, the gate structure 207 includes a gate dielectric layer 204 and a gate conductive material 205. The gate dielectric layer 204 is made of, but is not limited to, silicon dioxide, and serves as an isolation barrier. The gate conductive material 205 is made of, but is not limited to, polysilicon, and acts as a gate to control the pinch-off and on-resistance of the conduction channel between the drain and source.

[0112] In one embodiment, the gate structure 207 covers a portion of the sidewall of the trench near the bottom wall of the trench, and the gate dielectric layer 204 is further provided on the bottom wall of the trench. In another embodiment, the gate structure 207 covers a portion of the sidewall of the trench near the bottom wall of the trench, and the gate dielectric layer 204 is further provided on the bottom wall and the remaining sidewall of the trench.

[0113] In one embodiment, the body region 208 and the gate structure 207 partially overlap in the direction of the trench sidewall. The purpose is to ensure that when the gate structure 207 acts on the body region 208, the body region 208 can form a sufficiently long conductive channel. However, the channel is not necessarily the longer the better; therefore, partial overlap between the gate structure 207 and the body region 208 is sufficient.

[0114] A source electrode 209 is located in the body region 208 below the trench. The source electrode 209 has a second conductivity type, which is N-type in this embodiment, and is doped with N-type ions. In one embodiment, the source electrode 209 is connected to the bottom of the trench, and the distance d1 between the bottom of the source electrode 209 and the bottom wall of the trench ranges from 0.15 micrometers to 0.25 micrometers, preferably 0.2 micrometers. The doping range of the source electrode 209 can further accurately control the degree and position of amorphization.

[0115] A lead-out region 210 is located in the body region 208 below the source electrode 209. The lead-out region 210 has a first conductivity type, which in this embodiment is P-type, and is doped with P-type ions. The source electrode 209 and the lead-out region 210 are stacked in a direction perpendicular to the substrate 200. Compared to... Figure 1The structure shown allows the lead-out region 210 to remain within the dimensions of the source electrode 209, ensuring the optimal size of the source electrode 209 and improving device performance. Simultaneously, when the device is turned on, hole current can be directly collected by the lead-out region 210 through the body region 208, without bypassing the source electrode 209. This shortened current path reduces resistance, prevents the activation of parasitic NPN transistors, and further improves device performance. Furthermore, the ion doping concentration of the lead-out region 210 is higher than that of the body region 208, facilitating carrier concentration in the lead-out region 210. In one embodiment, the distance d2 between the bottom of the lead-out region 210 and the bottom wall of the trench ranges from 0.35 μm to 0.45 μm, preferably 0.4 μm. The doping range of the lead-out region 210 allows for more precise control over the degree and location of amorphization.

[0116] Drain 213 is located in the well region 210 on the outer periphery of the trench. The drain 213 has a second conductivity type, that is, the drain 213 is doped with N-type ions.

[0117] A first dielectric layer 211 is filled in the trench. The material of the first dielectric layer 211 includes, but is not limited to, silicon dioxide, and it serves as an electrical isolation layer.

[0118] A contact hole T is formed, which sequentially penetrates the first dielectric layer 211 and the source electrode 209, extending into the lead-out region 210. The contact hole T is filled with a conductive plug 215. Since the source electrode 209 is doped with N-type ions, this is equivalent to amorphizing the substrate in the corresponding region of the source electrode 209. Therefore... Figure 17 As shown, the contact hole T located at the bottom of the trench and at the source electrode 209 protrudes towards the central axis L of the contact hole T, which facilitates the growth of the adhesion layer and improves the contact effect. In one embodiment, an adhesion layer is formed at the bottom of the contact hole T. The adhesion layer covers the exposed surface of the source electrode 209 and the exposed surface of the lead-out region 210. Furthermore, the material of the adhesion layer includes titanium or titanium nitride, which helps the connection between the conductive plug 215 and the substrate and improves the contact effect.

[0119] In one embodiment, the doping dose of both the source 209 and the extraction region 210 is 1*102 20 Atoms per square centimeter allows for more precise control over the degree and location of amorphization, and better control over the morphology of the protruding structure of the contact hole T. Preferably, the doping dose of ions in the source 209 and the lead-out region 210 is the same. The sidewall of the conductive plug 215 located at the junction of the first dielectric layer 211 and the source 209 is recessed towards the central axis of the conductive plug 215.

[0120] In one embodiment, the aperture of the contact hole T ranges from 0.3 micrometers to 0.4 micrometers, and the depth of the contact hole T ranges from 2.8 micrometers to 2.9 micrometers. In one embodiment, in the three-dimensional structure of the device, the contact hole T is a long, narrow groove structure, which is convenient for fabrication. If the contact hole T adopts an intermittent contact hole structure, it is difficult to implement in terms of fabrication because the opening of the hole is already small and the aspect ratio of the hole is too large.

[0121] In summary, this embodiment provides a semiconductor device and its fabrication method. In the fabrication method of the semiconductor device, the same mask is used to form the source 209 and the lead-out region 210 separately using a self-aligned method, eliminating the need for separate masks to fabricate the source 209 and lead-out region 210, thus simplifying the process. Furthermore, the source 209 is stacked on the lead-out region 210; that is, the source 209 and the lead-out region 210 are stacked in a direction perpendicular to the substrate 200, so the lead-out region 210 does not affect the size of the source 209. Simultaneously, when the device is turned on, holes can directly enter the lead-out region 210 through the body region 208 without bypassing the source 209, reducing the current path and resistance, avoiding the activation of parasitic NPN, and improving device performance. Furthermore, this embodiment utilizes a conductive plug 212 to penetrate the source 209 and contact the lead-out region 210, achieving simultaneous lead-out of both the source 209 and the lead-out region 210. The region containing the source 210 undergoes amorphization treatment, which facilitates the growth of the adhesion layer in the conductive plug, resulting in good electrical contact. Therefore, the semiconductor device and its fabrication method provided in this embodiment not only achieve simultaneous lead-out of the source 209 and the lead-out region 210 but also simplify the process flow, reduce process difficulty, and improve the performance of the vertical channel MOS.

[0122] Furthermore, it should be understood that although the present invention has been disclosed above with reference to preferred embodiments, these embodiments are not intended to limit the present invention. For any person skilled in the art, many possible variations and modifications can be made to the technical solutions of the present invention based on the disclosed technical content, or equivalent embodiments can be modified accordingly, without departing from the scope of the present invention. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the present invention shall still fall within the scope of protection of the present invention.

Claims

1. A method for fabricating a semiconductor device, characterized in that, include: A substrate is provided in which a well region and a trench are formed extending downward from the upper surface of the substrate, and the trench penetrates the well region; A gate structure is formed, the gate structure covering the sidewalls of the trench; A body region is formed, which is located in the substrate below the well region and partially overlaps with the gate structure; A source electrode and a lead-out region are formed, both of which are located in the body region below the trench. The trench exposes at least a portion of the source electrode, and the source electrode is stacked on the lead-out region. A first dielectric layer is formed, and the first dielectric layer fills the trench; A drain is formed, the drain being located in the well region on the outer periphery of the trench; A contact hole is formed, which sequentially penetrates the first dielectric layer and the source electrode, and extends into the lead-out region. A conductive plug is formed in the contact hole to simultaneously lead out the source electrode and the lead-out region. The source electrode, the lead-out region, and the drain electrode are all led out from the upper surface of the substrate. The source electrode and the lead-out region are formed by a doping process, so that the bottom of the trench is amorphized, and the sidewall of the contact hole at the junction of the first dielectric layer and the source electrode protrudes toward the central axis of the contact hole.

2. The method for fabricating a semiconductor device according to claim 1, characterized in that, The body region and the drain are formed using a doping process; the body region and the lead-out region have a first conductivity type, and the doping concentration of the lead-out region is higher than that of the body region; the well region, the source, and the drain have a second conductivity type.

3. The method for fabricating a semiconductor device according to claim 1, characterized in that, The distance between the bottom of the source electrode and the bottom wall of the trench ranges from 0.15 micrometers to 0.25 micrometers; the distance between the bottom of the lead-out area and the bottom wall of the trench ranges from 0.35 micrometers to 0.45 micrometers.

4. The method for fabricating a semiconductor device according to claim 1, characterized in that, The provision includes a substrate having a well region and a trench extending downward from the upper surface of the substrate, wherein the trench penetrates the well region, comprising: A well region extending downward from the surface of the substrate is formed in the substrate; A patterned first mask layer is formed on the upper surface of the substrate; Using the patterned first mask layer as a barrier, the substrate is etched to form the trench that sequentially penetrates the first mask layer and the well region, and the trench also extends into the substrate below the well region.

5. The method for fabricating a semiconductor device according to claim 4, characterized in that, After forming a well region extending downward from the surface of the substrate in the substrate, and before forming a patterned first mask layer on the upper surface of the substrate, the method includes: forming an isolation structure embedded in the well region; The formation of a patterned first mask layer on the upper surface of the substrate includes: the patterned first mask layer exposing at least a portion of the isolation structure; During the etching of the substrate using the patterned first mask layer as a barrier, the isolation structure is also etched to form the trench that sequentially penetrates the first mask layer, the isolation structure, and the well region.

6. The method for fabricating a semiconductor device according to claim 4 or 5, characterized in that, The formation of the gate structure, the gate structure covering the sidewalls of the trench, includes: A gate dielectric layer is formed, which covers the surface of the first mask layer and the bottom and sidewalls of the trench; The trench is filled with gate conductive material and the gate conductive material is etched back, while the gate conductive material at the bottom of the trench is retained; A second dielectric layer is formed, which covers the gate conductive material at the bottom of the trench, the first mask layer, and the sidewalls of the trench; The second dielectric layer is etched in part to expose the first mask layer and the gate conductive material at the bottom of part of the trench, while retaining the second dielectric layer covering the sidewalls of the trench. Using the first mask layer and the second dielectric layer of the trench sidewall as barriers, the exposed portion of the gate conductive material at the bottom of the trench is etched until the etching stops at the gate dielectric layer at the bottom wall of the trench. The remaining gate conductive material at the bottom of the trench and the gate dielectric layer between the remaining gate conductive material at the bottom of the trench and the sidewall of the trench together constitute the gate structure.

7. The method for fabricating a semiconductor device according to claim 1, characterized in that, The formation of a contact hole, wherein the contact hole sequentially penetrates the first dielectric layer and the source electrode, and extends into the lead-out region, wherein a conductive plug is formed in the contact hole, comprising: A patterned second mask layer is formed, the patterned second mask layer covering the substrate surface and a portion of the first dielectric layer surface, and exposing a portion of the first dielectric layer surface; Using the patterned second mask layer as a barrier, a contact hole is etched to form penetrating the first dielectric layer and the source electrode, with at least a portion of the lead-out area exposed at the bottom of the contact hole; An adhesive layer is formed, which covers the bottom of the contact hole; The contact hole is filled with a conductive material to form the conductive plug.

8. The method for fabricating a semiconductor device according to claim 1 or 7, characterized in that, The aperture of the contact hole ranges from 0.3 micrometers to 0.4 micrometers; the depth of the contact hole ranges from 2.8 micrometers to 2.9 micrometers.

9. A semiconductor device, characterized in that, include: A substrate having a well region extending downward from the surface of the substrate; A body region located in the substrate below the well region; A trench that opens from the surface of the well region, penetrates the well region, and extends into the body region; A gate structure that covers the sidewalls of the trench and partially overlaps with the body region; Source electrode, the source electrode being located in the body region below the trench; The lead-out region is located in the body region below the source electrode; Drain electrode, the drain electrode being located in the well region on the outer periphery of the trench; A first dielectric layer fills the trench; A contact hole is provided, which sequentially penetrates the first dielectric layer and the source electrode, and extends into the lead-out region. The contact hole is filled with a conductive plug to simultaneously lead out the source electrode and the lead-out region. The source electrode, the lead-out region, and the drain electrode are all led out from the upper surface of the substrate. The source electrode and the lead-out region are formed by a doping process to make the bottom of the trench amorphous, and the sidewall of the contact hole at the junction of the first dielectric layer and the source electrode protrudes toward the central axis of the contact hole.

10. The semiconductor device according to claim 9, characterized in that, The source electrode is stacked on the lead-out region, and the distance between the bottom of the source electrode and the bottom wall of the trench ranges from 0.15 micrometers to 0.25 micrometers; the distance between the bottom of the lead-out region and the bottom wall of the trench ranges from 0.35 micrometers to 0.45 micrometers.

11. The semiconductor device according to claim 9, characterized in that, The depth-to-width ratio of the trench is 1.3:1 to 3:

1.

12. The semiconductor device according to claim 9, characterized in that, The aperture of the contact hole ranges from 0.3 micrometers to 0.4 micrometers; the depth of the contact hole ranges from 2.8 micrometers to 2.9 micrometers.

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