IGBT structure and method of manufacturing the same

Abstract

The application provides an IGBT structure and a preparation method thereof, and the preparation method comprises the following steps: providing a bottom structure; forming a first photoresist pattern layer on an interlayer dielectric layer through photolithography, and performing etching to form a contact hole; removing the first photoresist pattern layer, and sequentially forming a protective layer; depositing a voltage-resistant dielectric material layer above the protective layer and forming a second photoresist pattern layer through photolithography; performing etching on the voltage-resistant dielectric material layer to form a voltage-resistant dielectric structure; removing the second photoresist pattern layer and the protective layer to expose an active region or a polysilicon layer, and part of the protective layer is still reserved below the voltage-resistant dielectric structure; depositing a metal connecting layer, and forming a passivation layer to protect the metal connecting layer. Through adjusting the forming sequence of the contact hole and the voltage-resistant dielectric structure, the application eliminates the adverse effect of wafer warping caused by the voltage-resistant dielectric structure on the contact hole forming process; through introducing the protective layer, the application avoids the influence of the process of forming the voltage-resistant dielectric structure on the contact hole structure.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to an IGBT structure and its fabrication method. Background Technology

[0002] IGBT (Insulated Gate Bipolar Transistor) is a composite, fully controllable, voltage-driven power semiconductor device composed of BJT and MOSFET. IGBTs feature self-turn-off, low drive power, and low saturation voltage, making them suitable for power management systems with withstand voltages above 600V. Ultra-high voltage IGBTs, with operating voltages exceeding 1000V, present a significant challenge to the device's withstand voltage requirements.

[0003] Currently, to achieve the withstand voltage characteristics of ultra-high voltage IGBTs, a withstand voltage structure composed of a doped dielectric layer has been introduced into the dielectric layer of the device. This type of structure can improve the breakdown characteristics of the device by adjusting the electric field distribution.

[0004] However, the design pattern of the withstand voltage structure formed by the doped dielectric layer is generally non-uniformly distributed within the wafer surface. This will lead to poor wafer warpage, thus affecting the normal progress of subsequent processes. For example, contact hole lithography has high requirements for the precision of the lithography process and the wafer warpage. If abnormal wafer warpage is caused by the introduction of the withstand voltage structure, the wafer will be unable to be fabricated normally.

[0005] Therefore, it is necessary to propose a new IGBT structure and its fabrication method to solve the above problems. Summary of the Invention

[0006] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide an IGBT structure and its manufacturing method to solve the problems in the prior art where warping caused by the pressure-resistant structure prevents normal fabrication.

[0007] To achieve the above and other related objectives, the present invention provides a method for fabricating an IGBT structure, comprising the following steps:

[0008] 1) Provide an underlying structure, the underlying structure comprising: a substrate forming an active region, a polysilicon layer, and an interlayer dielectric layer;

[0009] 2) A first photoresist pattern layer is formed on the interlayer dielectric layer by photolithography; the first photoresist pattern layer is used as an etching mask to etch the interlayer dielectric layer and the underlying structure to form contact holes;

[0010] 3) Remove the first photoresist pattern layer, and sequentially form a protective layer on the sidewalls and bottom of the contact hole and on the surface of the interlayer dielectric layer;

[0011] 4) Deposit a pressure-resistant dielectric material layer above the protective layer and photolithographically form a second photoresist pattern layer on the pressure-resistant dielectric material layer; use the second photoresist pattern layer as an etching mask to etch the pressure-resistant dielectric material layer to form a pressure-resistant dielectric structure;

[0012] 5) Remove the second photoresist pattern layer and the protective layer to expose the active region or the polysilicon layer at the bottom of the contact hole, while retaining part of the protective layer below the voltage-resistant dielectric structure;

[0013] 6) Deposit a metal connection layer on the surface of the contact hole and the interlayer dielectric layer, and form a passivation layer on the surface of the metal connection layer to protect the metal connection layer.

[0014] As an optional embodiment of the present invention, a padding silicon dioxide layer is further formed between the interlayer dielectric layer and the protective layer to relieve stress between the protective layer and the substrate.

[0015] As an optional embodiment of the present invention, in step 5), after removing the second photoresist pattern layer and the protective layer, the lower pad silicon dioxide layer is further removed to completely expose the active region or the polysilicon layer at the bottom of the contact hole; a portion of the pad silicon dioxide layer is still retained below the voltage-resistant dielectric structure.

[0016] As an alternative to the present invention, the method for removing the pad silicon dioxide layer includes HF wet etching or plasma dry etching for silicon dioxide materials.

[0017] As an optional embodiment of the present invention, the projection of the pressure-resistant dielectric structure on the substrate does not coincide with the projection of the contact hole on the substrate.

[0018] As an optional embodiment of the present invention, the thickness of the substrate silicon dioxide layer is 200nm-500nm.

[0019] As an optional embodiment of the present invention, the protective layer is composed of a silicon nitride layer; in step 5), the silicon nitride layer is removed by hot phosphoric acid wet etching or plasma dry etching using CF4 / CHF3 as the etching gas.

[0020] As an optional embodiment of the present invention, after forming the metal interconnect layer and the passivation layer, the method further includes the steps of back-side thinning, back-side implantation, back-side annealing and back-side metallization of the substrate.

[0021] The present invention also provides an IGBT structure, comprising:

[0022] The bottom layer structure consists of a substrate forming the active region, a polysilicon layer, and an interlayer dielectric layer, which are stacked sequentially from bottom to top.

[0023] A contact hole is formed in the interlayer dielectric layer, and the bottom of the contact hole stops on the active region or the polysilicon layer;

[0024] A protective layer formed above the interlayer dielectric layer;

[0025] A pressure-resistant medium structure formed above the protective layer.

[0026] As an optional embodiment of the present invention, a padding silica layer is further formed between the interlayer dielectric layer and the protective layer; the distribution shape of the padding silica layer corresponds to the pressure-resistant dielectric structure.

[0027] As described above, the IGBT structure and its fabrication method provided by the present invention have the following beneficial effects:

[0028] This invention eliminates the adverse effects of wafer warpage caused by the dielectric structure on the contact hole formation process by adjusting the formation order of the contact hole and the dielectric structure; by introducing a protective layer, it avoids the process of forming the dielectric structure from affecting the contact hole structure, which helps to improve the process window and increase the process yield. Attached Figure Description

[0029] Figure 1 This is a flowchart of the fabrication method of the IGBT structure provided in the embodiments of the present invention.

[0030] Figure 2 This is a schematic diagram of the substrate provided in an embodiment of the present invention.

[0031] Figure 3 This is a schematic diagram of the formation of the first photoresist pattern layer provided in an embodiment of the present invention.

[0032] Figure 4 This is a schematic diagram of the formation of a contact hole provided in an embodiment of the present invention.

[0033] Figure 5 This is a schematic diagram of removing the first photoresist pattern layer provided in an embodiment of the present invention.

[0034] Figure 6 This is a schematic diagram of the formation of the padding silicon dioxide layer provided in an embodiment of the present invention.

[0035] Figure 7 This is a schematic diagram of the formation of a protective layer provided in an embodiment of the present invention.

[0036] Figure 8 This is a schematic diagram of the formation of a pressure-resistant dielectric material layer provided in an embodiment of the present invention.

[0037] Figure 9 This is a schematic diagram of the formation of the second photoresist pattern layer provided in an embodiment of the present invention.

[0038] Figure 10 This is a schematic diagram of the formation of a pressure-resistant medium structure provided in an embodiment of the present invention.

[0039] Figure 11 This is a schematic diagram of removing the second photoresist pattern layer provided in an embodiment of the present invention.

[0040] Figure 12 This is a schematic diagram of the removal of the protective layer provided in an embodiment of the present invention.

[0041] Figure 13 This is a schematic diagram of removing the silicon dioxide layer of the liner provided in an embodiment of the present invention.

[0042] Component designation explanation

[0043] 101 substrate

[0044] 102 Active Zone

[0045] 103 Polycrystalline Silicon Layer

[0046] 104 Interlayer Dielectric Layer

[0047] 105 First photoresist patterning layer

[0048] 106 Contact Hole

[0049] 107 Padding Silica Layer

[0050] 108 protective layer

[0051] 109 Pressure-resistant dielectric material layer

[0052] 110 Second photoresist patterning layer

[0053] 111 Pressure-resistant dielectric structure

[0054] S1~S6 Steps 1)~6) Detailed Implementation

[0055] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0056] Please see Figures 1 to 13It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Although the illustrations only show components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation, the shape, quantity and proportion of each component in the actual implementation can be arbitrarily changed, and the layout of the components may also be more complex.

[0057] Please see Figures 1 to 13 This embodiment provides a method for fabricating an IGBT structure, including the following steps:

[0058] 1) Provide an underlying structure, the underlying structure comprising: a substrate 101 forming an active region 102, a polysilicon layer 103, and an interlayer dielectric layer 104;

[0059] 2) A first photoresist pattern layer 105 is formed on the interlayer dielectric layer 104 by photolithography; the first photoresist pattern layer 105 is used as an etching mask to etch the interlayer dielectric layer 104 and the underlying structure to form a contact hole 106.

[0060] 3) Remove the first photoresist pattern layer 105, and sequentially form a protective layer on the sidewall and bottom of the contact hole 106 and on the surface of the interlayer dielectric layer 104;

[0061] 4) Deposit a pressure-resistant dielectric material layer 109 above the protective layer 108 and photolithographically form a second photoresist pattern layer 110 on the pressure-resistant dielectric material layer 109; use the second photoresist pattern layer 110 as an etching mask to etch the pressure-resistant dielectric material layer 109 to form a pressure-resistant dielectric structure 111.

[0062] 5) Remove the second photoresist pattern layer 110 and the protective layer 108 to expose the active region 102 or the polysilicon layer 103 at the bottom of the contact hole 106, while retaining part of the protective layer 108 below the voltage-resistant dielectric structure 109.

[0063] 6) Deposit a metal connection layer on the surface of the contact hole 106 and the interlayer dielectric layer 104, and form a passivation layer on the surface of the metal connection layer to protect the metal connection layer.

[0064] This invention eliminates the adverse effects of wafer warpage caused by the dielectric structure on the contact hole formation process by adjusting the formation order of the contact hole and the dielectric structure; by introducing a protective layer, it avoids the process of forming the dielectric structure from affecting the contact hole structure, which helps to improve the process window and increase the process yield.

[0065] In step 1), please refer to Figure 1 S1 step and Figure 2A bottom layer structure is provided, which includes a substrate 101 forming an active region 102, a polysilicon layer 103, and an interlayer dielectric layer 104.

[0066] As an example, the interlayer dielectric layer 104 includes, but is not limited to, a silicon dioxide layer. The substrate includes, but is not limited to, a silicon substrate. The active region 102 can be formed by, but is not limited to, ion implantation and thermal annealing processes. The active region 102 includes P-type and N-type well regions. The polysilicon layer 103 includes a polysilicon layer for a gate structure and a polysilicon layer as a wiring layer structure. A gate oxide layer is also formed between the gate structure and the substrate.

[0067] In step 2), please refer to Figure 1 S2 steps and Figures 3 to 4 A first photoresist pattern layer 105 is formed on the interlayer dielectric layer 104 by photolithography; the first photoresist pattern layer 105 is used as an etching mask to etch the interlayer dielectric layer 104 and the underlying structure to form a contact hole 106.

[0068] In one example, the method of forming the contact hole 106 includes:

[0069] like Figure 3 As shown, a first photoresist pattern layer 105 is formed on the interlayer dielectric layer 104 using a photolithography process. The first photoresist pattern layer 105 has a pattern of contact holes after photolithography development and exposure.

[0070] like Figure 4 As shown, using the first photoresist patterned layer 105 as an etching mask, the interlayer dielectric layer 104 is dry-etched to form the contact hole 106. The anisotropic dry etching process allows the pattern of the patterned first photoresist patterned layer 105 to be inherited onto the underlying interlayer dielectric layer 104. A portion of the active region 102 and the polysilicon layer 103, which serve as etching termination layers, are also etched away during the over-etching process.

[0071] In step 3), please refer to Figure 1 The S3 step and Figures 5 to 7 Remove the first photoresist pattern layer 105, and sequentially form a protective layer on the sidewall and bottom of the contact hole 106 and on the surface of the interlayer dielectric layer 104.

[0072] like Figure 5 As shown, the first photoresist pattern layer 105 is removed by ashing and wet cleaning. After ashing and wet cleaning, only the patterned contact holes 106 remain.

[0073] As an example, the protective layer 108 includes, but is not limited to, a silicon nitride layer. The silicon nitride layer can be obtained by CVD or ALD processes.

[0074] In one example, a spacer silicon dioxide layer 107 is further formed between the interlayer dielectric layer 104 and the protective layer 108. The spacer silicon dioxide layer 107 can be obtained by CVD or ALD processes. The spacer silicon dioxide layer 107 can relieve stress between the silicon nitride layer and the underlying silicon substrate and prevent defects such as film peeling. The thickness of the substrate silicon dioxide layer 107 is preferably 200nm-500nm.

[0075] In step 4), please refer to Figure 1 The S4 steps and Figures 8 to 10 A pressure-resistant dielectric material layer 109 is deposited above the protective layer 108, and a second photoresist pattern layer 110 is formed on the pressure-resistant dielectric material layer 109 by photolithography; the pressure-resistant dielectric material layer 109 is etched using the second photoresist pattern layer 110 as an etching mask to form a pressure-resistant dielectric structure 111.

[0076] As an example, the materials constituting the pressure-resistant dielectric structure 111 include, but are not limited to, phosphorus-doped silicon dioxide.

[0077] In one example, the method of forming the pressure-resistant dielectric structure 111 includes:

[0078] like Figures 8 to 9 As shown, a pressure-resistant dielectric material layer 109 is deposited above the protective layer 108; a second photoresist pattern layer 110 is formed on the pressure-resistant dielectric material layer 109 by photolithography.

[0079] like Figure 10 As shown, the second photoresist pattern layer 110 is used as an etching mask to dry etch the pressure-resistant dielectric material layer 109 to form the pressure-resistant dielectric structure 111.

[0080] In step 5), please refer to Figure 1 The S5 steps and Figures 11 to 13 Remove the second photoresist pattern layer 110 and the protective layer 108 to expose the active region 102 or the polysilicon layer 103 at the bottom of the contact hole 106, while a portion of the protective layer 108 remains below the dielectric structure 109.

[0081] like Figure 11 As shown, the second photoresist pattern layer 110 is removed by ashing and wet cleaning.

[0082] As an example, such as Figure 11As shown, the projection of the pressure-resistant dielectric structure 111 on the substrate 101 does not coincide with the projection of the contact hole 106 on the substrate 101.

[0083] As an example, such as Figure 12 As shown, the protective layer 108, composed of a silicon nitride layer, can be removed by hot phosphoric acid wet etching, which has a high selectivity for the underlying silicon dioxide layer 107, preventing damage to the underlying substrate. Alternatively, the silicon nitride layer can be removed by plasma dry etching using CF4 / CHF3 as the etching gas. After the above wet or dry etching processes, a portion of the silicon nitride layer remains beneath the dielectric structure 111.

[0084] As an example, such as Figure 13 As shown, after removing the protective layer 108, the underlying pad silicon dioxide layer 107 is further removed to completely expose the active region 102 or polysilicon layer 103 at the bottom of the contact hole 106. The method for removing the pad silicon dioxide layer 107 includes HF wet etching or plasma dry etching for silicon dioxide materials. After the above wet or dry etching process, a portion of the pad silicon dioxide layer remains beneath the dielectric structure 111.

[0085] As an example, after removing the protective layer 108, the process further includes forming a metal interconnect layer and a passivation layer. After forming the contact hole 106 and the pressure-resistant dielectric structure 111, a metal interconnect layer is deposited on the surface of the contact hole 106 and the interlayer dielectric layer, and the metal interconnect layer is patterned by photolithography and etching. Then, a passivation layer is deposited on top of the metal interconnect layer to protect it.

[0086] As an example, after forming the metal interconnect layer and the passivation layer, the process further includes sequentially performing back-side thinning, back-side implantation, back-side annealing, and back-side metallization on the substrate. For IGBT devices, back-side processes such as back-side thinning, back-side implantation, back-side annealing, and back-side metallization are optional processes for achieving advanced device performance.

[0087] like Figure 13 As shown, this embodiment also provides an IGBT structure, including:

[0088] The bottom layer structure includes a substrate 101 forming an active region 102, a polysilicon layer 103, and an interlayer dielectric layer 104, which are stacked sequentially from bottom to top.

[0089] A contact hole 106 is formed in the interlayer dielectric layer 104, and the bottom of the contact hole 106 stops on the active region 102 or the polysilicon layer 103.

[0090] A protective layer 108 is formed above the interlayer dielectric layer 104;

[0091] A pressure-resistant medium structure 111 is formed above the protective layer 108.

[0092] As an example, such as Figure 13 As shown, a padding silica layer 107 is also formed between the interlayer dielectric layer 104 and the protective layer 108; the distribution shape of the padding silica layer 107 corresponds to the pressure-resistant dielectric structure 111.

[0093] Compared to existing technologies that first form the dielectric structure and then form the contact holes, this invention introduces a protective layer, allowing the contact hole formation process to be performed before the dielectric structure is formed. This avoids the adverse effects of wafer warpage and other problems caused by the dielectric structure on the contact hole formation process, such as photolithography.

[0094] In summary, this invention provides an IGBT structure and its fabrication method, the fabrication method comprising the following steps:

[0095] 1) Provide an underlying structure, the underlying structure comprising, in sequence: a substrate having an active region formed thereon, a polysilicon layer, and an interlayer dielectric layer;

[0096] 2) A first photoresist pattern layer is formed on the interlayer dielectric layer by photolithography; the first photoresist pattern layer is used as an etching mask to etch the interlayer dielectric layer and the underlying structure to form a contact hole, wherein the bottom of the contact hole stops on the active region or the polysilicon layer.

[0097] 3) Remove the first photoresist pattern layer, and sequentially form a protective layer on the sidewalls and bottom of the contact hole and on the surface of the interlayer dielectric layer.

[0098] 4) Deposit a pressure-resistant dielectric material layer above the protective layer and photolithographically form a second photoresist pattern layer on the pressure-resistant dielectric material layer; use the second photoresist pattern layer as an etching mask to etch the pressure-resistant dielectric material layer to form a pressure-resistant dielectric structure;

[0099] 5) Remove the second photoresist pattern layer and the protective layer to expose the active region or the polysilicon layer at the bottom of the contact hole, while retaining part of the protective layer below the voltage-resistant dielectric structure;

[0100] 6) Deposit a metal connection layer on the surface of the contact hole and the interlayer dielectric layer, and form a passivation layer on the surface of the metal connection layer to protect the metal connection layer.

[0101] This invention eliminates the adverse effects of wafer warpage caused by the dielectric structure on the contact hole formation process by adjusting the formation order of the contact hole and the dielectric structure; by introducing a protective layer, it avoids the process of forming the dielectric structure from affecting the contact hole structure, which helps to improve the process window and increase the process yield.

[0102] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for fabricating an IGBT structure, characterized in that, Includes the following steps: 1) Provide an underlying structure, the underlying structure comprising: a substrate forming an active region, a polysilicon layer, and an interlayer dielectric layer; 2) A first photoresist pattern layer is formed on the interlayer dielectric layer by photolithography; Using the first photoresist pattern layer as an etching mask, the interlayer dielectric layer is etched and the underlying structure is etched to form contact holes; 3) Remove the first photoresist pattern layer, and sequentially form a protective layer on the sidewalls and bottom of the contact hole and on the surface of the interlayer dielectric layer; 4) Deposit a pressure-resistant dielectric material layer on top of the protective layer and photolithographically form a second photoresist pattern layer on the pressure-resistant dielectric material layer; The second photoresist pattern layer is used as an etching mask to etch the pressure-resistant dielectric material layer to form a pressure-resistant dielectric structure; 5) Remove the second photoresist pattern layer and the protective layer to expose the active region or the polysilicon layer at the bottom of the contact hole, while retaining part of the protective layer below the voltage-resistant dielectric structure; 6) Deposit a metal connection layer on the surface of the contact hole and the interlayer dielectric layer, and form a passivation layer on the surface of the metal connection layer to protect the metal connection layer.

2. The method for fabricating the IGBT structure according to claim 1, characterized in that, A padding silicon dioxide layer is also formed between the interlayer dielectric layer and the protective layer to relieve stress between the protective layer and the substrate.

3. The method for fabricating the IGBT structure according to claim 2, characterized in that, In step 5), after removing the second photoresist pattern layer and the protective layer, the lower pad silicon dioxide layer is further removed to completely expose the active area or the polysilicon layer at the bottom of the contact hole; a portion of the pad silicon dioxide layer is still retained below the voltage-resistant dielectric structure.

4. The method for fabricating the IGBT structure according to claim 3, characterized in that, Methods for removing the padding silicon dioxide layer include HF wet etching or plasma dry etching for silicon dioxide materials.

5. The method for fabricating the IGBT structure according to claim 1, characterized in that, The projection of the pressure-resistant dielectric structure onto the substrate does not coincide with the projection of the contact hole onto the substrate.

6. The method for preparing the IGBT structure according to any one of claims 2 to 4, characterized in that, The thickness of the silicon dioxide liner layer is 200nm-500nm.

7. The method for fabricating an IGBT structure according to any one of claims 1 to 4, characterized in that, The protective layer is composed of a silicon nitride layer; in step 5), the silicon nitride layer is removed by hot phosphoric acid wet etching or plasma dry etching using CF4 / CHF3 as the etching gas.

8. The method for fabricating an IGBT structure according to any one of claims 1 to 5, characterized in that, After forming the metal interconnect layer and the passivation layer, the process further includes back-side thinning, back-side implantation, back-side annealing, and back-side metallization of the substrate.

9. An IGBT structure, characterized in that, The IGBT structure is prepared using the fabrication method of any one of claims 1 to 8, wherein the IGBT structure comprises: The bottom layer structure consists of a substrate forming the active region, a polysilicon layer, and an interlayer dielectric layer, which are stacked sequentially from bottom to top. A contact hole is formed in the interlayer dielectric layer, and the bottom of the contact hole stops on the active region or the polysilicon layer; A protective layer formed above the interlayer dielectric layer; A pressure-resistant medium structure formed above the protective layer.

10. The IGBT structure according to claim 9, characterized in that, A liner silica layer is also formed between the interlayer dielectric layer and the protective layer; the distribution shape of the liner silica layer corresponds to the structure of the pressure-resistant dielectric.

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