Display device

Abstract

A display device is disclosed. The display device includes a stretchable lower substrate, a pattern layer disposed on the lower substrate. The pattern layer includes a plurality of first plate patterns and a plurality of second plate patterns, a plurality of first line patterns and a plurality of second line patterns. The device includes a plurality of pixels formed on the plurality of first plate patterns, a plurality of first connection lines connecting the plurality of pixels, a gate driver formed on the plurality of second plate patterns, a power supply formed on the plurality of second plate patterns, a plurality of second connection lines, and a stretchable upper substrate.

Description

Technical Field

[0001] This disclosure relates to a display device, and more specifically, to a stretchable display device. Background Technology

[0002] As display devices used as monitors for computers, televisions, or cellular phones, there are organic light-emitting display devices (OLEDs) that are self-emissive and liquid crystal display devices (LCDs) that require a separate light source.

[0003] The applications of display devices are diverse, ranging from personal digital assistants to computer and television monitors, and research is underway on display devices with large display areas and reduced size and weight.

[0004] Recently, display devices that are manufactured by forming display units and wiring on a flexible substrate, such as plastic, a flexible material, so that they can be stretched in a specific direction and changed in various forms, have attracted attention as the next generation of display devices. Summary of the Invention

[0005] One or more embodiments of this disclosure provide a display device in which the wiring is not damaged even by repeated stretching.

[0006] One or more embodiments of this disclosure provide a display device in which all areas are biaxially stretchable.

[0007] Other embodiments of this disclosure provide a display device for suppressing wire tearing during a lift-off process.

[0008] Other embodiments of this disclosure provide a display device for suppressing drive voltage drop.

[0009] The technical benefits of this disclosure are not limited to those described above, and other benefits not mentioned above will be clearly understood by those skilled in the art from the following description.

[0010] To achieve the above benefits, according to one aspect of this disclosure, a display device includes: a lower substrate, the lower substrate including a display area and a non-display area and being stretchable; a pattern layer disposed on the lower substrate, the pattern layer including a plurality of first plate patterns and a plurality of first line patterns formed in the display area and a plurality of second plate patterns and a plurality of second line patterns formed in the non-display area; a plurality of pixels formed on the plurality of first plate patterns; a plurality of first connecting lines connecting the plurality of pixels; a gating driver formed on the plurality of second plate patterns; and a power supply formed on the plurality of second plate patterns. The system comprises: an upper substrate; multiple second connecting lines disposed in the non-display area; and an upper substrate covering the gating driver, the power supply, and the plurality of pixels and being stretchable; wherein the non-display area includes: a first area located outside the display area, a second area located outside the first area and including the plurality of gating drivers disposed in the second area, and a third area located outside the second area and including the plurality of power supplies disposed in the third area, and wherein the plurality of second connecting lines disposed in the first area are in contact with a metal pattern disposed on a layer different from the plurality of second connecting lines through anchor holes.

[0011] According to another aspect of this disclosure, a display device includes: a flexible substrate; a plurality of rigid patterns formed on the flexible substrate; a plurality of pixels formed over a plurality of first plate patterns spaced apart from each other among the plurality of rigid patterns; and a power source formed over some of a plurality of second plate patterns spaced apart from each other among the plurality of rigid patterns, the power source providing driving voltages to the plurality of pixels and configured by a plurality of power blocks spaced apart from each other in a first direction and a second direction.

[0012] Further details of the implementation methods are included in the specific description and accompanying drawings.

[0013] According to this disclosure, anchoring holes are formed in the buffer lines to stably ensure the tensile reliability of the display device.

[0014] According to this disclosure, the buffer line is fixed by anchoring holes so that the display device is not damaged during peeling.

[0015] According to this disclosure, the non-display area is biaxially stretched to improve the applicability of the display device.

[0016] According to this disclosure, the power supply includes additional power blocks electrically connected between the power blocks to reduce or minimize the drive voltage drop.

[0017] The effects of this disclosure are not limited to the examples above, and many more effects are included in this specification. Attached Figure Description

[0018] The above and other aspects, features and other advantages of this disclosure will become more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0019] Figure 1 This is a plan view of a display device according to an embodiment of the present disclosure;

[0020] Figure 2 This is an enlarged plan view of the display area of ​​a display device according to an embodiment of the present disclosure;

[0021] Figure 3 It is along Figure 2 A cross-sectional view taken from line III-III';

[0022] Figure 4 It is along Figure 2 A cross-sectional view taken from line IV-IV';

[0023] Figure 5 It is along Figure 2 A cross-sectional view taken from line V-V';

[0024] Figure 6 This is a circuit diagram of a sub-pixel of a display device according to an embodiment of the present disclosure;

[0025] Figure 7 This is an enlarged plan view of the non-display area of ​​a display device according to an embodiment of the present disclosure;

[0026] Figure 8 This is an enlarged plan view of the first region of a display device according to an embodiment of the present disclosure;

[0027] Figure 9 It is along Figure 8 A cross-sectional view taken from line IX-IX';

[0028] Figure 10 This is an enlarged plan view of the third region of a display device according to an embodiment of the present disclosure;

[0029] Figure 11 It is along Figure 10 A cross-sectional view taken from line XI-XI';

[0030] Figure 12 This is an enlarged plan view of the third region of a display device according to another embodiment of the present disclosure; and

[0031] Figure 13 It is along Figure 12The cross-sectional view taken from line XIII-XIII'. Detailed Implementation

[0032] The advantages and features of this disclosure, as well as methods for achieving these advantages and features, will become clear from the following detailed description of embodiments in conjunction with the accompanying drawings. However, this disclosure is not limited to the embodiments disclosed herein, but will be implemented in various forms. The embodiments are provided by way of example only to enable those skilled in the art to fully understand the disclosure and scope of this disclosure.

[0033] The shapes, sizes, dimensions (e.g., length, width, height, thickness, radius, diameter, area, etc.), scales, angles, number of elements, etc., shown in the accompanying drawings to describe embodiments of the present disclosure are merely examples, and the present disclosure is not limited thereto. Throughout the specification, the same reference numerals generally denote the same elements. Furthermore, in the following description of the present disclosure, detailed descriptions of known related technologies may be omitted to avoid unnecessarily obscuring the subject matter of the disclosure. Unless the term is used in conjunction with the term "only," terms such as "comprising" or "having" as used herein are generally intended to allow for the addition of other components. Unless explicitly stated otherwise, any reference to the singular may include the plural.

[0034] Even if not explicitly stated, components are interpreted as including a normal error range.

[0035] When using terms such as “above,” “over,” “below,” and “adjacent” to describe the positional relationship between two parts, one or more parts may be placed between the two parts unless the term is used in conjunction with the terms “immediately” or “directly.”

[0036] When an element or layer is placed "on" another element or layer, the element may be located directly on the other layer or another element, or may be inserted between other elements.

[0037] Although the terms "first," "second," etc., are used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from other components. Therefore, the first component referred to below may be the second component in the technical concept of this disclosure.

[0038] Throughout the specification, the same reference numerals generally denote the same elements.

[0039] The dimensions and thicknesses of each component shown in the accompanying drawings are for illustrative purposes only, and this disclosure is not limited to the dimensions and thicknesses of the components shown.

[0040] Features of the various embodiments of this disclosure may be partially or wholly bonded or combined with each other, and may be interlocked and operated in various technical ways, and the embodiments may be performed independently or in association with each other.

[0041] The display device according to embodiments of this disclosure is a display device capable of displaying images even in a bent or stretched state, and is also referred to as a stretchable display device, a flexible display device, and a malleable display device. Compared to general display devices of the prior art, this display device not only has high flexibility but also stretchability. Therefore, a user can bend or stretch the display device, and the shape of the display device can be freely changed according to the user's manipulation. For example, when a user holds the end of the display device and pulls it, the display device can extend in the direction of the user's pull. Alternatively, when the user places the display device on an uneven outer surface, the display device can be configured to bend according to the shape of the outer surface. Furthermore, when the force applied by the user is removed, the display device can return to its original shape.

[0042] Stretchable substrate and patterned layer

[0043] Figure 1 This is a plan view of a display device according to an embodiment of the present disclosure.

[0044] Figure 2 This is an enlarged plan view of the display area of ​​a display device according to an embodiment of the present disclosure. Specifically, Figure 2 yes Figure 1 An enlarged plan view of region A shown.

[0045] Figure 3 It is along Figure 2 The cross-sectional view taken from line III-III'.

[0046] Reference Figure 1 The display device 100 according to embodiments of this disclosure may include a lower substrate 111, a pattern layer 120, a plurality of pixels PX, a gating driver GD, a data driver DD, and a power supply PS. The gating driver GD and the data driver DD may be referred to as driving circuits. The power supply PS may be referred to as power supply circuit PS. (See also...) Figure 3 The display device 100 according to the embodiments of the present disclosure may further include a filler layer 190 and an upper substrate 112.

[0047] The lower substrate 111 is a substrate that supports and protects several components of the display device 100. The upper substrate 112 is a substrate that covers and protects several components of the display device 100. That is, the lower substrate 111 is a substrate that supports a pattern layer 120 on which pixels PX, gating drivers GD, and power supplies PS are formed. The upper substrate 112 is a substrate that covers pixels PX, gating drivers GD, and power supplies PS.

[0048] The lower substrate 111 and upper substrate 112, serving as flexible substrates, can be made of a bendable or stretchable insulating material. For example, the lower substrate 111 and upper substrate 112 can be formed of silicone rubber such as polydimethylsiloxane (PDMS) or elastomers such as polyurethane (PU) or polytetrafluoroethylene (PTFE), thus possessing flexibility. Furthermore, the materials of the lower substrate 111 and upper substrate 112 can be the same, but are not limited to this, and can vary.

[0049] The lower substrate 111 and the upper substrate 112 are flexible substrates to allow for reversible stretching and contraction. Therefore, the lower substrate 111 may be referred to as a lower stretchable substrate, lower stretching substrate, lower stretchable substrate, lower flexible substrate, first stretchable substrate, first stretching substrate, first stretchable substrate, first stretchable substrate, or first flexible substrate. The upper substrate 112 may be referred to as an upper stretchable substrate, upper stretching substrate, upper stretchable substrate, upper flexible substrate, second stretchable substrate, second stretchable substrate, second stretchable substrate, or second flexible substrate. Furthermore, the elastic modulus of the lower substrate 111 and the upper substrate 112 can be from a few MPa to several hundred MPa. Furthermore, the ductile fracture rate of the lower substrate 111 and the upper substrate 112 can be 100% or higher. In some embodiments, the ductile fracture rate refers to the elongation rate when the object to be stretched breaks or fractures. In other embodiments, the ductile fracture rate refers to the elongation distance when the object to be stretched breaks or fractures. In other words, the ductile fracture rate is defined as the percentage of the original length of the object to the length of the stretched object when it has been sufficiently stretched to be considered to break. For example, if the length of an object (e.g., the lower substrate 111) is 100 cm when it is not stretched, and then, when the object is sufficiently stretched to break or fracture at that length, it reaches a length of 110 cm, and then it is stretched to 110% of its original length, then the ductile fracture rate of the object is 110%. This value can therefore also be called the ductile fracture ratio, because it is the ratio of the stretched length as the numerator to the original upward stretched length as the denominator when fracture occurs.

[0050] An object is considered broken when it no longer functions properly in a structure or circuit. For example, a wire that is a conductor will be considered broken when its ability to carry current is sufficiently degraded to be outside the circuit's specifications. Therefore, in some embodiments, a complete break in the wire may not be necessary for a wire to be considered broken; minor stress at the connection point, minor cracks, minor offsets in the wiring position, or other movements that cause it to no longer function as intended will be considered a broken wire. An insulator will be considered broken if it is stretched sufficiently that it no longer provides the amount of insulation required by the structure or circuit. In some embodiments, a break will also include inelastic stretching, where the object has been stretched sufficiently that it cannot return to its original length and / or shape when it is no longer stretched.

[0051] The thickness of the lower substrate can be from 10 μm to 1 mm, but is not limited to this.

[0052] The lower substrate 111 may have a display area AA and a non-display area NA surrounding the display area AA.

[0053] The display area AA is the area in the display device 100 where an image is displayed. A plurality of pixels PX are disposed in the display area AA. Each pixel PX may include a display element and various driving elements for driving the display element. The various driving elements may refer to at least one thin-film transistor (TFT) and a capacitor, but are not limited thereto. The plurality of pixels PX may be individually connected to various wirings. For example, each of the plurality of pixels PX may be connected to various wirings such as a gate line, a data line, a high-potential power line, a low-potential power line, and a reference voltage line.

[0054] The non-display area NA is the area where no image is displayed. The non-display area NA is adjacent to the display area AA to surround the display area AA. However, it is not limited to this; the non-display area NA corresponds to the area excluding the display area AA from the lower substrate 111, and can be modified and separated in various ways. Components for driving the multiple pixels PX disposed in the display area AA are disposed in the non-display area NA. That is, the gating driver GD and the power supply PS can be disposed in the non-display area NA. Multiple pads connected to the gating driver GD and the data driver DD can be disposed in the non-display area NA, and each pad can be connected to each of the multiple pixels PX in the display area AA.

[0055] A pattern layer 120 formed of a plastic material with a flexibility lower than that of the lower substrate 111 may be provided on the lower substrate 111. For example, the pattern layer 120 may be formed of polyimide (PI), polyacrylate, and polyacetate.

[0056] The pattern layer 120 may include a plurality of first plate patterns 121 (also referred to as a plurality of first plate structures 121) and a plurality of first line patterns 122 disposed in the display area AA, and a plurality of second plate patterns 123 (also referred to as a plurality of second plate structures 123) and a plurality of second line patterns 124 disposed in the non-display area NA.

[0057] Multiple first board patterns 121 are disposed in the display area AA of the lower substrate 111, such that multiple pixels PX are formed on the multiple first board patterns 121. Multiple second board patterns 123 are disposed in the non-display area NA of the lower substrate 111, such that a gate driver GD and a power supply PS are formed on the multiple second board patterns 123.

[0058] Multiple first plate patterns 121 and multiple second plate patterns 123 are arranged in the form of separate islands, allowing each first plate pattern 121 and multiple second plate patterns 123 to be individually isolated. Therefore, the multiple first plate patterns 121 and multiple second plate patterns 123 can be referred to as first island patterns and second island patterns, or first individual patterns and second individual patterns. The first plate patterns 121, spaced apart from each other, can be connected by first line patterns 122. In the non-display area NA, the second plate patterns 123, also spaced apart from each other, can be connected by second line patterns 124.

[0059] Specifically, the plurality of second board patterns 123 disposed in the non-display area NA may include a plurality of first sub-board patterns 123a, a plurality of second sub-board patterns 123b, and a plurality of third sub-board patterns 123c. Anchor holes are disposed in the plurality of first sub-board patterns 123a, a gating driver GD is disposed on the plurality of second sub-board patterns 123b, and a power supply PS is disposed on the plurality of third sub-board patterns 123c.

[0060] More specifically, such as Figure 1 As shown, a plurality of first sub-board patterns 123a are configured to be adjacent to the display area AA in a first direction (e.g., the X-axis direction) and spaced apart from each other in a second direction (e.g., the Y-axis direction). That is, the first sub-board patterns 123a can be disposed on both sides of the display area AA relative to the first direction X. However, this disclosure is not limited thereto, and the first sub-board patterns 123a can be disposed on only one side of the display area AA relative to the first direction X. Furthermore, anchoring holes for engaging multiple connecting lines can be disposed on the plurality of first sub-board patterns 123a.

[0061] A plurality of second sub-board patterns 123b are configured to be adjacent to a plurality of first sub-board patterns 123a in a first direction X, and are configured to be spaced apart from a plurality of first sub-board patterns 123a in a second direction Y. That is, the plurality of second sub-board patterns 123b may be disposed on both sides of the plurality of first sub-board patterns 123a relative to the first direction X. However, this disclosure is not limited thereto, and the second sub-board patterns 123b may be disposed on only one side of the plurality of first sub-board patterns 123a.

[0062] The gate driver GD can be mounted on multiple second daughter board patterns 123b. When manufacturing various components on the first daughter board pattern 121, the gate driver GD can be formed on the second daughter board pattern 123b in a gate-in-panel (GIP) manner. Therefore, various circuit structures constituting the gate driver GD (e.g., various transistors, capacitors, and wiring) can be arranged on the multiple second daughter board patterns 123b. However, this is not a limitation, and the gate driver GD can also be mounted in a chip-on-film (COF) manner.

[0063] Furthermore, a plurality of third sub-board patterns 123c are configured to be adjacent to a plurality of second sub-board patterns 123b in the first direction X, and spaced apart from the plurality of second sub-board patterns 123b in the second direction Y. That is, the plurality of third sub-board patterns 123c can be disposed on both sides of the plurality of second sub-board patterns 123b relative to the first direction X. However, this is not a limitation; the plurality of third sub-board patterns 123c can be disposed on only one side of the plurality of second sub-board patterns 123b relative to the first direction X. Additionally, power supplies PS can be mounted in the plurality of third sub-board patterns 123c. Power supplies PS are a plurality of power blocks patterned when manufacturing various components on the first board pattern 121, and can be formed on the third sub-board pattern 123c. Therefore, power blocks disposed on different layers can be disposed on the third sub-board pattern 123c.

[0064] Reference Figure 1 The size of the plurality of first sub-board patterns 123a can be smaller than the size of the plurality of first board patterns 121. Specifically, the size of each of the plurality of first sub-board patterns 123a can be smaller than the size of each of the plurality of first board patterns 121. As described above, anchoring holes AH are provided in each of the plurality of first sub-board patterns 123a. The area occupied by the anchoring holes AH is smaller than the area occupied by the pixel PX, such that the size of each of the plurality of first sub-board patterns 123a can be smaller than the size of each of the plurality of first board patterns 121.

[0065] Furthermore, the size of the plurality of second sub-board patterns 123b can be larger than the size of the plurality of first board patterns 121. Specifically, the size of each of the plurality of second sub-board patterns 123b can be larger than the size of each of the plurality of first board patterns 121. As described above, a gating driver GD is disposed on each of the plurality of second sub-board patterns 123b, and a stage of the gating driver GD is disposed in each of the plurality of second sub-board patterns 123b. Therefore, the area occupied by the various circuit configurations constituting a stage of the gating driver GD can be relatively larger than the area occupied by the pixel PX, such that the size of each of the plurality of second sub-board patterns 123b can be larger than the size of each of the plurality of first board patterns 121.

[0066] Despite Figure 1 In this embodiment, a plurality of second plate patterns 123 are disposed on both sides of the non-display area NA in the first direction X, but are not limited thereto, and can be arranged in any region of the non-display area NA. Furthermore, although the plurality of first plate patterns 121 and the plurality of second plate patterns 123 are shown to have quadrilateral shapes, they are not limited thereto, and the shapes of the plurality of first plate patterns 121 and the plurality of second plate patterns 123 can vary in various forms.

[0067] Reference Figure 1 and Figure 3 The pattern layer 120 may include a plurality of first line patterns 122 disposed in the display area AA and a plurality of second line patterns 124 disposed in the non-display area NA.

[0068] Multiple first line patterns 122 can be disposed in the display area AA. The multiple first line patterns 122 are patterns that connect adjacent first plate patterns 121 and are referred to as first connecting patterns. That is, the multiple first line patterns 122 are disposed between the multiple first plate patterns 121.

[0069] Multiple second line patterns 124 can be disposed in the non-display area NA. The multiple second line patterns 124 connect adjacent first board patterns 121 and second board patterns 123. For example, the multiple second line patterns can connect the first board pattern 121 located at the edge of the display area AA and the second board pattern 123 located in the non-display area NA adjacent to the first board pattern 121. Furthermore, the multiple second line patterns 124 can be patterns connecting multiple adjacent second board patterns 123. Therefore, the multiple second line patterns 124 can be referred to as second connecting patterns. That is, the multiple second line patterns 124 can be disposed between adjacent first board patterns 121 and second board patterns 123, and between multiple adjacent second board patterns 123.

[0070] Reference Figure 1The plurality of first line patterns 122 and the plurality of second line patterns 124 have a wavy shape. For example, the plurality of first line patterns 122 and the plurality of second line patterns 124 have a sinusoidal shape. However, the shapes of the plurality of first line patterns 122 and the plurality of second line patterns 124 are not limited thereto. For example, the plurality of first line patterns 122 and the plurality of second line patterns 124 may extend in a zigzag pattern, or may be formed in various shapes (e.g., shapes that extend by connecting a plurality of rhomboid substrates at their vertices). Furthermore, Figure 1 The number and shape of the multiple first line patterns 122 and multiple second line patterns 124 shown are examples and can be changed in various forms according to the design.

[0071] The plurality of first plate patterns 121, the plurality of first line patterns 122, the plurality of second plate patterns 123, and the plurality of second line patterns 124 are rigid patterns. That is, the plurality of first plate patterns 121, the plurality of first line patterns 122, the plurality of second plate patterns 123, and the plurality of second line patterns 124 can be harder than the lower substrate 111 and the upper substrate 112. In other words, the elastic modulus of the plurality of first plate patterns 121, the plurality of first line patterns 122, the plurality of second plate patterns 123, and the plurality of second line patterns 124 can be higher than the elastic modulus of the lower substrate 111. The elastic modulus is a parameter that represents the rate of deformation against stress applied to a substrate, and the higher the elastic modulus, the higher the hardness. Therefore, the plurality of first plate patterns 121, the plurality of first line patterns 122, the plurality of second plate patterns 123, and the plurality of second line patterns 124 can be referred to as a plurality of first rigid patterns, a plurality of second rigid patterns, a plurality of third rigid patterns, and a plurality of fourth rigid patterns, respectively. The elastic modulus of the plurality of first plate patterns 121, the plurality of first line patterns 122, the plurality of second plate patterns 123 and the plurality of second line patterns 124 may be 1,000 times higher than the elastic modulus of the lower substrate 111 and the upper substrate 112, but is not limited thereto.

[0072] The plurality of first plate patterns 121, the plurality of first line patterns 122, the plurality of second plate patterns 123, and the plurality of second line patterns 124, which are multiple rigid substrates, can be formed of a plastic material with lower flexibility than the lower substrate 111 and the upper substrate 112. For example, the plurality of first plate patterns 121, the plurality of first line patterns 122, the plurality of second plate patterns 123, and the plurality of second line patterns 124 can be formed of polyimide (PI), polyacrylate, polyacetate, etc. In this case, the plurality of first plate patterns 121, the plurality of first line patterns 122, the plurality of second plate patterns 123, and the plurality of second line patterns 124 can be formed of the same material, but are not limited thereto, and can be formed of different materials.

[0073] In some embodiments, the lower substrate 111 may be defined to include a plurality of first lower patterns and second lower patterns. The plurality of first lower patterns are disposed in the region of the lower substrate 111 that overlaps with the plurality of first plate patterns 121 and the plurality of second plate patterns 123. The second lower patterns may be disposed in a region other than the region where the plurality of first plate patterns 121 and the plurality of second plate patterns 123 are disposed, or may be disposed throughout the entire display device 100.

[0074] Furthermore, the upper substrate 112 is defined to include a plurality of first upper patterns and a plurality of second upper patterns. The plurality of first upper patterns are disposed in the region of the upper substrate 112 that overlaps with the plurality of first plate patterns 121 and the plurality of second plate patterns 123. The second upper pattern may be disposed in a region other than the region where the plurality of first plate patterns 121 and the plurality of second plate patterns 123 are disposed, or it may be disposed throughout the entire display device 100.

[0075] At this time, the elastic modulus of the plurality of first lower patterns and first upper patterns can be higher than that of the second lower patterns and second upper patterns. For example, the plurality of first lower patterns and first upper patterns can be formed of the same material as the plurality of first plate patterns 121 and the plurality of second plate patterns 123. The second lower patterns and second upper patterns can be formed of a material with an elastic modulus lower than that of the plurality of first plate patterns 121 and the plurality of second plate patterns 123.

[0076] In other words, the first lower pattern and the first upper pattern can be formed from polyimide (PI), polyacrylate, polyacetate, etc. Furthermore, the second lower pattern and the second upper pattern can be formed from silicone rubber such as polydimethylsiloxane (PDMS) or elastomers such as polyurethane (PU) or polytetrafluoroethylene (PTFE).

[0077] Non-active region driving element

[0078] A gating driver GD is a component that provides gating voltages to multiple pixels PX disposed in a display area AA. The gating driver GD includes multiple stages formed on a second sub-board pattern 123b in multiple second board patterns 123, and the stages of the gating driver GD are electrically connected to each other via multiple gating connection lines. Therefore, a gating voltage output from any stage can be transferred to another stage. Each stage can sequentially provide gating voltages to the multiple pixels PX connected to each stage.

[0079] A power supply PS is connected to a gating driver GD to provide a gating drive voltage and a gating clock voltage. Furthermore, the power supply PS is connected to a plurality of pixels PX to provide a pixel drive voltage to each of the plurality of pixels PX. Additionally, the power supply PS can be formed on a third sub-board pattern 123c among a plurality of second board patterns 123. That is, the power supply PS can be formed adjacent to the gating driver GD on the second board pattern 123. Furthermore, the power supply PS formed on the plurality of third sub-board patterns 123c is electrically connected to the gating driver GD and the plurality of pixels PX. That is, the plurality of power supplies PS formed on the plurality of third sub-board patterns 123c can be connected via gating power connection lines and pixel power connection lines. Therefore, each of the plurality of power supplies PS can provide a gating drive voltage, a gating clock voltage, and a pixel drive voltage.

[0080] A printed circuit board (PCB) is a component that transmits signals and voltages used to drive display elements from a control unit to the display elements. Therefore, a PCB can also be referred to as a driver substrate. Control units, such as IC chips or circuit units, can be mounted on the PCB. Furthermore, a memory or processor can also be mounted on the PCB. Additionally, the PCB 130 disposed in the display device 100 may include stretched and non-stretched areas to ensure stretchability. Furthermore, IC chips, circuit units, memory, and processors are mounted in the non-stretched areas, and wiring electrically connected to the IC chips, circuit units, memory, and processor can be provided in the stretched areas.

[0081] The data driver (DD) is a component that provides data voltage to multiple pixels (PX) located in the display area (AA). The data driver (DD) is configured as an IC chip, therefore it is also called a data integrated circuit (D-IC). Furthermore, the data driver (DD) can be mounted in the non-stretchable area of ​​a printed circuit board (PCB). That is, the data driver (DD) can be mounted on the PCB as a chip-on-board (COB). However, although in Figure 1 The diagram shows the data driver DD mounted as a chip-on-board (COB) package, but it is not limited to this, and the data driver DD can also be mounted as a chip-on-film (COF), chip-on-glass (COG), or cable-on-trace (TCP) package.

[0082] Furthermore, even in Figure 1 In this configuration, a data driver DD is configured to correspond to a first panel pattern 121 in a column of the display area AA, but is not limited thereto. That is, a data driver DD can be configured to correspond to a first panel pattern 121 in multiple columns.

[0083] In the following text, we will refer to... Figure 4 and Figure 5The display area AA of the display device 100 according to an embodiment of the present disclosure will be described in more detail.

[0084] The planar and cross-sectional structure of the display area

[0085] Figure 4 It is along Figure 2 The cross-sectional view taken from line IV-IV'.

[0086] Figure 5 It is along Figure 2 A cross-sectional view taken from line V-V'.

[0087] For ease of description, please refer to the following: Figures 1 to 3 Describe it.

[0088] Reference Figure 1 and Figure 2 Multiple first plate patterns 121 are disposed on a lower substrate 111 in the display area AA. The multiple first plate patterns 121 are spaced apart from each other on the lower substrate 111. For example, as... Figure 1 As shown, multiple first plate patterns 121 can be arranged in a matrix on the lower substrate 111, but are not limited thereto.

[0089] Reference Figure 2 and Figure 3 The pixel PX, comprising multiple sub-pixels SPX, is disposed in the first plate pattern 121. Furthermore, each sub-pixel SPX may include a light-emitting diode 170 as a display element, and a driving transistor 160 and a switching transistor 150 driving the light-emitting diode 170. However, the display element in the sub-pixel SPX is not limited to a light-emitting diode and may also be changed to an organic light-emitting diode. For example, the multiple sub-pixels SPX may include red sub-pixels, green sub-pixels, and blue sub-pixels, but are not limited to this, and the colors of the multiple sub-pixels SPX can be modified to various colors as needed.

[0090] Multiple subpixels SPX can be connected to multiple pixel connection lines 181 and 182. That is, multiple subpixels SPX can be electrically connected to a first pixel connection line 181 extending in a first direction X. In addition, multiple subpixels SPX can be electrically connected to a second pixel connection line 182 extending in a second direction Y.

[0091] Furthermore, the multiple pixel connection lines 181 and 182 set in the display area AA can be referred to as the first connection lines, and the buffer lines, gating connection lines or power lines set in the non-display area NA can be referred to as the second connection lines.

[0092] In the following text, reference will be made to Figure 3 Describe the cross-sectional structure of the display area AA in detail.

[0093] Reference Figure 3 Multiple inorganic insulating layers are disposed on multiple first board patterns 121. For example, the multiple inorganic insulating layers may include a buffer layer 141, a gate insulating layer 142, a first interlayer insulating layer 143, a second interlayer insulating layer 144, and a passivation layer 145, but are not limited thereto. Therefore, various inorganic insulating layers may be additionally disposed on the multiple first board patterns 121, or one or more of the buffer layer 141, gate insulating layer 142, first interlayer insulating layer 143, second interlayer insulating layer 144, and passivation layer 145 as inorganic insulating layers may be omitted.

[0094] Specifically, a buffer layer 141 is disposed on a plurality of first plate patterns 121. The buffer layer 141 is formed on the plurality of first plate patterns 121 to protect various components of the display device 100 from the penetration of moisture (H2O) and oxygen (O2) from the exterior of the lower substrate 111 and the plurality of first plate patterns 121. The buffer layer 141 may be made of an insulating material. For example, the buffer layer 141 may be a single layer or a double layer formed of at least one of silicon nitride (SiNx), silicon oxide (SiOx), and silicon oxynitride (SiON). However, depending on the structure or characteristics of the display device 100, the buffer layer 141 may be omitted.

[0095] In the display area AA, the buffer layer 141 may be formed only in the area where the lower substrate 111 overlaps with the plurality of first plate patterns 121. As described above, the buffer layer 141 may be formed of an inorganic material, making it prone to breakage or damage during the stretching of the display device 100. Therefore, in the display area AA, the buffer layer 141 is not formed in the area between the plurality of first plate patterns 121, but is patterned into a shape having the plurality of first plate patterns 121 formed only above the plurality of first plate patterns 121.

[0096] Furthermore, in the non-display area NA, the buffer layer 141 may be formed only in the region where the lower substrate 111 overlaps with the plurality of second plate patterns 123. As described above, the buffer layer 141 may be formed of an inorganic material, making it prone to breakage or damage during the stretching of the display device 100. Therefore, in the non-display area NA, the buffer layer 141 is not formed in the region between the plurality of second plate patterns 123, but is patterned into a shape having the plurality of second plate patterns 123 formed only above the plurality of second plate patterns 123.

[0097] As described above, the buffer layer 141 can be formed only in the region where the lower substrate 111 overlaps with the plurality of first plate patterns 121 and the plurality of second plate patterns 123. As described above, the buffer layer 141 can be formed of an inorganic material, making it prone to breakage or damage during the stretching of the display device 100. Therefore, the buffer layer 141 is not formed in the region between the plurality of first plate patterns 121 and the plurality of second plate patterns 123. Instead, the buffer layer 141 is patterned to have a shape with the plurality of first plate patterns 121 and the plurality of second plate patterns 123 only disposed above the plurality of first plate patterns 121 and the plurality of second plate patterns 123. Therefore, in the display device 100 according to the embodiment of the present disclosure, the buffer layer 141 is formed only in the region overlapping with the plurality of first plate patterns 121 and the plurality of second plate patterns 123, which are rigid patterns. Therefore, even if the display device 100 is bent or stretched, damage to various components of the display device 100 can be suppressed.

[0098] Reference Figure 3 A switching transistor 150, including a gate electrode 151, an active layer 152, a source electrode 153, and a drain electrode 154, and a driving transistor 160, including a gate electrode 161, an active layer 162, a source electrode, and a drain electrode 164, are formed on a buffer layer 141.

[0099] First, refer to Figure 3 The active layer 152 of the switching transistor 150 and the active layer 162 of the driving transistor 160 are disposed on the buffer layer 141. For example, the active layer 152 of the switching transistor 150 and the active layer 162 of the driving transistor 160 can be formed of oxide semiconductor. Alternatively, the active layer 152 of the switching transistor 150 and the active layer 162 of the driving transistor 160 can be formed of amorphous silicon (a-Si), polycrystalline silicon (poly-Si), organic semiconductor, etc.

[0100] A gate insulating layer 142 is disposed on the active layer 152 of the switching transistor 150 and the active layer 162 of the driving transistor 160. The gate insulating layer 142 is a layer that electrically insulates the gate electrode 151 of the switching transistor 150 from the active layer 152 of the switching transistor 150 and the gate electrode 161 of the driving transistor 160 from the active layer 162 of the driving transistor 160. Furthermore, the gate insulating layer 142 can be formed of an insulating material. For example, the gate insulating layer 142 can be composed of a single layer of silicon nitride (SiNx) or silicon oxide (SiOx) or multiple layers of silicon nitride (SiNx) or silicon oxide (SiOx) as inorganic materials, but is not limited thereto.

[0101] The gate electrode 151 of the switching transistor 150 and the gate electrode 161 of the driving transistor 160 are disposed on the gate insulating layer 142. The gate electrode 151 of the switching transistor 150 and the gate electrode 161 of the driving transistor 160 are disposed on the gate insulating layer 142 in a spaced-apart manner. Furthermore, the gate electrode 151 of the switching transistor 150 overlaps with the active layer 152 of the switching transistor 150, and the gate electrode 161 of the driving transistor 160 overlaps with the active layer 162 of the driving transistor 160.

[0102] The gate electrode 151 of the switching transistor 150 and the gate electrode 161 of the driving transistor 160 can be any one of various metallic materials such as molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and copper (Cu), or an alloy of two or more of them, or a multilayer thereof, but are not limited thereto.

[0103] A first interlayer insulating layer 143 is disposed on the gate electrode 151 of the switching transistor 150 and the gate electrode 161 of the driving transistor 160. The first interlayer insulating layer 143 insulates the gate electrode 161 of the driving transistor 160 from the intermediate metal layer IM. Similar to the buffer layer 141, the first interlayer insulating layer 143 can be formed of an inorganic material. For example, the first interlayer insulating layer 143 can be composed of a single layer of silicon nitride (SiNx) or silicon oxide (SiOx) or multiple layers of silicon nitride (SiNx) or silicon oxide (SiOx) as inorganic materials, but is not limited thereto.

[0104] An intermediate metal layer IM is disposed on the first interlayer insulating layer 143. Furthermore, the intermediate metal layer IM overlaps with the gate electrode 161 of the driving transistor 160. Therefore, a storage capacitor is formed in the overlapping region of the intermediate metal layer IM and the gate electrode 161 of the driving transistor 160. Specifically, the gate electrode 161 of the driving transistor 160, the first interlayer insulating layer 143, and the intermediate metal layer IM form a storage capacitor. However, the placement area of ​​the intermediate metal layer IM is not limited to this, and the intermediate metal layer IM can overlap with another electrode to form various forms of storage capacitors.

[0105] The intermediate metal layer IM can be any of a variety of metallic materials such as molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and copper (Cu), or an alloy of two or more of them, or multiple layers thereof, but is not limited thereto.

[0106] The second interlayer insulating layer 144 is disposed on the intermediate metal layer IM. The second interlayer insulating layer 144 insulates the gate electrode 151 of the switching transistor 150 from the source electrode 153 and drain electrode 154 of the switching transistor 150. Furthermore, the second interlayer insulating layer 144 insulates the intermediate metal layer IM from the source electrode and drain electrode 164 of the driving transistor 160. Similar to the buffer layer 141, the second interlayer insulating layer 144 can be formed of an inorganic material. For example, the first interlayer insulating layer 143 can be composed of a single layer of silicon nitride (SiNx) or silicon oxide (SiOx) or multiple layers of silicon nitride (SiNx) or silicon oxide (SiOx) as inorganic materials, but is not limited thereto.

[0107] The source electrode 153 and drain electrode 154 of the switching transistor 150 are disposed on the second interlayer insulating layer 144. Similarly, the source electrode and drain electrode 164 of the driving transistor 160 are disposed on the second interlayer insulating layer 144. The source electrode 153 and drain electrode 154 of the switching transistor 150 are disposed on the same layer but spaced apart from each other. Furthermore, even when… Figure 3 The source electrode of the driving transistor 160 is omitted, and it is also configured to be on the same layer and spaced apart from the drain electrode 164. In the switching transistor 150, the source electrode 153 and the drain electrode 154 can contact the active layer 152 for electrical connection. Furthermore, in the driving transistor 160, the source electrode and the drain electrode 164 can contact the active layer 162 for electrical connection. Additionally, the drain 154 of the switching transistor 150 contacts the gate electrode 161 of the driving transistor 160 through a contact hole for electrical connection.

[0108] The source electrode 153 and drain electrodes 154 and 164 can be any of a variety of metallic materials such as molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and copper (Cu), or alloys of two or more of them, or multiple layers thereof, but are not limited thereto.

[0109] Furthermore, even though the driving transistor 160 is described as having a coplanar structure in this specification, various transistors such as those with interleaved structures can also be used.

[0110] The gating pad GP and the data pad DP can be set on the second interlayer insulating layer 144.

[0111] Specifically, refer to Figure 4The gating pad GP is a pad that transmits the gating voltage to multiple sub-pixels SPX. The gating pad GP is connected to the first pixel connection line 181 via a contact hole CH. Furthermore, the gating voltage provided from the first pixel connection line 181 can be transmitted from the gating pad GP to the gate electrode 151 of the switching transistor 150 via wiring formed on the first board pattern 121.

[0112] Furthermore, the data pad DP is a pad that sends data voltage to multiple sub-pixels SPX. The data pad DP is connected to the second pixel connection line 182 via a contact hole. In addition, the data voltage provided from the second pixel connection line 182 can be transmitted from the data pad DP to the source electrode 153 of the switching transistor 150 through wiring formed on the first board pattern 121.

[0113] The gate pad GP and data pad DP can be formed from the same material as the source electrode 153 and the drain electrodes 154 and 164, but are not limited thereto.

[0114] Reference Figure 3 A passivation layer 145 is formed on the switching transistor 150 and the driving transistor 160. That is, the passivation layer 145 covers the switching transistor 150 and the driving transistor 160 to protect them from moisture and oxygen penetration. The passivation layer 145 can be formed of inorganic materials and can be a single layer or a double layer, but is not limited thereto.

[0115] Furthermore, the gate insulating layer 142, the first interlayer insulating layer 143, the second interlayer insulating layer 144, and the passivation layer 145 are patterned to be formed only in the regions overlapping with the plurality of first plate patterns 121. Similar to the buffer layer 141, the gate insulating layer 142, the first interlayer insulating layer 143, the second interlayer insulating layer 144, and the passivation layer 145 may also be formed from inorganic materials. Therefore, during the stretching of the display device 100, the gate insulating layer 142, the first interlayer insulating layer 143, the second interlayer insulating layer 144, and the passivation layer 145 may also be easily broken and damaged. Therefore, the gate insulating layer 142, the first interlayer insulating layer 143, the second interlayer insulating layer 144, and the passivation layer 145 are not formed in the regions between the plurality of first plate patterns 121. However, the gate insulating layer 142, the first interlayer insulating layer 143, the second interlayer insulating layer 144 and the passivation layer 145 are patterned into a shape having multiple first plate patterns 121 formed only above the multiple first plate patterns 121.

[0116] A planarization layer 146 is formed on the passivation layer 145. The planarization layer 146 planarizes the upper portions of the switching transistor 150 and the driving transistor 160. The planarization layer 146 can be composed of a single layer or multiple layers and can be formed of an organic material. Therefore, the planarization layer 146 can also be referred to as an organic insulating layer. For example, the planarization layer 146 can be formed of an acrylic-based organic material, but is not limited thereto.

[0117] Reference Figure 3 The planarization layer 146 may be configured to cover the upper and side layers of the buffer layer 141, gate insulating layer 142, first interlayer insulating layer 143, second interlayer insulating layer 144, and passivation layer 145 on a plurality of first board patterns 121. Furthermore, the planarization layer 146, together with the plurality of first board patterns 121, surrounds the buffer layer 141, gate insulating layer 142, first interlayer insulating layer 143, second interlayer insulating layer 144, and passivation layer 145. Specifically, the planarization layer 146 may be configured to cover the top and side surfaces of the passivation layer 145, the side surfaces of the first interlayer insulating layer 143, the second interlayer insulating layer 144, the side surfaces of the gate insulating layer 142, the side surfaces of the buffer layer 141, and a portion of the top surfaces of the plurality of first board patterns 121. Therefore, the planarization layer 146 can compensate for steps on the side surfaces of the buffer layer 141, the gate insulating layer 142, the first interlayer insulating layer 143, the second interlayer insulating layer 144, and the passivation layer 145. Furthermore, the planarization layer 146 can enhance the adhesion strength between the planarization layer 146 and the pixel interconnect lines 181 and 182 disposed on the side surfaces of the planarization layer 146.

[0118] Reference Figure 3 The tilt angle of the side surface of the planarization layer 146 can be smaller than the tilt angle formed by the side surfaces of the buffer layer 141, the gate insulating layer 142, the first interlayer insulating layer 143, the second interlayer insulating layer 144, and the passivation layer 145. For example, the side surface of the planarization layer 146 can have a gentler slope than the slope formed by the side surfaces of the passivation layer 145, the first interlayer insulating layer 143 and the second interlayer insulating layer 144, the gate insulating layer 142, and the buffer layer 141. Therefore, the pixel connection lines 181 and 182, which are configured to contact the side surface of the planarization layer 146, are provided with a gentle slope, so that the stress generated in the pixel connection lines 181 and 182 is reduced when the display device 100 is stretched. In addition, cracks or separation from the side surface of the planarization layer 146 caused in the pixel connection lines 181 and 182 can be suppressed.

[0119] Reference Figures 2 to 4Pixel interconnect lines 181 and 182 refer to wiring that electrically connects pads on a plurality of first board patterns 121. Pixel interconnect lines 181 and 182 are disposed on a plurality of first board patterns 122. Pixel interconnect lines 181 and 182 may extend onto the plurality of first board patterns 121 to electrically connect to strobe pads GP and data pads DP on the plurality of first board patterns 121. (See reference...) Figure 5 In the area between multiple first plate patterns 121, the first line pattern 122 is not set in the area where no pixel connection lines 181 and 182 are set.

[0120] Pixel connection lines 181 and 182 include a first pixel connection line 181 and a second pixel connection line 182. The first pixel connection line 181 and the second pixel connection line 182 are disposed between a plurality of first board patterns 121. Specifically, the first pixel connection line 181 refers to a wiring extending in the X-axis direction between the plurality of first board patterns 121 in pixel connection lines 181 and 182. The second pixel connection line 182 refers to a wiring extending in the Y-axis direction between the plurality of first board patterns 121 in pixel connection lines 181 and 182.

[0121] Pixel connection lines 181 and 182 may be formed from metallic materials such as copper (Cu), aluminum (Al), titanium (Ti) and molybdenum, or from a stacked structure of metallic materials such as copper / molybdenum-titanium (Cu / MoTi) or titanium / aluminum / titanium (Ti / Al / Ti), but are not limited thereto.

[0122] In typical display devices, various wirings, such as multiple gate lines and multiple data lines, extend in a straight line between multiple sub-pixels, and multiple sub-pixels are connected to a single signal line. Therefore, in typical display devices, various wirings, such as gate lines, data lines, high-potential power lines, and reference voltage lines, extend from one side of the organic light-emitting display device to the other without being interrupted on the substrate.

[0123] Conversely, in the display device 100 according to the present disclosure, various wirings, such as gate lines, data lines, high-potential power lines, or reference voltage lines, which are considered to be used in general organic light-emitting display devices, can be provided only on the plurality of first board patterns 121 and the plurality of second board patterns 123. That is, in the display device 100 according to the present disclosure, linear wirings can be provided only on the plurality of first board patterns 121 and the plurality of second board patterns 123.

[0124] In the display device 100 according to an embodiment of the present disclosure, in order to connect discontinuous wiring on a first board pattern 121 or a second board pattern 123, pads on two adjacent first board patterns 121 or two adjacent second board patterns 123 can be connected by pixel connection lines 181 and 182. That is, pixel connection lines 181 and 182 electrically connect gating pads GP or data pads DP on two adjacent first board patterns 121. Therefore, the display device 100 according to an embodiment of the present disclosure may include multiple pixel connection lines 181 and 182 that electrically connect various wirings such as gating lines, data lines, high-potential power lines, and reference voltage lines between multiple first board patterns 121 and multiple second board patterns 123. For example, gating lines may be provided on multiple first board patterns 121 arranged adjacent to each other along the X-axis direction, and gating pads GP may be provided at both ends of the gating lines. In this case, multiple gating pads GP on multiple first board patterns 121 adjacent to each other in the first direction X can be connected to each other by first pixel connection lines 181 serving as gating lines. Therefore, the gate lines provided on the plurality of first plate patterns 121 and the first pixel connection lines 181 provided on the second plate pattern 123 can be used as a single gate line. Furthermore, as described above, among all the various wiring lines included in the display device 100, wiring lines extending in the first direction X (e.g., transmission signal lines, low-potential power lines, and high-potential power lines) can also be electrically connected via the first pixel connection lines 181.

[0125] Reference Figure 2 and Figure 4 The first pixel connection line 181 can connect to two gating pads GPs arranged side-by-side on two of the plurality of adjacent first board patterns 121 arranged in the first direction X. The first pixel connection line 181 can be used as a gating line, a transmit signal line, a high-potential power line, or a low-potential power line, but is not limited thereto. For example, the first pixel connection line 181 can be used as a gating line and electrically connected to the gating pads GPs on two first board patterns 121 arranged side-by-side in the first direction X. Therefore, as described above, the gating pads GPs on the plurality of first board patterns 121 arranged in the first direction X can be connected and transmit a gating voltage through the first pixel connection line 181 used as a gating line.

[0126] In addition, refer to Figure 3The second pixel connection line 182 can connect two data pads DP on two adjacent first board patterns 121 arranged side-by-side in the second direction Y. The second pixel connection line 182 can be used as a data line, a high-potential power line, a low-potential power line, or a reference voltage line, but is not limited thereto. For example, the second pixel connection line 182 can be used as a data line and electrically connected to the data lines on two adjacent first board patterns 121 arranged side-by-side in the second direction Y. Therefore, as described above, the internal lines on the multiple first board patterns 121 arranged in the second direction Y can be connected and transmit a data voltage through multiple second pixel connection lines 182 used as data lines.

[0127] like Figure 4 As shown, the first pixel connection line 181 can be formed to extend to the top surface of the first line pattern 122 while contacting the top and side surfaces of the planarization layer 146 disposed on the first plate pattern 121. Furthermore, as... Figure 3 As shown, the second pixel connection line 182 is formed to extend to the top surface of the first line pattern 122 while contacting the top and side surfaces of the planarization layer 146 disposed on the first plate pattern 121.

[0128] However, as Figure 5 As shown, it is not necessary to set a rigid pattern in the area where the first pixel connection line 181 and the second pixel connection line 182 are not set. Therefore, the first line pattern 122, which is a rigid pattern, is not set below the first pixel connection line 181 and the second pixel connection line 182.

[0129] In addition, refer to Figure 3 A dam 147 is formed on the connecting pads CNT, pixel interconnects 181 and 182, and planarization layer 146. The dam 147 is a component that divides adjacent sub-pixels SPX. The dam 147 is provided to cover at least a portion of the pads PD, pixel interconnects 181 and 182, and planarization layer 146. The dam 147 can be formed of an insulating material. Furthermore, the dam 147 can include a black material. The dam 147 includes a black material to block wiring visible through the display area AA. For example, the dam 147 can be formed of a transparent carbon-based mixture, specifically including carbon black. However, it is not limited to this; the dam 147 can be formed of a transparent insulating material. Furthermore, although in Figure 3 The diagram shows that the height of the embankment 147 is lower than the height of the light-emitting diode 170, but this disclosure is not limited thereto, and the height of the embankment 147 may be equal to the height of the light-emitting diode 170.

[0130] Reference Figure 3A light-emitting diode 170 is disposed on the connection pad CNT and the first pixel connection line 181. The light-emitting diode 170 includes an n-type layer 171, an active layer 172, a p-type layer 173, an n-electrode 174, and a p-electrode 175. The light-emitting diode 170 of the display device 100 according to an embodiment of the present disclosure has a flip-chip structure in which the n-electrode 174 and the p-electrode 175 are formed on one surface.

[0131] An n-type layer 171 can be formed by implanting an n-type impurity into gallium nitride (GaN), which has excellent crystallinity. The n-type layer 171 can be disposed on a separate base substrate formed of a light-emitting material.

[0132] An active layer 172 is disposed on the n-type layer 171. The active layer 172 is a light-emitting layer that emits light in the light-emitting diode 170 and can be formed of a nitride semiconductor (e.g., indium gallium nitride (InGaN)). A p-type layer 173 is disposed on the active layer 172. The p-type layer 173 can be formed by implanting p-type impurities into gallium nitride (GaN).

[0133] As described above, a light-emitting diode 170 according to an embodiment of the present disclosure can be manufactured by sequentially stacking an n-type layer 171, an active layer 172, and a p-type layer 173, and then etching predetermined portions to form an n-electrode 174 and a p-electrode 175. In this case, predetermined portions serving as spaces for separating the n-electrode 174 and the p-electrode 175 from each other can be etched to expose a portion of the n-type layer 171. In other words, the surface of the light-emitting diode 170 on which the n-electrode 174 and the p-electrode 175 are disposed is not a flat surface, but rather has different heights.

[0134] As described above, the n-electrode 174 is disposed in the etched region and is formed of a conductive material. Furthermore, the p-electrode 175 is disposed in the unetched region and is also formed of a conductive material. For example, the n-electrode 174 is disposed on the n-type layer 171 exposed by the etching process, and the p-electrode 175 is disposed on the p-type layer 173. The p-electrode 175 may be formed of the same material as the n-electrode 174.

[0135] An adhesive layer AD is disposed on the top surface of the connection pad CNT and the first pixel connection line 181, and between the connection pad CNT and the first pixel connection line 181, so that the light-emitting diode 170 can be bonded to the connection pad CNT and the first pixel connection line 181. At this time, the n electrode 174 is disposed on the first pixel connection line 181, and the p electrode 175 can be disposed on the connection pad CNT.

[0136] The adhesive layer AD can be a conductive adhesive layer in which conductive spheres are dispersed in an insulating base component. Therefore, when heat or pressure is applied to the adhesive layer AD, the conductive spheres are electrically connected in the portions where heat or pressure is applied to have conductive properties, and the unpressurized areas can have insulating properties. For example, the n-electrode 174 is electrically connected to the first pixel connection line 181 by means of the adhesive layer AD, and the p-electrode 175 is electrically connected to the connection pad CNT by means of the adhesive layer AD. After the adhesive layer AD is applied to the top surfaces of the first pixel connection line 181 and the connection pad CNT by an inkjet method, the light-emitting diode 170 is transferred onto the adhesive layer AD and pressurized and heated. By doing so, the connection pad CNT is electrically connected to the p-electrode, and the first pixel connection line 181 is electrically connected to the n-electrode 174. However, the remaining portions of the adhesive layer AD, except for a portion disposed between the n-electrode 174 and the first pixel connection line 181 and a portion disposed between the p-electrode 175 and the connection pad CNT, have insulating properties. In addition, the adhesive layer AD can be divided into layers respectively disposed on the connecting pad CNT and the first pixel connection line 181.

[0137] Furthermore, the connection pad CNT is electrically connected to the drain electrode 164 of the driving transistor 160 to apply a driving voltage from the driving transistor 160 to drive the light-emitting diode 170. Additionally, a low-potential driving voltage is applied to the first pixel connection line 181 to drive the light-emitting diode 170. Therefore, when the display device 100 is turned on, different voltage levels applied to the connection pad CNT and the first pixel connection line 181 are transmitted to the n-electrode 174 and the p-electrode 175, causing the light-emitting diode 170 to emit light.

[0138] The upper substrate 112 is a substrate that supports various components disposed below the upper substrate 112. Specifically, the upper substrate 112 is formed by coating the lower substrate 111 and the first plate pattern 121 with a material constituting the upper substrate 112, and then curing the material that is in contact with the lower substrate 111, the first plate pattern 121, the first line pattern 122 and the pixel connection lines 181 and 182.

[0139] The upper substrate 112 can be formed of the same material as the lower substrate 111. For example, the upper substrate 112 can be formed of silicone rubber such as polydimethylsiloxane (PDMS) or elastomers such as polyurethane (PU) or polytetrafluoroethylene (PTFE), thus having flexibility. However, the material of the upper substrate 112 is not limited to these.

[0140] Furthermore, even if not in Figure 3As shown, a polarization layer may also be provided on the upper substrate 112. The polarization layer can perform the function of polarizing light incident from the outside of the display device 100 to reduce external light reflection. In addition, optical thin films other than the polarization layer may be provided on the upper substrate 112.

[0141] Furthermore, the filler layer 190 can be disposed on the entire surface of the lower substrate 111 to fill the spaces between components disposed on the upper substrate 112 and the lower substrate 111. The filler layer 190 can be made of a curable adhesive. Specifically, the material constituting the filler layer 190 is coated on the entire surface of the lower substrate 111 and then cured so that the filler layer 190 can be disposed between components disposed on the upper substrate 112 and the lower substrate 111. For example, the filler layer 190 can be an optically clear adhesive (OCA) and can be made of acrylic adhesives, silicone adhesives, and urethane adhesives.

[0142] Display area circuit structure

[0143] Figure 6 This is a circuit diagram of a sub-pixel of a display device according to an embodiment of the present disclosure.

[0144] In the following description, for ease of description, the structure and operation of the sub-pixel SPX of the display device according to an embodiment of the present disclosure will be described when it is a pixel circuit having 2T (transistors) and 1C (capacitors), but the present disclosure is not limited thereto.

[0145] Reference Figure 3 and Figure 6 According to embodiments of the present disclosure, the sub-pixel SPX of the display device can be configured to include a switching transistor 150, a driving transistor 160, a storage capacitor C, and a light-emitting diode 170.

[0146] The switching transistor 150 applies the data signal DATA provided through the second pixel connection line 182 to the driving transistor 160 and the storage capacitor C according to the strobe signal SCAN provided through the first pixel connection line 181.

[0147] In addition, the gate electrode 151 of the switching transistor 150 is electrically connected to the first pixel connection line 181, the source electrode 153 of the switching transistor 150 is connected to the second pixel connection line 182, and the drain electrode 154 of the switching transistor 150 is connected to the gate electrode 161 of the driving transistor 160.

[0148] The driving transistor 160 is operable to allow a driving current to flow in response to the data voltage DATA stored in the storage capacitor C, based on the high potential voltage VDD provided through the first pixel connection line 181 and the data voltage DATA.

[0149] In addition, the gate electrode 161 of the driving transistor 160 is electrically connected to the drain electrode 154 of the switching transistor 150, the source electrode of the driving transistor 160 is connected to the first pixel connection line 181, and the drain electrode 164 of the driving transistor 160 is connected to the light-emitting diode 170.

[0150] The light-emitting diode 170 can emit light according to the driving current generated by the driving transistor 160. Furthermore, as described above, the n-electrode 174 of the light-emitting diode 170 is connected to the first pixel connection line 181 to be applied a low-potential voltage VSS. The p-electrode 175 of the light-emitting diode 170 is connected to the drain electrode 164 of the driving transistor 160 to apply a driving voltage corresponding to the driving current.

[0151] As described above, the sub-pixel SPX of the display device according to embodiments of the present disclosure is configured with a 2T1C structure including a switching transistor 150, a driving transistor 160, a storage capacitor C, and a light-emitting diode 170. However, when a compensation circuit is added, the sub-pixel can be configured in various ways such as 3T1C, 4T2C, 5T2C, 6T1C, 6T2C, 7T1C, or 7T2C.

[0152] As described above, the display device according to the present disclosure includes a plurality of sub-pixels on a first substrate, which is a rigid substrate, and each of the plurality of sub-pixels SPX includes a switching transistor, a driving transistor, a storage capacitor, and a light-emitting diode.

[0153] Therefore, the display device according to the embodiments of the present disclosure can not only be stretched by the lower substrate, but can also include pixel circuits having a 2T1C structure on each first substrate to emit light according to the data voltage according to each gating timing.

[0154] Pattern layer in non-display areas

[0155] Figure 7 This is an enlarged plan view of the non-display area of ​​a display device according to an embodiment of the present disclosure.

[0156] Specifically, Figure 7 yes Figure 1 An enlarged plan view of region B is shown. For reference, in Figure 7 In the middle, the thin wavy line indicates that only the second line pattern is set, and the thick wavy line indicates that it is set on the second line pattern as a buffer line, gate connection line or power line of the second connection line.

[0157] like Figure 7As shown, the non-display area NA includes a first area A1 located outside the display area AA, a second area A2 located outside the first area A1, and a third area A3 located outside the second area A2. For example, the non-display area NA includes a first area A1 adjacent to the display area AA, a second area A2 adjacent to the first area A1, and a third area A3 adjacent to the second area A2. The second area A2 is located between the first area A1 and the third area A3.

[0158] Anchor hole AH is located in the first region A1, gating driver GD is located in the second region A2, and power block (PB) constituting power supply PS is located in the third region A3.

[0159] The first region A1, the second region A2, and the third region A3 are sequentially arranged outside the display region AA relative to the first direction X. Therefore, the anchor hole AH, the gating driver GD, and the power supply PS are sequentially arranged in the region adjacent to the display region AA relative to the first direction X.

[0160] The multiple second board patterns 123 forming the gate driver GD and the power supply PS can be disposed in the non-display area NA. A second line pattern 124 is disposed connecting the adjacent first board patterns 121 and second board patterns 123, and also connecting the multiple adjacent second board patterns 123. The second line pattern 124 can be referred to as a second connection pattern. For example, the second line pattern 124 can be disposed between the adjacent first board patterns 121 and second board patterns 123, and the second line pattern 124 can be disposed between the multiple adjacent second board patterns 123.

[0161] Specifically, the plurality of second board patterns 123 disposed in the non-display area NA include a plurality of first sub-board patterns 123a located in the first area A1, a plurality of second sub-board patterns 123b located in the second area A2, and a plurality of third sub-board patterns 123c located in the third area A3. Anchor holes AH are provided in the plurality of first sub-board patterns 123a, a gating driver GD is provided in the plurality of second sub-board patterns 123b, and a power supply PS is provided in the plurality of third sub-board patterns 123c.

[0162] More specifically, on one side of the non-display area NA, a plurality of first sub-board patterns 123a are arranged in a column along the second direction Y in the first area A1, and a plurality of second sub-board patterns 123b are arranged in a column along the second direction Y in the second area A2. A plurality of third sub-board patterns 123c are arranged in multiple columns along the second direction Y in the third area A3.

[0163] For example, a plurality of first sub-board patterns 123a are disposed in a first region A1 and spaced apart from each other only in the second direction Y, and a plurality of second sub-board patterns 123b are disposed in a second region A2 and spaced apart from each other only in the second direction Y. Furthermore, a plurality of third sub-board patterns 123c are disposed in a third region A3 and may be spaced apart from each other in the first direction X and the second direction Y.

[0164] The dimensions of the plurality of first sub-board patterns 123a can be smaller than the dimensions of the plurality of second sub-board patterns 123b. Specifically, the dimensions of each of the plurality of first sub-board patterns 123a can be smaller than the dimensions of each of the plurality of second sub-board patterns 123b. As described above, anchor holes AH can be provided in each of the plurality of first sub-board patterns 123a. The area of ​​the anchor holes AH provided in the plurality of first sub-board patterns 123a can be smaller than the area of ​​the gating driver GD provided in the plurality of second sub-board patterns 123b.

[0165] The plurality of second line patterns 124 disposed in the non-display area NA include a first sub-line pattern 124a disposed in the first area A1, a second sub-line pattern 124b disposed in the second area A2, and a third sub-line pattern 124c disposed in the third area A3.

[0166] The first sub-line pattern 124a can connect the first board pattern 121 disposed in the display area AA and the first sub-board pattern 123a disposed in the second board pattern 123 disposed in the non-display area NA. In addition, the first sub-line pattern 124a connects the first sub-board pattern 123a and the second sub-board pattern 123b disposed in the non-display area NA.

[0167] More specifically, the first sub-line pattern 124a may include a first-1 sub-line pattern 124a-1 and a first-2 sub-line pattern 124a-2. The first-1 sub-line pattern 124a-1 extends in the first direction X, connecting the first plate pattern 121 and the first sub-plate pattern 123a, and may also connect the first sub-plate pattern 123a and the second sub-plate pattern 123b. Furthermore, the first-2 sub-line pattern 124a-2 extends from the first-1 sub-line pattern 124a-1 and in the second direction Y, and may connect multiple first sub-plate patterns 123a.

[0168] The second sub-line pattern 124b extends in the second direction Y and connects to multiple second sub-board patterns 123b.

[0169] Furthermore, the third sub-line pattern 124c includes a 3-1 sub-line pattern 124c-1 and a 3-2 sub-line pattern 124c-2. The 3-1 sub-line pattern 124c-1 extends in the first direction X and can be connected to the third sub-board patterns 123c spaced apart in the first direction X. Furthermore, the 3-2 sub-line pattern 124c-2 extends in the second direction Y and can be connected to a plurality of third sub-board patterns 123c spaced apart in the second direction Y.

[0170] Furthermore, multiple gating connection lines 184 are disposed on a second sub-line pattern 124b disposed in the second region A2 to electrically connect multiple gating drivers GD. That is, a gating drive voltage and a gating clock voltage are applied to the multiple gating connection lines 184 disposed on the second sub-line pattern 124b to allow each of the multiple gating drivers GD to output a gating voltage. However, although in Figure 7 The diagram shows that the gate connection line 184 is provided in only some of the plurality of second sub-line patterns 124b, but this disclosure is not limited thereto, and the gate connection line 184 may be provided in all of the plurality of second sub-line patterns 124b.

[0171] Furthermore, the gate connection lines 184 formed on the second sub-line pattern 124b can have the same shape as the second sub-line pattern 124b. Specifically, the multiple gate connection lines 184 can have a wavy shape. For example, the multiple gate connection lines 184 can each have a sinusoidal shape. However, the shape of the multiple gate connection lines 184 is not limited to this, and for example, the multiple gate connection lines 184 can extend in a zigzag pattern, or can be formed into various shapes such as those extending by connecting multiple rhomboid substrates at the vertices. Furthermore, Figure 8 The number and shape of the multiple strobe lines 184 shown are exemplary, and the number and shape of the multiple strobe lines 184 can be varied according to the design.

[0172] However, in Figure 7 In this configuration, the gate connection line 184 is not provided on all second sub-line patterns 124b, but rather second sub-line patterns 124b on which the gate connection line 184 is not provided may exist. The second sub-line patterns 124b on which the gate connection line 184 is not provided may be additionally provided to ensure rigidity for tension in the second direction Y.

[0173] Configuration of the first region

[0174] Figure 8 This is an enlarged plan view of the first region of a display device according to an embodiment of the present disclosure.

[0175] Figure 9 It is along Figure 8 The cross-sectional view taken from line IX-IX'.

[0176] like Figure 8 As shown, a buffer line 183 connecting a gating driver GD and multiple pixels PX is provided in the first region A1. Furthermore, an anchoring hole AH for fixing the buffer line 183 can be provided in the first region A1. For example, the buffer line 183 is provided on a first sub-line pattern 124a connecting the first board pattern 121 and the first sub-board pattern 123a, to connect the gating driver GD provided in the first sub-board pattern 123a and the pixels PX provided in the first board pattern 121.

[0177] In addition, refer to Figure 8 The width at both ends of the first-1 sub-line pattern 124a-1 located between the first plate pattern 121 and the first sub-plate pattern 123a can be greater than the width of the central region of the first-1 sub-line pattern 124a-1. Furthermore, the width at both ends of the first-1 sub-line pattern 124a-1 located between the first sub-plate pattern 123a and the second sub-plate pattern 123b can be greater than the width of the central region of the first-1 sub-line pattern 124a-1.

[0178] Therefore, in the buffer line 183 formed on the first-1 pattern 124a-1, the width of the buffer line 183 provided in the area overlapping with the first plate pattern 121, the first sub-plate pattern 123a or the second sub-plate pattern 123b can be greater than the width of the buffer line 183 provided in the area overlapping with the first-1 sub-line pattern 124a-1.

[0179] In other words, the central region of the buffer line 183 is relatively thin, allowing it to be stretched with a smaller force. This improves the tensile strength of the buffer line 183. Furthermore, because the ends of the buffer line 183 are relatively thick, the contact area between the buffer line 183 and the first plate pattern 121, the first sub-plate pattern 123a, or the second sub-plate pattern 123b to be fixed can be increased. Therefore, even if the buffer line 183 is repeatedly stretched, it will not separate from the first plate pattern 121, the first sub-plate pattern 123a, or the second sub-plate pattern 123b. This improves the tensile reliability of the buffer line 183.

[0180] Each buffer line 183 extends in the first direction X to connect the gating driver GD and multiple pixels PX, and multiple buffer lines 183 are arranged in the second direction Y.

[0181] Furthermore, multiple buffer lines 183 are provided on the first sub-plate pattern 123a and the first sub-line pattern 124a. Specifically, the first sub-line pattern 124a is composed of a first-1 sub-line pattern 124a-1 extending in the first direction X and a first-2 sub-line pattern 124a-2 extending in the second direction Y, but the buffer lines 183 extend only in the first direction X. Therefore, the buffer lines 183 are provided on the first sub-plate pattern 123a and the first-1 sub-line pattern 124a-1. Furthermore, the buffer lines 183 may not be formed on the first-2 sub-line pattern 124a-2. Furthermore, the buffer lines 183 formed on the first-1 sub-line pattern 124a-1 may have the same shape as the first-1 sub-line pattern 124a-1. Specifically, each of the multiple buffer lines 183 has a wavy shape. For example, the multiple buffer lines 183 may have a sinusoidal shape. However, the shape of the multiple buffer lines 183 is not limited to this. For example, multiple buffer lines 183 can extend in a zigzag pattern, or can be formed in various shapes (e.g., a shape that extends by connecting multiple rhomboid substrates at the vertices). Furthermore, Figure 8 The number and shape of the multiple buffer lines 183 shown are exemplary, and the number and shape of the multiple buffer lines 183 can be varied according to the design.

[0182] Furthermore, the buffer line 183 formed on the first sub-plate pattern 123a can be a straight line extending in the first direction X. However, the shape of the buffer line 183 formed on the first sub-plate pattern 123a is not limited to this, and can have a wavy shape as described above. The width of the buffer line 183 formed on the first sub-plate pattern 123a can be greater than the width of the buffer line 183 formed on the 1-1 sub-plate pattern 124a-1. (Refer to...) Figure 8 The width of the first-1 sub-line pattern 124a-1 can vary. For example, the width of the first-1 sub-line pattern 124a-1 located in the region adjacent to the first sub-plate pattern 123a or the first plate pattern 121 can be greater than the width of the waveform region of the first-1 sub-line pattern 124a-1.

[0183] Therefore, some of the buffer lines 183 have a wavy shape, allowing the first region A1 of the non-display area NA to be stretched in the first direction X. Furthermore, the other buffer lines 183 have a linear shape, thereby reducing the resistance of the buffer lines 183. Therefore, the delay of the gating voltage transmitted by the buffer lines 183 can be reduced or minimized.

[0184] In addition, multiple anchor holes AH are formed on the first sub-board pattern 123a to allow multiple buffer lines 183 to contact the metal pattern MT (or conductive pattern MT) disposed on different layers.

[0185] like Figure 8As shown, the plurality of anchor holes AH can be formed to overlap with the buffer line 183 formed on the first sub-plate pattern 123a. Specifically, the buffer line 183 formed on the first sub-plate pattern 123a extends in the first direction X, such that the plurality of anchor holes AH can be arranged along the buffer line 183 formed on the first sub-plate pattern 123a in the first direction X.

[0186] For example, multiple buffer lines 183 extending in the first direction X are arranged on the first sub-plate pattern 123a in a manner that they are spaced apart from each other in the second direction Y, such that multiple anchoring holes AH provided in the first direction X can be arranged in a manner that they are spaced apart from each other in the second direction Y.

[0187] In addition, refer to Figure 9 Multiple buffer lines 183 can directly contact another metal pattern MT through multiple anchor holes AH.

[0188] The buffer layer 141, gate insulating layer 142, first interlayer insulating layer 143, second interlayer insulating layer 144, passivation layer 145, and planarization layer 146, which are inorganic insulating layers, can be disposed on the first sub-board pattern 123a disposed on the lower substrate 111.

[0189] Furthermore, a buffer line 183 is disposed on a planarization layer 146, and a metal pattern MT can be disposed between a buffer layer 141, a gate insulating layer 142, a first interlayer insulating layer 143, a second interlayer insulating layer 144, and a passivation layer 145, which serve as inorganic insulating layers.

[0190] For example, in Figure 9 In this configuration, the metal pattern MT can be formed of the same material as the source and drain electrodes of the transistor disposed between the second interlayer insulating layer 144 and the passivation layer 145. In other words, the metal pattern MT can be formed of the same material as the source and drain electrodes of the transistor, which are located on the same layer.

[0191] However, the metal pattern MT is not limited to this, and the metal pattern MT can be formed of the same material as the intermediate metal layer disposed between the first interlayer insulating layer 143 and the second interlayer insulating layer 144. Alternatively, the metal pattern MT can be formed of the same material as the gate electrode of the transistor disposed between the gate insulating layer 142 and the first interlayer insulating layer 143.

[0192] In addition, the filler layer 190 and the upper substrate 112 can be sequentially disposed on the buffer line 183 and the planarization layer.

[0193] As described above, the display device according to embodiments of the present disclosure may include an anchoring hole AH for fixing the buffer line 183. Therefore, even if the display device is repeatedly stretched, the buffer line 183 will not separate from the lower component. Furthermore, the buffer line 183 is fixed to the first sub-plate pattern 123a by means of the anchoring hole AH, thereby reducing the area of ​​flexible movement of the buffer line 183. Therefore, the tensile stress applied to the buffer line 183 can be reliably reduced. As a result, by forming the anchoring hole AH in the display device according to embodiments of the present disclosure, the tensile reliability of the display device can be stably ensured.

[0194] Furthermore, when manufacturing a display device, components are disposed on a lower substrate and peeled off, and then a filler layer and an upper substrate are bonded together. As described above, when components disposed on the lower substrate are peeled off, there is a problem that the buffer lines of the components disposed on the lower substrate are torn off. Therefore, in the display device according to the present disclosure, the buffer lines are fixed by anchor holes, so that the display device is not damaged during peeling. As a result, the display device according to the embodiment of the present disclosure can also achieve process stability.

[0195] Configuration of the third area

[0196] Figure 10 This is an enlarged plan view of the third region of a display device according to an embodiment of the present disclosure.

[0197] Figure 11 It is along Figure 10 The cross-sectional view taken from line XI-XI'.

[0198] like Figure 10 As shown, in the third region A3, there are multiple power blocks PB that constitute the power supply PS and power lines 185 that connect the multiple power blocks PB.

[0199] Multiple power blocks PB are formed on multiple third sub-board patterns 123c spaced apart from each other. As described above, the third sub-board patterns 123c can be formed by island shapes spaced apart from each other in the first direction X and the second direction Y. Therefore, the multiple power blocks PB can also be configured to have island shapes spaced apart from each other in the first direction X and the second direction Y.

[0200] Despite Figure 10 The present invention has shown multiple power blocks PB arranged in a 4×2 matrix within multiple third sub-board patterns 123c arranged in a 4×2 matrix, but the present disclosure is not limited thereto, and the multiple power blocks PB can be arranged in various forms. For example, not only can one power block PB be arranged in one third sub-board pattern 123c, but multiple power blocks PB can also be arranged in a matrix.

[0201] In addition, such as Figure 11 As shown, each of the multiple power blocks PB may include multiple power patterns PP disposed on different layers. Specifically, the multiple power blocks PB may include a first power pattern PP1 and a second power pattern PP2 disposed on different layers.

[0202] The buffer layer 141, gate insulating layer 142, first interlayer insulating layer 143, second interlayer insulating layer 144, passivation layer 145, and planarization layer 146, which are inorganic insulating layers, can be disposed on the third sub-board pattern 123c disposed on the lower substrate 111.

[0203] Furthermore, the first electrical pattern PP1 can be disposed between the buffer layer 141, the gate insulating layer 142, the first interlayer insulating layer 143, the second interlayer insulating layer 144, and the passivation layer 145, which serve as inorganic insulating layers. Furthermore, the second electrical pattern PP2 can be disposed on the planarization layer 146.

[0204] For example, in Figure 11 In this process, the first electrical pattern PP1 can be formed of the same material as the source and drain electrodes of the transistor disposed between the second interlayer insulating layer 144 and the passivation layer 145. That is, the first electrical pattern PP1 can be formed of the same material as the source and drain electrodes of the transistor on the same layer.

[0205] However, the first electrical pattern PP1 is not limited thereto, and the first electrical pattern PP1 may be formed of the same material as the intermediate metal layer disposed between the first interlayer insulating layer 143 and the second interlayer insulating layer 144. Alternatively, the first electrical pattern PP1 may be formed of the same material as the gate electrode of the transistor disposed between the gate insulating layer 142 and the first interlayer insulating layer 143.

[0206] However, despite Figure 11 The diagram shows a power block PB configured using only two power patterns PP1 and PP2, but this disclosure is not limited thereto, and the power block PB can be configured by three or more power pattern layers disposed on different layers of the power block PB.

[0207] In addition, the filler layer 190 and the upper substrate 112 can be sequentially disposed on the second electrical pattern PP2 and the planarization layer.

[0208] Multiple power lines 185 connect multiple power blocks PB arranged in an island-like configuration. Therefore, the multiple power lines 185 include a first power line 185a extending in a first direction X and a second power line 185b extending in a second direction Y.

[0209] Multiple first power lines 185a extending in the first direction X are provided on the third-1st sub-line pattern 124c-1 extending in the first direction X, and multiple second power lines 185b extending in the second direction Y are provided on the third-2nd sub-line pattern 124c-2 extending in the second direction Y.

[0210] Furthermore, the first electric field line 185a formed on the 3-1 sub-line pattern 124c-1 can have the same shape as the 3-1 sub-line pattern 124c-1, and the second electric field line 185b formed on the 3-2 sub-line pattern 124c-2 can have the same shape as the 3-2 sub-line pattern 124c-2. Specifically, the plurality of first electric field lines 185a and the plurality of second electric field lines 185b have a wavy shape. For example, the plurality of first electric field lines 185a and the plurality of second electric field lines 185b have a sinusoidal shape. However, the shape of the plurality of first electric field lines 185a and the plurality of second electric field lines 185b is not limited thereto. For example, the plurality of first electric field lines 185a and the plurality of second electric field lines 185b can extend in a zigzag pattern, or can be formed in various shapes (e.g., a shape that extends by connecting multiple rhomboid substrates at the vertices). Furthermore, in Figure 10 The diagram shows six first power lines 185a forming a group and electrically connected to a plurality of adjacent power blocks PB in a first direction X, and three second power lines 185b forming a group and electrically connected to a plurality of adjacent power blocks PB in a second direction Y. However, the number and shape of the multiple first power lines 185a and multiple second power lines 185b shown are illustrative, and the number and shape of the multiple first power lines 185a and multiple second power lines 185b can vary according to the design.

[0211] In addition, such as Figure 11 As shown, each of the plurality of first power lines 185a and the plurality of second power lines 185b may include multiple power line layers disposed on different layers. Specifically, the plurality of first power lines 185a may include a first-1 power line and a first-2 power line disposed on different layers. The plurality of second power lines 185b may include a second-1 power line 185b-1 and a second-2 power line 185b-2 disposed on different layers.

[0212] Figure 11 This is a cross-sectional view of the second electric field line 185b, which will describe the sandwich structure of the second electric field line 185b.

[0213] The second-first power line 185b-1 is disposed on the third-second sub-line pattern 124c-2 disposed on the lower substrate 111. A passivation layer 145 and a planarization layer 146 are disposed on the second-first power line 185b-1, and the second-second power line 185b-2 is disposed on the planarization layer 146.

[0214] The second-1 power line 185b-1 may be made of the same material as the first power pattern PP1, and the second-2 power line 185b-2 may be made of the same material as the second power pattern PP2.

[0215] For example, in Figure 11 In this embodiment, the second-first power line 185b-1 can be formed of the same material as the source and drain electrodes of the transistor. However, the second-first power line 185b-1 is not limited to this, and it can also be formed of the same material as the intermediate metal layer disposed between the first interlayer insulating layer 143 and the second interlayer insulating layer 144. Alternatively, the second-first power line 185b-1 can be formed of the same material as the gate electrode of the transistor disposed between the gate insulating layer 142 and the first interlayer insulating layer 143.

[0216] However, despite Figure 11 The second power line 185b is shown to be configured with only two power line layers 185b-1 and 185b-2, but this disclosure is not limited thereto and may be configured with three or more power line layers disposed on different layers of the second power line 185b.

[0217] The interlayer structure of the first electric field line 185a is the same as that of the second electric field line 185b.

[0218] Specifically, the first-1 power line can be disposed on the third-1 sub-line pattern 124c-1 disposed on the lower substrate 111. In addition, a passivation layer 145 and a planarization layer 146 are disposed on the first-1 power line, and a first-2 power line is disposed on the planarization layer 146.

[0219] The first-1 electric line can be made of the same material as the first electric pattern PP1, and the second-2 electric line can be made of the same material as the second electric pattern PP2.

[0220] Although the first power line 185a is shown to be configured with only two power line layers, this disclosure is not limited thereto and may be configured with three or more power line layers arranged on different layers of the first power line 185a.

[0221] As described above, the first-1 power line and the second-1 power line 185b-1 are made of the same material as the first power pattern PP1, such that the first-1 power line, the second-1 power line 185b-1, and the first power pattern PP1 can be electrically connected to each other. Therefore, a low-potential driving voltage can be applied to the plurality of first power patterns PP1 disposed on one side by means of the connecting lines. The low-potential driving voltage is stored in the first power pattern PP1 disposed on the other side by means of the first-1 power line and the second-1 power line 185b-1, and is provided to the plurality of pixels by means of the first-1 power line and the second-1 power line 185b-1.

[0222] The first-second and second-second power lines 185b-2 are made of the same material as the second power pattern PP2, allowing them to be electrically connected to each other. Therefore, a high-potential driving voltage can be applied to multiple second power patterns PP2 disposed on one side by means of connecting lines. The high-potential driving voltage is stored in the second power pattern PP2 located on the other side via the first-second and second-second power lines 185b-2, and is provided to multiple pixels via the first-second and second-second power lines 185b-2.

[0223] In other words, as described above, a high-potential driving voltage is provided to the pixel by means of the first-2 power line, the second-2 power line 185b-2, and the second power pattern PP2, which are components on the upper layer of the power supply PS. Furthermore, a low-potential driving voltage is provided to the pixel by means of the first-1 power line, the second-1 power line 185b-1, and the first power pattern PP1, which are components on the lower layer of the power supply PS.

[0224] However, this disclosure is not limited thereto. Therefore, a high-potential driving voltage can be provided by means of a link line to a component in one of the regions of the first-2 power lines, the second-2 power lines 185b-2, and the second power pattern PP2, which are disposed on the upper layer relative to the power supply PS. Furthermore, a low-potential driving voltage is provided by means of a link line to components disposed in other regions of the first-2 power lines, the second-2 power lines 185b-2, and the second power pattern PP2. The second power pattern PP2 disposed in the other regions is electrically connected via a contact hole to the first power pattern PP1 disposed on the lower layer relative to the PS. Therefore, a low-potential driving voltage is stored in the first-1 power line, the second-1 power line 185b-1, and the first power pattern PP1, so that a low-potential driving voltage can be provided to the pixel by means of the first-1 power line, the second-1 power line 185b-1, and the first power pattern PP1.

[0225] For example, such as Figure 10As shown, when the power block PB is set as a 4×2 matrix, the second power pattern PP2 of the power block PB, which is set in a 2×2 matrix inside the third region A3, is applied with a high-potential driving voltage from the link line, so as to apply the high-potential driving voltage to the pixel by means of the power line 185.

[0226] Furthermore, a low-potential driving voltage from a link line is applied to the second power pattern PP2 of the power block PB in the 2×2 matrix located on the outer side of the third region A3. Additionally, the low-potential driving voltage is transmitted to the first power pattern PP1 of the power block PB in the 4×2 matrix located on the third region A3 via a contact hole. Furthermore, the low-potential driving voltage can be applied to the pixel via a power line 185 connected to the first power pattern PP1.

[0227] In the above description, a high-potential driving voltage is applied to the power block PB in the 2×2 matrix located inside the third region A3, and a low-potential driving voltage is applied to the power block PB in the 2×2 matrix located outside the third region A3. Therefore, the power blocks PB in the 2×2 matrix located inside the third region A3 and the power blocks PB in the 2×2 matrix located outside the third region A3 should not be electrically connected. Therefore, the power line 185 may not be provided between the power blocks PB in the 2×2 matrix located inside the third region A3 and the power blocks PB in the 2×2 matrix located outside the third region A3.

[0228] As described above, in the display device according to embodiments of the present disclosure, the power supply PS can be formed on a plurality of third sub-board patterns 123c spaced apart from each other in an island-like manner. That is, the power supply PS includes power blocks PB spaced apart from each other in a biaxial direction and power lines 185 connecting them, such that the power supply PS itself can be stretched not only in the first direction X but also in the second direction Y. Therefore, the non-display area NA of the display device according to embodiments of the present disclosure is also biaxially stretched. Therefore, the applicability of the stretchable display device is expanded, thereby improving its suitability. Furthermore, the stretching direction of the stretchable display device is expanded, so that the tensile stress applied in one direction can be significantly reduced. Therefore, the stretchability of the display device according to embodiments of the present disclosure can be improved. Furthermore, different voltages are applied to the upper and lower layers of the power supply of the display device, so that various types of driving voltages can be applied in the power-constrained space. Furthermore, multiple power lines of the power supply are connected in parallel to reduce or minimize the driving voltage drop to be transmitted.

[0229] Another embodiment of this disclosure - additional power block

[0230] Hereinafter, a display device 200 according to another embodiment of the present disclosure will be described in detail. Compared with the display device 100 according to an embodiment of the present disclosure, the display device 200 according to another embodiment of the present disclosure has the difference of having an additional power block disposed in the third region. Therefore, repeated descriptions of the display device according to another embodiment of the present disclosure and the display device according to one embodiment of the present disclosure will be omitted, and the above-mentioned differences will be described in detail.

[0231] Figure 12 This is an enlarged plan view of the third region of a display device according to another embodiment of the present disclosure.

[0232] Figure 13 It is along Figure 12 The cross-sectional view taken from line XIII-XIII'.

[0233] According to another embodiment of the present disclosure, the display device 200 further includes a plurality of additional power blocks APB (or a plurality of supplementary power blocks APB) disposed on the fourth sub-board pattern 123d (or the fourth sub-board structure 123d) and additional power lines 186 connecting the additional power blocks APB.

[0234] like Figure 12 As shown, in a third region of the non-display area of ​​a display device 200 according to another embodiment of the present disclosure, a plurality of power blocks PB configured with a power supply PS and power lines 185 connecting the plurality of power blocks PB are provided. Furthermore, a plurality of additional power blocks APB and additional power lines 186 connecting the additional power blocks APB may be provided. In some embodiments, the plurality of additional power blocks APB and the additional power lines 186 are also part of the power supply circuit PS.

[0235] Multiple additional power blocks (APBs) are formed on multiple fourth sub-board patterns 123d spaced apart from each other. As described above, the fourth sub-board patterns 123d can be arranged between multiple third sub-board patterns 123c in the third direction Z and Z'. Furthermore, the fourth sub-board patterns 123d can also be arranged in an island-like form spaced apart from each other in the first direction X and the second direction Y. Therefore, the multiple additional power blocks (APBs) can also be arranged in an island-like form spaced apart from each other in the first direction X and the second direction Y.

[0236] In other words, refer to Figure 12 Multiple additional power blocks APB are set between multiple power blocks PB on the third-party directions Z and Z', or between multiple first power lines 185a, or between multiple second power lines 185b.

[0237] The aforementioned fourth sub-board pattern 123d is a component of the second board pattern, such that the fourth sub-board pattern 123d can be a quadrilateral rigid pattern.

[0238] Despite Figure 12 In the illustration, an additional power block APB is shown for each fourth sub-board pattern 123d; however, this disclosure is not limited to this, and the placement type of the additional power blocks APB can vary in various forms. For example, not only can one additional power block APB be set in a fourth sub-board pattern 123d, but multiple additional power blocks APB can also be set in a matrix.

[0239] Reference Figure 13 Each of the plurality of additional power blocks (APBs) may include a plurality of additional power patterns APP1 and APP2 disposed on different layers. Specifically, the plurality of additional power blocks (APBs) may include a first additional power pattern APP1 and a second additional power pattern APP2 disposed on different layers.

[0240] The first additional electrical pattern APP1 can be formed of the same material on the same layer as the first electrical pattern PP1, and the second additional electrical pattern APP2 can be formed of the same material on the same layer as the second electrical pattern PP2.

[0241] The first additional electrical pattern APP1 can be disposed between the buffer layer 141, the gate insulating layer 142, the first interlayer insulating layer 143, the second interlayer insulating layer 144, and the passivation layer 145, which serve as inorganic insulating layers. The second additional electrical pattern APP2 is disposed on the planarization layer 146.

[0242] For example, the first additional electrical pattern APP1 can be formed of the same material as the source and drain electrodes of the transistor disposed between the second interlayer insulating layer 144 and the passivation layer 145. That is, the first additional electrical pattern APP1 can be formed of the same material as the source and drain electrodes of the transistor on the same layer.

[0243] However, the first additional electrical pattern APP1 is not limited thereto, and the first electrical pattern PP1 may be formed of the same material as the intermediate metal layer disposed between the first interlayer insulating layer 143 and the second interlayer insulating layer 144. Alternatively, the first additional electrical pattern APP1 may be formed of the same material as the gate electrode of the transistor disposed between the gate insulating layer 142 and the first interlayer insulating layer 143.

[0244] However, despite Figure 13 The illustration shows an additional power block APB configured with only two additional power patterns PP1 and PP2, but this disclosure is not limited thereto. Therefore, the additional power block APB can be configured with three or more additional power pattern layers disposed on different layers of the additional power block APB.

[0245] In addition, multiple additional power lines 186 connect power block PB and additional power block APB. Power block PB and additional power block APB are spaced apart from each other in the third direction Z and Z', so that the multiple additional power lines 186 connecting power block PB and additional power block APB can extend in the third direction Z and Z'.

[0246] Furthermore, each of the multiple additional power lines 186 extending from the third party to Z and Z' can be set on multiple fourth sub-line patterns 124d extending from the third party to Z and Z'.

[0247] Furthermore, the shapes of the plurality of additional electric field lines 186 can be the same as the shapes of the plurality of fourth sub-line patterns 124d. Specifically, each of the plurality of fourth sub-line patterns 124d and the plurality of additional electric field lines 186 has a wavy shape. For example, each of the plurality of fourth sub-line patterns 124d and the plurality of additional electric field lines 186 has a sinusoidal shape. However, the shapes of each of the plurality of fourth sub-line patterns 124d and the plurality of additional electric field lines 186 are not limited thereto. For example, each of the plurality of fourth sub-line patterns 124d and the plurality of additional electric field lines 186 can extend in a zigzag pattern, or can be formed in various shapes (e.g., shapes that extend by connecting a plurality of rhomboid substrates at the vertices).

[0248] like Figure 13 As shown, each of the multiple additional power lines 186 may include multiple power line layers disposed on different layers. Specifically, the multiple additional power lines 186 may include a first additional power line 186-1 and a second additional power line 186-2 disposed on different layers.

[0249] The first additional power line 186-1 is disposed on the fourth sub-line pattern 124d disposed on the lower substrate 111, and the passivation layer 145 and the planarization layer 146 are disposed on the first additional power line 186-1, so that the second additional power line 186-2 is disposed on the planarization layer 146.

[0250] The first additional power line 186-1 is made of the same material as the first additional power pattern APP1 and the first power pattern PP1, and the second additional power line 186-2 is made of the same material as the first additional power pattern APP1 and the second power pattern PP2.

[0251] For example, in Figure 13In this embodiment, the first additional power line 186-1 may be formed of the same material as the source and drain electrodes of the transistor. However, the first additional power line 186-1 is not limited thereto, and may be formed of the same material as the intermediate metal layer disposed between the first interlayer insulating layer 143 and the second interlayer insulating layer 144. Alternatively, the first additional power line 186-1 may be formed of the same material as the gate electrode of the transistor disposed between the gate insulating layer 142 and the first interlayer insulating layer 143.

[0252] However, despite Figure 13 The illustration shows that the supplementary power line 186 is configured with only two supplementary power line layers 186-1 and 186-2, but this disclosure is not limited thereto. Therefore, the supplementary power line 186 can be configured with three or more supplementary power line layers arranged on different layers.

[0253] In a display device according to another embodiment of the present disclosure, the component of the power supply PS disposed on the upper layer may include not only the first-2 power lines, the second-2 power lines 185b-2, and the second power pattern PP2, but also the second additional power pattern APP2 and the second additional power line 186-2. That is, according to another embodiment of the present disclosure, the second additional power pattern APP2 and the second additional power line 186-2 are also included, thereby increasing the area of ​​the component storing the high-potential voltage. In other words, according to another embodiment of the present disclosure, the power supply reduces or minimizes the resistance of the component storing the high-potential voltage to reduce or minimize the voltage drop of the high-potential voltage.

[0254] Furthermore, the components of the power supply PS disposed on a relatively low layer may include not only the first-1 power line, the second-1 power line 185b-1, and the first power pattern PP1, but also the first additional power pattern APP1 and the first additional power line 186-1. That is, according to another embodiment of this disclosure, it also includes the first additional power pattern APP1 and the second additional power line 186-1, thereby increasing the area of ​​the component storing the low-potential voltage. In other words, according to another embodiment of this disclosure, the power supply reduces or minimizes the resistance of the component storing the low-potential voltage to reduce or minimize the voltage drop of the low-potential voltage.

[0255] In other words, in a display device according to another embodiment of the present disclosure, the power supply includes an additional power block to reduce or minimize the drive voltage drop. Therefore, a uniform voltage is applied to all pixels of the display device according to another embodiment of the present disclosure, thereby homogenizing the image quality.

[0256] The embodiments of this disclosure can also be described as follows:

[0257] According to one aspect of this disclosure, a display device includes: a lower substrate, the lower substrate including a display area and a non-display area and being stretchable; a pattern layer disposed on the lower substrate, the pattern layer including a plurality of first plate patterns and a plurality of first line patterns formed in the display area and a plurality of second plate patterns and a plurality of second line patterns formed in the non-display area; a plurality of pixels formed on the plurality of first plate patterns; a plurality of first connecting lines respectively connected to the plurality of pixels; a gating driver formed on the plurality of second plate patterns; a power supply formed on the plurality of second plate patterns; and a plurality of other power supplies. A plurality of second connecting lines are disposed in the non-display area; and an upper substrate covering the gating driver, the power supply, and the plurality of pixels and being stretchable; wherein the non-display area includes: a first area located outside the display area, a second area located outside the first area and including the plurality of gating drivers disposed in the second area, and a third area located outside the second area and including the plurality of power supplies disposed in the third area, and wherein the plurality of second connecting lines disposed in the first area are in contact with a metal pattern disposed on a layer different from the plurality of second connecting lines through anchor holes.

[0258] The plurality of second plate patterns include a plurality of first sub-plate patterns disposed in the first region, a plurality of second sub-plate patterns disposed in the second region, and a plurality of third sub-plate patterns disposed in the third region. The plurality of second line patterns include a plurality of first sub-line patterns disposed in the first region, a plurality of second sub-line patterns disposed in the second region, and a plurality of third sub-line patterns disposed in the third region. The anchoring hole is formed on the plurality of first sub-plate patterns.

[0259] Each of the plurality of pixels may include a transistor comprising a gate electrode, a source electrode, and a drain electrode, and a metal pattern may be formed on the same layer as the source electrode and the drain electrode.

[0260] Each of the plurality of pixels may include a transistor comprising a gate electrode, a source electrode, and a drain electrode, and a metal pattern may be formed on the same layer as the gate electrode.

[0261] The plurality of second sub-board patterns may be spaced apart from each other only in the second direction, and the plurality of third sub-board patterns may be spaced apart from each other in both the first and second directions.

[0262] Multiple stages constituting the gating driver can be set on multiple second daughterboard patterns, and multiple power blocks constituting the power supply can be set on multiple third daughterboard patterns.

[0263] Multiple power blocks may include a first power pattern and a second power pattern set on different layers.

[0264] Each of the plurality of pixels may include a transistor comprising a gate electrode, a source electrode, and a drain electrode, the first power pattern being formed of the same material as the source electrode and the drain electrode, and the second power pattern being formed of the same material as the second interconnect.

[0265] The plurality of third sub-line patterns may include: a 3-1 sub-line pattern, which may be connected to a plurality of third sub-board patterns spaced apart from each other in the first direction; and a 3-2 sub-line pattern, which may be connected to a plurality of third sub-board patterns spaced apart from each other in the second direction.

[0266] Multiple second connecting lines located in the third region can connect multiple power blocks, and the multiple second connecting lines located in the third region can include a first power line located on the 3-1 sub-line pattern and a second power line located on the 3-2 sub-line pattern.

[0267] The first power line may include power line 1-1 and power line 1-2 disposed on different layers, and the second power line may include power line 2-1 and power line 2-2 disposed on different layers.

[0268] The first-1 power line and the second-1 power line may be configured with the same material as the first power pattern, and the first-2 power line and the second-2 power line may be configured with the same material as the second power pattern.

[0269] The display device may further include a plurality of additional power blocks disposed between the plurality of power blocks and spaced apart from each other in a third direction.

[0270] Multiple additional power blocks may include a first additional power pattern and a second additional power pattern set on different layers.

[0271] The first additional power pattern can be electrically connected to the first power pattern, and the second additional power pattern can be electrically connected to the second power pattern.

[0272] According to another aspect of this disclosure, a display device includes: a flexible substrate; a plurality of rigid patterns formed on the flexible substrate, the plurality of rigid patterns including a plurality of first plate patterns and a plurality of second plate patterns; a plurality of pixels formed over the plurality of first plate patterns spaced apart from each other among the plurality of rigid patterns; and a power source formed over some of the plurality of second plate patterns spaced apart from each other among the plurality of rigid patterns, wherein the power source provides driving voltages for the plurality of pixels and is configured by a plurality of power blocks spaced apart from each other in a first direction and a second direction.

[0273] Multiple power blocks may include a first power pattern and a second power pattern set on different layers.

[0274] Different driving voltages can be applied to the first power pattern and the second power pattern.

[0275] Multiple power blocks can be connected by multiple first power lines extending in a first direction and multiple second power lines extending in a second direction.

[0276] The first power line may include power line 1-1 and power line 1-2 disposed on different layers, and the second power line may include power line 2-1 and power line 2-2 disposed on different layers.

[0277] The first-1 power line and the second-1 power line can be electrically connected to the first power pattern, and the first-2 power line and the second-2 power line can be electrically connected to the second power pattern.

[0278] The display device may also include a plurality of additional power blocks disposed between a plurality of first power lines and a plurality of second power lines.

[0279] Multiple additional power blocks may include a first additional power pattern and a second additional power pattern set on different layers.

[0280] The first additional power pattern can be electrically connected to the first power pattern, and the second additional power pattern can be electrically connected to the second power pattern.

[0281] The display device may also include a gating driver between a power supply and multiple pixels, and the gating driver and multiple pixels may be connected by multiple buffer lines, and the multiple buffer lines may be fixed to a metal layer formed on a different layer than the multiple buffer lines by means of anchor holes.

[0282] Anchor holes may be formed above other second plate patterns among the plurality of spaced-apart second plate patterns in the plurality of rigid patterns.

[0283] Although embodiments of the present disclosure have been described in detail with reference to the accompanying drawings, the present disclosure is not limited thereto and can be implemented in many different forms without departing from the technical concept of the present disclosure. Therefore, the embodiments of the present disclosure are provided for illustrative purposes only and are not intended to limit the technical concept of the present disclosure. The scope of the technical concept of the present disclosure is not limited thereto. Therefore, it should be understood that the above embodiments are illustrative in all respects and do not limit the present disclosure. The scope of protection of the present disclosure should be interpreted based on the appended claims, and all technical concepts within their equivalent scope should be interpreted as falling within the scope of the present disclosure.

[0284] The various embodiments described above can be combined to provide other embodiments. All U.S. patents, U.S. patent application publications, U.S. patent applications, foreign patents, foreign patent applications and non-patent publications mentioned in and / or listed in the application data sheets are incorporated herein by reference in their entirety. If necessary, aspects of the embodiments can be modified to incorporate the concepts of various patents, applications and publications to provide other embodiments.

[0285] Based on the detailed description above, these and other changes can be made to the embodiments. Generally, the terminology used in the following claims should not be construed as limiting the claims to the specific embodiments disclosed in the specification and claims, but should be interpreted to include all possible embodiments and the full scope of the authorized equivalents of these claims. Therefore, the claims are not limited to this disclosure.

[0286] Cross-reference to related applications

[0287] This application claims priority to Korean Patent Application No. 10-2021-0178782, filed on December 14, 2021, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference.

Claims

1. A display device, the display device comprising: A lower substrate, the lower substrate including a display area and a non-display area and being stretchable; A pattern layer is disposed on the lower substrate and includes a plurality of first plate patterns and a plurality of first line patterns formed in the display area and a plurality of second plate patterns and a plurality of second line patterns formed in the non-display area; Multiple pixels, the multiple pixels being formed on the multiple first plate patterns; Multiple first connection lines, each of which is connected to one of the multiple pixels; Multiple gating drivers are formed on the multiple second plate patterns; Multiple power sources are formed on the multiple second plate patterns; Multiple second connection lines are disposed in the non-display area; as well as An upper substrate, which covers the gating driver, the power supply, and the plurality of pixels, and is stretchable. The non-display area includes: a first area located outside the display area; a second area located outside the first area and including the plurality of gating drivers disposed in the second area; and a third area located outside the second area and including the plurality of power supplies disposed in the third area. In this configuration, the plurality of second connecting lines disposed in the first region contact a metal pattern disposed on a layer different from the plurality of second connecting lines via anchoring holes. The patterned layer has lower flexibility than the lower substrate, and The anchoring hole is formed above at least one of the plurality of second plate patterns.

2. The display device according to claim 1, wherein, The plurality of second plate patterns include a plurality of first sub-plate patterns disposed in the first region, a plurality of second sub-plate patterns disposed in the second region, and a plurality of third sub-plate patterns disposed in the third region. The plurality of second line patterns include a plurality of first sub-line patterns disposed in the first region, a plurality of second sub-line patterns disposed in the second region, and a plurality of third sub-line patterns disposed in the third region. The anchoring hole is formed on the plurality of first sub-plate patterns.

3. The display device according to claim 2, wherein, Each of the plurality of pixels includes a transistor comprising a gate electrode, a source electrode, and a drain electrode, and the metal pattern is formed on the same layer as the source electrode and the drain electrode.

4. The display device according to claim 2, wherein, Each of the plurality of pixels includes a transistor comprising a gate electrode, a source electrode, and a drain electrode, and the metal pattern is formed on the same layer as the gate electrode.

5. The display device according to claim 2, wherein, The plurality of second sub-board patterns are spaced apart from each other only in the second direction, and the plurality of third sub-board patterns are spaced apart from each other in both the first and second directions.

6. The display device according to claim 5, wherein, Multiple stages constituting the gating driver are arranged on the multiple second sub-board patterns, and multiple power blocks constituting the power supply are arranged on the multiple third sub-board patterns.

7. The display device according to claim 6, wherein, The plurality of power blocks include a first power pattern and a second power pattern disposed on different layers.

8. The display device according to claim 7, wherein, Each of the plurality of pixels includes a transistor comprising a gate electrode, a source electrode, and a drain electrode, the first power pattern being formed of the same material as the source electrode and the drain electrode, and the second power pattern being formed of the same material as the second interconnect.

9. The display device according to claim 7, wherein, The plurality of third sub-line patterns include: The third-1st sub-line pattern, wherein the third-1st sub-line pattern is connected to a plurality of third sub-plate patterns spaced apart from each other in the first direction; and The third-second sub-line pattern is connected to a plurality of third sub-plate patterns spaced apart from each other in the second direction.

10. The display device according to claim 9, wherein, Multiple second connecting lines disposed in the third region connect the multiple power blocks, and the multiple second connecting lines disposed in the third region include a first power line disposed on the 3-1 sub-line pattern and a second power line disposed on the 3-2 sub-line pattern.

11. The display device according to claim 10, wherein, The first power line includes a first-1 power line and a first-2 power line disposed on different layers; and The second power line includes a second-1 power line and a second-2 power line disposed on different layers.

12. The display device according to claim 11, wherein, The first-1 power line and the second-1 power line are configured with the same material as the first power pattern, and the first-2 power line and the second-2 power line are configured with the same material as the second power pattern.

13. The display device according to claim 7, further comprising: Multiple additional power blocks are disposed between the multiple power blocks and spaced apart from each other in a third direction.

14. The display device according to claim 13, wherein, The plurality of additional power blocks include: A first additional power pattern and a second additional power pattern are disposed on different layers.

15. The display device according to claim 14, wherein, The first additional power pattern is electrically connected to the first power pattern, and the second additional power pattern is electrically connected to the second power pattern.

16. A display device, the display device comprising: Flexible substrate; Multiple rigid patterns are formed on the flexible substrate, and the multiple rigid patterns include multiple first plate patterns and multiple second plate patterns; Multiple pixels are formed above the multiple first plate patterns that are spaced apart from each other in the multiple rigid patterns; A power source, which is formed above some of the plurality of second plate patterns that are spaced apart from each other in the plurality of rigid patterns; as well as A gating driver, located between the power supply and the plurality of pixels. The power supply provides the driving voltage for the plurality of pixels and is configured by a plurality of power blocks spaced apart from each other in a first direction and a second direction. The gating driver and the plurality of pixels are connected by multiple buffer lines, and the multiple buffer lines are fixed to a metal layer formed on a different layer by means of anchor holes. The anchoring hole is formed above at least one of the plurality of second plate patterns.

17. The display device according to claim 16, wherein, The plurality of power blocks include a first power pattern and a second power pattern disposed on different layers.

18. The display device according to claim 17, wherein, Different driving voltages are applied to the first power pattern and the second power pattern.

19. The display device according to claim 17, wherein, The plurality of power blocks are connected by a plurality of first power lines in the first direction and a plurality of second power lines in the second direction.

20. The display device according to claim 19, wherein, The first power line includes a first-1 power line and a first-2 power line disposed on different layers, and the second power line includes a second-1 power line and a second-2 power line disposed on different layers.

21. The display device according to claim 20, wherein, The first-1 power line and the second-1 power line are electrically connected to the first power pattern, and The first-2 power line and the second-2 power line are electrically connected to the second power pattern.

22. The display device according to claim 19, further comprising: Multiple additional power blocks are disposed between the multiple first power lines and the multiple second power lines.

23. The display device according to claim 22, wherein, The plurality of additional power blocks include a first additional power pattern and a second additional power pattern disposed on different layers.

24. The display device according to claim 23, wherein, The first additional power pattern is electrically connected to the first power pattern, and the second additional power pattern is electrically connected to the second power pattern.

25. The display device according to claim 16, wherein, The anchoring hole is formed above one of the other second plate patterns among the plurality of spaced-apart second plate patterns in the plurality of rigid patterns.

26. A display device, the display device comprising: A flexible substrate having a display area and a non-display area adjacent to the display area; A plurality of first plate structures are located on the display area of ​​the flexible substrate; A plurality of second plate structures are located on the non-display area of ​​the flexible substrate, each of the plurality of second plate structures being spaced apart from each other; At least one line pattern, the at least one line pattern being connected to at least one of the plurality of second plate structures; At least one buffer line, said at least one buffer line on said at least one of the plurality of second plate structures; as well as At least one anchoring hole is provided on the at least one second plate structure, and the at least one buffer line is electrically connected to a conductive pattern on the at least one of the plurality of second plate structures. The at least one anchoring hole secures the at least one buffer line to the at least one of the plurality of second plate structures. Each of the plurality of first plate structures and the plurality of second plate structures has a lower flexibility than the flexible substrate.

27. The display device according to claim 26, wherein, The conductive pattern is disposed in a layer different from the at least one buffer line, and the conductive pattern is electrically connected to the at least one buffer line via the at least one anchoring hole.

28. The display device according to claim 27, wherein, The conductive pattern is made of the same material as one of the source or drain electrodes of the driving transistor disposed in the display area of ​​the flexible substrate.

29. The display device according to claim 27, wherein, The non-display area of ​​the flexible substrate includes a first non-display area and a second non-display area, wherein the first non-display area is located between the display area and the second non-display area. The first non-display area includes at least one second plate structure having at least one anchoring hole thereon. The second non-display area includes a first group of the plurality of second board structures having driving circuits thereon, each of the second board structures in the first group being spaced apart from each other and electrically connected together by a plurality of first connecting lines.

30. The display device according to claim 26, wherein, The non-display area of ​​the flexible substrate includes a first non-display area, a second non-display area, and a third non-display area. The first non-display area is located between the display area and the second non-display area, and the second non-display area is located between the first non-display area and the third non-display area. The first non-display area includes at least one second plate structure having at least one anchoring hole thereon. The third non-display area includes a second group of the plurality of second board structures having power supply circuitry thereon. Each of the second board structures in the second group is spaced apart from each other and electrically connected together by a plurality of power lines. The plurality of power lines include a first power pattern and a second power pattern arranged in the same direction at different layers, and During operation, different voltages are applied to the first power pattern and the second power pattern.

31. The display device according to claim 30, wherein the display device comprises: At least one sub-board structure in the third non-display area, the at least one sub-board structure being disposed in an area not occupied by the second board structure of the second group and the plurality of power lines; An additional power block is provided on the at least one sub-board structure; as well as An additional power line is connected to the additional power block, the additional power line including a first additional power pattern and a second additional power pattern, the additional power line being connected to a second plate structure of the second group adjacent to the at least one sub-plate structure.

32. The display device according to claim 31, wherein, The first additional electrical pattern and the second additional electrical pattern are arranged in the same direction at different layers, and The first additional electrical pattern is formed of the same material as the first electrical pattern, and the second additional electrical pattern is formed of the same material as the second electrical pattern.

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