Semiconductor device and method of manufacturing semiconductor device

Abstract

A semiconductor device and a method of manufacturing a semiconductor device are disclosed. A semiconductor device having a transistor of a fin structure includes a channel layer disposed above a substrate and connected to the substrate via a semiconductor layer, a source layer disposed on a first side surface of the channel layer above the substrate and separated from the substrate via a first insulating layer, a drain layer disposed on a second side surface of the channel layer opposite the first side surface above the substrate and separated from the substrate via a second insulating layer, and a gate electrode including a first portion disposed above the channel layer and a second portion disposed between the substrate and the channel layer, a third side surface or a fourth side surface of the second portion facing the semiconductor layer.

Description

[0001] Cross-reference to related applications

[0002] This application is based on and claims priority to Japanese Patent Application No. 2021-202722, filed on December 14, 2021, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The embodiments discussed herein relate to a semiconductor device and a method of manufacturing the semiconductor device. Background Technology

[0004] A semiconductor device is known that has a transistor with a fin-like structure (a transistor structure that stands upright like a fin) on a silicon-on-insulator (SOI) substrate. Furthermore, fin transistors with a gate-all-around (GAA) structure have been proposed, in which the transistor channel is completely surrounded by the gate (see, for example, Japanese Patent Application Publication Nos. 2021-52173 and 2007-173784, and International Publication No. 2009 / 151001).

[0005] Incidentally, the channel of a fin transistor formed on an SOI substrate is electrically isolated from the semiconductor substrate. Therefore, charge, depending on the recent operating history, accumulates in the channel, and characteristic changes such as threshold voltage variations may occur. This phenomenon can be called the floating body effect.

[0006] To eliminate the floating body effect, a technique for conducting electricity between the channel and the substrate has been proposed (see, for example, Japanese Patent Application Publication No. 2008-10876).

[0007] However, if conductivity is made between the channel and the substrate to eliminate the floating body effect, the potential change in the channel region caused by the gate voltage may be reduced, which means that the advantages of the SOI structure may be lost. Summary of the Invention

[0008] According to one aspect, a semiconductor device is provided including a transistor having a finned structure. The semiconductor device includes: a channel layer disposed above a substrate, the channel layer being connected to the substrate via a semiconductor layer; a source layer disposed on a first side surface of the channel layer above the substrate, the source layer being separated from the substrate via a first insulating layer, and the source layer serving as a source of the transistor; a drain layer disposed on a second side surface of the channel layer above the substrate opposite to the first side surface, the drain layer being separated from the substrate via a second insulating layer, and the drain layer serving as a drain of the transistor; and a gate electrode including a first portion disposed above the channel layer and a second portion disposed between the substrate and the channel layer, the gate electrode serving as a gate of the transistor, wherein the second portion has a third side surface and a fourth side surface opposite to the third side surface, and the third or fourth side surface faces the semiconductor layer.

[0009] The objects and advantages of the present invention will be realized and obtained by means of the elements and combinations particularly pointed out in the claims.

[0010] It should be understood that the foregoing general description and the following detailed description are exemplary and illustrative, and do not limit the invention. Attached Figure Description

[0011] Figure 1 This is a perspective view showing an example of a semiconductor device according to the first embodiment;

[0012] Figure 2 It is along Figure 1 A sectional view taken from line II-II;

[0013] Figure 3 It is along Figure 2 A sectional view taken from line III-III;

[0014] Figure 4 It is along Figure 2 A sectional view taken along line IV-IV;

[0015] Figure 5 It is along Figure 2 A cross-sectional view taken from the VV line;

[0016] Figure 6 This is a schematic diagram of an example of a semiconductor device without a channel cut-off layer;

[0017] Figure 7 This is a schematic diagram of an example of a semiconductor device in which the thickness of the insulating layer is a lower limit;

[0018] Figure 8 This is a schematic diagram of an example of a semiconductor device in which the thickness of the insulating layer is less than the lower limit;

[0019] Figure 9This is a perspective view (part 1) showing one step included in a semiconductor device manufacturing method according to the first embodiment;

[0020] Figure 10 This is a perspective view (part 2) showing one step included in the semiconductor device manufacturing method according to the first embodiment;

[0021] Figure 11 This is a perspective view (part 3) showing one step included in the semiconductor device manufacturing method according to the first embodiment;

[0022] Figure 12 This is a perspective view (part 4) showing one step included in the semiconductor device manufacturing method according to the first embodiment;

[0023] Figure 13 This is a perspective view (part 5) showing one step included in the semiconductor device manufacturing method according to the first embodiment;

[0024] Figure 14 This is a perspective view (part 6) showing a step included in a semiconductor device manufacturing method according to the first embodiment;

[0025] Figure 15 This is a perspective view (part 7) showing one step included in the semiconductor device manufacturing method according to the first embodiment;

[0026] Figure 16 This is a perspective view (part 8) showing one step included in the semiconductor device manufacturing method according to the first embodiment;

[0027] Figure 17 This is a perspective view (part 9) showing one step included in the semiconductor device manufacturing method according to the first embodiment;

[0028] Figure 18 This is a perspective view (part 10) showing one step included in a semiconductor device manufacturing method according to the first embodiment;

[0029] Figure 19 This is a perspective view (part 11) showing a step included in a semiconductor device manufacturing method according to the first embodiment;

[0030] Figure 20 This is a schematic diagram of an example of two adjacent transistors with a fin-like structure;

[0031] Figure 21 This is a cross-sectional view showing an example of a semiconductor device, wherein the gate width below the channel layer is smaller than the gate width above the channel layer;

[0032] Figure 22This is a perspective view showing an example of a semiconductor device according to the second embodiment;

[0033] Figure 23 It is along Figure 22 A sectional view taken from line XXIII-XXIII;

[0034] Figure 24 It is along Figure 23 A sectional view taken from line XXIV-XXIV;

[0035] Figure 25 It is along Figure 23 A cross-sectional view taken from line XXV-XXV;

[0036] Figure 26 It is along Figure 23 A sectional view taken from line XXVI-XXVI;

[0037] Figure 27 This is a schematic diagram of an example of a semiconductor device without a channel cut-off layer;

[0038] Figure 28 This is a schematic diagram of an example of a semiconductor device with a thick insulating layer;

[0039] Figure 29 This is a schematic diagram of an example of a semiconductor device in which the thickness of the insulating layer is less than the lower limit;

[0040] Figure 30 This is a perspective view (part 1) showing a step included in a semiconductor device manufacturing method according to a second embodiment;

[0041] Figure 31 This is a perspective view (part 2) showing one step included in the semiconductor device manufacturing method according to the second embodiment;

[0042] Figure 32 This is a perspective view (part 3) showing one step included in the semiconductor device manufacturing method according to the second embodiment;

[0043] Figure 33 This is a perspective view (part 4) showing one step included in the semiconductor device manufacturing method according to the second embodiment;

[0044] Figure 34 This is a perspective view (part 5) showing a step included in a semiconductor device manufacturing method according to the second embodiment;

[0045] Figure 35 This is a perspective view (part 6) showing one step included in the semiconductor device manufacturing method according to the second embodiment;

[0046] Figure 36 This is a perspective view (part 7) showing a step included in a semiconductor device manufacturing method according to a second embodiment;

[0047] Figure 37 This is a perspective view (part 8) showing one step included in a semiconductor device manufacturing method according to the second embodiment;

[0048] Figure 38 This is a perspective view (part 9) showing one step included in a semiconductor device manufacturing method according to the second embodiment;

[0049] Figure 39 This is a perspective view (part 10) showing one step included in a semiconductor device manufacturing method according to the second embodiment;

[0050] Figure 40 This is a perspective view (part 11) showing a step included in a semiconductor device manufacturing method according to the second embodiment;

[0051] Figure 41 This is a schematic diagram of an example of two adjacent transistors with a fin-like structure;

[0052] Figure 42 This is a cross-sectional view illustrating an example of a semiconductor device, wherein the gate width below the channel layer is smaller than the gate width above the channel layer; and

[0053] Figure 43 This is a cross-sectional view showing an example of a semiconductor device, wherein the semiconductor layer is thick and fills between two channel layers and between the lower channel layer and the substrate. Detailed Implementation

[0054] In the following description, some embodiments will be described with reference to the accompanying drawings.

[0055] (First Embodiment)

[0056] Figure 1 This is a perspective view showing an example of a semiconductor device according to the first embodiment. Figure 2 It is along Figure 1 The sectional view taken from line II-II. Figure 3 It is along Figure 2 The sectional view taken from line III-III. Figure 4 It is along Figure 2 A cross-sectional view taken along line IV-IV. Figure 5 It is along Figure 2 A cross-sectional view taken from line VV.

[0057] The semiconductor device 10 of the first embodiment has a transistor having a channel layer 14 formed above a substrate 11 (see...). Figure 2The fin-like structure formed by the source layer 21a, drain layer 21b and gate electrode 22.

[0058] For example, substrate 11 is a silicon substrate. Furthermore, as... Figure 2 As shown, an impurity layer (hereinafter referred to as the channel cut layer) 12 is formed on the surface of the substrate 11. The channel cut layer 12 contains impurities of the same conductivity type as the channel layer 14, but the impurity concentration of the channel cut layer 12 is higher than that of the channel layer 14. Figure 2 In the example, the channel layer 14 is a p-type impurity region containing p-type impurities, and the channel cut-off layer 12 is a p+ type impurity region with a higher p-type impurity concentration than the channel layer 14.

[0059] It should be noted that a channel cut-off layer 12 is not required. However, in order to suppress source-drain leakage current, it is desirable to provide a channel cut-off layer 12, as described later.

[0060] In addition, shallow trench isolation (STI) 15a and 15b, which electrically isolate adjacent elements from each other, are formed in the substrate 11.

[0061] like Figure 2 As shown, the channel layer 14 is connected to the substrate 11 via the semiconductor layer 19, and the substrate 11 has a channel cut-off layer 12 formed on its surface. Figure 2 In the example, impurity diffusion regions 14a and 14b, containing impurities diffused from the source layer 21a and drain layer 21b, respectively, are formed in the channel layer 14. Impurity diffusion regions 14a and 14b contain impurities of the same conductivity type as those in the source layer 21a and drain layer 21b (impurities of a different conductivity type than those in the channel layer 14), and the impurity concentrations in impurity diffusion regions 14a and 14b are lower than the impurity concentrations in the source layer 21a and drain layer 21b.

[0062] The source layer 21a serves as the source of a transistor with a fin structure. The source layer 21a is disposed on the side surface of the channel layer 14 above the substrate 11 and is separated from the substrate 11 via the insulating layer 20a.

[0063] The drain layer 21b serves as the drain of a transistor with a fin structure. The drain layer 21b is disposed on the side surface of the channel layer 14 above the substrate 11, which is opposite to the side surface on which the source layer 21a is disposed, and the drain layer 21b is separated from the substrate 11 via the insulating layer 20b.

[0064] The conductivity type of the impurities contained in the source layer 21a and drain layer 21b (in Figure 2 The example shown is of type n, which is different from the conductivity type of channel layer 14.

[0065] The gate electrode 22 serves as the gate of a transistor with a finned structure and includes a first portion disposed above the channel layer 14 and a second portion disposed between the substrate 11 and the channel layer 14. Figure 2 Part 22a), such as Figure 2 As shown. Here, the portion 22a has a side surface 22a1 and a side surface 22a2 opposite to the side surface 22a1, the side surfaces 22a1 and 22a2 facing the semiconductor layer 19.

[0066] In addition, a sidewall insulating film 18 is formed on the side surface of the gate electrode 22.

[0067] In this respect, although not shown, a gate insulating film is formed between the portion of the gate electrode 22 above the channel layer 14 and the channel layer 14, between the portion 22a and the semiconductor layer 19, between the portion 22a and the channel layer 14, and between the portion 22a and the channel cut-off layer 12. For example, the gate insulating film is a silicon oxide film, a high-k film, etc. Materials used for high-k films are, but are not limited to, hafnium oxide (HfO2), hafnium silicon oxide (Hf-Si-O), hafnium silicon oxynitride (HfSiON), etc.

[0068] For example, semiconductor layer 19 is a silicon epitaxial layer, formed as described later. Semiconductor layer 19 is disposed between insulating layer 20a and side surface 22a1 and between insulating layer 20b and side surface 22a2, and connects channel layer 14 and substrate 11. In this respect, semiconductor layer 19 may be disposed only on side surface 22a1 or 22a2.

[0069] In addition, such as Figure 2 As shown, the semiconductor layer 19 can be disposed between the channel cut-off layer 12 and each insulating layer 20a and 20b, and between each insulating layer 20a and 20b and the channel layer 14. (Refer to...) Figure 2 For example, a sidewall insulating film 18 is formed on the sidewall of the gate electrode 22 above the channel layer 14, and the portion of the top surface of the insulating layers 20a and 20b located below the sidewall insulating film 18 contacts the bottom surface of the semiconductor layer 19 formed on the bottom surface of the channel layer 14.

[0070] Semiconductor layer 19 may contain impurities with a conductivity type opposite to that of channel layer 14, impurities with the same conductivity type as that of channel layer 14, or impurities with the same conductivity type as that of channel layer 14 and an impurity concentration that is the same as or lower than that of channel layer 14.

[0071] Furthermore, the semiconductor layer 19 can be an undoped layer. In this regard, for example, it contains an impurity concentration of 1.0 × 10⁻⁶. 15 cm -3Semiconductor layers 19 with lower n-type or p-type impurities can be considered essentially undoped layers.

[0072] The semiconductor device 10 described above has a transistor 25, the conductivity type of which is opposite to that of the fin transistor, and the transistor 25 is formed by a substrate 11, a channel layer 14, a semiconductor layer 19, and a portion 22a of a gate electrode 22. In the transistor 25, the substrate 11 serves as one of the source and drain, the channel layer 14 serves as the other of the source and drain, the semiconductor layer 19 serves as the channel, and the portion 22a serves as the gate.

[0073] A similar transistor is positioned on the side where the drain layer 21b is located.

[0074] When a voltage is applied to the gate electrode 22 to turn on the transistor with the finned structure, the density of carriers (electrons or holes) of the same conductivity type as the impurities in the channel layer 14 decreases in the semiconductor layer 19. As a result, the transistor 25 enters a cutoff state, and the channel layer 14 enters a state of electrical isolation from the substrate 11 (floating state). Therefore, the potential change in the channel layer 14 caused by the gate voltage increases, and thus a large source-drain current is obtained. In other words, the advantages of a silicon-on-insulator (SOI) structure are achieved.

[0075] On the other hand, when a voltage for turning off the finned transistor is applied to the gate electrode 22, the density of carriers of the same impurity conductivity type as the channel layer 14 increases in the semiconductor layer 19. As a result, the transistor 25 enters the on state, and the channel layer 14 enters a state of electrical connection with the substrate 11. Therefore, the floating body effect is suppressed, which helps reduce characteristic variations, such as threshold voltage variations, caused by charge accumulation depending on the recent operating history in the channel layer 14.

[0076] When the transistor with the fin structure is an n-channel metal-oxide-semiconductor field-effect transistor (MOSFET), the channel layer 14 contains p-type impurities. When the semiconductor layer 19 contains n-type impurities and the substrate 11 contains p-type impurities, the transistor 25 is a p-channel MOSFET. In this case, good electrical isolation is achieved between the channel layer 14 and the substrate when a voltage (a positive voltage higher than or equal to the threshold voltage) is applied to the gate electrode 22 to turn on the fin transistor.

[0077] On the other hand, when the semiconductor layer 19 contains p-type impurities with the same or lower impurity concentration as the channel layer 14, and the substrate 11 contains p-type impurities, the transistor 25 is a suppression-type p-channel MOSFET. In this case, the insulation between the channel layer 14 and the substrate 11 is worse than in the case where the transistor 25 is a p-channel MOSFET, during the application of a positive voltage higher than or equal to the threshold to the gate electrode 22. However, when the transistor 25 is a suppression-type p-channel MOSFET, a low-resistance connection exists between the channel layer 14 and the substrate 11 when the voltage (0V) used to turn off the fin transistor is applied to the gate electrode 22. This further improves the effect of reducing the floating body effect.

[0078] Furthermore, the source layer 21a and the drain layer 21b are insulated from the substrate 11 by insulating layers 20a and 20b, which prevents source-drain leakage current from flowing through the upper part of the substrate 11 and also reduces the capacitance between the source layer 21a and the substrate 11 and the capacitance between the drain layer 21b and the substrate 11.

[0079] also, Figure 2 The top surfaces of portions of the insulating layers 20a and 20b beneath the sidewall insulating film 18 are contacted with the bottom surface of the semiconductor layer 19 on the bottom surface of the channel layer 14. In other words, the semiconductor layer 19 is formed on the bottom surface of the channel layer 14 beneath the sidewall insulating film 18. The semiconductor layer 19 allows the channel layer 14 to have substantially increased thickness (length in the vertical direction), which provides the effect of reducing source-drain parasitic resistance. Note that the thickness of the channel layer 14 beneath the gate electrode 22 remains unchanged, therefore the controllability of the gate on the channel layer 14 remains unchanged.

[0080] As described above, the semiconductor device 10 of the first embodiment can suppress the buoyancy effect without losing the advantages of the SOI structure.

[0081] (First comparison example)

[0082] Figure 6 An example of a semiconductor device without a channel cut-off layer is shown. (Using...) Figure 2 The same reference numerals indicate Figure 6 The corresponding components.

[0083] Without the channel cut-off layer 12, leakage current could flow from the source layer 21a through the channel layer 14, the semiconductor layer 19, and the substrate 11 to the drain layer 21b, such as... Figure 6 As shown by arrow 26.

[0084] Therefore, such as Figure 2 As shown, it is desirable to provide a channel cut-off layer 12.

[0085] (Second comparison example)

[0086] Figure 7 An example of a semiconductor device in which the thickness of the insulating layer is a lower limit is shown. (Using...) Figure 2 The same reference numerals indicate Figure 7 The corresponding components.

[0087] Reference Figure 7 For example, insulation layers 20a and 20b are compared to Figure 2 The insulating layers 20a and 20b are thin. Figure 7 The top surfaces of portions of the insulating layers 20a and 20b below the sidewall insulating film 18 contact the bottom surface of the channel layer 14 (in Figure 7 In this process, the semiconductor layer 19 is integrated within impurity diffusion regions 14a and 14b in the bottom surface portion of the channel layer 14. In this respect, portions of the contact insulating layers 20a and 20b of the impurity diffusion regions 14a and 14b are formed by diffusing impurities from the source layer 21a and the drain layer 21b to... Figure 7 The portion formed in the semiconductor layer 19.

[0088] If the insulating layers 20a and 20b are further thinned, the following third comparative example is obtained.

[0089] (Third comparison example)

[0090] Figure 8 An example of a semiconductor device in which the thickness of the insulating layer is below the lower limit is shown. (Using...) Figure 2 The same reference numerals indicate Figure 8 The corresponding components.

[0091] Reference Figure 8 For example, the top surfaces of insulating layers 20a and 20b are positioned below Figure 7 The bottom surface of the channel layer 14 is shown. In this case, the source layer 21a and the drain layer 21b are respectively inserted between the bottom surface of the channel layer 14 and the top surface of the insulating layer 20a, and between the bottom surface of the channel layer 14 and the top surface of the insulating layer 20b. Therefore, the distance between the source layer 21a and the drain layer 21b decreases at the bottom of the channel layer 14, which may lead to the possibility of source-drain leakage current.

[0092] Therefore, the thickness of insulating layers 20a and 20b is ideally set such that the top surfaces of insulating layers 20a and 20b below the sidewall insulating film 18 are at the same height as or higher than the bottom surface of the channel layer 14. However, if insulating layers 20a and 20b are made too thick, it will result in thinner source layer 21a and drain layer 21b, a smaller contact area between the channel layer 14 and each of the source layer 21a and drain layer 21b, and a narrower path for the source-drain current (higher resistance). Therefore, for example, when the channel layer 14 has a thickness of 30 nm, it is desirable that insulating layers 20a and 20b be formed with a thickness such that the top surfaces of insulating layers 20a and 20b are approximately 5 nm higher than the bottom surface of the channel layer 14.

[0093] (Method for manufacturing semiconductor device 10)

[0094] The following describes an example of a method for manufacturing a semiconductor device 10 according to a first embodiment.

[0095] Figures 9 to 19 This is a perspective view illustrating the steps included in a semiconductor device manufacturing method according to a first embodiment.

[0096] In the example of the manufacturing method below, a silicon substrate is used as substrate 11. For example... Figure 9 As shown, impurities are first implanted into the surface of substrate 11 to form a channel cut-off layer 12. The channel cut-off layer 12 contains impurities of the same conductivity type as the channel layer 14 formed later, and the impurity concentration of the channel cut-off layer 12 is higher than that of the channel layer 14.

[0097] Impurity implantation techniques include ion implantation, vapor phase doping, plasma doping, plasma immersion ion implantation, cluster doping, implantation doping, liquid phase doping, and solid-state doping. N-type impurities include phosphorus (P) and arsenic (As). P-type impurities include boron (B), boron difluoride (BF2), gallium (Ga), and indium (In).

[0098] Then, a silicon-germanium (SiGe) epitaxial layer 13 is formed on the channel cut-off layer 12 by epitaxial growth, and an undoped silicon channel layer 14 is formed on the epitaxial layer 13 by further epitaxial growth. Epitaxial growth techniques include vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), etc.

[0099] For example, the silicon-germanium epitaxial layer 13 has a thickness of 5 nm to 10 nm, and the channel layer 14 has a thickness of 30 nm to 50 nm.

[0100] After that, Figure 9An etching process is performed on the stacked structure shown to form an STI formation region in the substrate 11, for example, with a depth of approximately 30 nm to 50 nm. Then, for example, after the etching process, a high-density plasma (HDP)-chemical vapor deposition (CVD) process is performed on the structure to embed a silicon oxide film in the STI formation region. Furthermore, a planarization process is performed by chemical mechanical polishing (CMP) and hydrofluoric acid treatment (HF) to reprocess the silicon oxide film and form fin structures and STIs 15a and 15b, as shown. Figure 10 As shown. STI15a and 15b are formed such that their top surfaces are flush with the bottom surface of the silicon-germanium epitaxial layer 13.

[0101] Then, impurities are implanted into the channel layer 14. Here, p-type impurities are implanted when the transistor with the fin structure is an n-channel MOSFET, and n-type impurities are implanted when the transistor with the fin structure is a p-channel MOSFET. In this respect, impurity implantation in the channel layer 14 can be performed when the channel layer 14 is formed by epitaxial growth. Furthermore, for example, if p-type impurities are pre-implanted in the channel layer 14 for the n-channel MOSFET during epitaxial growth, n-type impurities can be additionally implanted in the region of the channel layer 14 where the p-channel MOSFET is to be formed at that time. Similarly, for example, if n-type impurities are pre-implanted in the channel layer 14 for the p-channel MOSFET during epitaxial growth, p-type impurities can be additionally implanted in the region of the channel layer 14 where the n-channel MOSFET is to be formed at that time.

[0102] In this respect, when p-type impurities are implanted into the channel layer 14, a channel region (inversion layer) is formed in the channel layer 14 that is converted to n-type when the transistor with the fin structure is in the on state. Similarly, when n-type impurities are implanted into the channel layer 14, a channel region is formed in the channel layer 14 that is converted to p-type when the transistor with the fin structure is in the on state.

[0103] Then, thermal oxidation is performed to... Figure 10 A gate oxide film (not shown) with a thickness of approximately 1 nm to 3 nm is formed on the side and top surfaces of the stacked structure formed by the silicon-germanium epitaxial layer 13 and the channel layer 14. Furthermore, a CVD process is performed to sequentially deposit a polysilicon film and a hard mask layer. For example, the hard mask layer is a silicon nitride (SiN) film or a silicon oxide film. Then, an etching process is performed on the stacked film formed by the polysilicon film and the hard mask layer. In this respect, the etching process is stopped when the etching reaches the gate oxide film, so that the gate oxide film is not removed.

[0104] The etching process includes patterning that causes the polycrystalline silicon film to straddle over the fin structure, thereby forming a shape such as... Figure 11The dummy electrode (hereinafter referred to as the dummy gate) 16 and the hard mask 17 disposed on the dummy gate 16 are shown. For example, the dummy gate 16 is formed to have a gate width Wg of approximately 10 nm to 14 nm.

[0105] In this regard, in the steps described later, the dummy gate 16 is used by the gate electrode 22 (except for...). Figure 2 (Except for part 22a)

[0106] Subsequently, in order to form the sidewall insulating film 18, a CVD process is performed, for example, to... Figure 11 A silicon nitride film is deposited on the structure shown. Then, anisotropic etching is performed to etch back the silicon nitride film, leaving it on the sidewalls of the silicon-germanium epitaxial layer 13, the channel layer 14, the dummy gate 16, and the hard mask 17, thereby forming a structure as shown. Figure 12 The sidewall insulating film 18 is shown.

[0107] In this respect, the sidewall insulating film 18 has a width Ws, for example, of approximately 8 nm to 12 nm. Furthermore, the height Hs of the sidewall insulating film 18 formed on the sidewalls of the silicon-germanium epitaxial layer 13 and the channel layer 14 is greater than the thickness of the silicon-germanium epitaxial layer 13, so that the sidewall insulating film 18 can be used as a mask for etching the channel layer 14 in the process described later. For example, the height Hs is approximately 10 nm to 15 nm.

[0108] In order to form the sidewall insulating film 18 by the above-mentioned etch-back process, in the deposition step, the silicon nitride film is deposited to have a thickness of approximately 30% greater than the target thickness Ws.

[0109] Then, using hard mask 17 and sidewall insulating film 18 as masks, in Figure 13 Anisotropic etching is performed in the direction indicated by the arrow. As a result, portions of the silicon-germanium epitaxial layer 13 and the channel layer 14, except for those masked by the hard mask 17 and the sidewall insulating film 18, are removed. In this respect, in Figure 13 The dummy gate 16 is not shown in the following figures.

[0110] After anisotropic etching, isotropic etching is performed on the silicon-germanium epitaxial layer 13 remaining on the bottom surface of the channel layer 14, such that only the central portion of the silicon-germanium epitaxial layer 13 below the bottom surface of the channel layer 14 (the portion sandwiched between the lower parts of the dummy gate 16) is retained. Figure 14 As shown.

[0111] At this point, if the width of the remaining epitaxial layer 13 is much larger than the gate width Wg, the following problem arises: during the further steps described later, such as removing the remaining epitaxial layer 13 and embedding the metal material for the gate electrode 22 into the removed space, the metal material may not be able to properly fill the space. If this occurs, the gate electrode 22 and the semiconductor layer 19 may separate from each other. Due to this separation, the gate potential cannot affect the semiconductor layer 19, which may prevent the transistor 25 from functioning as described above.

[0112] Therefore, considering the process margin, it is desirable to adjust the etching time so that the width of the remaining epitaxial layer 13 is the same as or less than the gate width Wg. In the following text, it is assumed that the width of the remaining epitaxial layer 13 is the same as the gate width Wg.

[0113] Then, using the techniques described above for epitaxial growth, a silicon semiconductor layer 19 is formed on the top surface of the channel cut-off layer 12, the exposed side surface of the silicon-germanium epitaxial layer 13, and the exposed side and bottom surfaces of the channel layer 14, as shown below. Figure 15 As shown. The semiconductor layer 19 is formed to have a thickness of, for example, 1 nm to 5 nm.

[0114] As previously described, impurities of the opposite conductivity type to those of the channel layer 14 can be implanted into the semiconductor layer 19, or impurities of the same conductivity type as the channel layer 14 with a concentration lower than or equal to that of the channel layer 14 can be implanted. In this respect, it is not necessary to implant n-type or p-type impurities into the semiconductor layer 19. For example, the semiconductor layer 19 may contain an impurity concentration of 1.0 × 10⁻⁶. 15 cm -3 In the case of smaller n-type or p-type impurities, semiconductor layer 19 can be considered as an undoped layer with essentially no implanted impurities.

[0115] Then, as Figure 16 As shown, the insulating layers 20a and 20b of the silicon oxide film are embedded in the region between the sidewall insulating film 18 and the area beneath the channel layer 14 (where the silicon-germanium epitaxial layer 13 has been removed). To achieve proper embedding here, the deposition and etching of the silicon oxide film can be appropriately combined. For example, the silicon oxide film can be deposited in the order of CVD process, anisotropic etching, and HDP-CVD process. Anisotropic etching can be performed last.

[0116] If the silicon oxide film remains on the sidewall of the semiconductor layer 19 formed on the side surface of the channel layer 14, the silicon oxide film can be removed, for example, using hydrofluoric acid or the like.

[0117] Then, the semiconductor layer 19 formed on the side surface of the channel layer 14 can be removed (see...). Figure 17To remove the semiconductor layer 19, an isotropic or anisotropic etching can be performed using a hard mask 17 and a sidewall insulating film 18 as masks. The reason for removing the semiconductor layer 19 formed on the side surface of the channel layer 14 will be described later (see [reference]). Figure 21 ).

[0118] Then, as Figure 18 As shown, a source layer 21a and a drain layer 21b are formed. The source layer 21a and drain layer 21b are formed on two opposing side surfaces of the channel layer 14 by epitaxial growth. The shapes of the formed source layer 21a and drain layer 21b depend on the crystal planes, etc., of the two side surfaces of the channel layer 14 on which the epitaxial growth of the source layer 21a and drain layer 21b is performed. Furthermore, impurities of the opposite conductivity type to that of the channel layer 14 are implanted into the source layer 21a and drain layer 21b.

[0119] Then, although not shown, for example, a CVD process is performed to deposit a silicon oxide film as a cover. Figure 18 The interlayer insulating film with the structure shown. Then, CMP is performed to planarize the silicon oxide film.

[0120] In the case where the hard mask 17 is a silicon oxide film, the hard mask 17 is also removed by CMP, so that the top surface of the polysilicon dummy gate 16 is exposed.

[0121] When the hard mask 17 is a silicon nitride film, the top surface of the hard mask 17 is exposed by CMP. Thereafter, using a silicon oxide film as an interlayer insulating film as a mask, the hard mask 17 of the silicon nitride film is etched to remove the hard mask 17, thereby exposing the top surface of the polysilicon dummy gate 16.

[0122] Subsequently, a replacement metal gate (RMG) step is performed to replace the dummy gate 16 and the silicon-germanium epitaxial layer 13 remaining beneath the channel layer 14 with the gate electrode 22 (see [link to relevant documentation]). Figure 19 ).in this regard, Figure 19 Channel layer 14 is not shown in the diagram.

[0123] In the RMG step, the dummy gate 16 is removed by vapor phase etching, wet etching, etc. A gate oxide film (not shown) protects the channel layer 14, etc., during the removal of the dummy gate 16. Then, after removing the gate oxide film by hydrofluoric acid treatment, the epitaxial layer 13 retained below the channel layer 14 is removed by isotropic etching. Thereafter, a gate insulating film (not shown) is formed on the surfaces of the channel layer 14 and the substrate 11 exposed in the space between the removed dummy gate 16 and the epitaxial layer 13. Furthermore, on the gate insulating film, a metal material fills the areas where the removed dummy gate 16 and the hard mask 17, as well as the areas where the removed epitaxial layer 13 retained below the channel layer 14. Thus, a structure is formed as shown... Figure 19 The gate electrode 22 shown.

[0124] For example, the gate insulating film is a silicon oxide film, a high-k film, etc. Examples of metallic materials used for the gate electrode 22 include titanium nitride (TiN), titanium aluminum nitride (TiAl), titanium aluminum nitride (TiAlN), tungsten (W), titanium (Ti), tantalum (Ta), ruthenium (Ru), zirconium (Zr), cobalt (Co), copper (Cu), etc. Furthermore, the gate electrode 22 can be formed from a combination of various metallic materials.

[0125] The gate insulating film and gate electrode 22 can be formed by deposition techniques such as CVD, coating, atomic layer deposition (ALD), and vapor deposition.

[0126] Using the above manufacturing method, a product such as Figures 1 to 5 The semiconductor device 10 shown.

[0127] The following describes why the semiconductor layer 19 formed on the side surface of the channel layer 14 is removed.

[0128] Figure 20 An example of two adjacent transistors with a finned structure is shown. In this respect, their source layer 21a and drain layer 21b are... Figure 20 Not shown in the image.

[0129] Without removing the semiconductor layer 19 from the side surface of the channel layer 14, the space between the two transistors with the fin structure for forming the source layer 21a and the drain layer 21b may be too narrow.

[0130] For example, in Figure 20 In the example, each gate electrode 22 has a gate width Wg of approximately 10 nm to 14 nm, and each sidewall insulating film 18 has a width Ws of approximately 8 nm to 12 nm. For example, in the case where the gate-to-gate distance La (distance between adjacent sidewall insulating films) between two transistors with a fin structure is approximately 12 nm, and a semiconductor layer 19 with a thickness of 1 nm to 2 nm is formed on the side surface of the channel layer 14, the distance Lb between the semiconductor layers on which the source layer 21a and the drain layer 21b are formed is 8 nm to 10 nm, which is 20% to 30% shorter than La.

[0131] Therefore, it is desirable to remove the semiconductor layer 19 on the side surface of the channel layer 14 before forming the source layer 21a and the drain layer 21b.

[0132] However, if the distance from the La pair forming the source layer 21a and drain layer 21b is long enough, it is not necessary to remove the semiconductor layer 19.

[0133] (Fourth comparison example)

[0134] Figure 21This is a cross-sectional view illustrating an example of a semiconductor device, wherein the gate width below the channel layer is smaller than the gate width above the channel layer.

[0135] In adjustment Figure 14 The etching time shown for isotropic etching to remove the silicon-germanium epitaxial layer 13 is such that the width of the remaining epitaxial layer 13 is less than the gate width Wg, resulting in the following: Figure 21 The structure shown is such that the width Wga of the portion 22a of the gate electrode 22 located below the channel layer 14 is smaller than the gate width Wg of the portion of the gate electrode 22 located above the channel layer 14.

[0136] (Second Embodiment)

[0137] Figure 22 This is a perspective view showing an example of a semiconductor device according to a second embodiment. Figure 23 It is along Figure 22 The sectional view taken from line XXIII-XXIII. Figure 24 It is along Figure 23 A cross-sectional view taken from line XXIV-XXIV. Figure 25 It is along Figure 23 A cross-sectional view taken from line XXV-XXV. Figure 26 It is along Figure 23 A sectional view taken from line XXVI-XXVI.

[0138] The semiconductor device 30 of the second embodiment has a transistor having channel layers 34a and 34b formed above a substrate 31 (see...). Figure 23 The fin-like structure formed by the source layer 41a, drain layer 41b and gate electrode 42.

[0139] For example, substrate 31 is a silicon substrate. Furthermore, as... Figure 23 As shown, an impurity layer (hereinafter referred to as a channel cut-off layer) 32 is formed on the surface of substrate 31. The channel cut-off layer 32 contains impurities of the same conductivity type as channel layers 34a and 34b, but with a higher impurity concentration than those of channel layers 34a and 34b. Figure 23 In the example, channel layers 34a and 34b are p-type impurity regions containing p-type impurities, and channel cut-off layer 32 is a p+ type impurity region with a p-type impurity concentration higher than that of channel layers 34a and 34b.

[0140] It should be noted that a channel cut-off layer 32 is not required. However, in order to suppress source-drain leakage current, it is desirable to provide a channel cut-off layer 32, as described later.

[0141] In addition, STIs 35a and 35b are formed in substrate 31 to electrically isolate adjacent elements from each other.

[0142] like Figure 23 As shown, channel layer 34a is connected to substrate 31, on which channel cut-off layer 32 is formed, via semiconductor layer 39. Channel layer 34b is connected to substrate 31 via semiconductor layer 39 and channel layer 34a. In this respect, in Figure 23 In the example, impurity diffusion regions 34c and 34d, containing impurities diffused from the source layer 41a and drain layer 41b, are formed in the channel layers 34a and 34b. Impurity diffusion regions 34c and 34d contain impurities of the same conductivity type as those in the source layer 41a and drain layer 41b (and impurities of different conductivity types than those in the channel layers 34a and 34b), and the impurity concentration in impurity diffusion regions 34c and 34d is lower than the impurity concentration in the source layer 41a and drain layer 41b.

[0143] The source layer 41a serves as the source of a transistor with a fin structure. The source layer 41a is disposed on the side surfaces of the channel layers 34a and 34b above the substrate 31 and is separated from the substrate 31 via the insulating layer 40a.

[0144] The drain layer 41b serves as the drain of a transistor with a fin structure. The drain layer 41b is disposed on the side surface of the channel layers 34a and 34b above the substrate 31, opposite to the side surface on which the source layer 41a is disposed, and is separated from the substrate 31 via the insulating layer 40b.

[0145] Source layer 41a and drain layer 41b contain a different conductivity type than that of channel layers 34a and 34b (in Figure 23 The example in question is an n-type impurity.

[0146] Gate electrode 42 serves as the gate of a transistor with a finned structure, and as... Figure 23 The diagram shows a first portion disposed above the channel layer 34b and a second portion disposed between the substrate 31 and the channel layer 34a. Figure 23 Part 42a) and the third part disposed between channel layer 34a and channel layer 34b Figure 23 Part 42b).

[0147] Here, portion 42a has a side surface 42a1 and a side surface 42a2 opposite to side surface 42a1, both of which face the semiconductor layer 39. Similarly, portion 42b has a side surface 42b1 and a side surface 42b2 opposite to side surface 42b1, both of which face the semiconductor layer 39.

[0148] In addition, a sidewall insulating film 38 is formed on the side surface of the gate electrode 42.

[0149] In this respect, although not shown, a gate insulating film is formed between the portion of the gate electrode 42 above the channel layer 34b and the channel layer 34b, between each portion 42a and 42b and the semiconductor layer 39, between portion 42a and the channel layer 34a, between portion 42b and each channel layer 34a and 34b, and between portion 42a and the channel cut-off layer 32. For example, the gate insulating film is a silicon oxide film, a high-k film, etc.

[0150] For example, semiconductor layer 39 is a silicon epitaxial layer, formed as described later. Semiconductor layer 39 is disposed between insulating layer 40a and each side surface 42a1 and 42b1, and between insulating layer 40b and each side surface 42a2 and 42b2, and semiconductor layer 39 connects channel layers 34a and 34b to substrate 31. In this respect, semiconductor layer 39 may be disposed only on side surfaces 42a1 and 42b1 or only on side surfaces 42a2 and 42b2.

[0151] In addition, such as Figure 23 As shown, the semiconductor layer 39 can be disposed between the channel cut-off layer 32 and each insulating layer 40a and 40b, and between the insulating layers 40a and 40b and the channel layers 34a and 34b. (Refer to...) Figure 23 For example, a sidewall insulating film 38 is formed on the sidewall of the gate electrode 42 above the channel layer 34b, and the top surfaces of the insulating layers 40a and 40b below the sidewall insulating film 38 contact the bottom surfaces of the semiconductor layer 39 formed on the bottom surfaces of the channel layers 34a and 34b.

[0152] Semiconductor layer 39 may contain impurities with a conductivity type opposite to that of channel layers 34a and 34b, impurities with the same conductivity type as that of channel layers 34a and 34b, or impurities with the same conductivity type as that of channel layers 34a and 34b and an impurity concentration that is the same as or lower than that of channel layers 34a and 34b.

[0153] Furthermore, the semiconductor layer 39 can be an undoped layer. In this regard, for example, it contains an impurity concentration of 1.0 × 10⁻⁶. 15 cm -3 Semiconductor layers 39 with lower n-type or p-type impurities can be referred to as substantially undoped layers.

[0154] The aforementioned semiconductor device 30 has a transistor 45a, which has the opposite conductivity type to the fin transistor, and the transistor 45a is formed from a substrate 31, a channel layer 34a, a semiconductor layer 39, and a portion 42a of a gate electrode 42. In the transistor 45a, the substrate 31 serves as one of the source and drain, the channel layer 34a serves as the other of the source and drain, the semiconductor layer 39 serves as the channel, and the portion 42a serves as the gate.

[0155] Furthermore, the semiconductor device 30 also includes a transistor 45b, which has the opposite conductivity type to the fin transistor, and the transistor 45b is formed by a channel layer 34a, a channel layer 34b, a semiconductor layer 39, and a portion 42b of a gate electrode 42. In the transistor 45b, the channel layer 34a serves as one of the source and drain, the channel layer 34b serves as the other of the source and drain, the semiconductor layer 39 serves as the channel, and the portion 42b serves as the gate.

[0156] A similar transistor is positioned on the side where the drain layer 41b is located.

[0157] When the voltage used to turn on the finned transistor is applied to the gate electrode 42, the density of carriers (electrons or holes) of the same impurity conductivity type as the channel layers 34a and 34b decreases in the semiconductor layer 39. As a result, transistors 45a and 45b enter a cutoff state, and channel layers 34a and 34b enter a state of electrical isolation from the substrate 31 (floating state). Therefore, the potential change in channel layers 34a and 34b caused by the gate voltage increases, and thus a large source-drain current is obtained. In other words, the advantages of the SOI structure are achieved.

[0158] On the other hand, when a voltage for turning off the finned transistors is applied to the gate electrode 42, the density of carriers with the same impurity conductivity type as the channel layers 34a and 34b increases in the semiconductor layer 39. Consequently, transistors 45a and 45b enter the on-state, and channel layers 34a and 34b become electrically connected to the substrate 31. This suppresses the floating body effect, which helps reduce characteristic variations, such as threshold voltage variations, caused by charge accumulation depending on the recent operating history in the channel layers 34a and 34b.

[0159] When the transistor with the fin structure is an n-channel MOSFET, channel layers 34a and 34b contain p-type impurities. When semiconductor layer 39 contains n-type impurities and substrate 31 contains p-type impurities, transistors 45a and 45b are p-channel MOSFETs. In this case, when a voltage (a positive voltage higher than or equal to a threshold) is applied to the gate electrode 42 to turn on the transistor with the fin structure, good electrical isolation is achieved between each channel layer 34a and 34b and the substrate.

[0160] On the other hand, when semiconductor layer 39 contains p-type impurities with the same or lower impurity concentration as channel layers 34a and 34b, and substrate 31 contains p-type impurities, transistors 45a and 45b are suppression-type p-channel MOSFETs. In this case, during the application of a positive voltage higher than or equal to a threshold to gate electrode 42, the insulation between each channel layer 34a and 34b and substrate 31 is worse than in the case where transistors 45a and 45b are p-channel MOSFETs. However, when transistors 45a and 45b are suppression-type p-channel MOSFETs, when a voltage (0V) for turning off the finned transistor is applied to gate electrode 42, each channel layer 34a and 34b has a low-resistance connection to substrate 31. This further improves the effect of reducing the floating body effect.

[0161] Furthermore, the source layer 41a and the drain layer 41b are insulated from the substrate 31 by insulating layers 40a and 40b, which prevents source-drain leakage current from flowing through the upper part of the substrate 31 and also reduces the capacitance between the source layer 41a and the substrate 31 and the capacitance between the drain layer 41b and the substrate 31.

[0162] also, Figure 23 Partial top surfaces of insulating layers 40a and 40b beneath the sidewall insulating film 38 contact the bottom surface of semiconductor layer 39 formed on the bottom surfaces of channel layers 34a and 34b. In other words, semiconductor layer 39 is formed on the bottom surfaces of channel layers 34a and 34b beneath the sidewall insulating film 38. Semiconductor layer 39 allows each channel layer 34a and 34b to have substantially increased thickness (length in the vertical direction), which provides the effect of reducing source-drain parasitic resistance.

[0163] It should be noted that the thickness of the channel layers 34a and 34b below the gate electrode 42 remains unchanged, therefore the controllability of the gate on the channel layers 34a and 34b remains unchanged. Here, since the channel layers 34a and 34b of the semiconductor device 30 of the second embodiment are thinner than the channel layer 14 of the semiconductor device 10 of the first embodiment, the effect provided by increasing the thickness using the semiconductor layer 39 in the semiconductor device 30 of the second embodiment is greater than the effect in the semiconductor device 10 of the first embodiment.

[0164] As described above, the semiconductor device 30 of the second embodiment can suppress the buoyancy effect without losing the advantages of the SOI structure.

[0165] In this regard, the example above describes the case where two channel layers 34a and 34b are configured. The number of channel layers is not limited to this, and can be configured to have three or more layers.

[0166] (First comparison example)

[0167] Figure 27 An example of a semiconductor device without a channel cut-off layer is shown. (Using...) Figure 23 The same reference numerals indicate Figure 27 The corresponding components.

[0168] Without the channel cut-off layer 32, leakage current can flow from the source layer 41a through the channel layer 34a, the semiconductor layer 39, and the substrate 31 to the drain layer 41b, such as... Figure 27 As shown by arrow 46.

[0169] Therefore, such as Figure 23 As shown, it is desirable to provide a channel cut-off layer 32.

[0170] (Second comparison example)

[0171] Figure 28 An example of a semiconductor device with a thick insulating layer is shown. (Used with...) Figure 23 The same reference numerals indicate Figure 28 The corresponding components.

[0172] Reference Figure 28 For example, insulation layers 40a and 40b are compared to Figure 23 The insulating layers 40a and 40b are thick. As the thickness of the insulating layers 40a and 40b increases, the source layer 41a and drain layer 41b become thinner, the contact area between the channel layer 34a and each of the source layer 41a and drain layer 41b decreases, and the path through which the source and drain currents flow becomes narrower (higher resistance). For this reason, it is desirable that the insulating layers 40a and 40b are formed to have a thickness such that the top surface of the thicker portion of the insulating layers 40a and 40b is at most about 3 nm higher than the bottom surface of the semiconductor layer 39 (which serves as the channel layer 34a) disposed between the thinner portion of the channel layer 34a and the insulating layers 40a and 40b.

[0173] (Third comparison example)

[0174] Figure 29 An example of a semiconductor device in which the thickness of the insulating layer is less than the lower limit is shown. (Using...) Figure 23 The same reference numerals indicate Figure 29 The corresponding components.

[0175] Reference Figure 29 For example, the top surfaces of insulating layers 40a and 40b are positioned below the bottom surface of channel layer 34a (in Figure 29 In this process, the semiconductor layer 39 forming the bottom surface portion of the channel layer 34a is integrated within the impurity diffusion regions 34c and 34d.

[0176] In this case, the source layer 41a and the drain layer 41b are respectively inserted between the bottom surface of the channel layer 34a and the top surface of the insulating layer 40a, and between the bottom surface of the channel layer 34a and the top surface of the insulating layer 40b. Therefore, the distance between the source layer 41a and the drain layer 41b decreases at the bottom of the channel layer 34a, which may lead to the possibility of source-drain leakage current.

[0177] Therefore, the thickness of insulating layers 40a and 40b is preferably set such that the top surfaces of insulating layers 40a and 40b below the sidewall insulating film 38 are at the same or higher height as the bottom surface of the channel layer 34a (the bottom surface of the semiconductor layer 39 forms the bottom surface portion of the channel layer 34a).

[0178] (Method for manufacturing semiconductor device 30)

[0179] The following describes an example of a method for manufacturing a semiconductor device 30 according to a second embodiment.

[0180] Figures 30 to 40 This is a perspective view illustrating the steps included in a semiconductor device manufacturing method according to a second embodiment.

[0181] In the example of the manufacturing method below, a silicon substrate is used as substrate 31. For example... Figure 30 As shown, firstly, impurities are implanted into the surface of substrate 31 to form a channel cut-off layer 32. The channel cut-off layer 32 contains impurities of the same conductivity type (hereinafter referred to as p-type) as the channel layers 34a and 34b formed later, and the impurity concentration of the channel cut-off layer 32 is higher than that of the channel layers 34a and 34b.

[0182] Subsequently, a silicon-germanium epitaxial layer 33a is formed on the channel cut-off layer 32 by epitaxial growth, and then an undoped silicon channel layer 34a is formed on the epitaxial layer 33a by further epitaxial growth. Then, a silicon-germanium epitaxial layer 33b is formed on the channel layer 34a by epitaxial growth, and then an undoped silicon channel layer 34b is formed on the epitaxial layer 33b by epitaxial growth.

[0183] For example, epitaxial layers 33a and 33b and channel layers 34a and 34b each have a thickness of 4 nm to 8 nm.

[0184] After that, Figure 30 An etching process is performed on the stacked structure shown to form an STI formation region in the substrate 31, for example, with a depth of approximately 30 nm to 50 nm. Then, for example, an HDP-CVD process is performed on the structure after the etching process to embed a silicon oxide film in the STI formation region. Furthermore, a planarization process is performed by CMP and hydrofluoric acid treatment to reprocess the silicon oxide film and form fin structures and STIs 35a and 35b, as shown. Figure 31As shown. STI 35a and 35b are formed such that their top surfaces are flush with the bottom surface of the silicon-germanium epitaxial layer 33a.

[0185] Then, impurities are implanted in channel layers 34a and 34b. Here, p-type impurities are implanted when the transistor with the fin structure is an n-channel MOSFET, and n-type impurities are implanted when the transistor with the fin structure is a p-channel MOSFET. In this respect, impurity implantation in channel layers 34a and 34b can be performed when the channel layers 34a and 34b are formed by epitaxial growth. Furthermore, for example, if p-type impurities are pre-implanted in channel layers 34a and 34b for an n-channel MOSFET during epitaxial growth, n-type impurities can be additionally implanted in the regions of channel layers 34a and 34b where the p-channel MOSFET is to be formed at that time. Similarly, for example, if n-type impurities are pre-implanted in channel layers 34a and 34b for a p-channel MOSFET during epitaxial growth, p-type impurities can be additionally implanted in the regions of channel layers 34a and 34b where the n-channel MOSFET is to be formed at that time.

[0186] In this respect, when p-type impurities are implanted into channel layers 34a and 34b, a channel region (inversion layer) is formed in channel layers 34a and 34b that is converted to n-type when the transistor with the fin structure is in the on state. When n-type impurities are implanted into channel layers 34a and 34b, a channel region is formed in channel layer 14 that is converted to p-type when the transistor with the fin structure is in the on state.

[0187] Then, thermal oxidation is performed to... Figure 31 A gate oxide film (not shown) with a thickness of approximately 1 nm to 3 nm is formed on the side and top surfaces of the stacked structure. Furthermore, a CVD process is performed to sequentially deposit a polysilicon film and a hard mask layer. For example, the hard mask layer is a silicon nitride film or a silicon oxide film. Then, an etching process is performed on the stacked film formed by the polysilicon film and the hard mask layer. In this regard, the etching process is stopped when the etching reaches the gate oxide film, so that the gate oxide film is not removed.

[0188] The etching process includes patterning to allow a polysilicon film to sit transversely over the fin structure, thereby forming a dummy gate 36 and a hard mask 37 disposed on the dummy gate 36, as shown below. Figure 32 As shown. For example, the dummy gate 36 is formed to have a gate width Wg of approximately 10 nm to 14 nm.

[0189] In this regard, in the steps described later, the dummy gate 36 is used by the gate electrode 42 (except for...). Figure 23 (Except for parts 42a and 42b) are replaced.

[0190] Subsequently, in order to form the sidewall insulating film 38, a CVD process is performed, for example, to... Figure 32 A silicon nitride film is deposited on the structure shown. Then, anisotropic etching is performed to etch back the silicon nitride film, leaving it on the sidewalls of the silicon-germanium epitaxial layer 33a, the dummy gate 36, and the hard mask 37, thereby forming a structure as shown. Figure 33 The sidewall insulating film 38 is shown.

[0191] In this respect, the sidewall insulating film 38 has a width Ws, for example, of about 8 nm to 12 nm. Furthermore, the sidewall insulating film 38 formed on the sidewall of the epitaxial layer 33a has a height Hs of 4 nm to 8 nm, which is approximately the same as the thickness of the epitaxial layer 33a.

[0192] In order to form the sidewall insulating film 38 by the above-mentioned etch-back process, the silicon nitride film is deposited in the deposition step to have a thickness of approximately 30% greater than the target thickness Ws.

[0193] Then, using a hard mask 37 and a sidewall insulating film 38 as masks, in Figure 34 Anisotropic etching is performed in the direction indicated by the arrow. As a result, portions of the silicon-germanium epitaxial layers 33a and 33b, and the channel layers 34a and 34b, are removed except for those masked by the hard mask 37 and the sidewall insulating film 38. In this respect, in Figure 34 The dummy gate 36 is not shown in the following figures.

[0194] After anisotropic etching, isotropic etching is performed on the silicon-germanium epitaxial layers 33a and 33b, such that only the central portions of the silicon-germanium epitaxial layers 33a and 33b below the bottom surfaces of the channel layers 34a and 34b (the portions sandwiched between the lower portions of the dummy gate 36) are retained. Figure 35 As shown.

[0195] At this point, if the widths of the remaining epitaxial layers 33a and 33b are much larger than the gate width Wg, the following problem arises: during the subsequent steps of removing the remaining epitaxial layers 33a and 33b and embedding the metal material for the gate electrode 42 into the removed space, as described later, the metal material may not be able to properly fill the space. If this occurs, the gate electrode 42 and the semiconductor layer 39 may separate from each other. Due to this separation, the gate potential cannot affect the semiconductor layer 39, which may prevent the aforementioned transistors 45a and 45b from functioning.

[0196] Therefore, considering process margins, it is desirable to adjust the etching time so that the widths of the remaining epitaxial layers 33a and 33b are the same as or smaller than the gate width Wg. In the following text, it is assumed that the widths of the remaining epitaxial layers 33a and 33b are the same as the gate width Wg.

[0197] Then, using the techniques described above for epitaxial growth, a silicon semiconductor layer 39 is formed on the top surface of the channel cut-off layer 32, the exposed side surfaces of the silicon-germanium epitaxial layers 33a and 33b, the exposed side surface, top surface, and bottom surface of the channel layer 34a, and the exposed side surface and bottom surface of the channel layer 34b, as shown. Figure 36 As shown. The semiconductor layer 39 is formed to have a thickness of, for example, 1 nm to 5 nm.

[0198] As previously described, impurities with the opposite conductivity type to those of channel layers 34a and 34b can be implanted into semiconductor layer 39, or impurities with the same conductivity type as those of channel layers 34a and 34b and whose impurity concentration is lower than or equal to that of channel layers 34a and 34b can be implanted. In this respect, it is not necessary to implant n-type or p-type impurities into semiconductor layer 39. For example, semiconductor layer 39 may contain an impurity concentration of 1.0 × 10⁻⁶. 15 cm -3 In the case of smaller n-type or p-type impurities, semiconductor layer 39 can be considered as an undoped layer with virtually no implanted impurities.

[0199] Then, as Figure 37 As shown, the insulating layers 40a and 40b of the silicon oxide film are embedded in the region between the sidewall insulating film 38 and the region beneath the channel layers 34a and 34b (where the silicon-germanium epitaxial layers 33a and 33b have been removed). Here, to achieve proper embedding, the deposition and etching of the silicon oxide film can be appropriately combined. For example, the deposition of the silicon oxide film can be performed in the order of CVD process, anisotropic etching, and HDP-CVD process. Anisotropic etching can be performed last.

[0200] When the silicon oxide film remains on the sidewall of the semiconductor layer 39 formed on the side surfaces of the channel layers 34a and 34b, the silicon oxide film can be removed, for example, using hydrofluoric acid or the like.

[0201] Then, the semiconductor layer 39 formed on the side surfaces of the channel layers 34a and 34b can be removed (see...). Figure 38 To remove semiconductor layer 39, isotropic or anisotropic etching can be performed using a hard mask 37 and a sidewall insulating film 38 as masks. The reason for removing semiconductor layer 39 formed on the side surfaces of channel layers 34a and 34b will be described later (see [reference]). Figure 41 ).

[0202] Then, as Figure 39As shown, a source layer 41a and a drain layer 41b are formed. The source layer 41a and drain layer 41b are formed by epitaxial growth on two opposing side surfaces of the channel layers 34a and 34b. The shapes of the formed source layer 41a and drain layer 41b depend on the crystal planes, etc., of the two side surfaces of the channel layers 34a and 34b on which the epitaxial growth of the source layer 41a and drain layer 41b is performed. Furthermore, impurities of the opposite conductivity type to those of the channel layers 34a and 34b are implanted into the source layer 41a and drain layer 41b.

[0203] Then, although not shown, a CVD process is performed, for example, to deposit a silicon oxide film as a cover. Figure 39 The interlayer insulating film with the structure shown. Then, CMP is performed to planarize the silicon oxide film.

[0204] When the hard mask 37 is a silicon oxide film, the hard mask 37 is also removed by CMP, exposing the top surface of the polysilicon dummy gate 36.

[0205] When the hard mask 37 is a silicon nitride film, the top surface of the hard mask 37 is exposed by CMP. Subsequently, using a silicon oxide film as an interlayer insulating film as a mask, the hard mask 37 of the silicon nitride film is etched to remove the hard mask 37, thereby exposing the top surface of the polysilicon dummy gate 36.

[0206] Subsequently, the RMG step is performed to replace the dummy gate 36 and the silicon-germanium epitaxial layers 33a and 33b remaining beneath the channel layers 34a and 34b with the gate electrode 42 (see [link to RMG step]). Figure 40 ).in this regard, Figure 40 Channel layers 34a and 34b are not shown in the diagram.

[0207] In the RMG step, the dummy gate 36 is removed by vapor phase etching, wet etching, or the like. During the removal of the dummy gate 36, a gate oxide film (not shown) protects the channel layers 34a and 34b, etc. Then, after removing the gate oxide film by hydrofluoric acid treatment, the epitaxial layers 33a and 33b remaining beneath the channel layers 34a and 34b are removed by isotropic etching. Subsequently, a gate insulating film (not shown) is formed on the surfaces of the channel layers 34a and 34b and the substrate 31 exposed in the spaces where the dummy gate 36 and the epitaxial layers 33a and 33b have been removed. Furthermore, on the gate insulating film, a metal material fills the areas where the dummy gate 36 and the hard mask 37 have been removed, as well as the areas where the remaining epitaxial layers 33a and 33b remain beneath the removed channel layers 34a and 34b. Thus, a... Figure 40 The gate electrode 42 is shown.

[0208] For the gate insulating film and gate electrode 42, for example, the same materials as those provided in the semiconductor device 10 of the first embodiment can be used.

[0209] Using the above manufacturing method, a product such as Figures 22 to 26 The semiconductor device 30 shown.

[0210] The following describes why the semiconductor layer 39 formed on the side surfaces of the channel layers 34a and 34b is removed.

[0211] Figure 41 An example of two adjacent transistors with a finned structure is shown. In this respect, their source layer 41a and drain layer 41b are... Figure 41 Not shown in the image.

[0212] Without removing the semiconductor layer 39 from the side surfaces of the channel layers 34a and 34b, the space between the two transistors with the fin structure for forming the source layer 41a and the drain layer 41b may be too narrow.

[0213] For example, in Figure 41 In the example, each gate electrode 42 has a gate width Wg of approximately 10 nm to 14 nm, and each sidewall insulating film 38 has a width Ws of approximately 8 nm to 12 nm. For example, when the gate-to-gate distance La (distance between adjacent sidewall insulating films) between two transistors with a fin structure is approximately 12 nm, and a semiconductor layer 39 with a thickness of 1 nm to 2 nm is formed on the side surfaces of the channel layers 34a and 34b, the distance Lb between the semiconductor layers on which the source layer 41a and the drain layer 41b are formed is 8 nm to 10 nm, which is 20% to 30% shorter than La.

[0214] Therefore, it is desirable to remove the semiconductor layer 39 on the side surfaces of the channel layers 34a and 34b before forming the source layer 41a and the drain layer 41b.

[0215] However, if the distance from the La pair forming the source layer 41a and drain layer 41b is long enough, it is not necessary to remove the semiconductor layer 39.

[0216] (Fourth comparison example)

[0217] Figure 42 This is a cross-sectional view illustrating an example of a semiconductor device, wherein the gate width below the channel layer is smaller than the gate width above the channel layer.

[0218] In adjustment Figure 35 The etching time shown for isotropic etching to remove silicon-germanium epitaxial layers 33a and 33b is such that the widths of the remaining epitaxial layers 33a and 33b are smaller than the gate width Wg, resulting in the following: Figure 42The structure shown is such that the width Wga of the portions 42a and 42b of the gate electrode 42 below the channel layers 34a and 34b is smaller than the gate width Wg of the portion of the gate electrode 42 above the channel layer 34b.

[0219] (Fifth Comparative Example)

[0220] Figure 43 This is a cross-sectional view showing an example of a semiconductor device, wherein the semiconductor layer is thick and fills between two channel layers and between the lower channel layer and the substrate.

[0221] Reference Figure 43 For example, semiconductor layer 39 is thick and fills the space between channel layers 34a and 34b, and between channel layer 34a and substrate 31. In this case, as... Figure 43 As shown, below the sidewall insulating film 38, insulating layers 40a and 40b are not formed between channel layers 34a and 34b or between channel layer 34a and substrate 31. However, this structure provides the same effect as the semiconductor device 30 of the second embodiment described above.

[0222] The above embodiments have described one aspect of a semiconductor device and a method for manufacturing the semiconductor device. However, these are merely examples and are not limited to the descriptions above.

[0223] For example, Figure 2 and Figure 22 The illustration shows the case where the transistors with finned structures in semiconductor devices 10 and 30 are n-channel MOSFETs. However, these transistors could also be p-channel MOSFETs. In this case, the conductivity type of each element becomes the opposite conductivity type.

[0224] Furthermore, the above example uses a silicon substrate as substrates 11 and 31. The structure is not limited to this. Silicon, germanium, or other materials can be used for substrates 11 and 31. Different materials can be used for each element in semiconductor devices 10 and 30. For example, in the case where substrates 11 and 31 are silicon-germanium substrates, silicon can be used for epitaxial layers 13, 33a, and 33b, and silicon-germanium can be used for channel layers 14, 34a, and 34b.

[0225] According to one aspect, the disclosed embodiments enable the suppression of the buoyancy effect without losing the advantages of the SOI structure.

[0226] All examples and conditional language provided herein are intended for educational purposes to assist the reader in understanding the concepts of this invention and improvements contributed by the inventors, and should not be construed as limiting the scope of these specific examples and conditions. The organization of these examples in the specification does not imply any demonstration of the advantages or disadvantages of the invention. Although one or more embodiments of the invention have been described in detail, it should be understood that various changes, substitutions, and modifications can be made thereto without departing from the spirit and scope of the invention.

Claims

1. A semiconductor device including a transistor having a finned structure, the semiconductor device comprising: A channel layer is disposed above a substrate, and the channel layer is connected to the substrate via a semiconductor layer; A source layer is disposed on a first side surface of the channel layer above the substrate, the source layer being separated from the substrate via a first insulating layer, and the source layer serving as the source of the transistor; A drain layer is disposed on a second side surface of the channel layer above the substrate, opposite to the first side surface. The drain layer is separated from the substrate via a second insulating layer and serves as the drain of the transistor. as well as A gate electrode includes a first portion disposed above the channel layer and a second portion disposed between the substrate and the channel layer, the gate electrode serving as the gate of the transistor, wherein the second portion has a third side surface and a fourth side surface opposite to the third side surface, and the third side surface or the fourth side surface faces the semiconductor layer.

2. The semiconductor device of claim 1, wherein the channel layer is connected to the substrate via the semiconductor layer disposed between the first insulating layer and the third side surface of the second portion or between the second insulating layer and the fourth side surface of the second portion.

3. The semiconductor device of claim 1, wherein the substrate, the channel layer, the semiconductor layer, and the second portion of the gate electrode form a first transistor, the first transistor having an opposite conductivity type to the transistor.

4. The semiconductor device of claim 1, wherein the channel layer comprises a first impurity, and the semiconductor layer comprises a second impurity having a conductivity type opposite to that of the first impurity.

5. The semiconductor device of claim 1, wherein the channel layer comprises a first impurity, the semiconductor layer comprises a second impurity of the same conductivity type as the first impurity, and the impurity concentration of the semiconductor layer is lower than the impurity concentration of the channel layer.

6. The semiconductor device of claim 1, wherein the semiconductor layer is an undoped layer.

7. The semiconductor device according to claim 1, wherein The channel layer contains a first impurity, and An impurity layer is formed on the surface of the substrate. The impurity layer contains a second impurity with the same conductivity type as the first impurity, and the impurity concentration of the impurity layer is higher than that of the channel layer.

8. The semiconductor device of claim 1, further comprising a sidewall insulating film disposed on the sidewall of the first portion, wherein... The top surfaces of the first and second insulating layers below the sidewall insulating film contact the bottom surface of the semiconductor layer disposed on the bottom surface of the channel layer.

9. The semiconductor device of claim 1, wherein the width of the second portion of the gate electrode is smaller than the width of the first portion of the gate electrode.

10. The semiconductor device of claim 1, wherein The trench layer includes a first trench layer and a second trench layer disposed above the first trench layer, and The gate electrode also includes a third portion between the first channel layer and the second channel layer.

11. The semiconductor device of claim 10, wherein the third portion of the first channel layer, the second channel layer, the semiconductor layer, and the gate electrode forms a second transistor, the second transistor having a conductivity type opposite to that of the transistor.

12. The semiconductor device of claim 1, wherein the semiconductor layer is further disposed between the substrate and the first insulating layer and between the substrate and the second insulating layer.

13. The semiconductor device of claim 1, further comprising a sidewall insulating film on the side surface of the gate electrode, wherein... The sidewall insulating film is made of silicon nitride.

14. A method of manufacturing a semiconductor device including a transistor having a finned structure, the method comprising: A trench layer is formed above a substrate, the trench layer being connected to the substrate via a semiconductor layer; A source layer is formed on a first side surface of the channel layer above the substrate, the source layer being separated from the substrate via a first insulating layer, and the source layer serving as the source of the transistor; A drain layer is formed on a second side surface of the channel layer above the substrate, opposite to the first side surface. The drain layer is separated from the substrate via a second insulating layer and serves as the drain of the transistor. as well as A gate electrode is formed, the gate electrode including a first portion disposed above the channel layer and a second portion disposed between the substrate and the channel layer, the gate electrode serving as the gate of the transistor, wherein the second portion has a third side surface and a fourth side surface opposite to the third side surface, and the third side surface or the fourth side surface faces the semiconductor layer.

15. The method of manufacturing a semiconductor device according to claim 14, further comprising: The semiconductor layer is formed on the first or second side surface of the channel layer and on the bottom surface of a portion of the channel layer by epitaxial growth.

16. The method of manufacturing a semiconductor device according to claim 15, further comprising: Remove the semiconductor layer formed on the first side surface and the second side surface of the channel layer.

17. The method of manufacturing a semiconductor device according to claim 14, wherein... The formation of the channel layer includes: The trench layer is formed, comprising a first trench layer and a second trench layer disposed above the first trench layer. The formation of the gate electrode includes forming a gate electrode comprising a first portion disposed above the second channel layer, a second portion disposed between the substrate and the first channel layer, and a third portion disposed between the first channel layer and the second channel layer.

18. The method of manufacturing a semiconductor device according to claim 14, wherein the substrate, the channel layer, the semiconductor layer, and the second portion of the gate electrode form a first transistor, the first transistor having an opposite conductivity type to the transistor.

19. The method of manufacturing a semiconductor device according to claim 14, further comprising: A sidewall insulating film is formed on the side surface of the gate electrode, wherein the material of the sidewall insulating film is a silicon nitride film.

20. The method of manufacturing a semiconductor device according to claim 14, further comprising: A dummy electrode is formed before the gate electrode is formed, and then the gate electrode is used to replace the dummy electrode.

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