Ultrasonic knife handle button recognition circuit and recognition method

Abstract

The present invention discloses an ultrasonic scalpel handle key recognition circuit and recognition method thereof, comprising a carrier signal generating circuit and a signal amplitude detection circuit. The carrier signal generating circuit includes an FPGA and a signal amplification circuit. A third capacitor is connected in series between the carrier signal generating circuit and the signal amplitude detection circuit. The signal amplitude detection circuit includes four operational amplifiers, each with an inverting input electrically connected to the third capacitor and a non-inverting input electrically connected to four nodes of five series resistors. The signal output of the carrier signal generating circuit is electrically connected to a key signal sampling device in a conversion isolation manner. The key signal sampling device includes a key signal sampling circuit and an electrical connector connected to the handle key recognition circuit. The electrical connector adopts a two-electrical connection terminal structure. The circuit structure is simple, can control and identify the corresponding key state, reduce electromagnetic interference, and improve the stability and reliability of the ultrasonic scalpel.

Description

Technical Field

[0001] The present invention relates to an ultrasonic surgical knife, and in particular to an ultrasonic surgical knife handle button recognition circuit and a recognition method thereof used on the ultrasonic surgical knife. Background Art

[0002] As a common human-computer interaction circuit, key circuits are widely used in various industrial and commercial fields. Generally, key switches are used to control the on and off of the circuit, and a processor is used to monitor the circuit level to determine whether the key is pressed or disconnected. Each switch requires a complete control loop. Generally, two cables can be used to monitor one key. The more keys there are, the more cables are required, the higher the installation space requirements, and the more complex the circuit structure is. The electromagnetic compatibility issues generated are also more prominent. Judging the state of the key only by the level will lead to a high misjudgment rate. Summary of the Invention

[0003] The present invention aims to solve the problems of existing ultrasonic scalpel handle button recognition circuits, such as the need to use more cables to control and identify the corresponding button status, the increasing complexity of the circuit structure, the more prominent the electromagnetic compatibility problems, and the high misjudgment rate caused by judging the button status only by the level. The present invention provides an ultrasonic scalpel handle button recognition circuit and method that uses a simple circuit structure to control and identify the corresponding button status, reduce electromagnetic interference, and improve the stability and reliability of the use of ultrasonic scalpels.

[0004] The specific technical solution adopted by the present invention to solve the above technical problems is: an ultrasonic knife handle button recognition circuit, characterized in that: it includes a carrier signal generating circuit and a signal amplitude detection circuit, the carrier signal generating circuit includes an FPGA field programmable gate array for generating a pulse waveform and a signal amplification circuit for amplifying the pulse signal, a third capacitor is connected in series between the carrier signal generating circuit and the signal amplitude detection circuit, the signal output end of the carrier signal generating circuit is electrically connected to the third capacitor, and the signal amplitude detection circuit includes multiple groups of operational amplifiers, each group of operational amplifiers includes 2 operational amplifiers, and each group of operational amplifiers corresponds to one on the ultrasonic knife handle. A key switch is designed in such a way that if the inverting input of one amplifier in each group is electrically connected to a third capacitor, the non-inverting input of the corresponding amplifier in the same group is electrically connected to the corresponding series node of the multiple series resistors. Conversely, if the non-inverting input of one amplifier in each group is electrically connected to the third capacitor, the inverting input of the corresponding amplifier in the same group is electrically connected to the corresponding series node of the multiple series resistors. The signal output of the carrier signal generating circuit is electrically connected to a key signal sampling device via a sampling signal conversion isolation structure. The key signal sampling device includes a key signal sampling circuit located within the ultrasonic handle and an electrical connector connected to the handle key recognition circuit. This simple circuit structure allows control and recognition of the corresponding key status, reducing electromagnetic interference and improving the stability and reliability of the ultrasonic scalpel. Using a carrier wave to determine the status of the handle keys effectively reduces misoperation and improves the device's anti-interference capability. Even in locations with strong electromagnetic interference, the operating circuit is unaffected. This solution also allows the use of the same electrical connector to identify the status of both keys, reducing internal wiring space in the ultrasonic scalpel handle.

[0005] Preferably, the signal amplitude detection circuit includes four operational amplifiers, wherein the inverting input terminals of two operational amplifiers are electrically connected to the third capacitor, and the inverting input terminals of the other two operational amplifiers are electrically connected to the third capacitor; wherein the non-inverting input terminals of two operational amplifiers are respectively electrically connected to the front two series nodes of the five series resistors, and the inverting input terminals of the other two operational amplifiers are respectively electrically connected to the remaining two series nodes of the five series resistors, the front ends of the five series resistors are electrically connected to the power supply 15VDC, and the tail ends of the five series resistors are electrically connected to the power supply ground. This improves the reliability and effectiveness of key detection feedback.

[0006] Preferably, the electrical connector adopts a two-terminal electrical connection structure. At the same time, with this solution, two cables can be used to identify the status of two buttons, reducing the internal wiring space of the ultrasonic knife handle.

[0007] Preferably, the sampling signal conversion isolation structure includes a sampling transformer, a fourth capacitor, an eleventh resistor, and a twelfth resistor. One end of the sampling transformer output is electrically connected to the output end of the carrier signal generating circuit, the other end of the sampling transformer output is electrically connected to the circuit ground, the fourth capacitor is connected in parallel to both ends of the sampling transformer input, the eleventh resistor and the twelfth resistor are connected in series to both ends of the sampling transformer input, and the other ends of the eleventh resistor and the twelfth resistor are electrically connected to the two electrical connection ends of the electrical connector, respectively. This improves the effectiveness of conversion and isolation of key input signal levels.

[0008] Preferably, the five series resistors include a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, and a ninth resistor connected in series in sequence, the other end of the ninth resistor being electrically connected to the circuit ground, and the other end of the fifth resistor being electrically connected to a power supply 15VDC. Furthermore, the fifth resistor has a resistance of 20K, the sixth resistor has a resistance of 7.5K, the seventh resistor has a resistance of 4.99K, the eighth resistor has a resistance of 7.5K, and the ninth resistor has a resistance of 20K, which are equivalent to four trigger switches. Based on the combination of failures, the key is determined to be pressed, thereby improving the effectiveness of the detection and judgment feedback of the signal amplitude detection circuit. This improves the reliability and effectiveness of the detection settings of the non-inverting input terminals of the four operational amplifiers.

[0009] Preferably, the signal amplification circuit is connected in series with a first capacitor at the rear stage and then in series with a voltage divider circuit, the voltage divider circuit being electrically connected to a third capacitor and a key operation input circuit at the rear stage. The voltage divider circuit includes a first resistor and a second resistor connected in series, the series node between the first and second resistors being connected in series with a second capacitor and then electrically connected to the circuit ground, the other end of the first resistor being connected in series with the first capacitor, and the other end of the second resistor being connected in series with the third capacitor. This improves the effectiveness of voltage division and sharpening processing of pulse signals.

[0010] Preferably, the key signal sampling circuit includes multiple parallel single-channel key sampling circuits, each single-channel key sampling circuit uses a switching diode and a key switch connected in series, wherein the anode of each switching diode is electrically connected to an electrical connection end in the electrical connector, and the other switch contact end of each key switch is electrically connected to another electrical connection end in the electrical connector; when two parallel single-channel key sampling circuits are used, the first single-channel key sampling circuit uses the first switching diode and the first key switch connected in series, and the second single-channel key sampling circuit uses the second switching diode and the second key switch connected in series, and the anodes of the first switching diode and the second switching diode are both electrically connected to an electrical connection end in the electrical connector.

[0011] Preferably, the electrical connector is a first plug connector. Only two wire cores are needed to electrically connect to identify the button status on the handle. At the same time, identifying the button status based on the carrier state can effectively reduce interference, eliminate misoperation, and improve the stability of the ultrasonic surgical knife.

[0012] Preferably, the four operational amplifiers include a first operational amplifier, a second operational amplifier, a third operational amplifier, and a fourth operational amplifier. Each operational amplifier outputs four detection signals that are fed back to the FPGA field programmable gate array for judgment. These serve as four trigger switches, determining which key was pressed based on the combination of failures, thereby improving the effectiveness of the detection and judgment feedback of the signal amplitude detection circuit.

[0013] Preferably, the key signal sampling circuit is arranged inside the ultrasonic knife handle using a flexible circuit board structure, thereby improving the installation, reliability and effectiveness of the key signal sampling circuit in the limited space inside the ultrasonic knife handle.

[0014] Another invention object of the present invention application is to provide an ultrasonic knife handle button recognition circuit identification method, characterized in that: in the signal amplitude detection circuit provided in the ultrasonic knife handle button recognition circuit described in one of the above technical solutions, the voltage at the non-inverting input terminal of the first operational amplifier is set to 9-12V, the voltage at the non-inverting input terminal of the second operational amplifier is set to 7-8.5V, the voltage at the inverting input terminal of the third operational amplifier is set to 5-7V, and the voltage at the inverting input terminal of the fourth operational amplifier is set to 3-5V;

[0015] When the MAX button of the ultrasonic handle is pressed, the first operational amplifier keeps outputting a high level, and when the MIN button of the ultrasonic handle is pressed, the fourth operational amplifier keeps outputting a high level;

[0016] When the first operational amplifier keeps outputting a low level, the second operational amplifier keeps outputting a low level, the third operational amplifier keeps outputting a high level, and the fourth operational amplifier keeps outputting a high level, it indicates that the MIN button of the ultrasonic handle is pressed;

[0017] When the first operational amplifier keeps outputting high level, the second operational amplifier keeps outputting high level, the third operational amplifier keeps outputting low level, and the fourth operational amplifier keeps outputting low level, it indicates that the MAX button of the ultrasonic handle is pressed;

[0018] Other cases indicate that no button on the ultrasonic handle is pressed. The FPGA can determine the button status by judging the output level of the operational amplifier.

[0019] The MIN key corresponds to the second push button switch, and the MAX key corresponds to the first push button switch.

[0020] The present invention has the following beneficial effects: a simple circuit structure can be used to control and identify the status of corresponding buttons, reducing electromagnetic interference and improving the stability and reliability of ultrasonic surgical scalpels. Using a carrier wave to determine the status of the handle buttons effectively reduces misoperation and improves the device's anti-interference capability. Even in areas with strong electromagnetic interference, the operating circuit is not affected. This solution also allows the use of two cables to identify the status of two buttons, reducing the internal wiring space of the ultrasonic scalpel handle. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0022] Figure 1 The present invention is a schematic diagram of the circuit structure of an ultrasonic knife handle button recognition circuit and its recognition method.

[0023] Figure 2 The present invention is a schematic diagram of a 2KHZ pulse waveform generated by FPGA in an ultrasonic knife handle button recognition circuit and recognition method thereof.

[0024] Figure 3 It is a schematic diagram of a pulse waveform corresponding to the upper end of the third capacitor C3 under the condition that neither the button K1 nor the button K2 is pressed in an ultrasonic knife handle button recognition circuit and recognition method of the present invention.

[0025] Figure 4 This is a schematic diagram of a voltage waveform when the lower end of the third electrical appliance C3 provides a 7.5V floating voltage to the third capacitor C3 in an ultrasonic knife handle button recognition circuit and recognition method thereof of the present invention.

[0026] Figure 5 It is a schematic diagram of the voltage waveform corresponding to the lower end of the third capacitor C3 when the corresponding K2 button is pressed in the ultrasonic knife handle button recognition circuit and recognition method of the present invention.

[0027] Figure 6 It is a schematic diagram of the voltage waveform corresponding to the lower end of the third capacitor C when the corresponding K1 button is pressed in the ultrasonic knife handle button recognition circuit and recognition method of the present invention. DETAILED DESCRIPTION

[0028] Example 1:

[0029] Figure 1 、 Figure 2 、 Figure 3 、 Figure 4 、 Figure 5 、 Figure 6In the embodiment shown, an ultrasonic knife handle button recognition circuit 01 includes a carrier signal generating circuit 10 and a signal amplitude detection circuit 20. The carrier signal generating circuit 10 includes an FPGA 11 field programmable gate array for generating a pulse waveform and a signal amplifying circuit 12 for amplifying the pulse signal. A third capacitor C3 is connected in series between the carrier signal generating circuit 10 and the signal amplitude detection circuit 20. The signal output end of the carrier signal generating circuit 10 is electrically connected to the third capacitor C3. The signal amplitude detection circuit 20 includes four operational amplifiers, wherein the inverting input ends of two operational amplifiers are electrically connected to the third capacitor C3, and the inverting input ends of the other two operational amplifiers are electrically connected to the third capacitor; wherein the non-inverting input ends of the two operational amplifiers are electrically connected to the front end two resistor series nodes of the five series resistors, respectively, and the inverting input ends of the other two operational amplifiers are electrically connected to the remaining two series nodes of the five series resistors, respectively. The front ends of the five series resistors are electrically connected to the power supply 15VDC, and the tail ends of the five series resistors are electrically connected to the power ground. Of course, it is also possible to use a signal amplitude detection circuit including multiple groups of operational amplifiers, each group of operational amplifiers including 2 operational amplifiers, each group of operational amplifiers corresponding to a push button switch on the ultrasonic knife handle, and the inverting input terminal of one of the amplifiers in each group is electrically connected to the third capacitor, and the corresponding non-inverting input terminal of another amplifier in the same group is electrically connected to the corresponding series node of multiple series resistors; conversely, the non-inverting input terminal of one of the amplifiers in each group is electrically connected to the third capacitor, and the corresponding inverting input terminal of another amplifier in the same group is electrically connected to the corresponding series node of multiple series resistors; the signal output terminal of the carrier signal generating circuit 10 is electrically connected to the key signal sampling device through a sampling signal conversion isolation structure, and the key signal sampling device includes a key signal sampling circuit 40 provided in the ultrasonic handle and an electrical connector J1 connected to the handle key identification circuit, and the electrical connector J1 adopts a two-electrical connection terminal structure. The sampling signal conversion isolation structure includes a sampling transformer T1, a fourth capacitor C4, an eleventh resistor R11, and a twelfth resistor R12. One end of the output end of the sampling transformer T1 is electrically connected to the output end of the carrier signal generating circuit 10, and the other end of the output end of the sampling transformer T1 is electrically connected to the circuit ground. The fourth capacitor C4 is connected in parallel to both ends of the input end of the sampling transformer T1, and the eleventh resistor R11 and the twelfth resistor R12 are connected in series to both ends of the input end of the sampling transformer T1, respectively. The other ends of the eleventh resistor and the twelfth resistor are electrically connected to the two electrical connection ends of the electrical connector, respectively. The five series resistors include the fifth resistor R5, the sixth resistor R6, the seventh resistor R7, the eighth resistor R8 and the ninth resistor R9 connected in series in sequence, where the resistance of the fifth resistor R5 is 20K, the resistance of the sixth resistor R6 is 7.5K, the resistance of the seventh resistor R7 is 4.99K, the resistance of the eighth resistor R8 is 7.5K, and the resistance of the ninth resistor R9 is 20K. The other end of the ninth resistor is electrically connected to the circuit ground, and the other end of the fifth resistor is electrically connected to the power supply 15VDC.The inverting input terminal of each operational amplifier is electrically connected to the series node of the third resistor R3 and the fourth resistor R4. The other end of the third resistor is electrically connected to the power supply 15VDC, and the other end of the fourth resistor is electrically connected to the circuit ground. The signal amplification circuit is connected in series with the first capacitor C1 at the rear stage, and then in series with the voltage divider circuit 30. The rear stage of the voltage divider circuit 30 is electrically connected to the third capacitor C3 and the key operation input circuit. The key operation input circuit includes a sampling signal conversion isolation structure and a key signal sampling device. The voltage divider circuit includes a first resistor R1 and a second resistor R2 connected in series. The series node of the first resistor R1 and the second resistor R2 is connected in series with the second capacitor C2 and then electrically connected to the circuit ground. The other end of the first resistor R1 is connected in series with the first capacitor C1, and the other end of the second resistor R2 is connected in series with the third capacitor C3. The key signal sampling circuit 40 includes multiple parallel single-channel key sampling circuits. Each single-channel key sampling circuit uses a switching diode and a key switch connected in series, wherein the anode of each switching diode is electrically connected to an electrical connection terminal in the electrical connector, and the other switch contact terminal of each key switch is electrically connected to another electrical connection terminal in the electrical connector. When two parallel single-channel key sampling circuits are used, the first single-channel key sampling circuit uses a first switching diode D1 and a first key switch K1 connected in series, and the second single-channel key sampling circuit uses a second switching diode D2 and a second key switch K2 connected in series, with the anodes of the first and second switching diodes both electrically connected to an electrical connection terminal in the electrical connector. The electrical connector uses a first plug connector J1. The first plug connector J1 is a plug connector having two plug-in connection terminals. The four operational amplifiers include a first operational amplifier Q1, a second operational amplifier Q2, a third operational amplifier Q3, and a fourth operational amplifier Q4. Each operational amplifier outputs four detection signals that are fed back to the FPGA field programmable gate array for judgment (see. Figure 1 The output terminals HP_SW_DETECT_LEVEL1, HP_SW_DETECT_LEVEL2, HP_SW_DETECT_LEVEL3, and HP_SW_DETECT_LEVEL4 are shown in FIG. The key signal sampling circuit 40 is disposed inside the ultrasonic knife handle using a flexible circuit board structure. The inverting input terminals of the first operational amplifier Q1 and the second operational amplifier Q2 are both electrically connected to the series node of the third resistor and the fourth resistor, and the non-inverting input terminals of the third operational amplifier Q3 and the fourth operational amplifier Q4 are both electrically connected to the series node of the third resistor and the fourth resistor. The other end of the third resistor is electrically connected to the power supply 15VDC, and the other end of the fourth resistor is electrically connected to the circuit ground.

[0030] Figure 3As shown in the figure, the pulse signal generated by the FPGA passes through the signal amplifier, amplifying the amplitude of the pulse signal from 3.3V to 15V. The amplified pulse signal is sharpened by the first capacitor C1, divided by the first resistor R1 and the second resistor R2, and further sharpened by the third capacitor C3 to form the pulse waveform. Under the condition that neither the first push switch K1 nor the second push switch K2 is pressed, the pulse waveform corresponding to the upper end of the third capacitor C3 should be as follows: Figure 3 shown.

[0031] Figure 4 As shown, the lower end of the third capacitor C3 is connected between the third resistor R3 and the fourth resistor R4, providing a floating voltage of 7.5V for the third capacitor C3. The voltage waveform at the lower end of the third capacitor C3 is as follows: Figure 4 shown.

[0032] Figure 5 As shown in the figure, press the MIN button on the ultrasonic knife handle, corresponding to Figure 1 When the second switch button K2 is pressed, the drive circuit, D2, and K2 form a working circuit. Only the reverse voltage can pass through the capacitor C3. The voltage waveform corresponding to the lower end of C3 is as follows: Figure 5 shown.

[0033] Figure 6 As shown, press the MAX button on the ultrasonic knife handle, corresponding to Figure 1 When the first switch button K1 is pressed, the drive circuit, D1, and K1 form a working circuit. Only the positive voltage can pass through the capacitor C3. The voltage waveform at the bottom of C3 is as follows: Figure 6 shown.

[0034] Figure 1 The drive circuit shown belongs to the circuit of other parts of the system and is equivalent to a common end of the key circuit.

[0035] Example 2:

[0036] Figure 1 、 Figure 2 、 Figure 3 、 Figure 4 、 Figure 5 、 Figure 6 In the illustrated embodiment, a method for identifying a button recognition circuit for an ultrasonic scalpel handle is provided. In the signal amplitude detection circuit provided in the ultrasonic scalpel handle button recognition circuit described in Example 1, the voltage at the non-inverting input terminal of the first operational amplifier is set to 10V, the voltage at the non-inverting input terminal of the second operational amplifier is set to 8.125V, the voltage at the inverting input terminal of the third operational amplifier is set to 6.875V, and the voltage at the inverting input terminal of the fourth operational amplifier is set to 5V.

[0037] When the MAX button of the ultrasonic handle is pressed, the first operational amplifier Q1 keeps outputting a high level, and when the MIN button of the ultrasonic handle is pressed, the fourth operational amplifier Q4 keeps outputting a high level;

[0038] When the first operational amplifier Q1 keeps outputting a low level, the second operational amplifier Q2 keeps outputting a low level, the third operational amplifier Q3 keeps outputting a high level, and the fourth operational amplifier Q4 keeps outputting a high level, it indicates that the MIN button set on the ultrasonic handle is pressed;

[0039] When the first operational amplifier Q1 keeps outputting a high level, the second operational amplifier Q2 keeps outputting a high level, the third operational amplifier Q3 keeps outputting a low level, and the fourth operational amplifier Q4 keeps outputting a low level, it indicates that the MAX button set on the ultrasonic handle is pressed;

[0040] Other cases indicate that no button on the ultrasonic handle is pressed. The FPGA can determine the button status by judging the output level of the operational amplifier.

[0041] The MIN button provided on the ultrasonic handle corresponds to the second button switch, and the MAX button provided on the ultrasonic handle corresponds to the first button switch.

[0042] In the description of the positional relationship of the present invention, terms such as "inside", "outside", "up", "down", "left", "right", etc. that indicate orientation or positional relationship are based on the orientation or positional relationship shown in the drawings. They are only for the convenience of describing the embodiments and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation. Therefore, they should not be understood as limiting the present invention.

[0043] The above content and structure describe the basic principles, main features, and advantages of the product of the present invention, which should be understood by those skilled in the art. The above examples and description are merely illustrative of the principles of the present invention. Various changes and modifications may be made to the present invention without departing from the spirit and scope of the present invention, and such changes and modifications are intended to be within the scope of the invention. The scope of protection claimed in the present invention is defined by the appended claims and their equivalents.

Claims

1. A button recognition circuit for an ultrasonic knife handle, characterized by: It includes a carrier signal generating circuit and a signal amplitude detection circuit. The carrier signal generating circuit includes an FPGA field programmable gate array for generating a pulse waveform and a signal amplifying circuit for amplifying the pulse signal. A third capacitor is connected in series between the carrier signal generating circuit and the signal amplitude detection circuit. The signal output end of the carrier signal generating circuit is electrically connected to the third capacitor. The signal amplitude detection circuit includes multiple groups of operational amplifiers, each group of operational amplifiers includes two operational amplifiers, and each group of operational amplifiers corresponds to a key switch on the ultrasonic knife handle. The inverting input end of one of the amplifiers in each group is electrically connected to the third capacitor, and the corresponding non-inverting input end of another amplifier in the same group is electrically connected to the corresponding series node of the multiple series resistors; conversely, the non-inverting input end of one of the amplifiers in each group is electrically connected to the third capacitor, and the corresponding inverting input end of another amplifier in the same group is electrically connected to the corresponding series node of the multiple series resistors; the signal output end of the carrier signal generating circuit is electrically connected to a key signal sampling device through a sampling signal conversion isolation structure. The key signal sampling device includes a key signal sampling circuit provided in the ultrasonic handle and an electrical connector connected to the handle key recognition circuit; The signal amplitude detection circuit includes four operational amplifiers, wherein the inverting input terminals of two operational amplifiers are electrically connected to the third capacitor, and the non-inverting input terminals of the other two operational amplifiers are electrically connected to the third capacitor; wherein the non-inverting input terminals of two operational amplifiers are respectively electrically connected to the front two series nodes of the five series resistors, and the inverting input terminals of the other two operational amplifiers are respectively electrically connected to the remaining two series nodes of the five series resistors, the front ends of the five series resistors are electrically connected to the power supply 15VDC, and the tail ends of the five series resistors are electrically connected to the power supply ground; The electrical connector adopts a two-electrical connection end structure.

2. The ultrasonic knife handle button recognition circuit according to claim 1, characterized in that: The sampling signal conversion isolation structure includes a sampling transformer, a fourth capacitor, an eleventh resistor and a twelfth resistor. One end of the sampling transformer output is electrically connected to the output end of the carrier signal generating circuit, the other end of the sampling transformer output is electrically connected to the circuit ground, the fourth capacitor is connected in parallel at both ends of the sampling transformer input, the eleventh resistor and the twelfth resistor are connected in series at both ends of the sampling transformer input, and the other ends of the eleventh resistor and the twelfth resistor are electrically connected to the two electrical connection ends of the electrical connector, respectively.

3. The ultrasonic knife handle button recognition circuit according to claim 1, characterized in that: The five series resistors include the fifth resistor, the sixth resistor, the seventh resistor, the eighth resistor and the ninth resistor connected in series in sequence, the other end of the ninth resistor is electrically connected to the circuit ground, and the other end of the fifth resistor is electrically connected to the power supply 15VDC.

4. The ultrasonic knife handle button recognition circuit according to claim 1, characterized in that: The signal amplification circuit is connected in series with the first capacitor at the rear stage and then in series with the voltage divider circuit. The voltage divider circuit is electrically connected to the third capacitor and the key operation input circuit at the rear stage. The key operation input circuit includes a sampling signal conversion isolation structure and a key signal sampling device. The voltage divider circuit includes a first resistor and a second resistor connected in series. The series node between the first resistor and the second resistor is connected in series with the second capacitor and then electrically connected to the circuit ground. The other end of the first resistor is connected in series with the first capacitor, and the other end of the second resistor is connected in series with the third capacitor.

5. The ultrasonic knife handle button recognition circuit according to claim 1, characterized in that: The key signal sampling circuit includes multiple parallel single-channel key sampling circuits, each single-channel key sampling circuit uses a switching diode and a key switch connected in series, wherein the anode of each switching diode is electrically connected to an electrical connection end in the electrical connector, and the other switch contact end of each key switch is electrically connected to another electrical connection end in the electrical connector; when two parallel single-channel key sampling circuits are used, the first single-channel key sampling circuit uses the first switching diode and the first key switch connected in series, and the second single-channel key sampling circuit uses the second switching diode and the second key switch connected in series, and the anodes of the first switching diode and the second switching diode are both electrically connected to an electrical connection end in the electrical connector.

6. The ultrasonic knife handle button recognition circuit according to claim 1, characterized in that: The four operational amplifiers include a first operational amplifier, a second operational amplifier, a third operational amplifier and a fourth operational amplifier. Each operational amplifier outputs four detection signals that are fed back to the FPGA field programmable gate array for judgment.

7. The ultrasonic knife handle button recognition circuit according to claim 1 or 4, characterized in that: The key signal sampling circuit adopts a flexible circuit board structure and is arranged inside the ultrasonic knife handle.

8. A method for identifying a button recognition circuit of an ultrasonic knife handle, characterized by: In the signal amplitude detection circuit provided in the ultrasonic knife handle button recognition circuit according to any one of claims 1 to 7, the voltage at the non-inverting input terminal of the first operational amplifier is set to 9 to 12 V, the voltage at the non-inverting input terminal of the second operational amplifier is set to 7 to 8.5 V, the voltage at the inverting input terminal of the third operational amplifier is set to 5 to 7 V, and the voltage at the inverting input terminal of the fourth operational amplifier is set to 3 to 5 V; When the MAX button of the ultrasonic handle is pressed, the first operational amplifier keeps outputting a high level, and when the MIN button of the ultrasonic handle is pressed, the fourth operational amplifier keeps outputting a high level; When the first operational amplifier keeps outputting a low level, the second operational amplifier keeps outputting a low level, the third operational amplifier keeps outputting a high level, and the fourth operational amplifier keeps outputting a high level, it indicates that the MIN button of the ultrasonic handle is pressed; When the first operational amplifier keeps outputting high level, the second operational amplifier keeps outputting high level, the third operational amplifier keeps outputting low level, and the fourth operational amplifier keeps outputting low level, it indicates that the MAX button of the ultrasonic handle is pressed; Other cases indicate that no button on the ultrasonic handle is pressed. The FPGA can determine the button status by judging the output level of the operational amplifier. The MIN key corresponds to the second push button switch, and the MAX key corresponds to the first push button switch.

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