Semiconductor structure manufacturing method and semiconductor structure

Abstract

The present disclosure provides a method for fabricating a semiconductor structure and a semiconductor structure. The method includes forming a first stacked structure, forming a first target structure within the first stacked structure, forming a second stacked structure on the first stacked structure, and forming a second target structure in contact with the first target structure within the second stacked structure. In the present disclosure, the process of forming the target structure is divided into two processes: forming the first target structure and forming the second target structure. This reduces the depth of each process of forming the target structure and reduces the impact of an excessively large aspect ratio on the process.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a method for manufacturing a semiconductor structure and a semiconductor structure. Background Art

[0002] As semiconductor structures become more integrated, capacitor structures are developing toward higher aspect ratios and higher densities. During capacitor manufacturing, regions with different densities etch at different rates. When the aspect ratio of a capacitor structure is too large, these regions may exhibit different process progress, leading to under-etching in some areas and over-etching in others, impacting product yield. Summary of the Invention

[0003] The following is an overview of the subject matter described in detail in this disclosure. This overview is not intended to limit the scope of the claims.

[0004] The present disclosure provides a method for manufacturing a semiconductor structure and a semiconductor structure.

[0005] A first aspect of the present disclosure provides a method for manufacturing a semiconductor structure, the method comprising: forming a first stacking structure, forming a first target structure in the first stacking structure, forming a second stacking structure on the first stacking structure, and forming a second target structure in contact with the first target structure in the second stacking structure.

[0006] According to some embodiments of the present disclosure, the step of forming a first stacked structure and forming a first target structure in the first stacked structure includes:

[0007] forming a first sacrificial layer and a first supporting layer in sequence;

[0008] patterning the first sacrificial layer and the first supporting layer to form a first target pattern hole in the first stacked structure;

[0009] The first target structure is formed in the first target pattern hole.

[0010] According to some embodiments of the present disclosure, the step of forming the first target structure in the first target pattern hole includes:

[0011] A conductive material is deposited in the first target pattern hole to form the first target structure, wherein a top surface of the first target structure is not higher than a top surface of the first supporting layer.

[0012] According to some embodiments of the present disclosure, the step of forming a second stacked structure and forming a second target structure in the second stacked structure includes:

[0013] forming a second supporting layer and a dielectric layer in sequence on the first stacked structure;

[0014] patterning the second supporting layer and the dielectric layer to form a second target pattern hole in the second stacked structure, wherein the second target pattern hole at least exposes a portion of the first target structure;

[0015] The second target structure is formed in the second target pattern hole.

[0016] According to some embodiments of the present disclosure, the step of forming the dielectric layer includes:

[0017] A second sacrificial layer is formed on the second supporting layer, and a third sacrificial layer is formed on the second sacrificial layer.

[0018] According to some embodiments of the present disclosure, the step of forming the second target structure in the second target pattern hole includes:

[0019] A conductive material is deposited in the second target pattern hole to form the second target structure, where the second target structure covers the exposed portion of the first target structure.

[0020] According to some embodiments of the present disclosure, the manufacturing method further includes:

[0021] A portion of the second stacked structure and a portion of the first stacked structure are removed, and the remaining second stacked structure and the first stacked structure form a support structure.

[0022] According to some embodiments of the present disclosure, removing part of the second stacked structure and part of the first stacked structure includes:

[0023] forming a first mask layer, wherein the first mask layer covers a portion of a top surface of the second stacked structure and a portion of a top surface of the second target structure;

[0024] sequentially removing a portion of the third sacrificial layer, the second sacrificial layer, and a portion of the second supporting layer of the second stacked structure according to the first mask layer;

[0025] sequentially removing a portion of the first supporting layer and the first sacrificial layer of the first stacked structure according to the first mask layer;

[0026] The remaining first supporting layer and the second supporting layer form the supporting structure.

[0027] According to some embodiments of the present disclosure, the method for manufacturing the semiconductor structure includes:

[0028] providing a substrate, the substrate comprising a capacitor contact;

[0029] The first stacked structure is formed on the substrate.

[0030] According to some embodiments of the present disclosure, forming a first target structure in the first stacked structure includes:

[0031] The first target structure is formed, wherein the first target structure is in contact with the capacitor contact portion.

[0032] According to some embodiments of the present disclosure, the manufacturing method further includes:

[0033] forming a dielectric layer, the dielectric layer covering at least the exposed sidewalls of the first target structure, the exposed sidewalls of the second target structure, and a top surface of the second target structure;

[0034] An upper electrode layer is formed, where the upper electrode layer covers the dielectric layer.

[0035] A first aspect of the present disclosure provides a semiconductor structure, comprising:

[0036] a lower electrode, the lower electrode comprising a first target structure and a second target structure stacked on the first target structure;

[0037] A supporting structure includes an intermediate supporting layer, wherein the intermediate supporting layer covers a portion of a joint between the connecting surfaces of the first target structure and the second target structure.

[0038] According to some embodiments of the present disclosure, the semiconductor structure further includes:

[0039] An upper supporting layer is disposed on top of the second target structure and covers a portion of a sidewall of the second target structure.

[0040] According to some embodiments of the present disclosure, the semiconductor structure further includes:

[0041] a dielectric layer, the dielectric layer covering at least the exposed sidewalls of the first target structure, the exposed sidewalls of the second target structure, the top surface of the second target structure, and the support structure;

[0042] An upper electrode layer covers the dielectric layer.

[0043] According to some embodiments of the present disclosure, the semiconductor structure further includes:

[0044] a substrate comprising a capacitor contact;

[0045] The first target structure is disposed on the capacitor contact portion, and the first target structure is in contact with the capacitor contact portion.

[0046] In the semiconductor structure preparation method and semiconductor structure provided by the embodiments of the present disclosure, the process of forming the target structure is divided into two processes: forming the first target structure and forming the second target structure, which reduces the depth of each process of forming the target structure and reduces the impact of the process having an excessively large aspect ratio on the process.

[0047] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] The accompanying drawings, which are incorporated into and constitute a part of the specification, illustrate embodiments of the present disclosure and, together with the description, are used to explain the principles of the embodiments of the present disclosure. In these drawings, similar reference numerals are used to represent similar elements. The drawings described below are some embodiments of the present disclosure, not all embodiments. For those skilled in the art, other drawings can be derived from these drawings without inventive effort.

[0049] Figure 1 The figure is a flow chart of a method for manufacturing a semiconductor structure according to an exemplary embodiment.

[0050] Figure 2 The present invention is a flowchart of forming a first target structure in a method for manufacturing a semiconductor structure according to an exemplary embodiment.

[0051] Figure 3 The present invention is a flowchart of forming a second target structure in a method for manufacturing a semiconductor structure according to an exemplary embodiment.

[0052] Figure 4 The figure is a flow chart of a method for manufacturing a semiconductor structure according to an exemplary embodiment.

[0053] Figure 5 The present invention is a flowchart of removing a portion of the second stacked structure and a portion of the first stacked structure in a method for manufacturing a semiconductor structure according to an exemplary embodiment.

[0054] Figure 6 The figure is a flow chart of a method for manufacturing a semiconductor structure according to an exemplary embodiment.

[0055] Figure 7 FIG. 1 is a schematic diagram showing the formation of a first stacked structure according to an exemplary embodiment.

[0056] Figure 8 is a schematic diagram showing a patterned first buffer layer according to an exemplary embodiment.

[0057] Figure 9 FIG. 1 is a schematic diagram showing forming a first target pattern hole according to an exemplary embodiment.

[0058] Figure 10 yes Figure 9 A top view of a first target pattern hole is formed.

[0059] Figure 11 FIG. 4 is a schematic diagram showing forming a first conductive layer according to an exemplary embodiment.

[0060] Figure 12 FIG. 1 is a schematic diagram showing forming a first target structure according to an exemplary embodiment.

[0061] Figure 13 FIG. 1 is a schematic diagram showing the formation of a first stacked structure according to an exemplary embodiment.

[0062] Figure 14 is a schematic diagram showing a patterned second buffer layer according to an exemplary embodiment.

[0063] Figure 15 FIG. 4 is a schematic diagram showing forming a second target pattern hole according to an exemplary embodiment.

[0064] Figure 16 FIG. 4 is a schematic diagram showing forming a second conductive layer according to an exemplary embodiment.

[0065] Figure 17 FIG. 4 is a schematic diagram showing forming a second target structure according to an exemplary embodiment.

[0066] Figure 18 FIG. 4 is a schematic diagram showing forming a first mask layer according to an exemplary embodiment.

[0067] Figure 19 yes Figure 18 Top view of .

[0068] Figure 20 FIG. 1 is a schematic diagram showing removal of a portion of the third sacrificial layer according to an exemplary embodiment.

[0069] Figure 21 FIG. 1 is a schematic diagram showing removal of the second sacrificial layer according to an exemplary embodiment.

[0070] Figure 22 FIG. 1 is a schematic diagram showing forming a support structure according to an exemplary embodiment.

[0071] Figure 23 FIG. 1 is a schematic diagram showing removing a portion of the first sacrificial layer according to an exemplary embodiment.

[0072] Figure 24 FIG. 1 is a schematic diagram showing the formation of a dielectric layer according to an exemplary embodiment.

[0073] Figure 25 FIG. 4 is a schematic diagram showing the formation of an upper electrode layer according to an exemplary embodiment.

[0074] Figure 26 FIG. 1 is a schematic diagram showing the removal of the entire third sacrificial layer according to an exemplary embodiment.

[0075] Figure 27 yes Figure 26 Top view of .

[0076] Figure 28 FIG. 1 is a schematic diagram showing the formation of a dielectric layer according to an exemplary embodiment.

[0077] Figure 29 FIG. 4 is a schematic diagram showing the formation of an upper electrode layer according to an exemplary embodiment.

[0078] Reference numerals:

[0079] 01. Dense area; 02. Non-dense area; 10. First stacked structure; 11. First sacrificial layer; 12. First supporting layer; 100. Lower electrode; 101. First target graphic hole; 110. First target structure; 111. First conductive layer; 120. Second target structure; 121. Second conductive layer; 20. Second stacked structure; 21. Second supporting layer; 22. Dielectric layer; 200. Support structure; 201. Second target graphic hole; 210. Support unit; 221. Second sacrificial layer; 222. Third sacrificial layer; 30. Substrate; 300. Upper supporting layer; 31. Isolation layer; 40. Capacitor contact; 400. Dielectric layer; 50. First buffer layer; 51. First target pattern; 500. Upper electrode layer; 60. Patterned layer; 70. Second buffer layer; 71. Second target pattern; 80. First mask layer; 81. First pattern. DETAILED DESCRIPTION

[0080] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions in the disclosed embodiments will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, rather than all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of the present disclosure. It should be noted that, in the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other.

[0081] In an exemplary embodiment of the present disclosure, a method for manufacturing a semiconductor structure is provided. Figure 1 As shown, Figure 1 FIG2 shows a flow chart of a method for manufacturing a semiconductor structure according to an exemplary embodiment of the present disclosure. Figure 7-Figure 29 The schematic diagram of each stage of the semiconductor structure manufacturing method is shown below. Figure 7-Figure 29The fabrication method of semiconductor structures is introduced.

[0082] This embodiment does not limit the semiconductor structure. The semiconductor structure will be described below using a dynamic random access memory (DRAM) as an example, but this embodiment is not limited thereto. The semiconductor structure in this embodiment may also be other structures.

[0083] like Figure 1 As shown, a method for manufacturing a semiconductor structure provided by an exemplary embodiment of the present disclosure includes the following steps:

[0084] Step S110 : forming a first stacked structure, and forming a first target structure in the first stacked structure.

[0085] In this embodiment, if Figure 7 As shown, the first stacked structure 10 is formed on a substrate 30, which is a semiconductor substrate including a silicon-containing material. The substrate 30 may include a silicon substrate, a silicon germanium substrate or an SOI (silicon on insulator) substrate. In one example, referring to Figure 7 An isolation layer 31 is provided on the top surface of the substrate 30 .

[0086] like Figure 7 As shown, the substrate 30 includes a capacitor contact portion 40, a first stacked structure 10 is formed on the substrate 30, and a portion of the first stacked structure 10 is removed, as shown in FIG. Figure 12 As shown, a first target structure 110 is formed in the first stacked structure 10 , and the first target structure 110 is in contact with the capacitor contact portion 40 .

[0087] Step S120 : forming a second stacked structure on the first stacked structure, and forming a second target structure in contact with the first target structure in the second stacked structure.

[0088] like Figure 13 As shown, a second stacked structure 20 is formed, and the second stacked structure 20 covers the top surface of the first stacked structure 10 and the top surface of the first target structure 110. Figure 17 As shown, refer to Figure 13 , remove part of the second stacked structure 20, form a second target structure 120 in the second stacked structure 20, the bottom surface of the second target structure 120 at least covers part of the top surface of the first target structure 110, the second target structure 120 and the first target structure 110 are connected, and the first target structure 110 and the second target structure 120 serve as a target structure together.

[0089] The manufacturing method of this embodiment divides the process of forming the target structure into two processes: forming the first target structure and forming the second target structure, reducing the depth of each process and reducing the impact of an excessively large aspect ratio on the process.

[0090] According to an exemplary embodiment, this embodiment is an explanation of the implementation of the above step S110. During the implementation process, Figure 2 As shown, forming a first stacked structure and forming a first target structure in the first stacked structure includes the following steps:

[0091] Step S111: forming a first sacrificial layer and a first supporting layer in sequence.

[0092] like Figure 7 As shown, a first sacrificial layer 11 is formed on a substrate 30. The thickness of the first sacrificial layer 11 is set according to the height of a first target structure 110 to be formed. The higher the height of the first target structure 110 to be formed, the thicker the first sacrificial layer 11. A first supporting layer 12 is formed on the first sacrificial layer 11 to form a first stacked structure 10.

[0093] The material of the first sacrificial layer 11 includes silicon oxide or BPSG (Boro-phospho-silicate Glass), and the material of the first sacrificial layer 11 may be doped with boron or phosphorus. The material of the first supporting layer 12 includes any one of silicon nitride, silicon oxynitride, and silicon carbonitride, or a combination of any two or more thereof.

[0094] Step S112: patterning the first sacrificial layer and the first supporting layer to form a first target pattern hole in the first stacked structure.

[0095] like Figure 7 As shown, a first buffer layer 50 is formed on the top surface of the first stacked structure 10, and a patterned layer 60 is formed on the first buffer layer 50. The material of the first buffer layer 50 may include polysilicon. Figure 8 As shown, the first buffer layer 50 is patterned according to the patterning layer 60 to form a first target pattern 51 in the first buffer layer 50, wherein the first target pattern 51 may include a plurality of pattern regions, and the pattern density of each pattern region is the same or different. Figure 9 As shown, the first stacked structure 10 is etched using the patterned first buffer layer 50 as a mask, the first support layer 12 and the first sacrificial layer 11 exposed by the first target pattern 51 are removed, the first target pattern 51 is transferred to the first stacked structure 10, and a first target graphic hole 101 is formed in the first stacked structure 10. The first target graphic hole 101 exposes the capacitor contact portion 40 of the substrate 30.

[0096] In this embodiment, the first target pattern 51 is formed according to the distribution density of the capacitor contact portion 40 in the substrate 30. The first target pattern 51 includes a dense area 01 and a non-dense area 02. Figure 9 、 Figure 10 As shown, in this embodiment, a portion of the plurality of first target pattern holes 101 formed according to the first target pattern 51 is formed as a dense area 01 , and a portion is formed as a non-dense area 02 .

[0097] like Figure 9 As shown, in this embodiment, when etching the first stacked structure 10 using the first buffer layer 50 as a mask, the pattern density in the dense region 01 is relatively high, and the first buffer layer 50 at the top of the dense region 01 is consumed at a faster rate than the first buffer layer 50 at the top of the non-dense region 02. This embodiment reduces the process depth of the first target structure 110 and shortens the process time for forming the first target structure 110. This ensures that after the first target pattern holes 101 are formed in the non-dense region 02, a sufficiently thick first buffer layer 50 is still present at the top of the dense region 01 to prevent the top of the first stacked structure 10 from being damaged by etching.

[0098] Step S113: forming a first target structure in the first target pattern hole.

[0099] like Figure 12 As shown, a first target structure 110 is formed by depositing a conductive material in the first target pattern hole 101 , wherein the top surface of the first target structure 110 is not higher than the top surface of the first support layer 12 , and the bottom surface of the first target structure 110 contacts the capacitor contact portion 40 .

[0100] Among them, Figure 11 As shown, an atomic layer deposition process (ALD) can be used to deposit a conductive material to fill the first target pattern hole 101 and cover the top surface of the first stacked structure 10 to form a first conductive layer 111. Figure 12 As shown, the first conductive layer 111 covering the top surface of the first stacked structure 10 is removed by etching back to form a first target structure 110. The material of the first target structure 110 includes a compound formed by one or both of metal nitride and metal silicide, such as titanium nitride, titanium silicide, nickel silicide, titanium silicon nitride (TiSixNy), etc.

[0101] The formation method of this embodiment shortens the time for forming the first target graphic hole, ensuring that after the first target graphic hole is formed, the top surface of the first stacked structure is still protected by the first buffer layer, thereby avoiding the problem that the etching speed in the dense area is faster than that in the non-dense area, resulting in over-etching damage to the top of the first target graphic hole in the dense area, thereby ensuring that the formed first target structure has high dimensional accuracy.

[0102] According to an exemplary embodiment, this embodiment is an explanation of the implementation of the above step S120. During the implementation process, a second stacked structure is formed, and a second target structure is formed in the second stacked structure, such as Figure 3 As shown, the following steps are included:

[0103] Step S121: forming a second supporting layer and a dielectric layer in sequence on the first stacked structure.

[0104] like Figure 13 As shown, a second supporting layer 21 is formed on the first stacked structure 10 , and the second supporting layer 21 covers the top surface of the first supporting layer 12 and the top surface of the first target structure 110 . A dielectric layer 22 is formed on the second supporting layer 21 .

[0105] The material of the second supporting layer 21 includes any one of silicon nitride, silicon oxynitride, and silicon carbonitride, or a combination of any two or more thereof.

[0106] In this embodiment, if Figure 13 As shown, during the process of forming the dielectric layer 22, a second sacrificial layer 221 is formed on the second supporting layer 21. The thickness of the second sacrificial layer 221 is set according to the height of the second target structure 120 to be formed. The higher the height of the second target structure 120 to be formed, the thicker the second sacrificial layer 221. A third sacrificial layer 222 is formed on the second sacrificial layer 221.

[0107] The material of the third sacrificial layer 222 and the material of the second sacrificial layer 221 have etching selectivity. For example, the material of the second sacrificial layer 221 may include silicon oxide or BPSG (Boro-phospho-silicate Glass), and the material of the second sacrificial layer 222 may be doped with boron or phosphorus. The material of the third sacrificial layer may include any one of silicon nitride, silicon oxynitride, and silicon carbonitride, or a combination of any two or more thereof.

[0108] Step 122: patterning the second supporting layer and the dielectric layer to form a second target pattern hole in the second stacked structure, wherein the second target pattern hole at least exposes a portion of the first target structure.

[0109] like Figure 13 As shown, a second buffer layer 70 is formed on the top surface of the second stacked structure 20, as shown in FIG. Figure 14As shown, the second buffer layer 70 is patterned to form a second target pattern 71. Figure 15 As shown, the second stacked structure 20 is etched using the second buffer layer 70 as a mask to remove a portion of the third sacrificial layer 222, a portion of the second sacrificial layer 221, and a portion of the second supporting layer 21. The second target pattern 71 is transferred to the second stacked structure 20, forming a second target pattern hole 201 in the second stacked structure 20. The second target pattern hole 201 exposes at least a portion of the top surface of the first target structure 110. The material of the second buffer layer 70 may include polysilicon.

[0110] The arrangement of the second pattern holes 201 formed in this embodiment is the same as that of the first pattern holes 101 , with some of the second pattern holes 201 formed in the dense area 01 and others in the non-dense area 02 .

[0111] Similarly, refer to Figure 15 In this embodiment, by reducing the process depth of the second target pattern hole 201, the time for forming the second target pattern hole 201 is shortened, ensuring that after the second target pattern hole 201 is formed in the non-dense area 02, the top of the dense area 01 still has a sufficiently thick second buffer layer 70 to prevent the top of the second stacked pattern hole 201 from being damaged by etching, and the size accuracy of the formed second pattern hole 201 is high.

[0112] Step S123: forming a second target structure in the second target pattern hole.

[0113] like Figure 17 As shown, a second target structure 120 is formed by depositing a conductive material in the second target pattern hole 201 , and the second target structure covers the exposed portion of the first target structure.

[0114] like Figure 16 As shown, an atomic layer deposition process (ALD) can be used to deposit a conductive material to fill the second target pattern hole 201 and cover the top surface of the second stacked structure 20 to form a second conductive layer 121. Figure 17 As shown, the second conductive layer 121 covering the top surface of the second stacked structure 20 is etched back to form the second target structure 120. The material of the second conductive layer 121 includes a compound formed by one or both of metal nitride and metal silicide, such as titanium nitride, titanium silicide, nickel silicide, titanium silicon nitride (TiSixNy), etc. The material of the second target structure 120 can be the same as or different from the material of the first target structure 110.

[0115] The formation method of this embodiment reduces the process depth of each process, ensures the yield of the first target structure and the second target structure formed, and improves the yield of the finally formed semiconductor structure.

[0116] like Figure 4 As shown, an exemplary embodiment of the present disclosure provides a method for manufacturing a semiconductor structure, comprising the following steps:

[0117] Step S210 : forming a first stacked structure, and forming a first target structure in the first stacked structure.

[0118] Step S220 : forming a second stacked structure on the first stacked structure, and forming a second target structure in contact with the first target structure in the second stacked structure.

[0119] Step S230: removing a portion of the second stacked structure and a portion of the first stacked structure, and the remaining second stacked structure and the first stacked structure form a support structure.

[0120] Steps S210 - S220 of this embodiment are implemented in the same manner as steps S110 - S220 of the above embodiment, and are not described in detail herein.

[0121] In this embodiment, removing part of the second stacked structure and part of the first stacked structure includes: Figure 5 As shown,

[0122] Step S231 : forming a first mask layer, where the first mask layer covers a portion of the top surface of the second stacked structure and a portion of the top surface of the second target structure.

[0123] like Figure 18 、 Figure 19 As shown, refer to Figure 17 The first mask layer 80 forms a plurality of first patterns 81 on the top surface of the second target structure 120 . The plurality of first patterns 81 are arranged according to the setting position and distribution density of the second target structure 120 . Each first pattern 81 covers at least a portion of the top surface of the second stacked structure 20 .

[0124] Step S232: sequentially removing a portion of the third sacrificial layer, the second sacrificial layer, and a portion of the second supporting layer of the second stacked structure according to the first mask layer.

[0125] like Figure 20 As shown, the third sacrificial layer 222 exposed by the first mask layer 80 is removed by dry or wet etching using the first mask layer 80 as a mask to expose the second sacrificial layer 221. Figure 21 As shown, the entire second sacrificial layer 221 is removed by wet acid method to expose the second supporting layer 21. Figure 22As shown, the second supporting layer 21 exposed by the first mask layer 80 is removed by dry or wet etching, and the first pattern 81 is transferred to the first stacked structure 10 .

[0126] Step S233: sequentially removing a portion of the first supporting layer and the first sacrificial layer of the first stacked structure according to the first mask layer.

[0127] like Figure 22 As shown, the first support layer 12 exposed by the first mask layer 80 is removed by dry or wet etching to expose the first sacrificial layer 11. Figure 23 As shown, the entire first sacrificial layer 11 is removed by wet acid removal.

[0128] like Figure 23 As shown, the second target structure 120 is superimposed on the first target structure 110, the first target structure 110 and the second target structure 120 form a target structure, and the retained first support layer 12 and the second support layer 21 form a support structure 200, which covers at least part of the joint between the first target structure 110 and the second target structure 110.

[0129] In this embodiment, the retained third sacrificial layer 222 forms an upper support layer 300. The upper support layer 300 is disposed on top of the second target structure 120 and covers a portion of the sidewalls of the second target structure 120. The upper support layer 300 and the support structure 200 have the same shape. The upper support layer 300 and the support structure 200 jointly support the target structure formed by the first target structure 110 and the second target structure 120. When the target structure is relatively high, the presence of the upper support layer 300 can provide greater support for the target structure, ensuring the stability of the semiconductor structure and preventing the semiconductor structure from tipping over.

[0130] In the semiconductor structure formed in this embodiment, the support structure is disposed at the connection position between the first target structure and the second target structure, ensuring that the first target structure and the second target structure are firmly connected.

[0131] According to an exemplary embodiment, Figure 19 As shown, when forming the first mask layer 80, a plurality of adjacently arranged second target structures 120 are grouped together, and a first pattern 81 is formed correspondingly on the top surface of each group of second target structures. The first pattern 81 exposes a portion of the structure of each second target structure 120 in the group of second target structures.

[0132] In the semiconductor structure formed in this embodiment, the first target structure and the second target structure are stacked to form a target structure, and multiple target structures are grouped together. The multiple target structures in each group of target structures are connected into a whole through a supporting structure, thereby improving the anti-tilting ability of the semiconductor structure and improving the stability of the semiconductor structure.

[0133] In one embodiment, if Figure 19 As shown, when the first mask layer 80 is formed, three adjacent second target structures 120 are grouped together, and the first pattern 81 is a ring pattern set on the top surface of a group of second target structures. The first pattern 81 covers a portion of the top surface of each second target structure 120 in the group of second target structures and a portion of the top surface of the third sacrificial layer 222 surrounding it.

[0134] The support structure formed by the first mask layer according to this embodiment includes three independently set target structures. The three target structures in each group are connected into a whole through the support structure. Any two of the three target structures in each group are connected through a support unit, which reduces the space occupied by the support structure in the semiconductor structure and increases the available space in the semiconductor.

[0135] In this embodiment, the area of ​​the third sacrificial layer exposed by the first mask layer is larger, and the process window for removing the third sacrificial layer exposed by the first mask layer is larger, which reduces the process difficulty of removing the third sacrificial layer. Similarly, the difficulty of removing other parts of the second stack structure and removing the first stack structure is also reduced.

[0136] In other embodiments, Figure 5 As shown, removing part of the second stacking structure and part of the first stacking structure, further comprising the following steps:

[0137] Step S234: removing the retained third sacrificial layer.

[0138] In this embodiment, Figure 26 As shown, the entire third sacrificial layer is removed by dry or wet etching, and the formed semiconductor structure does not include the upper supporting layer, which reduces the space occupied by the upper supporting layer in the semiconductor structure and increases the available space in the semiconductor; moreover, removing the third sacrificial layer also exposes more sides of the second target structure. The target structure formed in this embodiment serves as the lower electrode, and the contact area of ​​the lower electrode is larger, which can further improve the electrical performance of the formed capacitor structure.

[0139] like Figure 6 As shown, an exemplary embodiment of the present disclosure provides a method for manufacturing a semiconductor structure, comprising the following steps:

[0140] Step S310 : forming a first stacked structure, and forming a first target structure in the first stacked structure.

[0141] Step S320 : forming a second stacked structure on the first stacked structure, and forming a second target structure in contact with the first target structure in the second stacked structure.

[0142] Step S330: removing a portion of the second stacked structure and a portion of the first stacked structure, and the remaining second stacked structure and the first stacked structure form a support structure.

[0143] Steps S310 - S330 of this embodiment are implemented in the same manner as steps S210 - S230 of the above embodiment, and are not described in detail herein.

[0144] Step S340 : forming a dielectric layer, wherein the dielectric layer at least covers the exposed sidewalls of the first target structure, the exposed sidewalls of the second target structure, and the top surface of the second target structure.

[0145] Atomic layer deposition (ALD) may be used to deposit the dielectric layer 400. The dielectric layer 400 is made of a high-k dielectric material having a dielectric constant greater than that of silicon dioxide.

[0146] like Figure 24 As shown, the dielectric layer 400 covers the exposed sidewalls of the first target structure 110, the exposed sidewalls of the second target structure 120, the top surface of the second target structure 120, and the support structure 200. When the semiconductor structure includes the upper support layer 300, the dielectric layer 400 also covers the upper support layer 300.

[0147] In this embodiment, the high dielectric material may include a compound of one or more of rare earth elements, Hf, Rh, Ba, and Al. The high dielectric material may include hafnium (IV) oxide, titanium dioxide, aluminum oxide, lanthanum oxide, and the like.

[0148] S350: forming an upper electrode layer, where the upper electrode layer covers the dielectric layer.

[0149] like Figure 25 As shown, refer to Figure 24 The upper electrode layer 500 may be formed by atomic layer deposition (ALD). The material of the upper electrode layer 500 includes a compound formed by one or both of metal nitride and metal silicide. In this embodiment, the upper electrode layer 500 may include one or both of titanium nitride, titanium silicide, nickel silicide, and titanium silicon nitride (TiSixNy).

[0150] In this embodiment, Figure 25 or Figure 29 As shown, the stacked first target structure 110 and the second target structure 120 are used as the lower electrode 100, and a dielectric layer 400 and an upper electrode layer 500 are sequentially formed on the lower electrode 100. The lower electrode 100, the dielectric layer 400 and the upper electrode layer 500 form a capacitor structure.

[0151] The capacitor structure formed in this embodiment uses the stacked first target structure and the second target structure as the lower electrode. The lower electrode is formed through two processes so that the first target structure and the second target structure of the lower electrode both have high dimensional accuracy. The lower electrode has high dimensional accuracy. Even if a capacitor structure with a high aspect ratio is formed, it can still be ensured that the formed capacitor structure maintains high dimensional accuracy, and the semiconductor structure has better performance and higher yield.

[0152] In an exemplary embodiment of the present disclosure, a semiconductor structure is provided, such as Figure 23 、 Figure 26 As shown, the semiconductor structure of this embodiment includes: a lower electrode 100 and a support structure 200. The lower electrode 100 includes a first target structure 110, a second target structure 120 stacked on the first target structure 110, and the support structure 200. The support structure 200 covers a portion of the joint between the first target structure 110 and the second target structure 120.

[0153] In the semiconductor structure of this embodiment, along the stacking direction, the first target structure 110 can be a structure with the same size from bottom to top, the first target structure 110 can be a structure with gradually increasing size from bottom to top, or the first target structure 110 can be a structure with gradually increasing size from bottom to top.

[0154] The second target structure 120 may be a structure with the same size from bottom to top, a structure with gradually increasing size from bottom to top, or a structure with gradually increasing size from bottom to top.

[0155] The semiconductor structure of this embodiment, such as Figure 26 、 Figure 27 As shown, it includes multiple lower electrodes 100 and multiple supporting structures 200, wherein one or several lower electrodes 100 form a group, and each group of lower electrodes 100 is connected into a whole through a supporting structure 200, so that each lower electrode 100 can be connected to the supporting structure 200, and the lower electrode 100 in the semiconductor structure is more stable and has better anti-tilting performance.

[0156] According to an exemplary embodiment, most of the contents of this embodiment are the same as the above embodiments. The difference between this embodiment and the above embodiments is that the projection pattern of the support structure 200 on the substrate includes multiple arc structures with the same curvature.

[0157] like Figure 27As shown, the support structure 200 includes multiple arc-shaped support units 210, and the projections of the multiple support units 210 on the substrate are located on the same circle, wherein each support unit 210 is connected to the joint of the first target structure 110 and the second target structure 120 of two adjacent lower electrodes 100.

[0158] In this embodiment, a support structure 200 connects three lower electrodes 100. The support structure 200 includes three support units 210 of identical curvature. The three support units 210 sequentially connect the three lower electrodes 100 to form a single entity. The line connecting the center points of the three lower electrodes 100 forms an inscribed triangle within the circle containing the projections of the multiple support units 210 on the substrate 30. This embodiment provides the semiconductor structure with the best anti-tilting properties, the highest overall stability, and the best semiconductor structural stability.

[0159] According to an exemplary embodiment, the semiconductor structure further comprises: Figure 23 As shown, an upper support layer 300 is disposed on top of the second target structure 120 and covers a portion of the sidewall of the second target structure 120. The upper support layer 300 and the support structure 200 have the same shape.

[0160] In this embodiment, the upper support layer 300 is arranged on the top of the semiconductor structure. When the semiconductor structure has a high aspect ratio, the upper support layer 300 increases the supporting force for the top of the semiconductor structure, improves the stability of the semiconductor structure, and reduces the risk of the semiconductor structure tipping over.

[0161] According to an exemplary embodiment, Figure 25 、 Figure 29 As shown, the semiconductor structure further includes: a dielectric layer 400 and an upper electrode layer 500. The dielectric layer 400 covers at least the exposed sidewalls of the first target structure 110, the exposed sidewalls of the second target structure 120, the top surface of the second target structure 120, and the support structure 200. When the semiconductor structure includes the upper electrode layer 300, the dielectric layer 400 also covers the upper support layer 300. The upper electrode layer 500 covers the dielectric layer 400.

[0162] According to an exemplary embodiment, the semiconductor structure further comprises, Figure 25 、 Figure 29 As shown, the substrate 30 includes a capacitor contact portion 40 ; the first target structure 110 is disposed on the capacitor contact portion 40 , and the first target structure 110 is in contact with the capacitor contact portion 40 .

[0163] In the semiconductor structure of this embodiment, the lower electrode 100 includes two parts: a first target structure 110 and a second target structure 120, which reduces the process difficulty of forming the lower electrode. The support structure 200 covers the connection position of the first target structure 110 and the second target structure 120 to ensure that the first target structure 110 and the second target structure 120 are firmly connected.

[0164] The various embodiments or implementation methods in this specification are described in a progressive manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the various embodiments can be referenced to each other.

[0165] In the description of this specification, reference to the terms "embodiment", "exemplary embodiment", "some embodiments", "illustrative embodiment", "example", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present disclosure.

[0166] In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any suitable manner in any one or more embodiments or examples.

[0167] In the description of the present disclosure, it should be noted that the terms "center", "up", "down", "left", "right", "vertical", "horizontal", "inside", "outside", etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings. They are only for the convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, they cannot be understood as limitations on the present disclosure.

[0168] It is to be understood that the terms "first", "second", etc. used in the present disclosure can be used to describe various structures in the present disclosure, but these structures are not limited by these terms. These terms are only used to distinguish a first structure from another structure.

[0169] In one or more of the accompanying drawings, identical elements are represented by similar reference numerals. For clarity, many parts in the accompanying drawings are not drawn to scale. In addition, certain well-known parts may not be shown. For simplicity, a structure obtained after several steps may be described in a single figure. Many specific details of the present disclosure, such as device structure, materials, dimensions, processing techniques, and technologies, are described below to facilitate a clearer understanding of the present disclosure. However, as will be appreciated by those skilled in the art, the present disclosure may be practiced without following these specific details.

[0170] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present disclosure, rather than to limit them. Although the present disclosure has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present disclosure.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that: include: forming a first stacked structure, forming a first target structure in the first stacked structure, forming a second stacked structure on the first stacked structure, and forming a second target structure in contact with the first target structure in the second stacked structure; The step of forming a first stacked structure and forming a first target structure in the first stacked structure includes: forming a first sacrificial layer and a first supporting layer in sequence; patterning the first sacrificial layer and the first supporting layer to form a first target pattern hole in the first stacked structure; forming the first target structure in the first target pattern hole; The step of forming a second stacked structure and forming a second target structure in the second stacked structure includes: forming a second supporting layer and a dielectric layer in sequence on the first stacked structure; patterning the second supporting layer and the dielectric layer to form a second target pattern hole in the second stacked structure, wherein the second target pattern hole at least exposes a portion of the first target structure; forming the second target structure in the second target pattern hole; The production method further comprises: A portion of the second stacked structure and a portion of the first stacked structure are removed, and the remaining second stacked structure and the first stacked structure form a support structure.

2. The method for manufacturing a semiconductor structure according to claim 1, wherein: The step of forming the first target structure in the first target pattern hole comprises: A conductive material is deposited in the first target pattern hole to form the first target structure, wherein a top surface of the first target structure is not higher than a top surface of the first supporting layer.

3. The method for manufacturing a semiconductor structure according to claim 1, wherein: The steps of forming the dielectric layer include: A second sacrificial layer is formed on the second supporting layer, and a third sacrificial layer is formed on the second sacrificial layer.

4. The method for manufacturing a semiconductor structure according to claim 1, wherein: The step of forming the second target structure in the second target pattern hole comprises: A conductive material is deposited in the second target pattern hole to form the second target structure, where the second target structure covers the exposed portion of the first target structure.

5. The method for manufacturing a semiconductor structure according to claim 3, wherein: Removing a portion of the second stacked structure and a portion of the first stacked structure, comprising: forming a first mask layer, wherein the first mask layer covers a portion of a top surface of the second stacked structure and a portion of a top surface of the second target structure; sequentially removing a portion of the third sacrificial layer, the second sacrificial layer, and a portion of the second supporting layer of the second stacked structure according to the first mask layer; sequentially removing portions of the first supporting layer and the first sacrificial layer of the first stacked structure according to the first mask layer; The remaining first supporting layer and the second supporting layer form the supporting structure.

6. The method for manufacturing a semiconductor structure according to claim 1, wherein: The method for manufacturing the semiconductor structure comprises: providing a substrate, the substrate comprising a capacitor contact; The first stacked structure is formed on the substrate.

7. The method for manufacturing a semiconductor structure according to claim 6, wherein: The forming of a first target structure in the first stacked structure includes: The first target structure is formed, wherein the first target structure is in contact with the capacitor contact portion.

8. The method for manufacturing a semiconductor structure according to claim 1, wherein: The production method further comprises: forming a dielectric layer, wherein the dielectric layer covers at least the exposed sidewalls of the first target structure, the exposed sidewalls of the second target structure, and the top surface of the second target structure; An upper electrode layer is formed, where the upper electrode layer covers the dielectric layer.

9. A semiconductor structure manufactured by the manufacturing method according to any one of claims 1 to 8, characterized in that: The semiconductor structure comprises: a lower electrode, the lower electrode comprising a first target structure and a second target structure stacked on the first target structure; A supporting structure includes an intermediate supporting layer, wherein the intermediate supporting layer covers a portion of a joint between the connecting surfaces of the first target structure and the second target structure.

10. The semiconductor structure according to claim 9, wherein: The semiconductor structure further comprises: An upper supporting layer is disposed on top of the second target structure and covers a portion of a sidewall of the second target structure.

11. The semiconductor structure according to claim 9, wherein: The semiconductor structure further comprises: a dielectric layer, the dielectric layer covering at least the exposed sidewalls of the first target structure, the exposed sidewalls of the second target structure, the top surface of the second target structure, and the support structure; An upper electrode layer covers the dielectric layer.

12. The semiconductor structure according to claim 9, wherein: The semiconductor structure further comprises: a substrate comprising a capacitor contact; The first target structure is disposed on the capacitor contact portion, and the first target structure is in contact with the capacitor contact portion.

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