Method for forming semiconductor structure, stacked structure and method for forming the same

Abstract

Embodiments of the present disclosure provide a method for forming a semiconductor structure, a stacked structure, and a method for forming the same. The method for forming the semiconductor structure includes: providing a stacked structure; the stacked structure includes a sacrificial layer and a support layer that are alternately stacked in sequence, and the support layer includes a doped region and a body region; the hardness of the doped region is less than the hardness of the body region; performing a first etching process to form a first void that penetrates the body region and the sacrificial layer in the stacked structure; depositing a first material layer on the inner wall of the first void; performing a second etching process to remove the doped region and the sacrificial layer, and form a second void between adjacent first voids. By the present disclosure, the manufacturing process of the semiconductor structure can be simplified.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and relates to, but is not limited to, a method for forming a semiconductor structure, a stacked structure, and a method for forming the same. Background Art

[0002] Dynamic Random Access Memory (DRAM) is a commonly used semiconductor memory device in computers. DRAM consists of many repeated memory cells. Each memory cell contains a transistor and a capacitor. Among them, the gate of the transistor is connected to the word line, the drain is connected to the bit line, and the source is connected to the capacitor. The voltage signal on the word line can control the opening or closing of the transistor, and then read the data information stored in the capacitor through the bit line, or write the data information into the capacitor through the bit line for storage.

[0003] In the related art, during the manufacturing process of the capacitor, it is usually necessary to first open the top support structure, remove the sacrificial material below the top support structure, then open the middle support structure, remove the sacrificial material below the middle support structure, and finally deposit a high-k dielectric material and an electrode plate material to form the capacitor. Therefore, the preparation process of the capacitor in the related art is complex. Summary of the Invention

[0004] In view of this, embodiments of the present disclosure provide a method for forming a semiconductor structure, a stacked structure, and a method for forming the same.

[0005] In a first aspect, embodiments of the present disclosure provide a method for forming a semiconductor structure, the method comprising:

[0006] Providing a stacked structure; the stacked structure includes a sacrificial layer and a support layer that are alternately stacked in sequence, the support layer includes a doped region and a body region; the hardness of the doped region is less than the hardness of the body region;

[0007] Performing a first etching process to form a first void penetrating through the body region and the sacrificial layer in the stacked structure;

[0008] Depositing a first material layer on the inner wall of the first void;

[0009] Performing a second etching process to remove the doped region and the sacrificial layer, and forming a second void between adjacent first voids.

[0010] In some embodiments, the sacrificial layer includes a first sacrificial layer and a second sacrificial layer; the support layer includes a first support layer and a second support layer; the stacked structure includes the first sacrificial layer, the first support layer, the second sacrificial layer, and the second support layer stacked in sequence;

[0011] Among them, the first support layer includes a first doped region and a first body region; the second support layer includes a second doped region and a second body region; the second doped region is located directly above the first doped region, and the hardness of the first doped region is less than the hardness of the first body region, and the hardness of the second doped region is less than the hardness of the second body region.

[0012] In some embodiments, the stacked structure is formed on a substrate; providing the stacked structure includes:

[0013] Providing the substrate;

[0014] Forming the first sacrificial layer and the first initial support layer on the surface of the substrate in sequence;

[0015] Performing ion implantation on a part of the first initial support layer to form the first support layer;

[0016] Forming the second sacrificial layer and the second initial support layer on the surface of the first support layer in sequence;

[0017] Performing ion implantation on a part of the second initial support layer to form the second support layer.

[0018] In some embodiments, the first doped region is formed through the following steps:

[0019] Forming a first photoresist layer on the surface of the first initial support layer; the first photoresist layer has a preset pattern, and the preset pattern exposes the surface of a part of the first initial support layer;

[0020] Performing ion implantation on the exposed part of the first initial support layer to form the first doped region.

[0021] In some embodiments, the ions during the ion implantation are formed by at least one of the following materials: hydrogen atoms, helium atoms, or boron atoms.

[0022] In some embodiments, the process parameters during the ion implantation include: ion implantation angle, ion implantation energy, and ion implantation dose;

[0023] Among them, the ion implantation angle is from 0 degrees to 55 degrees; the ion implantation energy is from 1000 electron volts to 100000 electron volts; the ion implantation dose is 10 13 atoms per square millimeter to 10 16 atoms per square millimeter.

[0024] In some embodiments, the etching selectivity between the first doped region and the substrate is greater than the etching selectivity between the first body region and the substrate.

[0025] In some embodiments, the second doped region is formed by the following steps:

[0026] A second photoresist layer is formed on the surface of the second initial support layer; the second photoresist layer has the preset pattern, and the preset pattern exposes the surface of a part of the second initial support layer;

[0027] The exposed part of the second initial support layer is subjected to ion implantation to form the second doped region.

[0028] In some embodiments, the etching selectivity between the second doped region and the substrate is greater than the etching selectivity between the second body region and the substrate.

[0029] In some embodiments, the stacked structure further includes a bottom support layer, and the first sacrificial layer is located on the surface of the bottom support layer; the first void is formed by the following steps:

[0030] A patterned mask layer is formed on the surface of the stacked structure;

[0031] Through the patterned mask layer, the second support layer, the second sacrificial layer, the first support layer, the first sacrificial layer, and the bottom support layer are sequentially etched until the surface of the substrate is exposed, forming the first void and the stacked structure.

[0032] In some embodiments, while depositing a first material layer on the inner wall of the first void, the first material layer is deposited on the top of the stacked structure.

[0033] In some embodiments, before removing the doped region and the sacrificial layer, the method further includes:

[0034] Removing the first material layer on the top of the stacked structure to expose the second doped region and the second body region.

[0035] In some embodiments, the second void is formed by the following steps:

[0036] Using a wet etching process, the second doped region, the second sacrificial layer, the first doped region, and the first sacrificial layer in the stacked structure are simultaneously removed to form the second void located between two adjacent first voids.

[0037] In some embodiments, the second void is formed by the following steps:

[0038] Using a wet etching process, the second doped region, the second sacrificial layer, the first doped region, and the first sacrificial layer in the stacked structure are simultaneously removed to form the second void located between two adjacent first voids.

[0039] In some embodiments, the etching solution used in the wet etching process includes: a dilute hydrofluoric acid solution and a mixed solution of hydrofluoric acid and ammonium fluoride.

[0040] In some embodiments, the process temperature of the wet etching process is 20°C to 60°C.

[0041] In some embodiments, after removing the doped region and the sacrificial layer, the method further includes:

[0042] A second material layer and a third material layer are sequentially formed on the surface of the first material layer.

[0043] In a second aspect, embodiments of the present disclosure provide a stacked structure, including: a sacrificial layer and a support layer that are alternately stacked in sequence;

[0044] Wherein, the support layer includes a doped region and a body region, and the hardness of the doped region is less than the hardness of the body region.

[0045] In some embodiments, the sacrificial layer includes a first sacrificial layer and a second sacrificial layer; the support layer includes a first support layer and a second support layer; the stacked structure includes the first sacrificial layer, the first support layer, the second sacrificial layer, and the second support layer stacked in sequence;

[0046] Wherein, the first support layer includes a first doped region and a first body region; the second support layer includes a second doped region and a second body region; the second doped region is directly above the first doped region, and the hardness of the first doped region is less than the hardness of the first body region, and the hardness of the second doped region is less than the hardness of the second body region.

[0047] In a third aspect, embodiments of the present disclosure provide a method for forming a stacked structure, the stacked structure being located on the surface of a substrate; the method includes:

[0048] A sacrificial layer and an initial support layer are alternately formed in sequence on the surface of the substrate;

[0049] Ion implantation is performed on a part of the initial support layer to form a support layer including a doped region and a body region;

[0050] Wherein, the hardness of the doped region is less than the hardness of the body region.

[0051] In some embodiments, the sacrificial layer includes a first sacrificial layer and a second sacrificial layer; the initial support layer includes a first initial support layer and a second initial support layer; the support layer includes a first support layer and a second support layer;

[0052] The sacrificial layer and the support layer are formed through the following steps:

[0053] The first sacrificial layer and the first initial support layer are sequentially formed on the surface of the substrate;

[0054] Ion implantation is performed on a part of the first initial support layer to form the first support layer including a first doped region and a first body region;

[0055] The second sacrificial layer and the second initial support layer are sequentially formed on the surface of the first support layer;

[0056] Ion implantation is performed on a part of the second initial support layer to form the second support layer including a second doped region and a second body region;

[0057] Wherein, the second doped region is located directly above the first doped region, and the hardness of the first doped region is less than that of the first body region, and the hardness of the second doped region is less than that of the second body region.

[0058] The method for forming a semiconductor structure provided by an embodiment of the present disclosure, a stacked structure and a method for forming the same. Among them, the method for forming a semiconductor structure includes: providing a stacked structure; the stacked structure includes sacrificial layers and support layers that are alternately stacked in sequence, the support layer includes a doped region and a body region; the hardness of the doped region is less than that of the body region; performing a first etching process to form a first void penetrating the body region and the sacrificial layer in the stacked structure; depositing a first material layer on the inner wall of the first void; performing a second etching process to remove the doped region and the sacrificial layer, and forming a second void between adjacent first voids. In the embodiment of the present disclosure, since the support layer includes a doped region with a smaller hardness, in subsequent manufacturing processes, the doped region with a smaller hardness can be etched and removed simultaneously with the sacrificial layer, thereby simplifying the manufacturing process of the semiconductor structure. Description of the Drawings

[0059] In the drawings (which are not necessarily drawn to scale), similar reference numerals may describe similar components in different views. Similar reference numerals with different letter suffixes may represent different examples of similar components. The drawings generally illustrate, by way of example and not limitation, the various embodiments discussed herein.

[0060] Figure 1 It is a schematic flowchart of a method for forming a semiconductor structure provided by an embodiment of the present disclosure;

[0061] Figures 2a - 2m It is a schematic structural diagram of the semiconductor structure formation process provided by an embodiment of the present disclosure;

[0062] Figure 3 It is a schematic structural diagram of a stacked structure provided by an embodiment of the present disclosure;

[0063] Figure 4A flowchart of a method for forming a stacked structure provided by an embodiment of the present disclosure;

[0064] Description of reference numerals:

[0065] 200 - Substrate; 201 / 301 - Bottom support layer; 202 / 302 - First sacrificial layer; 203a - First initial support layer; 203 / 303 - First support layer; 204 - First photoresist layer; 205 - Second sacrificial layer; 206a - Second initial support layer; 206 / 305 - Second support layer; 207 - Second photoresist layer; 208 - Patterned mask layer; 209a - First void; 209b - Second void; 210 - Stacked structure; 211 - First material layer; 212 - Second material layer; 213 - Third material layer; 214 - Conductive material; 30 - Stacked structure; B1 / 303b - First body region; B2 / 305b - Second body region; D1 / 303a - First doped region; D2 / 305a - Second doped region; C - Preset pattern. Detailed implementation manners

[0066] Hereinafter, the exemplary embodiments of the present disclosure will be described in more detail with reference to the accompanying drawings. Although the exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the specific embodiments set forth herein. On the contrary, these embodiments are provided so that the present disclosure can be more thoroughly understood and the scope of the present disclosure can be fully conveyed to those skilled in the art.

[0067] In the following description, numerous specific details are given to provide a more thorough understanding of the present disclosure. However, it is obvious to those skilled in the art that the present disclosure can be implemented without one or more of these details. In other examples, some well-known technical features are not described in order to avoid confusion with the present disclosure; that is, not all features of the actual embodiments are described here, and the well-known functions and structures are not described in detail.

[0068] In the drawings, for clarity, the dimensions of layers, regions, elements and their relative dimensions may be exaggerated. The same reference numerals denote the same elements throughout.

[0069] It should be understood that when an element or layer is referred to as being "on", "adjacent to", "connected to", or "coupled to" another element or layer, it can be directly on, adjacent to, connected, or coupled to the other element or layer, or there can be intervening elements or layers. In contrast, when an element is referred to as being "directly on", "directly adjacent to", "directly connected to", or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Thus, without departing from the teachings of the present disclosure, the first element, component, region, layer, or part discussed below can be referred to as the second element, component, region, layer, or part. And when discussing the second element, component, region, layer, or part, it does not imply that there must be a first element, component, region, layer, or part in the present disclosure.

[0070] The purpose of the terms used herein is only to describe specific embodiments and is not a limitation of the present disclosure. As used herein, the singular forms "a", "an", and "the" are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" and / or "including", when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. As used herein, the term "and / or" includes any and all combinations of the related listed items.

[0071] Based on the problems existing in the related art, embodiments of the present disclosure provide a method for forming a semiconductor structure, a stacked structure, and a method for forming the same. Among them, the method for forming a semiconductor structure includes: providing a stacked structure; the stacked structure includes a sacrificial layer and a support layer alternately stacked in sequence, the support layer includes a doped region and a body region; the hardness of the doped region is less than the hardness of the body region; performing a first etching process to form a first void penetrating the body region and the sacrificial layer in the stacked structure; depositing a first material layer on the inner wall of the first void; performing a second etching process to remove the doped region and the sacrificial layer, and forming a second void between adjacent first voids. In the embodiments of the present disclosure, since the support layer includes a doped region with a smaller hardness, thus, in subsequent manufacturing processes, the doped region with a smaller hardness can be etched and removed simultaneously with the sacrificial layer, thereby simplifying the manufacturing process of the semiconductor structure.

[0072] Embodiments of the present disclosure provide a method for forming a semiconductor structure, Figure 1 is a schematic flow diagram of a method for forming a semiconductor structure provided by an embodiment of the present disclosure, as Figure 1As shown, the method for forming a semiconductor structure includes the following steps:

[0073] Step S101: Provide a stacked structure; the stacked structure includes a sacrificial layer and a support layer that are alternately stacked in sequence, and the support layer includes a doped region and a body region; the hardness of the doped region is less than that of the body region.

[0074] In an embodiment of the present disclosure, the stacked structure can be used to form a capacitor structure, and the stacked structure includes a sacrificial layer and a support layer that are alternately stacked in sequence. Among them, the hardness of the support layer is greater than that of the sacrificial layer, and the support layer can provide a supporting effect on the subsequently formed capacitor structure to prevent the collapse of the capacitor structure.

[0075] The support layer includes a doped region and a body region, where the doped region is a region formed after ion doping of a part of the initial support layer. In an embodiment of the present disclosure, the doped region and the body region can be arranged alternately.

[0076] In an embodiment of the present disclosure, the doped region formed after ion doping of the initial support layer has a smaller hardness and is more easily etched and removed compared to the body region that has not undergone ion doping.

[0077] In an embodiment of the present disclosure, the support layer can be a silicon carbide layer or a silicon carbonitride layer. The sacrificial layer can be an oxide layer or a doped oxide layer, for example, a silicon oxide layer or a borophosphosilicate glass (BPSG).

[0078] Step S102: Perform a first etching process to form a first void that penetrates the body region and the sacrificial layer in the stacked structure.

[0079] In an embodiment of the present disclosure, the first etching process can be a dry etching process, and the first void can be a capacitor via. After forming the first void in the stacked structure, the remaining stacked structure forms a stacked structure.

[0080] Step S103: Deposit a first material layer on the inner wall of the first void.

[0081] In an embodiment of the present disclosure, the first material layer can be a titanium nitride layer, a titanium metal layer, a titanium oxide layer, or other metal thin film layers. The first material layer can be used as an electrode plate of the capacitor structure, for example, the lower electrode of the capacitor structure.

[0082] Step S104: Perform a second etching process to remove the doped region and the sacrificial layer, and form a second void between adjacent first voids.

[0083] In the embodiments of the present disclosure, the second etching process may be a wet etching process. Removing the doped region and the sacrificial layer means removing the doped region in the stacked structure and the sacrificial layer in the stacked structure simultaneously. For example, the doped region in the stacked structure and the sacrificial layer in the stacked structure may be removed by wet etching with a dilute hydrofluoric acid solution and a mixed solution of hydrofluoric acid and ammonium fluoride.

[0084] In the embodiments of the present disclosure, since the support layer includes a doped region with a relatively low hardness, in subsequent processes, the doped region with a relatively low hardness can be etched and removed simultaneously with the sacrificial layer, thereby simplifying the manufacturing process of the semiconductor structure.

[0085] Figures 2a - 2m FIG. is a schematic structural diagram of the formation process of the semiconductor structure provided by the embodiments of the present disclosure. Next, please refer to Figures 2a - 2m for a further detailed description of the method for forming the semiconductor structure provided by the embodiments of the present disclosure.

[0086] First, reference may be made to Figures 2a - 2f to perform step S101: Provide a stacked structure; the stacked structure includes a sacrificial layer and a support layer that are alternately stacked in sequence, and the support layer includes a doped region and a body region.

[0087] In the embodiments of the present disclosure, the sacrificial layer includes a first sacrificial layer 202 and a second sacrificial layer 205; the support layer includes a first support layer 203 and a second support layer 206, and the stacked structure includes the first sacrificial layer 202, the first support layer 203, the second sacrificial layer 205, and the second support layer 206 that are stacked in sequence from bottom to top. Among them, the first support layer 203 includes a first doped region D1 and a first body region B1; the second support layer 206 includes a second doped region D2 and a second body region B2; the second doped region D2 is located directly above the first doped region D1, and the hardness of the first doped region D1 is less than the hardness of the first body region B1, and the hardness of the second doped region D2 is less than the hardness of the second body region B2.

[0088] In some embodiments, the stacked structure further includes a bottom support layer 201, and the first sacrificial layer 202 is located on the surface of the bottom support layer 201.

[0089] Please continue to refer to Figures 2a - 2f , in some embodiments, the stacked structure is used to form a capacitor structure, and the stacked structure is formed on a substrate 200. The substrate 200 includes at least a contact structure (such as a landing pad), and the contact structure is used for electrical connection with the formed capacitor structure. In the embodiments of the present disclosure, the material of the contact structure may be any one of conductive materials, such as tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof.

[0090] Please continue to refer to Figures 2a - 2f, in other embodiments, the substrate 200 may further include a semiconductor substrate, a word line structure inside the semiconductor substrate, and a bit line structure on the surface of the semiconductor substrate, etc. Among them, the semiconductor substrate may be a silicon substrate, and the semiconductor substrate may also include other semiconductor elements, such as: germanium (Ge), or include semiconductor compounds, such as: silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs) or indium antimonide (InSb), or include other semiconductor alloys, such as: silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP), and / or gallium indium arsenide phosphide (GaInAsP) or a combination thereof.

[0091] Please continue to refer to Figures 2a - 2f , providing the stacked structure may include the following steps: providing a substrate 200; sequentially forming a bottom support layer 201, a first sacrificial layer 202, and a first initial support layer 203a on the surface of the substrate 200; performing ion implantation on a part of the first initial support layer 203a to form a first support layer 203; sequentially depositing and forming a second sacrificial layer 205 and a second initial support layer 206a on the surface of the first support layer 203; performing ion implantation on a part of the second initial support layer 206a to form a second support layer 206.

[0092] As Figure 2a shown, a bottom support layer 201, a first sacrificial layer 202, and a first initial support layer 203a are sequentially formed on the surface of the substrate 200. In the embodiments of the present disclosure, the bottom support layer 201 is a silicon nitride layer, the first sacrificial layer 202 is a boron phosphosilicate glass, and the first initial support layer 203a is a silicon carbonitride layer. In the embodiments of the present disclosure, the bottom support layer 201, the first sacrificial layer 202, and the first initial support layer 203a can be formed by any suitable deposition process. For example, Chemical Vapor Deposition (CVD) process, Physical Vapor Deposition (PVD) process, Atomic Layer Deposition (ALD) process, spin coating process or coating process. In the embodiments of the present disclosure, since the hardness of the boron phosphosilicate glass is less than the hardness of the silicon oxide, therefore, using the softer boron phosphosilicate glass as the first sacrificial layer 202 is beneficial to maintaining the pattern during the etching process.

[0093] As Figure 2b and 2cAs shown, the first support layer 203 includes a first doped region D1 and a first body region B1. Among them, the first doped region D1 is formed by ion implantation of a part of the first initial support layer 203a. For example, the first doped region D1 can be formed through the following steps: forming a first photoresist layer 204 on the surface of the first initial support layer 203a; the first photoresist layer 204 has a preset pattern C, and the preset pattern C exposes a part of the surface of the first initial support layer 203a, and ion implantation is performed on the exposed first initial support layer 203a to form the first doped region D1.

[0094] Please continue to refer to Figure 2b and 2c , in the embodiments of the present disclosure, atoms with relatively small atomic numbers such as hydrogen atoms, helium atoms, and boron atoms can be used. At an ion implantation angle of 0 degrees to 55 degrees, an ion implantation energy of 1000 electron volts to 100000 electron volts, and an ion implantation dose of 10 13 atoms per square millimeter to 10 16 atoms per square millimeter, ion implantation is performed on the exposed first initial support layer 203a to form the first doped region D1 as shown in Figure 2c . Among them, the part of the first initial support layer 203a blocked by the first photoresist layer 204 is not ion implanted, forming the first body region B1 as shown in Figure 2c . The first doped region D1 and the first body region B1 together form the first support layer 203. The first doped region D1 and the first body region B1 are, for example, arranged alternately.

[0095] Please continue to refer to Figure 2b and 2c, in the embodiments of the present disclosure, the first initial support layer 203a may be a silicon carbonitride layer, and the materials for ion doping include atoms with relatively small atomic numbers such as hydrogen atoms, helium atoms, or boron atoms. Since the radii of hydrogen atoms, helium atoms, or boron atoms are relatively small, hydrogen atoms, helium atoms, or boron atoms can be easily doped into silicon carbonitride. Hereinafter, taking hydrogen atoms as doping ions as an example, the process of ion doping will be described in detail. After hydrogen atoms are doped into the silicon nitride layer, some of the silicon-nitrogen bonds (Si-N) and silicon-carbon bonds (Si-C) in the silicon carbonitride will be broken, and new silicon-hydrogen bonds (Si-H) will be formed. Since the bond energies of Si-N bonds and Si-C in silicon carbonitride are both greater than the bond energy of Si-H, the undoped Si-N bonds and Si-C are more stable. Therefore, the hardness of the undoped silicon carbonitride (corresponding to the first body region B1 in this application) is relatively high. After doping with hydrogen atoms, due to the formation of new Si-H bonds, the hardness of the doped silicon carbonitride (corresponding to the first doped region D1 in this application) is reduced, that is, the doped silicon carbonitride becomes softer and is more easily etched away. That is to say, the etching selectivity between the first doped region D1 and the substrate 200 is greater than the etching selectivity between the first body region B1 and the substrate 200.

[0096] Please continue to refer to Figure 2b and 2c , in the embodiments of the present disclosure, since the bond energy of the silicon-oxygen bond (Si-O) in the first sacrificial layer 202 is less than the bond energy of the Si-C bond, the difference between the bond energy of the Si-H bond in the first doped region D1 and the bond energy of the Si-O bond in the first sacrificial layer is reduced. Thus, when etching the first doped region D1, the first sacrificial layer 202 located below the first doped region D1 can be removed simultaneously. The etching selectivity between the first doped region D1 and the substrate 200 is reduced relative to the etching selectivity between the first sacrificial layer 202 and the substrate 200. Thus, the first doped region D1 and the first sacrificial layer 202 can be etched and removed simultaneously.

[0097] Please continue to refer to Figure 2b and 2c , in some embodiments, after forming the first doped region D1, the method for forming the semiconductor structure further includes: removing the first photoresist layer 204. In the embodiments of the present disclosure, the first photoresist layer 204 can be removed by ashing process, dry etching technology, or wet etching technology.

[0098] Such as Figure 2dAs shown, in the embodiments of the present disclosure, the second sacrificial layer 205 may be a silicon oxide layer, and the second initial support layer 206a may be a silicon carbonitride layer. Here, the second sacrificial layer 205 and the second initial support layer 206a may be formed by any suitable deposition process. For example, chemical vapor deposition process, physical vapor deposition process, atomic layer deposition process, spin coating process or coating process.

[0099] As Figure 2e and 2f shown, the second support layer 206 includes a second doped region D2 and a second body region B2. Among them, the second doped region D2 is formed by ion implantation of a part of the second initial support layer 206a. For example, the second doped region D2 may be formed through the following steps: forming a second photoresist layer 207 on the surface of the second initial support layer 206a; the second photoresist layer 207 has a preset pattern C, and the preset pattern C exposes the surface of a part of the second initial support layer 206a; performing ion implantation on the exposed second initial support layer 206a to form the second doped region D2.

[0100] Please continue to refer to Figure 2e and 2f , in the embodiments of the present disclosure, atoms with a relatively small atomic number such as hydrogen atoms, helium atoms or boron atoms are used. At an ion implantation angle of 0 degrees to 55 degrees, an ion implantation energy of 1000 electron volts to 100000 electron volts, and an ion implantation dose of 10 13 atoms / mm² to 10 16 atoms / mm², ion implantation is performed on the exposed second initial support layer 206a to form the second doped region D2 as shown in Figure 2f . Among them, the part of the second initial support layer 206a blocked by the second photoresist layer 207 is not ion implanted, forming the second body region B2 as shown in Figure 2f . The second doped region D2 and the second body region B2 together form the second support layer 206.

[0101] Please continue to refer to Figure 2e and 2f, in the embodiments of the present disclosure, the second initial support layer 206a may be a silicon carbonitride layer, and the materials for ion doping include atoms with relatively small atomic numbers such as hydrogen atoms, helium atoms, or boron atoms. Since the radii of hydrogen atoms, helium atoms, or boron atoms are relatively small, hydrogen atoms, helium atoms, or boron atoms can be easily doped into silicon carbonitride. Hereinafter, taking boron atoms as the doping ions as an example, the process of ion doping will be described in detail. After boron atoms are doped into the silicon nitride layer, some Si-N bonds and Si-C bonds in the silicon carbonitride are broken, and new silicon-boron bonds (Si-B) are formed. Since the bond energies of Si-N bonds and Si-C in the silicon carbonitride are both greater than the bond energy of Si-B, the undoped Si-N bonds and Si-C are more stable. Therefore, the hardness of the undoped silicon carbonitride (corresponding to the second body region B2 in the present application) is relatively high. After ion doping with boron atoms, since new Si-B bonds are formed, the hardness of the doped silicon carbonitride (corresponding to the second doped region D2 in the present application) is reduced, that is, the doped silicon carbonitride becomes softer and is more easily etched away. That is to say, the etching selectivity between the second doped region D2 and the substrate 200 is greater than the etching selectivity between the second body region B2 and the substrate 200.

[0102] Please continue to refer to Figure 2e and 2f , in the embodiments of the present disclosure, since the bond energy of the Si-O bond in the second sacrificial layer 205 is less than the bond energy of the Si-C bond, the gap between the bond energy of the Si-B bond in the second doped region D2 and the bond energy of the Si-O bond in the second sacrificial layer is reduced. Thus, when etching the second doped region D2, the second sacrificial layer 205 located under the second doped region D2 can be removed simultaneously. The etching selectivity between the second doped region D2 and the substrate 200 is reduced relative to the etching selectivity between the second sacrificial layer 205 and the substrate 200. Thus, the second doped region D2 and the second sacrificial layer 205 can be etched and removed simultaneously.

[0103] Please continue to refer to Figure 2e and 2f , in some embodiments, after forming the second doped region D2, the method for forming the semiconductor structure further includes: removing the second photoresist layer 207. In the embodiments of the present disclosure, the second photoresist layer 207 can be removed by an ashing process, a dry etching technique, or a wet etching technique.

[0104] It should be noted that in the embodiments of the present disclosure, the doping concentration of the first doping region and the doping concentration of the second doping region may be equal or unequal, and in the embodiments of the present disclosure, the doping concentrations of the first doping region and the second doping region are not limited. For example, the doping concentration of the first doping region is equal to that of the second doping region, so as to ensure that the first doping region and the second doping region have the same etching rate. At the same time, the doping ions in the first doping region and the doping ions in the second doping region may also be the same or different.

[0105] Next, reference may be made to Figures 2g - 2i , and step S102 is executed to perform a first etching process to form a first void 209a penetrating the body region and the sacrificial layer in the stacked structure.

[0106] As Figure 2g and 2h shown, in some embodiments, the first void 209a may be formed through the following steps: forming a patterned mask layer 208 on the surface of the stacked structure; through the patterned mask layer 208, sequentially etching the second support layer 206, the second sacrificial layer 205, the first support layer 203, the first sacrificial layer 202, and the bottom support layer 201 until the surface of the substrate 200 is exposed, forming the first void 209a and the stacked structure 210.

[0107] Please continue to refer to Figure 2g and 2h , in the embodiments of the present disclosure, the patterned mask layer 208 may be formed by gradually doubling the pattern of multiple hard mask layers through the Self-aligned Double Patterning (SADP) technology. The patterned mask layer 208 has a pattern defining the first void 209a. By sequentially etching the second support layer 206, the second sacrificial layer 205, the first support layer 203, the first sacrificial layer 202, and the bottom support layer 201 through the patterned mask layer 208 until the surface of the substrate 200 is exposed, multiple first voids 209a as shown in Figure 2h are formed, and the remaining stacked structure after etching forms a stacked structure 210 as shown in Figure 2h . In the embodiments of the present disclosure, the stacked structure 210 includes two types of stacked layers. One is a stacked layer composed of the bottom support layer 201, the first sacrificial layer 202, the first body region B1, the second sacrificial layer 205, and the second body region B2; the other is a stacked layer composed of the bottom support layer 201, the first sacrificial layer 202, the first doping region D1, the second sacrificial layer 205, and the second doping region D2.

[0108] Figure 2i is a top view of the first void provided by the embodiments of the present disclosure. As Figure 2iAs shown, the first voids 209a penetrating the stacked structure are arranged in an array. It should be noted that in the embodiments of the present disclosure, the etching process of the first voids 209a is only exemplarily shown from one direction. In fact, during the etching process of the first voids 209a, etching needs to be performed from two directions.

[0109] Next, reference may be made to Figure 2j to perform step S103 of depositing a first material layer 211 on the inner wall of the first voids 209a.

[0110] As Figure 2j shown, in the embodiments of the present disclosure, while the first material layer 211 is deposited on the inner wall of the first voids 209a, the first material layer 211 is also formed on the top surface of the stacked structure 210. In the embodiments of the present disclosure, the first material layer 211 can be formed by any suitable deposition process.

[0111] Next, reference may be made to Figure 2k and 2l to perform step S104 of performing a second etching process to remove the doped regions and the sacrificial layer and form second voids 209b between adjacent first voids 209a.

[0112] As Figure 2k shown, in some embodiments, before removing the doped regions and the sacrificial layer in the stacked structure 210, the method for forming a semiconductor structure further includes: removing the first material layer 211 on the top of the stacked structure 210 to expose the second doped region D2 and the second body region B2 in the stacked structure 210. In the embodiments of the present disclosure, the first material layer 211 on the top of the stacked structure 210 can be removed by a dry etching process, such as a plasma etching process, a reactive ion etching process, or an ion milling process.

[0113] Combined with Figure 2k and 2lAs shown, in the embodiments of the present disclosure, removing the doped regions and the sacrificial layers in the stacked structure 210 can be achieved through wet etching technology to simultaneously remove the second doped region D2 in the stacked structure 210, the second sacrificial layer 205 in the stacked structure 210, the first doped region D1 in the stacked structure 210, and the first sacrificial layer 202 in the stacked structure 210, so as to form a second void 209b located between two adjacent first voids 209a. For example, by using a dilute hydrofluoric acid (DHF) solution and a mixed solution of hydrofluoric acid and ammonium fluoride, at a process temperature of 20°C to 60°C, such as 30 - 50°C, simultaneously etch and remove the second doped region D2 in the stacked structure 210, the second sacrificial layer 205 in the stacked structure 210, the first doped region D1 in the stacked structure 210, and the first sacrificial layer 202 in the stacked structure 210, and retain the first material layer 211 on the sidewalls of the first void 209a, the second body region B2 in the stacked structure 210, and the first body region B1 in the stacked structure 210, so as to form a second void 209b between adjacent first voids 209a. In the embodiments of the present disclosure, since no ion implantation is performed on the second body region B2, the bond energy of the second body region B2 is greater than that of the second doped region D2. That is to say, the second body region B2 is more stable than the second doped region D2, which means the second body region B2 has a higher hardness than the second doped region D2. Since the bond energy of the second body region B2 is greater than that of the second doped region D2, breaking the bonds of the second body B2 requires more energy. That is, the second doped region D2 is more easily etched than the second body region B2, and thus the second doped region D2 can be removed while ensuring that the second body region B2 is not etched. At the same time, since the bond energy of the second doped region D2 is close to that of the second sacrificial layer 205, the second doped region D2 and the second sacrificial layer 205 can be removed simultaneously. Similarly, in the embodiments of the present disclosure, the first doped region D1 and the first sacrificial layer 202 can be removed simultaneously. Therefore, in the embodiments of the present disclosure, the second doped region D2, the second sacrificial layer 205, the first doped region D1, and the first sacrificial layer 202 can be removed simultaneously, while retaining the second body region B2 and the first body region B1. The first body region B1 and the second body region B2 can be used to support the capacitor structure and prevent the capacitor structure from collapsing.

[0114] In the embodiments of the present disclosure, after doping the first initial support layer and the second initial support layer with atoms having a relatively small atomic number, new chemical bonds are generated in the first initial support layer, and the bond energy of the new chemical bonds is less than the bond energy of the original chemical bonds in the first initial support layer or the second initial support layer. Therefore, the hardness of the doped first initial support layer (i.e., the first doped region) is lower than that of the undoped first initial support layer (i.e., the first body region), and the hardness of the doped second initial support layer (i.e., the second doped region) is lower than that of the undoped second initial support layer (i.e., the second body region). Thus, the first doped region and the second doped region are easier to be etched and removed compared with the first body region and the second body region. Therefore, the second doped region, the second sacrificial layer, the first doped region, and the first sacrificial layer in the stacked structure can be removed simultaneously in a single etching process, greatly simplifying the manufacturing process of the semiconductor structure.

[0115] Combined with Figure 2l and 2m As shown, after removing the second doped region D2, the second sacrificial layer 205, the first doped region D1, and the first sacrificial layer 202 in the stacked structure 210, the method for forming a semiconductor structure further includes: sequentially forming a second material layer 212 and a third material layer 213 on the surface of the first material layer 211. A conductive material 214 is filled in the gap between the third material layers 213, thereby forming a complete capacitor structure. In the embodiments of the present disclosure, the second material layer can be used as the second material layer of the capacitor structure, and the third material layer can be used as another electrode layer of the capacitor structure, for example, the upper electrode of the capacitor structure.

[0116] Please continue to refer to Figure 2m , in the embodiments of the present disclosure, the second material layer 212 can be a zirconia layer and / or an alumina layer, or other high-k dielectric material layers. The third material layer 213 can also be a titanium nitride layer, a titanium metal layer, a titanium oxide layer, or other metal thin film layers. The third material layer 213 can be the same as or different from the first material layer 211. The conductive material 214 can be polysilicon, or any other suitable conductive material, for example, tungsten, cobalt, or doped polysilicon.

[0117] For the capacitor structure formed in the embodiments of the present disclosure, the height of the capacitor structure is 600 nm to 1300 nm, for example, it can be 800 nm or 1000 nm; the critical dimension of the capacitor is 30 nm to 60 nm, for example, it can be 35 nm or 50 nm.

[0118] In the method for forming a semiconductor structure provided by an embodiment of the present disclosure, since the first support layer in the stacked structure includes a first doped region with a relatively low hardness, the second support layer in the stacked structure includes a second doped region with a relatively low hardness, and the position of the first doped region corresponds to the position of the second doped region. Thus, in subsequent manufacturing processes, the first doped region with a relatively low hardness and the second doped region with a relatively low hardness in the stacked structure can be etched and removed simultaneously with the first sacrificial layer and the second sacrificial layer in the stacked structure, thereby simplifying the manufacturing process of the semiconductor structure.

[0119] An embodiment of the present disclosure provides a stacked structure. Figure 3 As shown in the structural schematic diagram of the stacked structure provided by an embodiment of the present disclosure, Figure 3 as shown, the stacked structure 30 includes sacrificial layers and support layers stacked alternately in sequence; among them, the sacrificial layers include a first sacrificial layer 302 and a second sacrificial layer 304; the support layers include a first support layer 303 and a second support layer 305; the stacked structure 30 includes a first sacrificial layer 302, a first support layer 303, a second sacrificial layer 304, and a second support layer 305 stacked in sequence from bottom to top.

[0120] Please continue to refer to Figure 3 , in some embodiments, the stacked structure 30 further includes a bottom support layer 301, and the first sacrificial layer 302 is located on the surface of the bottom support layer 301.

[0121] In some embodiments, the support layer includes a doped region and a body region, and the hardness of the doped region is less than the hardness of the body region. Please continue to refer to Figure 3 , the first support layer 303 includes a first doped region 303a and a first body region 303b, and the hardness of the first doped region 303a is less than the hardness of the first body region 303b; the second support layer 305 includes a second doped region 305a and a second body region 305b, and the hardness of the second doped region 305a is less than the hardness of the second body region 305b; the second doped region 305a is located directly above the first doped region 303a.

[0122] In the stacked structure provided by an embodiment of the present disclosure, both the first support layer and the second support layer include a doped region and a body region, and the hardness of the doped region in the first support layer and the second support layer is less than the hardness of the body region. Therefore, the doped regions in the first support layer and the second support layer are more easily etched and removed relative to the body regions, that is, in the embodiment of the present disclosure, the body regions and the doped regions in the first support layer and the second support layer have different etching selectivity ratios. Thus, a stacked structure with different etching selectivity ratios can be provided. The stacked structure provided by an embodiment of the present disclosure can be used to form a capacitor via, and after forming the capacitor via, a first material layer, a second material layer, and a third material layer can also be formed in the capacitor via. For the formation process of forming the first material layer, the second material layer, and the third material layer, please refer to the above embodiments.

[0123] The stacked structure provided by the embodiments of the present disclosure is similar to the stacked structure in the above embodiments. For the technical features not exhaustively disclosed in the embodiments of the present disclosure, please refer to the above embodiments for understanding, and will not be elaborated here.

[0124] In addition, the embodiments of the present disclosure further provide a method for forming a stacked structure, and the stacked structure is located on the surface of a substrate. Figure 4 As shown in the flowchart of a method for forming a stacked structure provided by the embodiments of the present disclosure, Figure 4 as shown in the figure, the method for forming a stacked structure includes the following steps:

[0125] Step S401: Alternately form a sacrificial layer and an initial support layer on the surface of the substrate in sequence.

[0126] In the embodiments of the present disclosure, the stacked structure is used to form a capacitor structure, and the substrate at least includes a contact structure for electrically connecting to the formed capacitor structure. In other embodiments, the substrate further includes a semiconductor substrate, a word line structure inside the semiconductor substrate, and a bit line structure on the surface of the semiconductor substrate, etc. The initial support layer is used to provide support for the formed capacitor structure to prevent the collapse of the capacitor structure.

[0127] Step S402: Perform ion implantation on a part of the initial support layer to form a support layer including a doped region and a body region.

[0128] In the embodiments of the present disclosure, atoms with a relatively small atomic number such as hydrogen atoms, helium atoms, or boron atoms are used to perform ion implantation on a part of the initial support layer to form a doped region, and the initial support layer without ion implantation forms a body region. The doped region and the body region together form the support layer.

[0129] In the embodiments of the present disclosure, the process parameters for ion implantation of the initial support layer include ion implantation angle, ion implantation energy, and ion implantation dose; among them, the ion implantation angle is from 0° to 55°, for example, it can be 10°, 30°, or 50°; the ion implantation energy is from 1000 electron volts to 100000 electron volts, for example, it can be 5000 electron volts or 60000 electron volts; the ion implantation dose is 10 13 atoms / mm² to 10 16 atoms / mm², for example, it can be 10 14 atoms / mm² or 10 15 atoms / mm².

[0130] In the embodiments of the present disclosure, by performing ion implantation on a part of the initial support layer with hydrogen atoms, helium atoms, or boron atoms having a relatively small atomic number, etc., it is possible to easily dope hydrogen atoms, helium atoms, or boron atoms into the initial support layer, and the doped ions can break the original chemical bonds in the initial support layer and generate new chemical bonds. The bond energy of the new chemical bonds is less than the bond energy of the original chemical bonds in the initial support layer, so that the hardness of the doped initial support layer (i.e., the doped region) is lower than that of the undoped initial support layer (i.e., the bulk region). Therefore, the doped region is easier to be etched and removed relative to the bulk region. In this way, a first support layer with different etching selectivity ratios can be obtained.

[0131] In some embodiments, the sacrificial layer includes a first sacrificial layer and a second sacrificial layer; the initial support layer includes a first initial support layer and a second initial support layer; the support layer includes a first support layer and a second support layer; the sacrificial layer and the support layer are formed through the following steps:

[0132] Step S1: Form a first sacrificial layer and a first initial support layer on the surface of the substrate in sequence.

[0133] Step S2: Perform ion implantation on a part of the first initial support layer to form the first support layer including a first doped region and a first bulk region.

[0134] Step S3: Form a second sacrificial layer and a second initial support layer on the surface of the first support layer in sequence.

[0135] Step S4: Perform ion implantation on a part of the second initial support layer to form the second support layer including a second doped region and a second bulk region.

[0136] In the embodiments of the present disclosure, the process of ion implantation on the first initial support layer and the second initial support layer is the same as the ion implantation process in the above embodiments, and will not be elaborated here.

[0137] In the embodiments of the present disclosure, the second doped region is located directly above the first doped region, and the hardness of the first doped region is less than that of the first bulk region, and the hardness of the second doped region is less than that of the second bulk region.

[0138] The method for forming the stacked structure in the embodiments of the present disclosure is similar to the stacked structure in the above embodiments. For the technical features not elaborated in the embodiments of the present disclosure, please refer to the above embodiments for understanding and will not be elaborated here.

[0139] The laminated structure formed by the method for forming a laminated structure provided in the embodiments of the present disclosure has a support layer including a doped region and a body region, and the hardness of the doped region in the support layer is less than that of the body region. Therefore, the doped region in the support layer is more easily etched and removed relative to the body region. That is, in the embodiments of the present disclosure, the body region and the doped region in the support layer have different etching selectivity ratios. Thus, a laminated structure with different etching selectivity ratios can be prepared.

[0140] In several embodiments provided by the present disclosure, it should be understood that the disclosed devices and methods can be implemented in a non-target manner. The device embodiments described above are merely illustrative. For example, the division of the units is only a logical function division. In actual implementation, there may be other division methods. For example, multiple units or components can be combined, or can be integrated into another system, or some features can be ignored, or not executed. Additionally, the couplings between the various components shown or discussed are either direct couplings.

[0141] The units described above as separate components may or may not be physically separated, and the components shown as units may or may not be physical units. That is, they can be located in one place or distributed to multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0142] The features disclosed in several method or device embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments or device embodiments.

[0143] As described above, these are only some implementation manners of the embodiments of the present disclosure, but the protection scope of the embodiments of the present disclosure is not limited thereto. Any person skilled in the art within the technical scope disclosed by the embodiments of the present disclosure can easily think of changes or substitutions, which should all be covered by the protection scope of the embodiments of the present disclosure. Therefore, the protection scope of the embodiments of the present disclosure shall be subject to the protection scope of the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, The method includes: Providing a stacked structure; the stacked structure includes a sacrificial layer and a support layer that are alternately stacked in sequence, the support layer includes a doped region and a body region; the hardness of the doped region is less than the hardness of the body region; Performing a first etching process to form a first void in the stacked structure that penetrates the body region and the sacrificial layer; Depositing a first material layer on the inner wall of the first void; Performing a second etching process to remove the doped region and the sacrificial layer, and forming a second void between adjacent first voids.

2. The method according to claim 1, wherein The sacrificial layer includes a first sacrificial layer and a second sacrificial layer; the support layer includes a first support layer and a second support layer; the stacked structure includes the first sacrificial layer, the first support layer, the second sacrificial layer, and the second support layer stacked in sequence; Wherein, the first support layer includes a first doped region and a first body region; the second support layer includes a second doped region and a second body region; the second doped region is directly above the first doped region, and the hardness of the first doped region is less than the hardness of the first body region, and the hardness of the second doped region is less than the hardness of the second body region.

3. The method according to claim 2, wherein The stacked structure is formed on a substrate; The providing the stacked structure includes: Providing the substrate; Sequentially forming the first sacrificial layer and a first initial support layer on the surface of the substrate; Performing ion implantation on part of the first initial support layer to form the first support layer; Sequentially forming the second sacrificial layer and a second initial support layer on the surface of the first support layer; Performing ion implantation on part of the second initial support layer to form the second support layer.

4. The method according to claim 3, wherein The first doped region is formed through the following steps: Forming a first photoresist layer on the surface of the first initial support layer; the first photoresist layer has a preset pattern, and the preset pattern exposes part of the surface of the first initial support layer; Performing ion implantation on the exposed part of the first initial support layer to form the first doped region.

5. The method according to claim 4, wherein The ions during the ion implantation are formed by at least one of the following materials: hydrogen atoms, helium atoms, or boron atoms.

6. The method according to claim 4, wherein The process parameters during the ion implantation include: ion implantation angle, ion implantation energy, and ion implantation dose; Among them, the ion implantation angle is from 0 degrees to 55 degrees; the ion implantation energy is from 1000 electron volts to 100000 electron volts; the ion implantation dose is from 10 13 atoms per square millimeter to 10 16 atoms per square millimeter.

7. The method according to claim 4, wherein The etching selectivity between the first doped region and the substrate is greater than the etching selectivity between the first body region and the substrate.

8. The method according to any one of claims 4 to 7, characterized in that The second doped region is formed through the following steps: Forming a second photoresist layer on the surface of the second initial support layer; the second photoresist layer has the preset pattern, and the preset pattern exposes part of the surface of the second initial support layer; Performing ion implantation on the exposed part of the second initial support layer to form the second doped region.

9. The method according to claim 8, characterized in that, The etching selectivity between the second doped region and the substrate is greater than the etching selectivity between the second body region and the substrate.

10. The method according to claim 3, wherein The stacked structure further includes a bottom support layer, the first sacrificial layer is located on the surface of the bottom support layer; the first void is formed through the following steps: Forming a patterned mask layer on the surface of the stacked structure; Through the graphical mask layer, the second support layer, the second sacrificial layer, the first support layer, the first sacrificial layer, and the bottom support layer are etched in sequence until the surface of the substrate is exposed, forming the first void and the stacked structure.

11. The method according to claim 10, characterized in that, While depositing a first material layer on the inner wall of the first void, the first material layer is deposited on the top of the stacked structure.

12. The method according to claim 11, wherein Before removing the doped region and the sacrificial layer, the method further includes: Removing the first material layer on the top of the stacked structure to expose the second doped region and the second body region.

13. The method according to any one of claims 10 to 12, characterized in that The second void is formed by the following steps: Adopting a wet etching process to simultaneously remove the second doped region, the second sacrificial layer, the first doped region, and the first sacrificial layer in the stacked structure, forming the second void located between two adjacent first voids.

14. The method according to claim 13, wherein The etching solution used in the wet etching process includes: a dilute hydrofluoric acid solution and a mixed solution of hydrofluoric acid and ammonium fluoride.

15. The method according to claim 13, wherein The process temperature of the wet etching process is 20°C to 60°C.

16. The method according to claim 1, wherein After removing the doped region and the sacrificial layer, the method further includes: Sequentially depositing a second material layer and a third material layer on the surface of the first material layer.

17. A stacked structure, characterized in that, The stacked structure includes sacrificial layers and support layers that are alternately stacked in sequence; Wherein, the support layer includes a doped region and a body region, and the hardness of the doped region is less than the hardness of the body region.

18. The laminated structure according to claim 17, wherein The sacrificial layer includes a first sacrificial layer and a second sacrificial layer; the support layer includes a first support layer and a second support layer; the stacked structure includes a first sacrificial layer, a first support layer, a second sacrificial layer, and a second support layer stacked in sequence; Wherein, the first support layer includes a first doped region and a first body region; the second support layer includes a second doped region and a second body region; the second doped region is directly above the first doped region, and the hardness of the first doped region is less than the hardness of the first body region, and the hardness of the second doped region is less than the hardness of the second body region.

19. A method for forming a stacked structure, characterized in that, The stacked structure is located on the surface of the substrate; the method includes: Sequentially and alternately forming sacrificial layers and initial support layers on the surface of the substrate; Performing ion implantation on part of the initial support layer to form a support layer including a doped region and a body region; Wherein, the hardness of the doped region is less than the hardness of the body region.

20. The method according to claim 19, wherein The sacrificial layer includes a first sacrificial layer and a second sacrificial layer; the initial support layer includes a first initial support layer and a second initial support layer; the support layer includes a first support layer and a second support layer; The sacrificial layer and the support layer are formed by the following steps: Sequentially forming the first sacrificial layer and the first initial support layer on the surface of the substrate; Performing ion implantation on part of the first initial support layer to form the first support layer including a first doped region and a first body region; Sequentially forming the second sacrificial layer and the second initial support layer on the surface of the first support layer; Performing ion implantation on part of the second initial support layer to form the second support layer including a second doped region and a second body region; Wherein, the second doped region is located directly above the first doped region, and the hardness of the first doped region is less than that of the first body region, and the hardness of the second doped region is less than that of the second body region.

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