A chip scan chain test method based on power voltage control and a chip

Abstract

A chip scan chain test method based on power voltage control, characterized in that the method comprises the following steps: step 1, comparing the power voltage with a first threshold voltage, and generating a shift / capture control signal based on the comparison result; step 2, comparing the power voltage with a second threshold voltage, and generating a shift input / output control signal based on the comparison result; step 3, based on the shift input / output control signal, realizing the control of the shift or capture state of the first test pin in the chip; step 4, based on the capture control signal, realizing the control of the input or output state of the second test pin in the chip. The present application has simple principle, accurate test result, wide application range, and is effectively suitable for small chips with less pins.

Description

Technical Field

[0001] This invention relates to the field of integrated circuits, and more specifically, to a chip scan chain test method and chip based on power supply voltage control. Background Technology

[0002] Currently, scan chain testing is the most commonly used method for digital circuit testing during the chip final product testing phase. This is because, as a crucial method for integrated circuit testing, scan chain testing differs from conventional testing. As an important means of structural testing, test engineers do not need to understand the chip's circuit structure or basic functions; they only need to view the chip as a combination of numerous registers and logic elements to perform the test. Furthermore, this test can effectively test all circuits within the chip and can effectively detect any anomalies in the chip's combinational circuits or sequential logic functions, thereby effectively eliminating defective chips and improving the overall quality of the chips before they leave the factory.

[0003] Based on the principles of scan chain testing, proper chip testing requires the use of multiple pins on the chip for data input and output interaction. For example, scan chain testing utilizes five different signals: the scan mode signal SCAN_MOD, the input signal SCAN_IN, the clock signal SCAN_CLK, the scan enable signal SCAN_EN, and the output signal SCAN_OUT. The scan chain test circuit is connected to the chip under test to achieve the input or output of these five signals. This necessitates that the chip have at least five corresponding pins or wafer-level bonding pads.

[0004] However, some small integrated circuits with limited size and simple functionality do not have five chip pins, making scan chain testing of the chip impossible. Furthermore, even if some chips or integrated circuits have five or more chip pins, it is difficult to provide five chip pins for scan chain testing while simultaneously implementing multiple output functions of the chip.

[0005] Although existing technologies offer some solutions for multiplexing scan chain test pins with other functional pins of the chip—for example, patent document CN16291337B describes an apparatus and method for adjusting chip mode during scan chain testing—while it proposes a solution that reuses conventional ports used in scan chain testing based on a mode switching circuit, these solutions still struggle to reduce the number of corresponding chip pins in scan chain testing to less than three.

[0006] Therefore, there is an urgent need for a new chip scan chain test method and chip with power supply voltage control. Summary of the Invention

[0007] To address the shortcomings of existing technologies, the present invention aims to provide a chip scan chain test method and chip with power supply voltage control. The method uses the amplitude of the power supply voltage as the state control reference of the chip, realizes pin multiplexing for both shift and capture functions, and further reduces the number of pins by multiplexing the test data input and output ports.

[0008] The present invention adopts the following technical solution.

[0009] The first aspect of this invention relates to a chip scan chain testing method based on power supply voltage control, wherein the method includes the following steps: Step 1, comparing the power supply voltage with a first threshold voltage, and generating a shift / capture control signal based on the comparison result; Step 2, comparing the power supply voltage with a second threshold voltage, and generating a shift input / output control signal based on the comparison result; Step 3, controlling the shift or capture state of a first test pin in the chip based on the shift / capture control signal; Step 4, controlling the input or output state of a second test pin in the chip based on the shift input / output control signal.

[0010] Preferably, when the power supply voltage is higher than the first threshold voltage, the shift / capture control signal is in a low-level state, the first test pin receives the scan clock signal, and controls the second pin to perform test data shifting operation based on the scan clock signal; when the power supply voltage is lower than the first threshold voltage, the shift / capture control signal is in a high-level state, the first test pin receives the positive pulse signal, and performs chip capture operation based on the control of the positive pulse signal.

[0011] Preferably, when the power supply voltage is higher than the second threshold voltage, the shift input / output control signal is high, and the second test pin serves as an input pin to receive the data signal of the scan chain and input it into the chip; when the power supply voltage is lower than the second threshold voltage, the shift input / output control signal is low, and the second test pin serves as an output pin to receive the data signal of the chip and scan its output value into the scan chain.

[0012] Preferably, the power supply voltage of the chip has three operating states; wherein, in the first operating state, the power supply voltage is higher than a first threshold voltage; in the second operating state, the power supply voltage is between the first threshold voltage and the second threshold voltage; and in the third operating state, the power supply voltage is lower than the second threshold voltage.

[0013] Preferably, the first threshold voltage is 4.5V and the second threshold voltage is 3.5V.

[0014] A second aspect of the present invention relates to a chip, wherein the chip includes a pattern recognition unit and an input / output switching unit; the pattern recognition unit is connected to the input / output switching unit and a first test pin, respectively, and is used to receive a power supply voltage, a first threshold reference voltage and a second threshold reference voltage from the chip, generate a shift / capture control signal and a shift input / output control signal, and output the shift / capture control signal to the input / output switching unit; the input / output switching unit is connected to a second test pin, and is used to receive the shift input / output control signal from the pattern recognition unit, and realize data input or output based on the control signal.

[0015] Preferably, the pattern recognition unit includes a first comparator, a second comparator, a buffer, and a NAND gate; wherein, the positive input terminal of the first comparator is connected to the power supply voltage Vdd, the negative input terminal is connected to the second threshold reference voltage, and the output terminal is connected to the input terminal of the buffer and one input terminal of the NAND gate, respectively; the positive input terminal of the second comparator is connected to the power supply voltage Vdd, the negative input terminal is connected to the first threshold reference voltage, and the output terminal is connected to the other input terminal of the NAND gate; the buffer outputs a shift input / output control signal SCAN_IN_EN, and the NAND gate outputs a shift / capture control signal SCAN_EN.

[0016] Preferably, the input / output switching unit includes a NOR gate, an output transistor, and a voltage-limiting resistor; wherein, one input terminal of the NOR gate is connected to the shift input / output control signal SCAN_IN_EN, the other input terminal is connected to the chip's data signal, and the output terminal is connected to the gate of the output terminal; the source of the output transistor is grounded, and the drain is connected to the voltage-limiting resistor and the second test pin respectively to receive the data signal from the second test pin.

[0017] The beneficial effects of this invention are that, compared with the prior art, the power supply voltage controlled chip scan chain test method and chip of this invention can use the amplitude of the power supply voltage as the state control reference of the chip, realize pin multiplexing for both shift and capture functions, and further reduce the number of pins by multiplexing the test data input and output ports. This invention has a simple principle, accurate test results, wide applicability, and is effectively adapted to small chips with a small number of pins. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of the control signal timing in a chip scan chain testing method according to the prior art of the present invention;

[0019] Figure 2 This is a schematic flowchart of the chip scan chain testing method based on power supply voltage control according to the present invention.

[0020] Figure 3This is a schematic diagram of the control signal timing for a chip scan chain testing method based on power supply voltage control according to the present invention.

[0021] Figure 4 This is a schematic diagram of the circuit structure of a pattern recognition unit in a chip according to the present invention;

[0022] Figure 5 This is a schematic diagram of the circuit structure of an input / output switching unit in a chip according to the present invention. Detailed Implementation

[0023] The present application will be further described below with reference to the accompanying drawings. The following embodiments are only used to more clearly illustrate the technical solutions of the present invention, and should not be construed as limiting the scope of protection of the present application.

[0024] Figure 1 This is a schematic diagram of the control signal timing in a chip scan chain testing method according to the prior art of this invention. Figure 1 As shown in the timing diagram of the existing scan chain testing method, according to the principle of scan chain, the main testing process includes at least a shift phase and a capture phase that switch between each other. Typically, in the shift phase, the input or output data moves serially in position following the clock cycle, while in the capture phase, the chip performs parallel capture of the input and output data.

[0025] In the existing technology, the scan mode signal SCAN_MOD will be in a high level state for a long time. This signal can be achieved by the power supply voltage signal inside the chip. However, the other four signals, such as the input signal SCAN_IN, the clock signal SCAN_CLK, the scan enable signal SCAN_EN, and the output signal SCAN_OUT, need to be connected or output using different chip pins.

[0026] To reduce the number of chip pins used in the scan chain test method, this invention proposes a new test method and a corresponding chip that can be tested using this method.

[0027] Figure 2 This is a schematic flowchart of the chip scan chain testing method based on power supply voltage control according to the present invention. Figure 3 This is a schematic diagram of the control signal timing for a chip scan chain testing method based on power supply voltage control according to the present invention. Figure 2 , Figure 3 As shown, a chip scan chain test method based on power supply voltage control is provided, wherein the method includes steps 1 to 4.

[0028] Step 1: Compare the power supply voltage with the first threshold voltage and generate a shift / capture control signal based on the comparison result.

[0029] It is understood that the power supply voltage and the first threshold voltage in this invention can be compared, thereby obtaining a control signal with high and low level switching based on the comparison result.

[0030] Before proceeding to step 1 of this invention, the chip should first be put into scan chain mode via a communication interface connection. Specifically, this invention can use the only data pin with SCAN_IN and SCAN_OUT modes as the pin for receiving scan chain scan mode signals. To enable the chip to enter scan chain mode, a fixed-length data content can be input into the chip using methods commonly used in the prior art, thereby setting the registers in the chip and entering scan chain mode. After entering this mode, when SCAN_IN and SCAN_OUT, SCAN_EN and SCAN_EN_IN signals are input to this pin, the registers in the chip can effectively recognize the content of the aforementioned signals.

[0031] The first threshold in this invention can classify the power supply voltage into two categories, and control signals with high and low levels are implemented based on the classification results. This control signal is called a shift / capture signal because when this signal is high or low, it can put the chip in a shift state for scan chain testing, or when it is both low and high, it can put the chip in a capture state for scan chain testing.

[0032] Preferably, when the power supply voltage is higher than the first threshold voltage, the shift / capture control signal is in a low-level state, the first test pin receives the scan clock signal, and controls the second pin to perform test data shifting operation based on the scan clock signal; when the power supply voltage is lower than the first threshold voltage, the shift / capture control signal is in a high-level state, the first test pin receives the positive pulse signal, and performs chip capture operation based on the control of the positive pulse signal.

[0033] It is understood that in this invention, if the power supply voltage is higher than the first threshold voltage, the control signal is implemented in a low-level state. At this time, the clock signal should be a pulse signal with a normal clock cycle. When the power supply voltage is lower than the first threshold voltage, the control signal is implemented in a high-level state. At this time, the clock signal no longer outputs a pulse signal that switches between high and low levels, but instead outputs only a single positive pulse during the entire high-level period of the control signal. This pulse is used to instruct other circuits in the chip to perform data capture operations.

[0034] Step 2: Compare the power supply voltage with the second threshold voltage, and generate a shift input / output control signal based on the comparison result.

[0035] It is understood that the methods in steps 1 and 2 of this invention can be implemented simultaneously. That is, in this invention, when comparing the power supply voltage with the first threshold voltage, the power supply voltage can be compared with the second threshold voltage simultaneously. The second threshold voltage's further binary classification of the power supply voltage allows the chip, while in the shift state of the scan chain test, to determine whether the port in the chip that multiplexes input and output functions should be in the state of receiving input signals or in the state of outputting signals.

[0036] Preferably, when the power supply voltage is higher than the second threshold voltage, the shift input / output control signal is high, and the second test pin serves as an input pin to receive the data signal of the scan chain and input it into the chip; when the power supply voltage is lower than the second threshold voltage, the shift input / output control signal is low, and the second test pin serves as an output pin to receive the data signal of the chip and scan its output value into the scan chain.

[0037] It is understood that when the power supply voltage in this invention is greater than the second threshold voltage, the control signal is implemented as a high level. At this time, the second test pin can receive external input and input the received signal into the chip in a serial shift manner, waiting for the relevant circuit inside the chip to capture it.

[0038] In addition, when the power supply voltage is less than the second threshold voltage, the control signal is low. At this time, the MOS transistor in the second test pin is turned on, and the gate of the MOS transistor receives the internal output of the chip. The chip pin transmits the output voltage of the internal MOS transistor to the external test circuit through the pin.

[0039] Preferably, the power supply voltage of the chip has three operating states; wherein, in the first operating state, the power supply voltage is higher than a first threshold voltage; in the second operating state, the power supply voltage is between the first threshold voltage and the second threshold voltage; and in the third operating state, the power supply voltage is lower than the second threshold voltage.

[0040] It is easy to understand that, in order for the two control signals—the shift / capture control signal and the input / output control signal mentioned above—to accurately determine the current operating state of the chip, the power supply voltage should have at least three different amplitudes under high-level conditions. For example, in one embodiment of the present invention, the power supply voltage under normal chip operating conditions is 4V, but to implement the test method of the present invention, the power supply voltage can also be in a state of 3V or 5V.

[0041] Preferably, the first threshold voltage is 4.5V and the second threshold voltage is 3.5V.

[0042] In one embodiment of the present invention, the first threshold voltage is set to be higher than the second threshold voltage. However, to achieve the function of the present invention, the first threshold voltage can also be reasonably set to be lower than the second threshold voltage.

[0043] In this invention, since the power supply voltage has three operating states of 3V, 4V and 5V, the intermediate value can be selected from two adjacent states of the three operating states, so as to more accurately distinguish the state of the chip, that is, to obtain the most accurate first threshold voltage and second threshold voltage.

[0044] Step 3: Based on the shift / capture control signal, control the shift or capture state of the first test pin in the chip;

[0045] Step 4: Based on the shift input / output control signal, control the input or output state of the second test pin in the chip;

[0046] In this invention, steps 3 and 4 are based on the judgment premises in steps 1 and 2, respectively. When the corresponding control signal is judged and generated, the corresponding circuit inside the chip can be used to realize the corresponding state of the chip.

[0047] A second aspect of the present invention relates to a chip.

[0048] The chip includes a pattern recognition unit and an input / output switching unit. The pattern recognition unit is connected to the input / output switching unit and a first test pin, respectively. It receives the power supply voltage, a first threshold reference voltage, and a second threshold reference voltage from the chip, generates a shift / capture control signal and a shift input / output control signal, and outputs the shift / capture control signal to the input / output switching unit. The input / output switching unit is connected to a second test pin. It receives the shift input / output control signal from the pattern recognition unit and implements data input or output based on the control signal.

[0049] It is understood that the pattern recognition unit in this invention can implement steps 1 and 3 in the method described in the first part of this invention, while the input / output switching unit in this invention can implement steps 2 and 4 in the method described in the second part of this invention.

[0050] In this invention, after the shift / capture control signal is generated, the content recorded in the signal can be read by the internal scan register of the chip, and the shift or capture function can be executed accordingly.

[0051] As mentioned above, generally speaking, in order for a chip to enter the scanning logic, the chip's internal registers include both a normal input interface and a scan input interface. When the circuit is not in the scanning state, the normal input interface is used for data reading and writing. However, when the circuit enters the scanning state, it uses the scan input interface to read the corresponding data obtained during the scan.

[0052] Figure 4 This is a schematic diagram of the circuit structure of a pattern recognition unit in a chip according to the present invention. Figure 4 As shown, preferably, the pattern recognition unit includes a first comparator, a second comparator, a buffer, and a NAND gate; wherein, the positive input terminal of the first comparator is connected to the power supply voltage Vdd, the negative input terminal is connected to the second threshold reference voltage, and the output terminal is connected to the input terminal of the buffer and one input terminal of the NAND gate, respectively; the positive input terminal of the second comparator is connected to the power supply voltage Vdd, the negative input terminal is connected to the first threshold reference voltage, and the output terminal is connected to the other input terminal of the NAND gate; the buffer outputs a shift input / output control signal SCAN_IN_EN, and the NAND gate outputs a shift / capture control signal SCAN_EN.

[0053] It is understood that the pattern recognition unit in this invention includes two comparators, which can compare the power supply voltage with the first and second threshold voltages respectively, and generate a shift input / output control signal SCAN_IN_EN and a shift / capture control signal SCAN_EN after simple processing.

[0054] It should be noted that, in order to maintain complete synchronization between the shift input / output control signal SCAN_IN_EN and the shift / capture control signal SCAN_EN, a buffer needs to be connected before the shift input / output control signal SCAN_IN_EN in this invention, so that the buffer can output the signal synchronously with the NAND gate.

[0055] Figure 5 This is a schematic diagram of the circuit structure of an input / output switching unit in a chip according to the present invention. Figure 5 As shown, preferably, the input / output switching unit includes a NOR gate, an output transistor, and a voltage-limiting resistor; wherein, one input terminal of the NOR gate is connected to the shift input / output control signal SCAN_IN_EN, the other input terminal is connected to the chip's data signal, and the output terminal is connected to the gate of the output terminal; the source of the output transistor is grounded, and the drain is connected to the voltage-limiting resistor and the second test pin respectively to receive the data signal from the second test pin.

[0056] It is understood that the MOS transistor in this invention can be turned on or off according to the control of the shift input / output control signal SCAN_IN_EN. When the transistor is on, the output signal SCAN_OUT can be output from the chip to the external test circuit. When the transistor is off, the input signal SCAN_IN can be shifted from the external test circuit to the inside of the chip.

[0057] The beneficial effects of this invention are that, compared with the prior art, the power supply voltage controlled chip scan chain test method and chip of this invention can use the amplitude of the power supply voltage as the state control reference of the chip, realize pin multiplexing for both shift and capture functions, and further reduce the number of pins by multiplexing the test data input and output ports. This invention has a simple principle, accurate test results, wide applicability, and is effectively adapted to small chips with a small number of pins.

[0058] The applicant of this invention has provided a detailed description of the embodiments of the invention in conjunction with the accompanying drawings. However, those skilled in the art should understand that the above embodiments are merely preferred embodiments of the invention. The detailed description is only intended to help readers better understand the spirit of the invention and is not intended to limit the scope of protection of the invention. On the contrary, any improvements or modifications made based on the inventive spirit of the invention should fall within the scope of protection of the invention.

Claims

1. A chip scan chain testing method based on power supply voltage control, characterized in that, The method includes the following steps: Step 1: Compare the power supply voltage with the first threshold voltage, and generate a shift / capture control signal based on the comparison result; Step 2: Compare the power supply voltage with the second threshold voltage, and generate a shift input / output control signal based on the comparison result; Step 3: Based on the shift / capture control signal, control the shift or capture state of the first test pin in the chip; Step 4: Based on the shift input / output control signal, control the input or output state of the second test pin in the chip; When the power supply voltage is higher than the first threshold voltage, the shift / capture control signal is in a low level state, the clock signal is a pulse signal with a normal clock cycle, the first test pin receives the scan clock signal, and controls the second test pin to perform test data shifting operation based on the scan clock signal; When the power supply voltage is lower than the first threshold voltage, the shift / capture control signal is in a high-level state. At this time, the clock signal no longer outputs a pulse signal that switches between high and low levels. Instead, it outputs only a positive pulse during the entire high-level period of the control signal. The first test pin receives the positive pulse signal and implements the capture operation of the chip based on the control of the positive pulse signal. When the power supply voltage is higher than the second threshold voltage, the shift input / output control signal is high, and the second test pin serves as an input pin to receive the data signal of the scan chain and input it into the chip; When the power supply voltage is lower than the second threshold voltage, the shift input / output control signal is low, and the second test pin, as an output pin, receives the data signal from the chip and outputs its value into the scan chain.

2. The chip scan chain testing method based on power supply voltage control as described in claim 1, characterized in that: The chip's power supply voltage has three operating states; among them, In the first operating state, the power supply voltage is higher than the first threshold voltage; In the second operating state, the power supply voltage is between the first threshold voltage and the second threshold voltage; In the third operating state, the power supply voltage is lower than the second threshold voltage.

3. The chip scan chain testing method based on power supply voltage control according to claim 2, characterized in that: The first threshold voltage is 4.5V, and the second threshold voltage is 3.5V.

4. A chip based on the method of any one of claims 1-3, characterized in that: The chip includes a pattern recognition unit and an input / output switching unit; wherein... The pattern recognition unit is connected to the input / output switching unit and the first test pin, respectively, and is used to receive the power supply voltage, the first threshold reference voltage and the second threshold reference voltage from the chip, generate a shift / capture control signal and a shift input / output control signal, and output the shift / capture control signal to the input / output switching unit; The input / output switching unit is connected to the second test pin and is used to receive shift input / output control signals from the pattern recognition unit, and to realize data input or output based on the control signals.

5. A chip according to claim 4, characterized in that: The pattern recognition unit includes a first comparator, a second comparator, a buffer, and a NAND gate; wherein, The positive input terminal of the first comparator is connected to the power supply voltage Vdd, the negative input terminal is connected to the second threshold reference voltage, and the output terminal is connected to the input terminal of the buffer and one input terminal of the NAND gate, respectively. The positive input terminal of the second comparator is connected to the power supply voltage Vdd, the negative input terminal is connected to the first threshold reference voltage, and the output terminal is connected to the other input terminal of the NAND gate. The buffer outputs the shift input / output control signal SCAN_IN_EN, and the NAND gate outputs the shift / capture control signal SCAN_EN.

6. A chip according to claim 5, characterized in that: The input / output switching unit includes a NOR gate, an output transistor, and a voltage-limiting resistor; wherein, One input of the NOR gate is connected to the shift input / output control signal SCAN_IN_EN, the other input is connected to the data signal of the chip, and the output is connected to the gate of the output gate. The source of the output transistor is grounded, and the drain is connected to a voltage limiting resistor and a second test pin, respectively, to receive data signals from the second test pin.

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