In-memory arithmetic devices and their operation methods

Abstract

This invention provides an in-memory computing device and its computing method. The memory array includes a shift weight storage area storing shift weight values, a shift information storage area storing the number of shift units, and a shift unit quantity storage area storing the amount of shift units. The shift recovery circuit recovers the weight shift amount of the shifted product sum based on the number of shift units of the shift weight values ​​and the column shift unit quantity, thereby generating multiple recovered product sums.

Description

Technical Field

[0001] This invention relates to a computing device, and more particularly to an in-memory computing device and its computing method. Background Technology

[0002] Artificial intelligence (AI) refers to the technology of using computer programs to represent human intelligence. Currently, it has achieved superior levels in areas such as image recognition, language analysis, and board games. Taking AI networks for image recognition as an example, convolutional neural networks (CNNs) are currently widely used for image recognition. These involve many multiply-accumulate (MAC) calculations, which involve multiplying the values ​​(weights) in each memory component stored in the memory array by the input value and summing all products. This involves a large amount of data movement, thus leading to high power consumption. Summary of the Invention

[0003] This invention provides an in-memory computing device and its computing method, which can effectively reduce the power consumption of the in-memory computing device.

[0004] The in-memory computing device of the present invention includes a memory control circuit, a memory array, a sensing circuit, and a shift recovery circuit. The memory array is coupled to the memory control circuit, which controls data access to the memory array. The memory array includes a shift weight storage area, a shift information storage area, and a shift unit quantity storage area. The shift weight storage area stores multiple shift weight values ​​and provides multiple shift product sums based on multiple input signals provided by the memory control circuit through multiple first word lines. The shift information storage area stores the number of shift units for the shift weight values ​​and provides the number of shift units for the shift weight values ​​based on multiple control signals provided by the memory control circuit through multiple second word lines. The shift unit quantity storage area stores shift unit quantities and provides column shift unit quantities based on input signals, wherein the column shift unit quantity is equal to the sum of the product of the input signal and the shift unit quantity. The sensing circuit is coupled to the memory array and senses multiple current signals provided by the shift weight storage area, the shift information storage area, and the shift unit quantity storage area to obtain the shift product sum, the number of shift units for the shift weight values, and the column shift unit quantity. The shift recovery circuit is coupled to the sensing circuit and recovers the weight shift amount of the shifted product sum based on the number of shift units of the shifted weight value and the column shift unit amount, so as to generate multiple recovered product sums.

[0005] The present invention also provides an operation method for an in-memory computing device, wherein the in-memory computing device includes a memory array, the memory array including a shifted weight storage area, a shift information storage area, and a shift unit quantity storage area. The shifted weight storage area stores multiple shifted weight values, the shift information storage area stores the number of shift units for the shifted weight values, and the shift unit quantity storage area stores the number of shift units. The operation method of the in-memory computing device includes the following steps: Providing multiple control signals to the shift information storage area to cause the shift information storage area to provide the number of shift units for the shifted weight values. Providing multiple input signals to the shifted weight storage area and the shift unit quantity storage area to cause the shifted weight storage area to provide multiple shifted product sums, and to cause the shift unit quantity storage area to provide column shift unit quantities, wherein the column shift unit quantities are equal to the product sum of the input signals and the shift unit quantities. Recovering the weight shift amount of the shifted product sum based on the number of shift units for the shifted weight values ​​and the column shift unit quantities to generate multiple recovered product sums.

[0006] Based on the above, the memory array of this embodiment includes a shift weight storage area for storing shift weight values, a shift information storage area for storing the number of shift units, and a shift unit quantity storage area for storing the amount of shift units. The shift recovery circuit can recover the weight shift amount of the shifted product sum based on the number of shift units of the shift weight values ​​and the column shift unit quantity, thereby generating multiple recovered product sums. By storing the shift weight values ​​in the shift weight storage area and then using the number of shift units of the shift weight values ​​and the column shift unit quantity to recover the weight shift amount of the shifted product sum, the current value on the bit lines of the in-memory computing device during product sum operations can be effectively reduced, thus significantly reducing the power consumption of the in-memory computing device.

[0007] To make the above features and advantages of the present invention more apparent and understandable, specific embodiments are described below in conjunction with the accompanying drawings. Attached Figure Description

[0008] Figure 1 This is a schematic diagram of an in-memory computing device according to an embodiment of the present invention;

[0009] Figure 2 This is a circuit diagram of an in-memory computing device according to another embodiment of the present invention;

[0010] Figure 3 This is a schematic diagram of a shift restoration unit according to an embodiment of the present invention;

[0011] Figure 4 This is a schematic diagram of an in-memory computing device according to another embodiment of the present invention;

[0012] Figure 5This is a flowchart illustrating an in-memory computing device operation method according to an embodiment of the present invention. Detailed Implementation

[0013] Please refer to the following: Figure 1 , Figure 1 This is a schematic diagram of an in-memory computing device according to an embodiment of the present invention. The in-memory computing device may include a memory control circuit 102, a memory array 104, a sensing circuit 106, and a shift recovery circuit 108. The memory array 104 is coupled to the memory control circuit 102 and the sensing circuit 106, and the sensing circuit 106 is also coupled to the shift recovery circuit. The memory array 104 may include a shifted weight storage area 110, a shift information storage area 112, and a shift unit quantity storage area 114. The shifted weight storage area 110 stores a plurality of shifted weight values, the shift information storage area 112 stores the number of shift units NSF0 to NSFm corresponding to the plurality of shifted weight values, and the shift unit quantity storage area 114 stores the number of shift units.

[0014] The memory control circuit 102 can control the data access of the memory array 104. Furthermore, the memory control circuit 102 can provide multiple control signals X0 to XFi to the shift information storage area 112 via word lines WLF0 to WLFi, so that the shift information storage area 112 provides multiple shift unit numbers NSF0 to NSFm of shifted weight values ​​according to the control signals X0 to XFi, where i and m are positive integers. In addition, the memory control circuit 102 can provide multiple input signals X0 to Xj to the shifted weight storage area 110 and the shift unit quantity storage area 114 via word lines WL0 to WLj (where j is a positive integer), so that the shifted weight storage area 110 provides multiple shifted products YS0 to YSm according to the multiple input signals X0 to Xj, and the shift unit quantity storage area 114 provides column shift unit quantities Yu via bit line BLu according to the input signals X0 to Xj. The shifted product sum YS0~YSm is the sum of the product of the input signals X0~Xj and multiple shifted weight values. For example, the shifted product sum YS0 and YS1 can be represented by the following equations (1) and (2):

[0015]

[0016]

[0017] Where Xn is the input signal of word line WLn, and SF0 and SF1 are the shift amounts of the shifted weight values ​​stored in the memory cells on bit lines BL0 and BL1, respectively. Wn0 is the weight value before shifting the shifted weight value stored in the memory cell on bit line BL0 corresponding to word line WLn, and Wn1 is the weight value before shifting the shifted weight value stored in the memory cell on bit line BL1 corresponding to word line WLn, that is, Wn0 and Wn1 are the original weight values, "Wn0-SF0" is the shifted weight value stored in the memory cell on bit line BL0 corresponding to word line WLn, and "Wn1-SF1" is the shifted weight value stored in the memory cell on bit line BL1 corresponding to word line WLn. Similarly, YS2 to YSm can also be represented in a similar way to equation (1) or (2), which will not be elaborated here.

[0018] The sensing circuit 106 can sense the current signals provided by the shifted weight storage area 110, the shift unit quantity storage area 114, and the shift information storage area 112 to obtain the number of shift units NSF0 to NSFm and the column shift unit quantity Yu corresponding to the shifted product sums YS0 to YSm and the bit lines BL0 to BLm, where the column shift unit quantity Yu is equal to the sum of the product of the input signals X0 to Xj and the shift unit quantity stored in the shift unit quantity storage area 114. The shift recovery circuit 108 can recover the weight shift amount of the shifted product sums YS0 to YSm according to the number of shift units NSF0 to NSFm and the column shift unit quantity Yu to generate multiple recovered product sums Y0 to Ym. For example, the recovered product sum Y0 can be represented by the following equation (3):

[0019]

[0020] As shown in equation (3), in this embodiment, the column shift unit quantity Yu is the sum of the product of the input signals X0~Xj and the shift unit quantity (in this embodiment, the shift unit quantity stored in each storage unit in the shift unit quantity storage area 114 is set to 1, but this is not a limitation, and the shift unit quantity can be set as needed), and the product value (shift adjustment amount) of the column shift unit quantity Yu and the number of shift units NSF0 is designed to be equal to the shift amount SF0 of the shifted weight value corresponding to the bit line BL0. Therefore, the restored product sum Y0 with the weight shift amount restored can be obtained. Similarly, the restored product sum Y1 can be shown in equation (4) below:

[0021]

[0022] Similarly, Y2~Ym can also be expressed in a manner similar to equation (3) or (4), which will not be elaborated here.

[0023] By storing the shifted weight values ​​in the shifted weight storage area 110, and then using the number of shift units NSF0 to NSFm of the shifted weight values ​​and the number of column shift units Yu to restore the weight shift amount of the shifted product and YS0 to YSm, the current value on the bit lines BL0 to BLm of the memory arithmetic device during product and sum operations can be effectively reduced, thereby significantly reducing the power consumption of the memory arithmetic device.

[0024] Figure 2 This is a circuit diagram of an in-memory processing device according to another embodiment of the present invention. Further, Figure 1 The memory array 104 in the embodiment may, for example, Figure 2 As shown, it is implemented using a NOR flash memory array, wherein the shifted weight storage area 110 includes multiple storage cells C1, the shifted information storage area 112 includes multiple storage cells C2, the shifted cell quantity storage area 114 includes multiple storage cells C3, and the sensing circuit 106 includes sensors SA0 to SAm and sensor SAu.

[0025] Each memory cell C1, C2, and C3 has one end coupled to the corresponding sensor via a corresponding bit line, and the other end coupled to the source line SL. The control terminal is coupled to the corresponding word line. For example, memory cells C1 and C2 on bit line BL0 have one end coupled to sensor SA0 via bit line BL0, and the other end coupled to the source line SL. The control terminal of memory cell C1 on bit line BL0 is coupled to word lines WL0 to WLj, and the control terminal of memory cell C2 on bit line BL0 is coupled to word lines WLF0 to WLFi. Similarly, memory cell C3 on bit line BL0 has one end coupled to bit line BL0, the other end coupled to the source line SL, and the control terminal coupled to word lines WL0 to WLj and WLF0 to WLFi.

[0026] Multiple memory cells C1 can receive input signals X0 to Xj from word lines WL0 to WLj, and provide current signals representing the shifted product and YS0 to YSm to sensors SA0 to SAm via bit lines BL0 to BLm based on the input signals X0 to Xj. The memory control circuit 102 can adjust the shifted weight values ​​stored in memory cells C1, for example, by adjusting the threshold voltage or resistance value of the memory cells C1, so that the shifted weight values ​​have a desired offset. Memory cells C1 on the same bit line store shifted weight values ​​with the same shift amount; for example, memory cells C1 on bit line BL0 store shifted weight values ​​with the same shift amount SF0. ​​Multiple memory cells C2 can receive control signals XF0 to XFi from word lines WLF0 to WLFi, and provide current signals representing the number of shift units NSF0 to NSFm of the shifted weight values ​​to sensors SA0 to SAm via bit lines BL0 to BLm based on the control signals XF0 to XFi. In addition, multiple storage cells C3 can receive input signals X0 to Xj from word lines WL0 to WLj, and provide current signals representing column shift unit quantity Yu to sensor SAu through bit line BLu based on input signals X0 to Xj.

[0027] Sensors SA0 to SAm and SAu are coupled to corresponding bit lines BL0 to BLm, BLu, and shift recovery circuit 108. They provide sensing results such as the shifted product sum YS0 to YSm, the number of shift units NSF0 to NSFm, and the column shift unit quantity Yu to shift recovery circuit 108 to restore the weighted shift amount of the shifted product sum YS0 to YSm, thereby generating the restored product sum Y0 to Ym. The shift recovery circuit 108 can be implemented as follows: Figure 3 As shown, the circuit includes a shift register 302 and an adder circuit 304. The shift register 302 is coupled to sensors SA0-SAm and sensor SAu, and the adder circuit 304 is coupled to the shift register 302. The shift register 302 can receive shift unit numbers NSF0-NSFm and column shift unit amounts Yu provided by sensors SA0-SAm and sensor SAu, and generate shift adjustment amounts AD0-ADm based on the shift unit numbers NSF0-NSFm and column shift unit amounts Yu to restore the shifted products and sums YS0-YSm. The adder circuit 304 can add the shifted products and sums YS0-YSm provided by sensors SA0-SAm to the corresponding shift adjustment amounts AD0-ADm to generate multiple restored products and sums Y0-Ym.

[0028] It is worth noting that although the shifted weight storage area 110 and the shifted information storage area 112 in the above embodiments share bit lines BL0 to BLm, in other embodiments, the shifted weight storage area 110 and the shifted information storage area 112 may use different bit lines. For example, in Figure 4 In this embodiment, the shifted weight storage area 110 is coupled to bit lines BL0 to BLm, while the shifted information storage area 112 is coupled to bit lines BLK0 to BLKm. Since the shifted weight storage area 110 and the shifted information storage area 112 in this embodiment do not share bit lines, it is not necessary to drive the shifted information storage area 112 and the shifted weight storage area 110 sequentially to obtain the number of shifted units NSF0 to NSFm and the shifted product sum YS0 to YSm. Instead, the shifted information storage area 112 and the shifted weight storage area 110 can be driven simultaneously, so that the shifted information storage area 112 and the shifted weight storage area 110 simultaneously provide the number of shifted units NSF0 to NSFm and the shifted product sum YS0 to YSm, thereby effectively improving the computational efficiency of the in-memory computing device.

[0029] Figure 5 This is a flowchart illustrating an in-memory computing device operation method according to an embodiment of the present invention. The in-memory computing device includes a memory array, which includes a shift weight storage area, a shift information storage area, and a shift unit quantity storage area. The shift weight storage area stores multiple shift weight values, the shift information storage area stores the number of shift units for each shift weight value, and the shift unit quantity storage area stores the number of shift units. The shift weight storage area may include multiple first storage units, the shift information storage area may include multiple second storage units, and the shift unit quantity storage area may include multiple third storage units. The multiple first storage units and the multiple second storage units share multiple bit lines, and the multiple first storage units and the multiple third storage units use different bit lines.

[0030] As can be seen from the above embodiments, the operation method of the in-memory computing device may include at least the following steps. First, multiple control signals are provided to the shift information storage area to enable the shift information storage area to provide multiple shift unit numbers of shifted weight values ​​(step S502), wherein the shifted weight values ​​stored in the first storage cell can be adjusted by adjusting the threshold voltage value or resistance value of the first storage cell, and the shifted weight values ​​stored in the first storage cell on the same bit line have the same shift amount. Next, multiple input signals are provided to the shifted weight storage area and the shift unit amount storage area to enable the shifted weight storage area to provide multiple shifted product sums, and the shift unit amount storage area to provide column shift unit amounts (step S504), wherein the column shift unit amount is equal to the sum of the products of the multiple input signals and the shift unit amounts. Finally, the weight shift amount of the sum of the multiple shifted products is restored based on the number of shift units and column shift units of the multiple shifted weight values ​​to generate multiple restored product sums (step S506). Further, multiple shift adjustment amounts can be generated based on the number of shift units and column shift units of the multiple shifted weight values, and then the multiple shifted product sums are added to their corresponding shift adjustment amounts to generate the multiple restored product sums. Furthermore, it is worth noting that in some embodiments, the bit lines coupled to the shifted weight storage area may be different from the bit lines coupled to the shift information storage area, which can effectively improve the computational efficiency of the in-memory processing device.

[0031] In summary, the memory array of this embodiment includes a shifted weight storage area for storing shifted weight values, a shift information storage area for storing the number of shift units, and a shift unit quantity storage area for storing the column shift unit quantity. The shift recovery circuit can recover the weight shift amount of the shifted product sum based on the number of shift units of the shifted weight values ​​and the column shift unit quantity, thereby generating multiple recovered product sums. By storing the shifted weight values ​​in the shifted weight storage area and then using the number of shift units of the shifted weight values ​​and the column shift unit quantity to recover the weight shift amount of the shifted product sum, the current value on the bit lines during product sum operations in the memory can be effectively reduced, thus significantly reducing the power consumption of the memory-based computing device. In some embodiments, the bit lines coupled to the shifted weight storage area may be different from the bit lines coupled to the shift information storage area, which can effectively improve the computing efficiency of the memory-based computing device.

[0032] Although the present invention has been disclosed above with reference to embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the claims.

Claims

1. An in-memory computing device, characterized in that, include: Memory control circuit; A memory array, coupled to the memory control circuit, the memory control circuit controlling data access of the memory array, the memory array comprising: The shifted weight storage area stores multiple shifted weight values, and provides multiple shifted product sums based on multiple input signals provided by the memory control circuit through multiple first word lines; A shift information storage area stores the number of shift units for the plurality of shifted weight values, and provides the number of shift units for the plurality of shifted weight values ​​based on multiple control signals provided by the memory control circuit through multiple second word lines; and A shift unit quantity storage area stores shift unit quantities and provides column shift unit quantities based on the plurality of input signals, wherein the column shift unit quantities are equal to the sum of the products of the plurality of input signals and the shift unit quantities; A sensing circuit, coupled to the memory array, senses multiple current signals provided by the shifted weight storage area, the shift information storage area, and the shift unit quantity storage area to obtain the sum of the multiple shifted products, the number of shift units for the multiple shifted weight values, and the number of column shift units; and A shift recovery circuit, coupled to the sensing circuit, recovers the weight shift amount of the sum of multiple shifted products based on the number of shift units of the multiple shifted weight values ​​and the number of column shift units, so as to generate multiple recovered product sums.

2. The in-memory computing device according to claim 1, characterized in that, The sensing circuit includes multiple first sensors and second sensors. The shifted weight storage area includes multiple first storage units. The shifted information storage area includes multiple second storage units. The shifted unit quantity storage area includes multiple third storage units. The multiple first storage units and the multiple second storage units are coupled to the multiple first sensors through multiple first bit lines. The multiple third storage units are coupled to the second sensors through second bit lines. The multiple first storage units and the multiple third storage units share the multiple first word lines. The multiple second storage units are coupled to the multiple second word lines.

3. The in-memory computing device according to claim 2, characterized in that, The plurality of first storage units receive the plurality of input signals from the plurality of first word lines, and provide the plurality of current signals representing the plurality of shifted product sums to the plurality of first sensors through the plurality of first bit lines based on the plurality of input signals. The plurality of third storage units receive the plurality of input signals from the plurality of first word lines, and provide the plurality of current signals representing the column shift unit amount to the second sensors through the second bit lines based on the plurality of input signals. The plurality of second storage units receive the plurality of control signals from the plurality of second word lines, and provide the plurality of current signals representing the number of shift units of the plurality of shifted weight values ​​to the plurality of first sensors through the plurality of first bit lines based on the plurality of control signals.

4. The in-memory computing device according to claim 2, characterized in that, The shift recovery circuit includes: A shift register, coupled to the plurality of first sensors and the second sensors, generates a plurality of shift adjustment amounts based on the number of shift units of the plurality of shifted weight values ​​and the column shift unit amount; and An adder circuit, coupled to the shift register and the plurality of first sensors, adds the plurality of shifted product sums provided by the plurality of first sensors to the corresponding shift adjustment amounts to generate a plurality of restored product sums.

5. The in-memory computing device according to claim 2, characterized in that, In the shifted weight storage area, the multiple shifted weight values ​​stored in multiple first storage cells on the same bit line have the same shift amount.

6. The in-memory computing device according to claim 2, characterized in that, The memory control circuit adjusts the critical voltage or resistance values ​​of the plurality of first storage cells to adjust the plurality of shifted weight values.

7. The operational method of the in-memory arithmetic device according to claim 1, characterized in that, The bit lines coupled to the shifted weight storage area are different from the bit lines coupled to the shifted information storage area.

8. An operational method for an in-memory arithmetic device, characterized in that, The in-memory computing device includes a memory array, which includes a shift weight storage area, a shift information storage area, and a shift unit quantity storage area. The shift weight storage area stores multiple shift weight values, the shift information storage area stores the number of shift units for the multiple shift weight values, and the shift unit quantity storage area stores the number of shift units. The computing method of the in-memory computing device includes: Multiple control signals are provided to the shift information storage area so that the shift information storage area provides the number of shift units of the multiple shifted weight values; Provide multiple input signals to the shifted weight storage area and the shift unit quantity storage area, such that the shifted weight storage area provides a multiple shifted product sum, and the shift unit quantity storage area provides a column shift unit quantity, wherein the column shift unit quantity is equal to the product sum of the multiple input signals and the shift unit quantity; and The weight shift amount of the multiple shifted product sum is restored based on the number of shift units of the multiple shifted weight values ​​and the number of column shift units, so as to generate multiple restored product sums.

9. The operation method of the in-memory arithmetic device according to claim 8, characterized in that, The shifted weight storage area includes multiple first storage units, the shifted information storage area includes multiple second storage units, and the shifted unit quantity storage area includes multiple third storage units.

10. The operation method of the in-memory arithmetic device according to claim 9, characterized in that, The plurality of first storage cells and the plurality of second storage cells share multiple bit lines, while the plurality of first storage cells and the plurality of third storage cells use different bit lines.

11. The operation method of the in-memory arithmetic device according to claim 9, characterized in that, include: Multiple shift adjustment amounts are generated based on the number of shift units of the multiple shifted weight values ​​and the column shift unit amount; as well as The sum of the multiple shifted products is added to the corresponding shift adjustment amount to generate the sum of the multiple restored products.

12. The operation method of the in-memory arithmetic device according to claim 9, characterized in that, In the shifted weight storage area, the multiple shifted weight values ​​stored in multiple first storage cells on the same bit line have the same shift amount.

13. The operation method of the in-memory arithmetic device according to claim 9, characterized in that, include: Adjust the critical voltage or resistance values ​​of the plurality of first storage cells to adjust the plurality of shifted weight values.

14. The operation method of the in-memory arithmetic device according to claim 8, characterized in that, The bit lines coupled to the shifted weight storage area are different from the bit lines coupled to the shifted information storage area.

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