Display device and driving method thereof

Abstract

A display device and its driving method are disclosed. The present invention provides a display device comprising: a display panel configured to display an image; a data driving circuit configured to supply data voltage to the display panel; and a timing controller configured to control the data driving circuit, wherein the data driving circuit comprises: a first converter configured to output a voltage based on a plurality of resistors; a gain circuit configured to selectively receive at least two different voltages from the first converter; and amplify the voltage input through an input terminal to output the amplified voltage to at least two output terminals or to output at least two different voltages without amplification and without change; and a second converter configured to interpolate and output the at least two voltages output from the gain circuit.

Description

Technical Field

[0001] This invention relates to a display device and its driving method. Background Technology

[0002] With the development of information technology, the market for display devices, which serve as the connection medium between users and information, is also growing. Consequently, the use of display devices such as light-emitting diode (LED), quantum dot (QDD), and liquid crystal display (LCD) devices is increasing.

[0003] The aforementioned display devices all include: a display panel including sub-pixels; a driving unit configured to output driving signals for driving the display panel; a power supply unit configured to generate power to be supplied to the display panel or the driving unit; and so on.

[0004] In each display device, when a drive signal (e.g., a scan signal, a data signal, etc.) is provided to a subpixel formed in the display panel, an image can be displayed by transmitting light through the selected subpixel or by directly emitting light. Summary of the Invention

[0005] Therefore, the present invention relates to a display device and its driving method that substantially eliminate one or more problems caused by the limitations and disadvantages of the prior art.

[0006] The purpose of this invention is to reduce the size of the data drive circuit by minimizing the area occupied by the resistors and wires included in the DA converter.

[0007] Further advantages, objects, and features of the invention will be set forth in part in the description which follows, and in part will be apparent to those skilled in the art upon examination of the description, or may be learned by practice of the invention. The objects and other advantages of the invention may be realized and obtained by means of the structures particularly pointed out in the written description, the claims, and the drawings.

[0008] To achieve these and other advantages, and according to the purposes of the invention, as embodied and broadly described herein, a display device includes: a display panel configured to display an image; a data driving circuit configured to provide a data voltage to the display panel; and a timing controller configured to control the data driving circuit, wherein the data driving circuit includes a first converter configured to divide and output a voltage based on a plurality of resistors; a gain circuit configured to selectively receive at least two different voltages from the first converter and amplify the voltage input through an input terminal to output the amplified voltage to at least two output terminals, or to output the at least two different voltages without amplification and without alteration; and a second converter configured to interpolate and output the at least two voltages output from the gain circuit.

[0009] The gain circuit can amplify and output voltage in response to a gain adjustment signal output from the timing controller, or output voltage without amplification and without change.

[0010] The timing controller can generate a gain adjustment signal based on the data signal to be provided to the data drive circuit and the compensation value used to compensate for the degradation of components included in the display panel.

[0011] The timing controller can analyze data signals and compensation values, compare the analyzed values ​​with reference values, and generate a logic low-gain adjustment signal or a logic high-gain adjustment signal based on the comparison results.

[0012] The gain circuit can amplify and output the voltage input through the input terminal using a combination of at least one gain amplifier and at least two switches, or output the voltage input through the input terminal without amplification or modification.

[0013] The first converter may include an n-bit (n is 4 to 6) resistor-to-DA converter, the gain circuit may include a j-fold (j is 2 to 16) gain amplifier, and the second converter may include a 3-bit interpolation DA converter.

[0014] The timing controller can output a gain adjustment signal through a communication interface connected to the data drive circuit or through a signal line connected separately to the data drive circuit.

[0015] In another aspect of the invention, a method for driving a display device is provided, the display device including a display panel configured to display an image, a data driving circuit configured to provide a data voltage to the display panel, and a timing controller configured to control the data driving circuit. The method includes the steps of: generating a gain adjustment signal based on a data signal to be provided to the data driving circuit and a compensation value for compensating for degradation of components included in the display panel; sending the gain adjustment signal to the data driving circuit; and controlling the presence or absence of voltage amplification of a gain circuit included in a DA converter of the data driving circuit in response to the gain adjustment signal.

[0016] The steps of generating a gain adjustment signal may include analyzing the data signal and the compensation value, comparing the analyzed value with the reference value, and generating a logic low gain adjustment signal or a logic high gain adjustment signal based on the comparison result.

[0017] The gain circuit is configured to amplify and output the input voltage in response to a logic high gain adjustment signal, and the gain circuit is also configured to output the input voltage without amplification and without change in response to a logic low gain adjustment signal.

[0018] It should be understood that the foregoing general description and the following detailed description of the invention are exemplary and illustrative, and are intended to provide further explanation of the claimed invention. Attached Figure Description

[0019] The accompanying drawings are included to provide a further understanding of the invention and are incorporated in and constitute a part of this application. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention. In the drawings:

[0020] Figure 1 It is a block diagram schematically showing the configuration of LEDs. Figure 2 This is a schematic diagram showing the subpixels included in the display panel. Figure 3 This is an exemplary configuration of a device associated with a gate scan drive unit in a panel. Figure 4A and Figure 4B This is an exemplary arrangement diagram of the gate scan driving unit in the panel, and Figure 5 This is a diagram that briefly illustrates the light emission operation of a sub-pixel;

[0021] Figure 6 This is a diagram used to describe the communication interface connecting the timing controller and the data drive unit. Figure 7 This is a block diagram schematically showing the internal blocks of the data-driven unit, and Figure 8 This is a circuit diagram illustrating a DA converter according to a first embodiment of the present invention;

[0022] Figures 9 to 11This is a circuit diagram illustrating an implementation example of a DA converter and its operation according to a first embodiment of the present invention, and Figure 12 This is a circuit diagram showing a conventional DA converter;

[0023] Figures 13 to 15 This is a circuit diagram illustrating an implementation example of a DA converter and its operation according to a second embodiment of the present invention; and

[0024] Figure 16 This is a block diagram illustrating the process of generating a gain adjustment signal using a timing controller according to a third embodiment of the present invention, and Figure 17 and Figure 18 This is a block diagram describing a method for applying a gain adjustment signal to a data driving unit according to a third embodiment of the present invention. Detailed Implementation

[0025] Reference will now be made in detail to preferred embodiments of the invention, examples of which are shown in the accompanying drawings. Wherever possible, the same reference numerals are used in all the drawings to denote the same or similar parts.

[0026] The display device according to the present invention can be implemented as a television, image player, personal computer (PC), home theater, automotive electronics, smartphone, etc., and is not limited thereto. The display device according to the present invention can be implemented as LED, QDD, LCD, etc.

[0027] However, for ease of description, the following text uses an LED that directly emits light to present an image as an example. LEDs can be implemented based on inorganic light-emitting diodes or organic light-emitting diodes. For ease of description, the following text uses an LED implemented based on an organic light-emitting diode as an example.

[0028] Figure 1 It is a block diagram schematically showing the configuration of LEDs. Figure 2 This is a schematic diagram showing the subpixels included in the display panel. Figure 3 This is an exemplary configuration of a device associated with a gate scan drive unit in a panel. Figure 4A and Figure 4B This is an exemplary arrangement diagram of the gate scan driving unit in the panel, and Figure 5 This is a diagram that briefly illustrates the emission operation of a sub-pixel.

[0029] like Figures 1 to 5 As shown, the LED may include an image providing unit (circuit) 110, a timing controller 120, a scanning driving unit (circuit) 130, a data driving unit (circuit) 140, a display panel 150, a power supply unit (circuit) 180, etc.

[0030] The image providing unit (or host system) 110 can output various drive signals along with data signals provided from an external source or stored in internal memory. The image providing unit 110 can provide data signals and various drive signals to the timing controller 120.

[0031] The timing controller 120 can output a gating timing control signal GDC for controlling the operation timing of the scan drive unit 130, a data timing control signal DDC for controlling the operation timing of the data drive unit 140, and various synchronization signals (Vsync as a vertical synchronization signal and Hsync as a horizontal synchronization signal). The timing controller 120, together with the data timing control signal DDC, can provide the data signal DATA from the image providing unit 110 to the data drive unit 140. The timing controller 120 can be formed as an integrated circuit (IC) and mounted on a printed circuit board, but is not limited thereto.

[0032] The power supply unit 180 can convert externally supplied power into a first power with a high potential and a second power with a low potential, and output power through the first power line EVDD and the second power line EVSS under the control of the timing controller 120. In addition to the first power and the second power, the power supply unit 180 can generate and output the voltage required to drive the scan drive unit 130 (e.g., a gating voltage including a gating high voltage and a gating low voltage) or the voltage required to drive the data drive unit 140 (a drain voltage including a drain voltage and a half-drain voltage).

[0033] The data driving unit 140 can sample and latch the data signal DATA in response to the data timing control signal DDC provided from the timing controller 120, convert the digital data signal into an analog data voltage based on the gamma reference voltage, and output the analog data voltage. The data driving unit 140 can provide data voltage to the sub-pixels included in the display panel 150 via data lines DL1 to DLn. The data driving unit 140 can be formed as an IC and mounted on the display panel 150 or mounted on a printed circuit board, but is not limited thereto.

[0034] The scan drive unit 130 can output a scan signal (or scan voltage) in response to a gating timing control signal GDC provided from the timing controller 120. The scan drive unit 130 can provide scan signals to sub-pixels included in the display panel 150 via gating lines GL1 to GLm. The scan drive unit 130 can be formed as an IC, or it can be directly formed on the display panel 150 using a gate method in the panel, but is not limited thereto.

[0035] The gate-type scan drive unit 130 in the panel may include a scan shift register 131 and a level shifter 135. The level shifter 135 may generate and output one or more clock signals Clk and a start signal Vst based on the signal output from the timing controller 120. The clock signal Clk may be generated and output in the form of K (K is an integer greater than or equal to 2) different phases (e.g., two-phase, four-phase, and eight-phase).

[0036] The scan shift register 131 can be operated based on the signals Clk and Vst output from the level shifter 135, and output scan signals Scan[1] to Scan[m] that can turn off or turn off the transistors formed on the display panel. The scan shift register 131 can be formed as a thin film on the display panel using the gate method in the panel.

[0037] Typically, the scan shift register 131 can be located in the non-display area NA of the display panel 150. In this case, the scan shift register 131 can be set as follows: Figure 4A The settings shown are located in the left and right portions of the non-display area NA in the display panel 150, or as... Figure 4B The arrangement is shown in the upper and lower parts of the non-display area NA in the display panel 150.

[0038] At the same time, Figure 4A and Figure 4B As an example, the first side scan shift register 131a and the second side scan shift register 131b are shown and described as being located in the non-display areas NA on the left and right sides, or on the upper and lower sides, of the display area AA. However, the first side scan shift register 131a and the second side scan shift register 131b can be located on one of the left, right, upper, or lower sides. Alternatively, the scan shift register 131 can be separately located in the non-display area NA and the display area AA, or it can be distributed only in the display area AA.

[0039] Furthermore, unlike the scan shift register 131, the level shifter 135 can be formed as a separate IC or can be included in the power supply unit 180. However, this is only an example, and depending on the implementation of the LED, one or more of the timing controller 120, scan drive unit 130, and data drive unit 140 can be implemented in various forms, such as integrated into a single IC.

[0040] Display panel 150 can operate in conjunction with scan drive unit 130, data drive unit 140, and power supply unit 180 to display images. Display panel 150 can be manufactured based on a rigid or flexible substrate (such as glass, silicon, polyimide, etc.). Display panel 150 may include directly light-emitting (self-emissive) subpixels. Subpixels may include pixels containing red, green, and blue, or pixels containing red, green, blue, and white.

[0041] A sub-pixel SP can be connected to a first data line DL1, a first gate line GL1, a first power line EVDD, and a second power line EVSS. A sub-pixel SP can include an organic light-emitting diode (OLED). A sub-pixel SP can include a switching transistor, a driving transistor, a capacitor, etc. A sub-pixel SP can cause the OLED to emit light based on a scan signal Scan, a data voltage Vdata, etc. In addition to the OLED, a sub-pixel can include circuitry for compensating for degradation of the driving transistor.

[0042] Figure 6 This is a diagram used to describe the communication interface connecting the timing controller and the data drive unit. Figure 7 This is a block diagram schematically showing the internal blocks of the data-driven unit, and Figure 8 This is a circuit diagram illustrating a DA converter according to a first embodiment of the present invention.

[0043] like Figure 6 and Figure 7 As shown, the data driving unit 140 can receive digital data signal DATA via the communication interface EPI connected to the timing controller 120, convert the digital data signal DATA into an analog data voltage Vdata, and output the analog data voltage Vdata. Here, as an example, the embedded clock point-to-point interface (EPI) is connected between the data driving unit 140 and the timing controller 120. However, the invention is not limited thereto.

[0044] The data drive unit 140 may include a data receiver 141 (e.g., an EPI RX block) for receiving data signal DATA from the timing controller 120, a data converter 145 for converting the received data signal DATA into a data voltage Vdata, etc.

[0045] The data converter 145 may include a shift register 142, a first latch 143 (e.g., a first line latch), a second latch 144 (e.g., a second line latch), a DA converter 146, an output unit 147 (e.g., a multi-channel output), etc.

[0046] Shift register 142 can be used to generate control signals that allow digital data signals sent from timing controller 120 to be applied line by line. First latch 143 can be used to sample and then output the externally input digital data signal under the control of shift register 142. First latch 143 can be referred to as a bar sampling latch for sampling the data signal. Second latch 144 can be used to hold the digital data signal output from first latch 143 and then output a data signal in response to the source output signal SOE. Second latch 144 can be referred to as a bar holding latch for holding (maintaining) the data signal.

[0047] The DA converter 146 can be used to convert the digital data signal output from the second latch 144 into an analog data voltage, and then output the data voltage. The DA converter 146 can convert the digital data signal into an analog data voltage based on the gamma reference voltage GMA<1:i> output from the gamma unit. The output unit 147 can be used to output the analog data voltage converted by the DA converter 146 through a corresponding output channel. The data voltage output from the output unit 147 can be applied to the sub-pixel through a data line.

[0048] like Figure 8 As shown, the DA converter 146 according to the first embodiment of the present invention may include a first DA converter 146a, a gain circuit unit 146b, and a second DA converter 146c.

[0049] The first DA converter 146a may include a resistor string RS. The first DA converter 146a can divide the first gamma reference voltage GMA1 based on the resistor string RS, which includes multiple resistors, and output the i-th gamma reference voltage GMAi. The first DA converter 146a may be referred to as an n-bit resistor-DA converter (n-bit R-DAC). Here, n can be 4 to 6, and i can be an integer of 6 or greater.

[0050] Gain circuit unit 146b may include switches S1 to Sm and gain amplifiers GAMP1 to GAMPk. Gain circuit unit 146b can amplify a voltage input through its input terminal by a factor of j using a combination of at least one gain amplifier GAMP1 and at least two switches S1 and S2, and output that voltage to its output terminal, or output the voltage without amplification or alteration. Gain circuit unit 146b may be connected to a voltage divider node including resistors in the first DA converter 146a to selectively receive at least two different voltages through its input terminal. Gain circuit unit 146b may be referred to as a j-fold gain amplifier (×j gain AMP). Here, j can be 2 to 16, m can be an integer of 4 or greater, and k can be an integer of 2 or greater. Simultaneously, switches S1 to Sm can be turned on or off in response to a gain adjustment signal GAS output from timing controller 120. However, the invention is not limited thereto.

[0051] The second DA converter 146c can interpolate at least two voltages input in 3-bit form through two input terminals INA and INB, and output the voltages to the output terminals. The second DA converter 146c can be referred to as a 3-bit interpolated DA converter (3-bit interpolated DAC).

[0052] The n-bit resistor-DA converter (n-bit R-DAC) and j-fold gain amplifier (×j-gain AMP) included in the DA converter 146 are related to reduce the number of resistors and wires. For example, when implementing the DA converter 146 with a level similar to that of a 7-bit DA converter, the device can be configured using a 4-bit resistor-DA converter and a 16-fold gain amplifier or a 6-bit resistor-DA converter and a 2-fold gain amplifier. However, the complexity of the device may increase when increasing the gain factor of the gain amplifier rather than decreasing the number of bits in the resistor-DA converter, which needs to be considered.

[0053] Figures 9 to 11 This is a circuit diagram illustrating an implementation example of a DA converter and its operation according to a first embodiment of the present invention. Figure 12 This is a circuit diagram showing a conventional DA converter.

[0054] according to Figure 9 In the first embodiment of the present invention shown, the first DA converter 146a can be configured as a 6-bit resistor-DA converter (6-bit R-DAC), and the gain circuit unit 146b can be configured as a dual-gain amplifier (x2 gain AMP). Furthermore, the first DA converter 146a can receive a first gamma reference voltage GMA1 of 8V to an i-th gamma reference voltage GMAi of 0V as the gamma tap voltage.

[0055] The 6-bit resistor-DA converter (6-bit R-DAC) provided in the first DA converter 146a can be formed based on resistors and 64ea of ​​wire. Furthermore, the dual-gain amplifier (x2 gain AMP) provided in the gain circuit unit 146b can be formed based on a combination of two gain amplifiers GAMP1 and GAMP2 and four switches S1 to S4, so as to amplify the voltage input through the two input terminals by 2 times and output the voltage to the two output terminals, or output the voltage without amplification and without alteration.

[0056] like Figure 10 As shown, when the logic low gain adjustment signal GAS[L] is applied, the second switch S2 and the fourth switch S4 of the gain circuit unit 146b can be turned on, and the first switch S1 and the third switch S3 can be turned off. When the second switch S2 and the fourth switch S4 of the gain circuit unit 146b are turned on, the 8V voltage input to the first input terminal of the gain circuit unit 146b and the 7.6V voltage input to the second input terminal of the gain circuit unit 146b can be output without amplification or change.

[0057] like Figure 11 As shown, when the logic high-gain adjustment signal GAS[H] is applied, the first switch S1 and the third switch S3 of the gain circuit unit 146b can be turned on, and the second switch S2 and the fourth switch S4 of the gain circuit unit 146b can be turned off. When the first switch S1 and the third switch S3 of the gain circuit unit 146b are turned on, the 8V voltage input to the first input terminal of the gain circuit unit 146b can be amplified to a voltage of 16V and output, and the 7.6V voltage input to the input terminal can be amplified to a voltage of 15.2V and output.

[0058] like Figure 10 and Figure 11 As shown, when a logic low gain adjustment signal GAS[L] is applied, the gain circuit unit 146b can output the voltage input through the input terminal without amplification or change. On the other hand, when a logic high gain adjustment signal GAS[H] is applied, the gain circuit unit 146b can amplify and output the voltage input through the input terminal. However, this is only an example, and the present invention is not limited thereto.

[0059] As described above, the DA converter 146 according to the first embodiment of the present invention does not use the amplification function of the gain circuit unit 146b to output a voltage corresponding to the low voltage range (0V to 8V), and can use the amplification function of the gain circuit unit 146b to output a voltage corresponding to the high voltage range (8V to 12V). Through the above configuration and operation, the DA converter 146 according to the first embodiment of the present invention can reduce the size of the data drive unit while exhibiting voltage resolution with levels similar to those of a 7-bit DA converter, as will be described below.

[0060] like Figure 12 As shown, in the conventional method, the 7-bit DA converter 146 is implemented based on a 7-bit resistor-DA converter (7-bit R-DAC) and a 3-bit interpolation DA-DA converter (3-bit interpolation DAC). The conventional method is based on a 7-bit resistor-DA converter (7-bit R-DAC) and may require 128ea of ​​resistors and wires.

[0061] On the other hand, the first implementation is based on a 6-bit resistor-to-DA converter (6-bit R-DAC), a dual-gain amplifier (x2 gain AMP), etc., such as Figure 9 As shown, the 128ea resistor and wires can be simplified to 64ea. Therefore, the DA converter 146 according to the first embodiment can provide the advantage of reducing the size of the data drive unit by minimizing the area occupied by the resistors and wires.

[0062] Figures 13 to 15 This is a circuit diagram used to describe an implementation example of a DA converter according to a second embodiment of the present invention and its operation.

[0063] according to Figure 13 In the second embodiment shown, the first DA converter 146a can be configured as a 6-bit + a resistor-DA converter (6-bit + a R-DAC), and the gain circuit unit 146b can be configured as an amplifier (x2 gain AMP). Furthermore, the first DA converter 146a can receive a first gamma reference voltage GMA1 of 8V to an i-th gamma reference voltage GMAi of 0V as the gamma tap voltage.

[0064] The 6-bit + a resistor-to-DA converter (6-bit + a R-DAC) provided in the first DA converter 146a can be formed based on 96ea of ​​resistors and wires. Furthermore, the dual-gain amplifier (x2 gain AMP) provided in the gain circuit unit 146b can be formed based on a combination of three gain amplifiers GAMP1 to GAMP3 and five switches S1 to S5, so as to amplify the voltage input through the three input terminals by 2 times and output the voltage to the two output terminals, or output the voltage without amplification.

[0065] Meanwhile, the resistor-to-DA converter included in the second embodiment is named 6-bit+a to emphasize that, compared to the resistor-to-DA converter included in the first embodiment, voltage resolution can be further improved by forming a circuit based on more 96ea resistors and wires. As in the second embodiment, when using a voltage input through three input terminals by adding an input terminal between the two input terminals, voltage resolution in the high voltage range (High) can be increased. As a result, high-brightness resolution can be improved when rendering an image.

[0066] like Figure 14 As shown, when the logic low gain adjustment signal GAS[L] is applied, the second switch S2 and the fifth switch S5 of the gain circuit unit 146b are turned on, and the first switch S1, the third switch S3, and the fourth switch S4 can be turned off. When the second switch S2 and the fifth switch S5 of the gain circuit unit 146b are turned on, the 8V voltage input to the first input terminal of the gain circuit unit 146b and the 7.6V voltage input to the third input terminal of the gain circuit unit 146b can be output without amplification or change. On the other hand, since there is no input / output path, the 7.8V voltage input to the second input terminal may not be output from the gain circuit unit 146b.

[0067] like Figure 15 As shown, when the logic high-gain adjustment signal GAS[H] is applied, the first switch S1 and the third switch S3 of the gain circuit unit 146b can be turned on, and the second switch S2, the fourth switch S4, and the fifth switch S5 of the gain circuit unit 146b can be turned off. When the first switch S1 and the third switch S3 of the gain circuit unit 146b are turned on, the 8V voltage input to the first input terminal of the gain circuit unit 146b can be amplified to a voltage of 16V and output, and the 7.6V voltage input to the third input terminal can be amplified to a voltage of 15.2V and output. At the same time, since there is no input / output path, the 7.6V voltage input to the third input terminal does not need to be output from the gain circuit unit 146b.

[0068] like Figure 14 and Figure 15 As shown, when a logic low gain adjustment signal GAS[L] is applied, the gain circuit unit 146b can output the voltage input through the input terminal without amplification or modification. On the other hand, when a logic high gain adjustment signal GAS[H] is applied, the gain circuit unit 146b can amplify and output the voltage input through the input terminal. However, this is merely an example, and the invention is not limited thereto.

[0069] As described above, the DA converter 146 according to the second embodiment of the present invention does not use the amplification function of the gain circuit unit 146b to output a voltage corresponding to the low voltage range of 0V to 8V (Low), and can use the amplification function of the gain circuit unit 146b to output a voltage corresponding to the high voltage range of 8V to 12V (High). Through the above configuration and operation, the DA converter 146 according to the second embodiment of the present invention can reduce the size of the data drive unit while exhibiting voltage resolution equivalent to a 7-bit DA converter.

[0070] Furthermore, according to the first and second embodiments of the present invention, the DA converter 146 can easily achieve low brightness (low brightness voltage) or high brightness (high brightness voltage) based on the gain adjustment signal output from the timing controller.

[0071] Figure 16 This is a block diagram illustrating the process of generating a gain adjustment signal using a timing controller according to a third embodiment of the present invention. Figure 17 and Figure 18 This is a block diagram describing a method for applying a gain adjustment signal to a data driving unit according to a third embodiment of the present invention.

[0072] like Figure 16 As shown, the timing controller 120 can generate a gain adjustment signal GAS that will be applied to the data converter 145 of the data drive unit 140 based on the data signal DATA provided from the outside, which will be described below.

[0073] First (1), the timing controller 120 can store the data signal DATA provided from the outside in the memory 125 (frame memory; DDR). The data signal DATA can be stored in the memory 125 in units of one frame of data. One frame of data can include 30 bits, including red data signal, green data signal and blue data signal, and 2 bits for the algorithm for controlling current limiting, etc. However, the present invention is not limited thereto.

[0074] Next (2), the timing controller 120 can obtain a compensation value for compensating for the degradation of components included in the display panel together with the data signal DATA stored in the memory 125, and then add the compensation value to the data signal DATA.

[0075] Next (3), the timing controller 120 can analyze the data signal DATA and the compensation value (or compensation code value), compare the analyzed value with the reference value, and generate a logic low gain adjustment signal GAS[L] or a logic high gain adjustment signal GAS[H] based on the result. For example, the timing controller 120 can generate a logic low gain adjustment signal GAS[L] when the data signal (10 bits

[1023] ) + compensation value is less than the reference value 512, and generate a logic high gain adjustment signal GAS[H] when the data signal (10 bits

[1023] ) + compensation value is greater than the reference value 512.

[0076] In short, the timing controller 120 can generate a logic high gain adjustment signal GAS[H] when it is determined that the data signal DATA has a voltage range higher than 8V, and can generate a logic low gain adjustment signal GAS[L] when it is determined that the data signal DATA is equal to 8V or has a voltage range lower than 8V.

[0077] Next (4), the timing controller 120 can output a gain adjustment signal GAS prepared based on the data signal DATA and the compensation value through a communication interface connected to the data drive unit 140 or a separate signal line.

[0078] Next (5), the data drive unit 140 can convert the digital data signal into an analog data voltage Vdata and output the analog data voltage Vdata, while controlling the switches included in the gain circuit unit 146b of the data converter 145 based on the gain adjustment signal GAS applied from the timing controller 120.

[0079] like Figure 17 In the first example shown, the data drive unit 140 can receive the gain adjustment signal GAS via the communication interface EPI connected to the timing controller. The gain adjustment signal GAS can be sent to the data converter 145 via the data receiver 141 included in the data drive unit 140. Thereafter, the gain adjustment signal GAS can be applied to a switch in the gain circuit unit included in the DA converter 146 via the second latch 144. However, it should be noted that this is only an example.

[0080] like Figure 18 In the second example shown, the data drive unit 140 can receive the gain adjustment signal GAS via a separate signal line connected to the timing controller. The gain adjustment signal GAS can be applied directly to a switch included in the gain circuit unit of the DA converter 146. However, it should be noted that this is just an example.

[0081] As in Figure 17 The first example and Figure 18As described in the second example, the gain adjustment signal GAS can be sent via a communication interface connected between the timing controller and the data drive unit 140, and can also be sent via a separate signal line prepared between them.

[0082] As described above, the present invention has the effect of reducing the size of the data drive unit by minimizing the area occupied by the resistors and wires included in the DA converter. Furthermore, the present invention has the effect of reducing the number of bits in the DA converter based on controlling the gain amplifier and implementing low brightness (low brightness voltage) or high brightness (high brightness voltage). Moreover, the present invention has the effect of selectively reducing the resistors and wires included in the DA converter according to the amplification ratio of the gain amplifier.

[0083] It will be apparent to those skilled in the art that various modifications and variations can be made to the invention without departing from its spirit or scope. Therefore, this invention is intended to cover any modifications and variations falling within the scope of the appended claims and their equivalents.

[0084] Cross-reference to related applications

[0085] This application claims the benefit of Korean Patent Application No. 10-2021-0181915, filed on December 17, 2021, which is incorporated herein by reference as if fully set forth herein.

Claims

1. A display device, the display device comprising: Display panel, the display panel being configured to display images; A data driving circuit configured to provide a data voltage to the display panel; as well as A timing controller configured to control the data drive circuit. The data driving circuit includes: A first converter, configured to output a voltage based on a plurality of resistors; A gain circuit configured to selectively receive at least two different voltages from the first converter, and in response to a gain adjustment signal output from the timing controller, amplify the voltage input through the input terminals to output the amplified voltage to at least two output terminals, or output the at least two different voltages without amplification and without alteration; and A second converter is configured to interpolate and output at least two voltages from the gain circuit.

2. The display device according to claim 1, wherein, The timing controller generates the gain adjustment signal based on the data signal to be provided to the data driving circuit and a compensation value for compensating for the degradation of components included in the display panel.

3. The display device according to claim 2, wherein, The timing controller analyzes the data signal and the compensation value, compares the analyzed value with the reference value, and generates a logic low gain adjustment signal or a logic high gain adjustment signal based on the comparison result.

4. The display device according to claim 1, wherein, The gain circuit uses a combination of at least one gain amplifier and at least two switches to amplify and output the voltage input through the input terminal, or to output the voltage input through the input terminal without amplification and without alteration.

5. The display device according to claim 4, wherein, The first converter includes an n-bit resistor-DA converter, where n is 4 to 6; The gain circuit includes a j-fold gain amplifier, where j is between 2 and 16; and The second converter includes a 3-bit interpolation DA converter.

6. The display device according to claim 1, wherein, The timing controller outputs the gain adjustment signal through a communication interface connected to the data drive circuit or through a signal line separately connected to the data drive circuit.

7. A method of driving a display device, the display device comprising a display panel configured to display an image, a data driving circuit configured to provide a data voltage to the display panel, and a timing controller configured to control the data driving circuit, the method comprising the following steps: The timing controller generates a gain adjustment signal based on the data signal to be provided to the data driving circuit and a compensation value for compensating for the degradation of the components included in the display panel; The gain adjustment signal is sent to the data drive circuit by the timing controller; as well as The timing controller controls the gain circuit included in the DA converter of the data drive circuit to respond to the presence or absence of voltage amplification of the gain adjustment signal.

8. The method according to claim 7, wherein, The step of generating the gain adjustment signal includes: analyzing the data signal and the compensation value, comparing the analyzed value with the reference value, and generating a logic low gain adjustment signal or a logic high gain adjustment signal based on the comparison result.

9. The method according to claim 8, wherein, The gain circuit is configured to amplify and output the input voltage in response to the logic high-gain adjustment signal; and The gain circuit is further configured to output the input voltage without amplification and without alteration in response to the logic low gain adjustment signal.

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