Semiconductor Components and Their Fabrication Methods

Abstract

This invention discloses a semiconductor device and its fabrication method. The method mainly includes providing a substrate having a high-voltage region, a medium-voltage region, and a low-voltage region, and then forming a first transistor in the high-voltage region and a second transistor in the low-voltage region. The first transistor includes a first base disposed on the substrate, a first gate dielectric layer disposed on the first base, and a first gate electrode disposed on the first gate dielectric layer. The second transistor includes a fin-like structure disposed on the substrate and a second gate electrode disposed on the fin-like structure, wherein the top surface of the first gate dielectric layer is lower than the top surface of the fin-like structure.

Description

Technical Field

[0001] This invention relates to a method for manufacturing semiconductor devices, and more particularly to a method for integrating high-voltage devices, medium-voltage devices, and low-voltage devices. Background Technology

[0002] With current semiconductor technology, the industry can integrate control circuits, memory, low-voltage operating circuits, and high-voltage operating circuits and components onto a single chip, thereby reducing costs and improving operational performance. High-voltage components such as vertically diffused metal-oxide-semiconductors (VDMOS), insulated-gate bipolar transistors (IGBTs), and laterally diffused metal-oxide-semiconductors (LDMOS), which are fabricated on the chip, are frequently used due to their superior power switching efficiency. As those skilled in the art know, these high-voltage components are often required to withstand high breakdown voltages and operate at low resistance values.

[0003] Furthermore, as device dimensions continue to shrink, the development of existing planar field-effect transistors (FETs) has reached the limits of fabrication technology. To overcome these limitations, replacing planar FETs with non-planar FETs, such as fin field-effect transistors (FFETs), has become the mainstream development trend. Because the three-dimensional structure of fin FETs increases the contact area between the gate and the fin structure, it further enhances the gate's control over the carrier channel region, thereby reducing the drain-induced barrier lowering (DIBL) effect faced by small-sized devices and suppressing the short-channel effect (SCE). Moreover, since fin FETs have a wider channel width for the same gate length, they can achieve double the drain drive current. Even more significantly, the threshold voltage of the transistor can be controlled by adjusting the work function of the gate.

[0004] However, with the continuous shrinking of component size, there are still many challenges in integrating existing high-voltage components with finned structures, such as controlling leakage current and breakdown voltage. Therefore, improving the existing high-voltage component architecture is an important issue today. Summary of the Invention

[0005] One embodiment of the present invention discloses a method for fabricating a semiconductor device, which mainly involves first providing a substrate having a high-voltage region, a medium-voltage region, and a low-voltage region, and then forming a first transistor in the high-voltage region and a second transistor in the low-voltage region. The first transistor includes a first base disposed on the substrate, a first gate dielectric layer disposed on the first base, and a first gate electrode disposed on the first gate dielectric layer. The second transistor includes a fin-like structure disposed on the substrate and a second gate electrode disposed on the fin-like structure, wherein the top surface of the first gate dielectric layer is lower than the top surface of the fin-like structure.

[0006] Another embodiment of the present invention discloses a semiconductor device, which mainly includes a substrate having a high-voltage region, a medium-voltage region, and a low-voltage region. A first transistor is disposed in the high-voltage region, and a second transistor is disposed in the low-voltage region. The first transistor includes a first base disposed on the substrate, a first gate dielectric layer disposed on the first base, and a first gate electrode disposed on the first gate dielectric layer. The second transistor includes a fin-like structure disposed on the substrate and a second gate electrode disposed on the fin-like structure, wherein the top surface of the first gate dielectric layer is lower than the top surface of the fin-like structure. Attached Figure Description

[0007] Figures 1 to 11 This is a schematic diagram of a method for fabricating a semiconductor device according to an embodiment of the present invention.

[0008] Explanation of main component symbols

[0009] 12: Base

[0010] 14: High-voltage area

[0011] 16: Medium-pressure zone

[0012] 18 Low-pressure area

[0013] 20: Base

[0014] 22: Base

[0015] 24: Fin-like structure

[0016] 26: Padding layer

[0017] 28: Padding layer

[0018] 30: Hard Mask

[0019] 32: Insulation layer

[0020] 34: Doped region

[0021] 36: Hard Mask

[0022] 38: Patterned Mask

[0023] 40: Groove

[0024] 42: Gate dielectric layer

[0025] 44: Hard Mask

[0026] 46: Patterned Mask

[0027] 48: Gate dielectric layer

[0028] 50: Shallow trench isolation

[0029] 52: Gate dielectric layer

[0030] 54: Gate structure

[0031] 56: Gate structure

[0032] 58: Gate structure

[0033] 60: Gate material layer

[0034] 62: Hard Mask

[0035] 64: Hard Mask

[0036] 66: Gate electrode

[0037] 68: Epitaxial layer

[0038] 70: Source / Drain Region

[0039] 72: Electrostatic Discharge Protection Ring

[0040] 74: Interlayer dielectric layer

[0041] 76: High dielectric constant dielectric layer

[0042] 78: Work function metal layer

[0043] 80: Low-resistivity metal layer

[0044] 82: Hard Mask

[0045] 84: Contact plug

[0046] 114: High-voltage components

[0047] 116: Medium-voltage components

[0048] 118: Low-voltage components Detailed Implementation

[0049] Please refer to Figures 1 to 11 , Figures 1 to 11 This is a schematic diagram of a method for fabricating a semiconductor device according to an embodiment of the present invention, wherein... Figure 1 A top view of a semiconductor device fabricated according to an embodiment of the present invention. Figures 2 to 11 Then it is Figure 1 A cross-sectional schematic diagram of a semiconductor device is fabricated along tangents AA', BB', and CC'. (See diagram below.) Figures 1 to 2 As shown, a substrate 12, such as a silicon substrate or a silicon-on-insulator (SOI) substrate, is first provided, on which three or more transistor regions are defined, such as a high-voltage region 14, a medium-voltage region 16, and a low-voltage region 18. The high-voltage region 14 contains a high-voltage element 114, the medium-voltage region 16 contains a medium-voltage element 116, and the low-voltage region 18 contains a low-voltage element 118. Figures 2 to 11 It is better to follow along Figure 1 A schematic diagram illustrating a method for fabricating semiconductor devices along the directions of tangent AA' in high-voltage region 14, tangent BB' in medium-voltage region 14, and tangent CC' in low-voltage region 18. In this embodiment, high-voltage region 14, medium-voltage region 16, and low-voltage region 18 may contain transistor regions of the same or different conductivity types, such as PMOS transistor regions and / or NMOS transistor regions, and the three regions are respectively intended for subsequent fabrication of gate structures with different threshold voltages. In this embodiment, a P-type deep well region can be first formed in high-voltage region 14 and medium-voltage region 16 using an ion implantation process, and an N-type deep well region can be formed in low-voltage region 18, but the conductivity type of each region is not limited to this.

[0050] Then, bases 20 and 22 are formed on the substrates 12 of the high-pressure region 14 and the medium-pressure region 16, respectively, and a plurality of fin structures 24 are formed on the substrate of the low-pressure region 18. According to a preferred embodiment of the present invention, the bases 20 and 22 and the fin structures 24 are preferably fabricated by sidewall image transfer (SIT) technology, the procedure of which generally includes: providing a layout pattern to a computer system and performing appropriate calculations to define the corresponding pattern in a photomask. Subsequently, multiple equidistant and equal-width patterned sacrificial layers or mandrels are formed on the substrate by photolithography and etching processes, so that their individual appearance is strip-shaped. Then, deposition and etching processes are performed sequentially to form spacers on each sidewall of the patterned sacrificial layer. The patterned sacrificial layer is then removed, and an etching process is performed under the cover of the spacers, so that the pattern formed by the spacers is transferred into the substrate, and then the desired patterned structure, such as a strip-shaped patterned fin structure, is obtained by a fin cut process.

[0051] In addition, the formation of the bases 20, 22 and the fin structure 24 may also include first forming a patterned mask (not shown) on the substrate 12, and then transferring the pattern of the patterned mask to the substrate 12 through an etching process to form the bases 20, 22 and the fin structure 24. Alternatively, the bases 20, 22 and the fin structure 24 may also be formed by first fabricating a patterned hard mask layer (not shown) on the substrate 12, and then using an epitaxial fabrication process to grow a semiconductor layer, such as silicon-germanium, on the substrate 12 exposed above the patterned hard mask layer. This semiconductor layer can then serve as the corresponding bases 20, 22 and the fin structure 24. These embodiments of forming the bases 20, 22 and the fin structure 24 are all within the scope of this invention.

[0052] In this embodiment, each base 20, 22 and the top surface of the fin structure 24 may have a pad layer 26, a pad layer 28 and a hard mask 30 on the substrate 12 during the above patterning process. The pad layer 26 preferably contains silicon oxide, the pad layer 28 preferably contains silicon nitride, and the hard mask 30 preferably contains silicon oxide, but are not limited to these.

[0053] Then as Figure 3 As shown, a flowable chemical vapor deposition (FCVD) process is used to form an insulating layer 32 made of silicon oxide on the substrates 20, 22 and the fin structure 24, filling the groove between the substrates 20, 22 and the fin structure 24. Then, a planarization process is performed, for example, by chemical mechanical polishing (CMP) to remove the hard mask 30 so that the top surface of the pad layer 28 is flush with the top surface of the insulating layer 32.

[0054] Subsequently, as Figure 4 As shown, the silicon nitride liner 28 is first removed by etching to expose the silicon oxide liner 26 underneath, making the top surfaces of the insulating layers 32 on both sides slightly higher than the top surface of the liner 26, and simultaneously forming grooves (not shown) directly above the liner 26. Then, an ion implantation process is performed to form doped regions 34 on both sides of the base 20 of the high-voltage region 14, wherein the doped regions 34 preferably serve as lightly doped drains for subsequent high-voltage components. Next, a hard mask 36 is formed on the bases 20 and 22, fin structure 24, and insulating layer 32 of the high-voltage region 14, medium-voltage region 16, and low-voltage region 18, filling the grooves above the liner 26. In this embodiment, the hard mask 36 preferably contains silicon nitride, but is not limited to this.

[0055] Subsequently, as Figure 5As shown, a patterned mask 38 is first formed on the hard mask 36 of the medium-voltage region 16 and the low-voltage region 18, for example, a patterned photoresist is applied. The patterned mask 38 has an opening that exposes part of the surface of the hard mask 36 of the high-voltage region 14. Then, an etching process is performed using the patterned mask 38 as a mask to remove part of the hard mask 36 of the high-voltage region 14, part of the base 20, and part of the insulating layer 32 on both sides of the base 22 to form a groove 40.

[0056] like Figure 6 As shown, an oxide growth process or more specifically a rapid thermal oxidation (RTO) process is then performed to form a gate dielectric layer 42 made of silicon oxide on the substrate 20 of the high voltage region 14, and then the patterning mask 38 and the underlying hard mask 36 are completely removed. The grown gate dielectric layer 42 still retains portions of the grooves 40 previously formed using the patterning mask on both sides, and the top surface of the gate dielectric layer 42 is preferably lower than the top surface of the insulating layer 32 of the medium voltage region 16 and the low voltage region 18.

[0057] Next, another patterned mask (not shown) can be formed. For example, a patterned photoresist can be used to cover the insulating layer 32 of the high-voltage region 14 and the medium-voltage region 16, and the patterned mask has an opening to expose the pad layer 26 and the top surface of the insulating layer 32 of the low-voltage region 18. An ion implantation process is then performed to implant the dopant into the fin structure 24 of the low-voltage region 18 to adjust the threshold voltage of the element, and then the patterned mask is removed.

[0058] Subsequently, as Figure 7 As shown, a hard mask 44 made of silicon nitride is first formed to cover the high-voltage region 14, the medium-voltage region 16, and the low-voltage region 18, including the gate dielectric layer 42 of the high-voltage region 14, the base 24 of the medium-voltage region 16, and the fin structure 24 of the low-voltage region 18. Then, another patterned mask 46, such as a patterned photoresist, is formed to cover the insulating layer 32 of the high-voltage region 14 and the low-voltage region 16, and the patterned mask 46 has an opening that exposes the hard mask 44 of the medium-voltage region 16. Next, an etching process is performed using the patterned mask 46 as a mask to remove the hard mask 44 of the medium-voltage region 16, part of the insulating layer 32, the pad layer 26, and even part of the base 22, exposing the surface of the base 22.

[0059] Then as Figure 8As shown, a second oxide growth process, such as a rapid thermal oxidation (RTO) process, is first performed to form a gate dielectric layer 48 made of silicon oxide on the substrate 22 of the intermediate voltage region 16. Preferably, the top surface of the gate dielectric layer 48 in the intermediate voltage region 16 is higher than the top surface of the gate dielectric layer 42 in the high voltage region 14, and the thickness of the gate dielectric layer 42 in the high voltage region 14 is preferably greater than the thickness of the gate dielectric layer 48 in the intermediate voltage region 16. In this embodiment, the thickness of the gate dielectric layer 42 in the high voltage region 14 is preferably more than one time, for example, 1.5 times or even two times, the thickness of the gate dielectric layer 48 in the intermediate voltage region 16.

[0060] Next, the patterned mask 46 and the remaining hard mask 44 originally located in the high-voltage region 14, medium-voltage region 16, and low-voltage region 18 are removed. Then, an etching process is performed to completely remove the pad layer 26 on top of the fin structure 24 in the low-voltage region 14, exposing the top surface of the fin structure 24. Part of the insulating layer 32 in the high-voltage region 14, medium-voltage region 16, and low-voltage region 18 is also removed, so that the top surface of the remaining insulating layer 32 is slightly lower than the bases 20 and 22 of the high-voltage region 14 and medium-voltage region 16, and the top surface of the fin structure 24 in the low-voltage region 18, forming a shallow trench isolation (STI) 50. It should be noted that in this stage, the top surface of the gate dielectric layer 42 in the high-voltage region 14 is preferably lower than the top surface of the gate dielectric layer 48 in the medium-voltage region 16 and the top surface of the fin structure 24 in the low-voltage region 18, while the top surface of the gate dielectric layer 48 in the medium-voltage region 16 is preferably flush with the top surface of the fin structure 24 in the low-voltage region 18.

[0061] like Figure 9As shown, a gate dielectric layer 52 made of silicon oxide is then formed on the surface of the fin structure 24 in the low-voltage region 18 using an oxide fabrication process, such as in-situ steam generation (ISSG). Next, gate structures 54, 56, and 58, or dummy gates, can be formed on the bases 20 and 22 in the high-voltage region 14, the medium-voltage region 16, and the fin structure 24 in the low-voltage region 18, respectively. In this embodiment, the gate structures 54, 56, and 58 can be fabricated using a gate-first fabrication process, a high-k-first fabrication process in the gate-last fabrication process, or a high-k-last fabrication process in the gate-last fabrication process, depending on the fabrication process requirements. Taking the high dielectric constant dielectric layer fabrication process of this embodiment as an example, a gate material layer 60 made of polysilicon, a hard mask 62 made of silicon nitride, and a hard mask 64 made of silicon oxide can be sequentially formed on the gate dielectric layers 42, 48, and 52 of each region. A patterned photoresist (not shown) is used as a mask to perform a pattern transfer fabrication process. In a single etching or successive etching step, part of the hard mask 62, 64 and part of the gate material layer 60, and even part of the gate dielectric layer 48 of the medium voltage region 16, are removed. Then, the patterned photoresist is stripped to form gate structures 54, 56, and 58 made of gate dielectric layers 42, 48, and 52 and patterned gate material layer 60 on the substrate 12 of each region. The patterned gate material layer 60 preferably becomes the gate electrode 66 of each region.

[0062] Subsequently, at least one spacer wall (not shown) is formed on the sidewalls of gate structures 54, 56, and 58, respectively. In this embodiment, the spacer wall can be a single spacer wall or a composite spacer wall. For example, it may include a bias spacer wall (not shown) and a main spacer wall (not shown). The bias spacer wall and the main spacer wall preferably contain different materials, and both can be selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, and silicon carbide nitride, but are not limited thereto.

[0063] Please continue to refer to Figure 10 , Figure 10 As an embodiment of the present invention, along Figure 1 A schematic diagram illustrating the method for fabricating semiconductor devices along the directions of tangent AA' in high-voltage region 14, tangent BB' in medium-voltage region 14, and tangent DD' in low-voltage region 18. (See diagram below.) Figure 10As shown, a dry etching and / or wet etching process is performed, using the gate structure 58 and spacer wall of the low-voltage region 18 as an etching mask. The substrate 12 is etched downwards along the spacer wall in one or more passes to form grooves (not shown) in the substrate 12 on both sides of the gate structure 58. Then, a selective epitaxial growth (SEG) process is performed to form an epitaxial layer 68 in the groove. It should be noted that in this embodiment, the epitaxial layer 68 is formed only on both sides of the gate structure 58 of the low-voltage region 18, but preferably no epitaxial layer is formed in the high-voltage region 14 and the medium-voltage region 16. Additionally, the hard mask 64 of the low-voltage region 18 can be partially removed during the formation of the groove, so that the top surface of the hard mask 64 of the low-voltage region 18 is slightly lower than the top surface of the hard masks 64 of the high-voltage region 14 and the medium-voltage region 16.

[0064] from Figure 10 In cross-section, the epitaxial layer 68 of the low-voltage region 18 preferably has the same cross-sectional shape as the groove, such as an arc, a hexagon (also known as Sigma-Σ), or an octagon, but other cross-sectional shapes are also possible. In a preferred embodiment of the invention, the epitaxial layer 68 may be made of different materials depending on the type of metal-oxide-semiconductor (MOS) transistor. For example, if the MOS transistor is a P-type transistor (PMOS), the epitaxial layer 68 may be made of germanium silicide (SiGe), germanium boron silicide (SiGeB), or germanium tin silicide (SiGeSn). In another embodiment of the invention, if the MOS transistor is an N-type transistor (NMOS), the epitaxial layer 68 may be made of silicon carbide (SiC), silicon carbide phosphide (SiCP), or silicon phosphide (SiP). Furthermore, selective epitaxial fabrication can be performed in a single-layer or multi-layer manner, and the heteroatoms (such as germanium atoms or carbon atoms) can be changed in a gradual manner. However, it is preferable to make the surface of the epitaxial layer 68 lighter or free of germanium atoms to facilitate the formation of the subsequent metal silicide layer.

[0065] Subsequently, photolithography and etching processes can be used to remove part of the gate dielectric layer 48 in the intermediate voltage region 16, exposing the top surface of the base 22 on both sides of the gate structure 56. Then, one or more ion implantation processes are performed to form source / drain regions 70 in the bases 20 and 22 on both sides of the gate structures 54 and 56 in the high voltage region 14 and the intermediate voltage region 16, respectively. A doped region is also formed in the base 20 outside the high voltage transistor in the high voltage region 14 as an electrostatic discharge protection ring 72. Preferably, the source / drain regions 70 and the electrostatic discharge protection ring 72 in the high voltage region 14 contain dopants of different conductivity types, such as one containing N-type dopants and the other containing P-type dopants.

[0066] According to one embodiment of the present invention, the source / drain region 70 can be selectively formed in part or all of the epitaxial layer 68 in the low-voltage region 18. In one embodiment, the formation of the source / drain region 70 in the low-voltage region 18 can also be performed in-situ during a selective epitaxial growth process. For example, when the metal-oxide semiconductor is PMOS, a germanium silicide epitaxial layer, a germanium boron silicide epitaxial layer, or a germanium tin silicide epitaxial layer is formed, which may be accompanied by the implantation of P-type dopants; or when the metal-oxide semiconductor is NMOS, a carbon silicide epitaxial layer, a carbon phosphorus silicide epitaxial layer, or a phosphorus silicide epitaxial layer is formed, which may be accompanied by the implantation of N-type dopants. This eliminates the need for subsequent additional ion implantation steps to form the source / drain region 70 of the P-type / N-type transistor. Furthermore, in another embodiment, the dopants in the source / drain region 70 can also be formed in a gradient manner.

[0067] Then as Figure 11 As shown, a contact etch stop layer (CESL) (not shown) made of silicon nitride can be selectively formed on the substrate 12 to cover the gate structures 54, 56, and 58 of the high-voltage region 14, the medium-voltage region 16, and the low-voltage region 18. Then, an interlayer dielectric layer 74 is formed on the contact etch stop layer. Next, a planarization process is performed, for example, by using chemical mechanical polishing (CMP) to remove part of the interlayer dielectric layer 74 and part of the contact etch stop layer so that the upper surface of the hard mask 64 is flush with the upper surface of the interlayer dielectric layer 74.

[0068] Subsequently, a metal gate replacement fabrication process is performed to convert the gate structures 54, 56, and 58 of the high-voltage region 14, medium-voltage region 16, and low-voltage region 18 into metal gates. For example, a selective dry etching or wet etching process can be performed first, such as using an etching solution such as ammonia hydroxide (NH4OH) or tetramethylammonium hydroxide (TMAH) to remove the gate material layer 60 in the hard masks 62 and 64 and the gate structures 54, 56, and 58 to form a groove (not shown) in the interlayer dielectric layer 74. Then, a high dielectric constant dielectric layer 76 and a conductive layer including at least a work function metal layer 78 and a low impedance metal layer 80 are sequentially formed in the groove. A planarization process is then performed to make the surfaces of the U-shaped high dielectric constant dielectric layer 76, the U-shaped work function metal layer 78 and the low impedance metal layer 80 flush with the surface of the interlayer dielectric layer 74. Preferably, the high dielectric constant dielectric layer 76, the work function metal layer 78 and the low impedance metal layer 80 are the gate electrode 66 of each transistor or each device.

[0069] In this embodiment, the high dielectric constant dielectric layer 76 comprises a dielectric material with a dielectric constant greater than 4, such as hafnium oxide (HfO2), hafnium silicon oxide (HfSiO4), hafnium silicon oxynitride (HfSiON), aluminum oxide (Al2O3), lanthanum oxide (La2O3), tantalum oxide (Ta2O5), yttrium oxide (Y2O3), zirconium oxide (ZrO2), strontium titanate oxide (SrTiO3), zirconium silicon oxide (ZrSiO4), hafnium zirconium oxide (HfZrO4), and strontium bismuth tantalum oxide. lead zirconate titanate (SrBi₂Ta₂O₉, SBT) and lead zirconate titanate (PbZr) x Ti 1-x O3, PZT), barium strontium titanate (Ba x Sr 1- x The group consisting of TiO3, BST, or combinations thereof.

[0070] The work function metal layer 78 is preferably used to adjust the work function of the metal gate to make it suitable for N-type transistors (NMOS) or P-type transistors (PMOS). If the transistor is an N-type transistor, the work function metal layer 78 can be made of a metal material with a work function of 3.9 electron volts (eV) to 4.3 eV, such as titanium aluminide (TiAl), zirconium aluminide (ZrAl), tungsten aluminide (WAl), tantalum aluminide (TaAl), hafnium aluminide (HfAl), or TiAlC (titanium aluminum carbide), but is not limited thereto. If the transistor is a P-type transistor, the work function metal layer 78 can be made of a metal material with a work function of 4.8 eV to 5.2 eV, such as titanium nitride (TiN), tantalum nitride (TaN), or tantalum carbide (TaC), but is not limited thereto. Another barrier layer (not shown) may be included between the work function metal layer 78 and the low impedance metal layer 80. The barrier layer may be made of materials such as titanium (Ti), titanium nitride (TiN), tantalum (Ta), or tantalum nitride (TaN). The low impedance metal layer 80 may be selected from low resistance materials such as copper (Cu), aluminum (Al), tungsten (W), titanium-aluminum alloy (TiAl), cobalt-tungsten phosphide (CoWP), or combinations thereof. Since the conversion of a dummy gate into a metal gate according to the metal gate replacement fabrication process is a well-known technique in this field, it will not be described in detail here. Next, a portion of the high dielectric constant dielectric layer 76, a portion of the work function metal layer 78, and a portion of the low impedance metal layer 80 may be removed to form a groove (not shown). Then, a hard mask 82 is filled into the groove and made flush with the surface of the interlayer dielectric layer 74. The hard mask 82 may be selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, and silicon carbide.

[0071] A pattern transfer fabrication process can then be performed. For example, a patterned mask can be used to remove a portion of the interlayer dielectric layer 74 and a portion of the contact hole etching stop layer adjacent to the gate structures 54, 56, and 58 to form multiple contact holes (not shown) and expose the source / drain regions 70. Then, the desired metal material is filled into each contact hole, such as a barrier layer material including titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), etc., and a low-resistance metal layer selected from low-resistance materials or combinations thereof, such as tungsten (W), copper (Cu), aluminum (Al), titanium-aluminum alloy (TiAl), cobalt tungsten phosphide (CoWP), etc. A planarization process is then performed, for example, by chemical mechanical polishing to remove a portion of the metal material to form contact plugs 84 in each contact hole to electrically connect the source / drain regions 70. This completes the fabrication of the semiconductor device according to the preferred embodiment of the present invention.

[0072] Please refer to again Figure 1 and Figure 11 , Figure 1 and Figure 11 A schematic diagram of the structure of a semiconductor device according to one embodiment of the present invention is also disclosed. For example... Figure 1 and Figure 11 As shown, the semiconductor device mainly includes a substrate 12 having a high-voltage region 14, a medium-voltage region 16, and a low-voltage region 18. A high-voltage element 114 is disposed in the high-voltage region 14, a medium-voltage element 116 is disposed in the medium-voltage region 16, and a low-voltage element 118 is disposed in the low-voltage region 18. An electrostatic discharge protection ring 72 surrounds the high-voltage element 114, and a shallow trench isolation 50 surrounds the high-voltage element 114, the medium-voltage element 116, and the low-voltage element 118. The high-voltage element 114 includes a base 20 disposed on the substrate 12, a gate dielectric layer 42 disposed on the base 20, a gate electrode 66 composed of a high dielectric constant dielectric layer 76, a work function metal layer 78, and a low impedance metal layer 80 disposed on the gate dielectric layer 42, and source / drain regions 70 disposed within the base 20 on both sides of the gate electrode 66.

[0073] The medium-voltage element 116 includes a base 22 disposed on a substrate 12, a gate dielectric layer 48 disposed on a base 20, a gate electrode 66 composed of a high dielectric constant dielectric layer 76, a work function metal layer 78, and a low impedance metal layer 80 disposed on the gate dielectric layer 48, and a source / drain region 70 disposed within the base 22 on both sides of the gate electrode 66. The low-voltage element 118 includes multiple fin structures 24 disposed on a substrate 12, a gate dielectric layer 52 disposed on the fin structures 24, a gate electrode 66 composed of a high dielectric constant dielectric layer 76, a work function metal layer 78, and a low impedance metal layer 80 disposed on the gate dielectric layer 52, and a source / drain region 70 disposed within the fin structures 24 or the substrate 12 on both sides of the gate electrode 66.

[0074] In detail, the top surface of the gate electrode 66 in the high voltage region 14 is preferably aligned with the top surface of the gate electrode 66 in the medium voltage region 16 and the low voltage region 18. The top surface of the gate dielectric layer 42 in the high voltage region 14 is preferably lower than the top surface of the gate dielectric layer 48 in the medium voltage region 16 and the top surface of the fin structure 24 in the low voltage region 18, but aligned with the top surface of the shallow trench isolation 50. The top surface of the gate dielectric layer 48 in the medium voltage region 16 is preferably aligned with the top surface of the fin structure 24 in the low voltage region 18. The top surface of the gate dielectric layer 52 in the low voltage region 18 may be slightly higher than the top surface of the gate dielectric layer 48 in the medium voltage region 16. The top surface of the source / drain region 70 in the high voltage region 14 is aligned with the top surface of the fin structure 24 in the low voltage region 18, and the top surface of the electrostatic discharge protection ring 72 is aligned with the top surface of the source / drain region 70.

[0075] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention should be included within the scope of the present invention.

Claims

1. A method of manufacturing a semiconductor device, characterized by, Comprising: a substrate comprising a high voltage region, a medium voltage region, and a low voltage region; forming a high voltage device in the high voltage region, the high voltage device comprising: a first pedestal disposed on the substrate; a first gate dielectric disposed on the first pedestal; and a first gate electrode disposed on the first gate dielectric; forming a low voltage device in the low voltage region, the low voltage device comprising: a fin structure disposed on the substrate; and a second gate electrode disposed on the fin structure, wherein a top surface of the first gate dielectric is lower than a top surface of the fin structure; forming a shallow trench isolation surrounding the high voltage device and the low voltage device, wherein a top surface of the shallow trench isolation is flush with a top surface of the first gate dielectric.

2. The method of claim 1, wherein a top surface of the first gate electrode is flush with a top surface of the second gate electrode.

3. The method of claim 1, further comprising: forming the first pedestal in the high voltage region, a second pedestal in the medium voltage region, and the fin structure in the low voltage region; forming an insulating layer surrounding the first pedestal, the second pedestal, and the fin structure; removing a portion of the first pedestal; forming the first gate dielectric on the first pedestal; forming a second gate dielectric on the second pedestal; removing the insulating layer to form the shallow trench isolation; forming a third gate dielectric on the fin structure; forming the first gate electrode on the first gate dielectric, the second gate electrode on the third gate dielectric, and a third gate electrode on the second gate dielectric; forming a first source / drain region adjacent to the first gate electrode; and forming a second source / drain region adjacent to the second gate electrode.

4. The method of claim 3, wherein a top surface of the first gate dielectric is lower than a top surface of the second gate dielectric.

5. The method of claim 3, wherein a top surface of the first gate electrode is flush with a top surface of the third gate electrode.

6. The method of claim 3, wherein a top surface of the first source / drain region is flush with a top surface of the fin structure.

7. The method of claim 3, further comprising forming an electrostatic discharge protection ring surrounding the high voltage device.

8. The method of claim 7, wherein a top surface of the electrostatic discharge protection ring is flush with a top surface of the first source / drain region.

9. A semiconductor element characterized by comprising: Comprising: a substrate comprising a high voltage region, a medium voltage region, and a low voltage region; a high voltage device in the high voltage region, the high voltage device comprising: a first pedestal disposed on the substrate; a first gate dielectric disposed on the first pedestal; and a first gate electrode disposed on the first gate dielectric; a low voltage device in the low voltage region, the low voltage device comprising: a fin structure disposed on the substrate; and a second gate electrode disposed on the fin structure, wherein a top surface of the first gate dielectric is lower than a top surface of the fin structure; and a shallow trench isolation surrounding the high voltage device and the low voltage device, wherein a top surface of the shallow trench isolation is flush with a top surface of the first gate dielectric.

10. The semiconductor device of claim 9, wherein a top surface of the first gate electrode is flush with a top surface of the second gate electrode.

11. The semiconductor device of claim 9, wherein the high voltage device includes a source / drain region disposed adjacent to the first gate electrode, and a top surface of the source / drain region is aligned with a top surface of the fin structure.

12. The semiconductor device of claim 11, wherein the shallow trench isolation is disposed between the first pedestal and the source / drain region.

13. The semiconductor device of claim 11, further comprising an electrostatic discharge protection ring formed around the high voltage device.

14. The semiconductor device of claim 13, wherein a top surface of the electrostatic discharge protection ring is aligned with a top surface of the source / drain region.

15. The semiconductor device of claim 9, further comprising a medium voltage device disposed in the medium voltage region, the medium voltage device comprising: a second pedestal disposed on the substrate; a second gate dielectric layer disposed on the second pedestal; and a third gate electrode disposed on the second gate dielectric layer.

16. The semiconductor device of claim 15, wherein a top surface of the first gate dielectric layer is lower than a top surface of the second gate dielectric layer.

17. The semiconductor device of claim 15, wherein a top surface of the first gate electrode is aligned with a top surface of the third gate electrode. ​ ​ ​

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