Structures including transistors using buried insulator layers as gate dielectrics and trench isolation in the source and drain

Abstract

The present disclosure relates to structures including transistors using a buried insulator layer as gate dielectric and trench isolation in the source and drain. A structure including a semiconductor-on-insulator (SOI) substrate. The SOI substrate includes a SOI layer over a buried insulator layer over a base semiconductor layer. The structure includes a high voltage first field effect transistor (FET) adjacent to a high performance low voltage second FET. The high voltage FET has a gate electrode on the buried insulator layer and a source and drain in the base semiconductor layer below the buried insulator layer. Thus, the buried insulator layer works as a gate dielectric for the high voltage FET. The low voltage FET has a source and drain on the buried insulator layer (i.e., in the SOI layer). Trench isolation is in each of the source and drain of the first high voltage FET. The source of the high voltage FET surrounds the trench isolation therein.

Description

Technical Field

[0001] This disclosure relates to integrated circuits, and more specifically to structures including high-performance or low-power transistors and high-voltage transistors located on a semiconductor-on-insulator substrate. The high-voltage transistor has a gate electrode located on a buried insulating layer, a source and drain located in a substrate semiconductor layer, and trench isolation located in the source and drain. Background Technology

[0002] Integrated circuit (IC) structures are increasingly combining high-voltage transistors with high-performance low-voltage transistors. Fabricating high-voltage transistors on a fully depleted semiconductor-on-insulator (FDSOI) substrate with fabrication processes compatible with low-voltage transistors presents a challenge. The additional processing required to fabricate high-voltage transistors on FDSOI substrates increases the manufacturing time and cost of these IC structures. Summary of the Invention

[0003] One aspect of this disclosure relates to a structure comprising: a semiconductor-on-insulator (SOI) substrate including a semiconductor-on-insulator (SOI) layer above a buried insulator layer above a substrate semiconductor layer; a first field-effect transistor (FET) adjacent to a second FET, the first FET having a gate electrode on the buried insulator layer and a source and drain in the substrate semiconductor layer below the buried insulator layer, the second FET having a source and drain above the buried insulator layer; and a trench isolation located in each of the source and drain of the first FET, the source of the first FET surrounding the trench isolation therein.

[0004] Another aspect of this disclosure includes a structure comprising: a trench isolation layer in a substrate semiconductor layer in a first region, and a semiconductor-on-insulator (SOI) substrate in a second region; a first field-effect transistor (FET) in the first region adjacent to a second FET in the second region, the first FET having a source and a drain in the substrate semiconductor layer below the trench isolation layer and a gate electrode above the trench isolation layer above the substrate semiconductor layer, the second FET having a source and a drain in a semiconductor-on-insulator (SOI) layer above a buried insulator layer of the SOI substrate; and a deep trench isolation in each of the source and drain of the first FET, the deep trench isolation being integral with the trench isolation layer, the source of the first FET surrounding the deep trench isolation therein.

[0005] One aspect of this disclosure relates to a method comprising: forming a first field-effect transistor (FET) in a first region of an FDSOI substrate, comprising a semiconductor-on-insulator (SOI) layer over a buried insulator layer located above a substrate semiconductor layer, prior to forming a first trench isolation and a second trench isolation spaced apart from the first trench isolation in the substrate semiconductor layer; doping the substrate semiconductor layer to form a source surrounding the first trench isolation and a drain surrounding the second trench isolation, the source of the first FET surrounding the first trench isolation therein; epitaxially growing a semiconductor region over the SOI layer; and forming the gate electrode in the semiconductor region and the SOI layer using the buried insulator layer as a gate dielectric for a gate electrode.

[0006] The above and other features of this disclosure will become apparent from the following more detailed description of embodiments thereof. Attached Figure Description

[0007] Embodiments of this disclosure will be described in detail with reference to the following accompanying drawings, wherein like reference numerals denote like elements, and wherein:

[0008] Figure 1 A cross-sectional view of a structure including a low-voltage FET and a high-voltage FET according to an embodiment of the present disclosure is shown, wherein the high-voltage FET uses a buried insulating layer as a gate dielectric.

[0009] Figure 2 A cross-sectional view of a preliminary structure including trench isolation for a method, according to an embodiment of the present disclosure, is shown.

[0010] Figure 3 A cross-sectional view of the well and source / drain regions of a high-voltage FET according to an embodiment of the present disclosure is shown.

[0011] Figure 4 A cross-sectional view of the gate electrode of a low-voltage FET according to an embodiment of the present disclosure is shown.

[0012] Figure 5 A cross-sectional view of the gate electrode of a high-voltage FET according to an embodiment of the present disclosure is shown.

[0013] Figure 6 A cross-sectional view of a high-voltage FET according to an alternative embodiment of the present disclosure is shown.

[0014] Figure 7A cross-sectional view of a structure including a low-voltage FET and a high-voltage FET according to an embodiment of the present disclosure is shown, wherein the high-voltage FET uses a shallow trench isolation layer as part of the gate dielectric.

[0015] Please note that the accompanying drawings of this disclosure are not necessarily drawn to scale. The drawings are intended to depict only typical aspects of this disclosure and should not be considered as limiting the scope of this disclosure. In the drawings, the same reference numerals denote the same elements between the figures. Detailed Implementation

[0016] In the following description, reference is made to the accompanying drawings, which form a part thereof, and specific exemplary embodiments in which the present teachings may be practiced are illustrated. These embodiments have been described in sufficient detail to enable those skilled in the art to practice the present teachings, and it should be understood that other embodiments may be used and modifications may be made without departing from the scope of the present teachings. Therefore, the following description is merely illustrative.

[0017] It will be understood that when an element, such as a layer, region, or substrate, is described as being "on" or "above" another element, it can be directly on the other element, or there may be intermediate elements. In contrast, when an element is described as being "directly on" or "directly above" another element, there are no intermediate elements. It should also be understood that when an element is described as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or there may be intermediate elements. In contrast, when an element is described as being "directly connected" or "directly coupled" to another element, there are no intermediate elements.

[0018] References to "one embodiment" or "embodiment" and other variations thereof in this specification mean that a particular feature, structure, characteristic, etc., described in connection with that embodiment is included in at least one embodiment of this disclosure. Therefore, the phrase "in one embodiment" or "in an embodiment," and any other variations appearing throughout the specification, do not necessarily refer to the same embodiment. It should be understood that the use of any of the following words, such as "A / B," "A and / or B," and "at least one of A and B," is intended to encompass selecting only the first listed option (a), or only the second listed option (B), or both options (A and B). As other examples, in the cases of “A, B, and / or C” and “at least one of A, B, and C”, these phrases are intended to encompass selecting only the first listed option (A), or only the second listed option (B), or only the third listed option (C), or only the first and second listed options (A and B), or only the first and third listed options (A and C), or only the second and third listed options (B and C), or all three options (A, B, and C). As will be apparent to those skilled in the art, this can be extended to many of the listed items.

[0019] Embodiments of this disclosure provide a structure including a semiconductor-on-insulator (SOI) substrate. The SOI substrate includes an SOI layer above a buried insulator layer located above a substrate semiconductor layer. The structure includes a high-voltage first FET adjacent to a high-performance, low-voltage second field-effect transistor (FET). The high-voltage FET has a gate electrode located on the buried insulator layer, and source and drain electrodes located in the substrate semiconductor layer below the buried insulator layer. Thus, the buried insulator layer serves as the gate dielectric of the high-voltage FET. The low-voltage FET has a source and drain electrode located above the buried insulator layer (i.e., within the SOI layer). Trench isolation is located in each of the source and drain electrodes of the first high-voltage FET. Thus, the source of the high-voltage FET is isolated around the trench therein. The SOI substrate may be a fully depleted SOI substrate (FDSOI), indicating that it uses an ultrathin buried insulator layer (or buried oxide (BOX)) located on top of the substrate semiconductor substrate, and an extremely thin SOI layer providing a transistor channel located above the buried insulator, i.e., for a high-performance, low-voltage FET. The ultrathin SOI layer does not need to be doped to form a channel, thus allowing the transistor to be "completely depleted".

[0020] The embodiments disclosed herein provide high-voltage FETs and high-performance low-voltage FETs using a process fully compatible with FDSOI technology and requiring no additional masks (meaning there is no additional cost to the structure). The high-voltage FETs can operate at voltages up to, for example, 25 volts. This structure also simplifies the design of high-voltage applications in analog circuits, such as analog switches, digital voltage level shifters, and operational amplifier circuits.

[0021] Figure 1 A cross-sectional view of structure 100 according to an embodiment of the present disclosure is shown. Structure 100 includes a semiconductor-on-insulator (SOI) substrate 102, the substrate 102 including an SOI layer 104 above a buried insulating layer 106 located above a substrate semiconductor layer 108. The SOI layer 104 and the substrate semiconductor layer 106 may include, for example, silicon, silicon-germanium, germanium, or other semiconductor materials. The buried insulating layer 106 may include any suitable dielectric, such as, but not limited to, silicon oxide.

[0022] Structure 100 also includes a first field-effect transistor (FET) 120 located in a first region 122 of the SOI substrate 102, adjacent to a second FET 124 in a second region 126 of the SOI substrate 102. The first FET 120 is a high-voltage transistor, and the second FET 124 is a high-performance low-voltage transistor. Therefore, the first FET 120 operates at a voltage higher than that of the second FET 124. In a non-limiting example, the first FET 120 can operate at a voltage up to 10 volts (V). DD The second FET 124 operates at voltages below 4 volts (V). DD The first FET 120 and the second FET 124 operate at a threshold voltage (Vt) of approximately 1V and less than approximately 0.5V, respectively. In the following text, the first FET 120 will be referred to as "high-voltage FET 120" and the second FET 124 will be referred to as "low-voltage FET 124".

[0023] The low-voltage FET 124 may include any now-known or later-developed transistor formed above the SOI substrate 102. The low-voltage FET 124 has a source 130 and a drain 132 located above the buried insulating layer 106 (i.e., within the SOI layer 104). The source 130 and drain 132 of the low-voltage FET 124 are at least partially located within the SOI layer 104. As shown, the source / drain 130, 132 may also include epitaxially raised semiconductor regions 133. The source / drain 130, 132 of the low-voltage FET 124 may include any suitable dopant for the desired polarity of the FET, such as an n-type dopant for an nFET. The low-voltage FET 124 also includes a gate electrode 134 located above the SOI layer 104, forming a channel 136 within the SOI layer 104. The SOI layer 104 may be shaped as a fin, and the gate electrode 134 may surround the fin.

[0024] Gate electrode 134 may include any gate material now known or developed hereafter. In one example, gate electrode 134 may include a high-dielectric-constant metal gate (HKMG). Gate electrode 134 may include one or more conductive components for providing a gate terminal for a transistor. For example, gate electrode 134 may include a high-dielectric-constant (high-K) layer, a work function metal layer, and a gate conductor (not all shown for clarity). The high-K layer may include any high-K material now known or developed hereafter that is commonly used for metal gates, such as, but not limited to: metal oxides, such as tantalum oxide (Ta2O5), barium titanium oxide (BaTiO3), hafnium oxide (HfO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3); or metal silicates, such as hafnium silicate (HfO2). A1 Si A2 O A3 ) or hafnium oxysilicate (Hf) Al Si A2 O A3 N A4A1, A2, A3, and A4 represent relative proportions, each greater than or equal to 0, and A1 + A2 + A3 + A4 (1 being the total relative molar amount). The work function metal layer can include various metals, depending on whether it is used for an NFET or PFET device, but can include, for example: aluminum (Al), zinc (Zn), indium (In), copper (Cu), indium copper (InCu), tin (Sn), tantalum (Ta), tantalum nitride (TaN), tantalum carbide (TaC), titanium (Ti), titanium nitride (TiN), titanium carbide (TiC), TiAlC, TiAl, tungsten (W), tungsten nitride (WN), tungsten carbide (WC), polycrystalline silicon (polycrystalline Si), and / or combinations thereof. The gate conductor can include any gate conductor now known or developed later, such as copper (Cu). A gate cap (not shown) made of, for example, nitride can also be formed above the gate electrode 134.

[0025] The low-voltage FET 124 is isolated from other devices via trench isolation 138. Various wells 140 may be formed in the substrate semiconductor layer 108 to allow for better control of the threshold voltage of the low-voltage FET 124, for example, by applying a backbias. Well connections 142 may also be formed to contact the substrate semiconductor layer 108.

[0026] The high-voltage FET 120 is configured differently from the low-voltage FET 124 to allow operation at higher voltages. The high-voltage FET 120 has a gate electrode 150 located on a buried insulating layer 106, and a source 152 and a drain 154 located in a substrate semiconductor layer 108 beneath the buried insulating layer 106. The buried insulating layer 106 in both the high-voltage and low-voltage FETs 120 and 124 is the same layer, meaning it has the same composition and thickness in both. The source / drain electrodes 152 and 154 of the high-voltage FET 120 can include any suitable dopant for the desired polarity of the high-voltage FET 120, such as an n-type dopant for an nFET.

[0027] exist Figure 1 In this high-voltage FET 120, the gate electrode 150 includes an epitaxial semiconductor layer 156 located above an SOI layer 104. The epitaxial semiconductor layer 156 and the SOI layer 104 of the gate electrode 150 may include any suitable doping. A buried insulating layer 106 provides a gate dielectric 158 for the gate electrode 150, with a channel 160 located within the substrate semiconductor layer 108. The gate electrode 150 of the high-voltage FET 120 may overlap with trench isolations 162 and 164 in the source 152 and drain 154 of the high-voltage FET 120.

[0028] The high-voltage FET 120 also includes trench isolations 162, 164 located in each of its source 152 and drain 154. The trench isolations (TIs) 162, 164 (first and second TIs) allow for high-voltage operation. The drain 154 of the high-voltage FET 120 surrounds the trench isolation 164 therein, and the source 152 of the high-voltage FET 120 surrounds the trench isolation 162 therein. That is, the TIs 162, 164 are completely surrounded by doped portions of the substrate semiconductor layer 108 that provides the source 152 and drain 154.

[0029] The high-voltage FET 120 is isolated from other devices by additional (third and fourth) trench isolation (TI) 170, 172. Various wells 140, 142, 174 may be formed in the substrate semiconductor layer 108. Well connections 142, 172 may be formed to contact the substrate semiconductor layer 108. Other wells (not shown) may be provided in the first region 122, for example, to provide an extended junction (similar to a lightly doped drain (LDD) implant) to better control the threshold voltage of the high-voltage FET 120, for example, by applying a reverse bias.

[0030] Figures 2 to 5 A cross-sectional view of the method for forming structure 100 is shown. Generally, a high-voltage FET 120 and a low-voltage FET 124 are formed simultaneously. First, the high-voltage FET 120 is formed in a first region 122 of the SOI substrate 102, and the low-voltage FET 124 is formed in a second region 126 of the SOI substrate 102. The second region 126 of the SOI substrate 102 may be adjacent to the first region 122 and electrically isolated from the first region 122, for example, by trench isolation 170.

[0031] Figure 2 A preliminary structure 200 of the method after some initial processing is shown. The processing begins with an SOI substrate 102, which may comprise a fully depleted semiconductor-on-insulator substrate including an SOI layer 104 above a buried insulator layer 106 located above a substrate semiconductor layer 108. Figure 2 In this process, further processing has been performed on the SOI substrate 102. More specifically, the SOI substrate 102 has TI 138(2), 170, 162, 164, and 172 formed therein. TI can be formed using any process now known or developed later. For example, various trenches (not labeled) through the SOI substrate 102 can be formed using masking and etching processes. Etching removes portions of the SOI layer 104, the buried insulating layer 106, and the substrate semiconductor layer 108. Notably, etching removes what will become... Figure 3A buried insulating layer 106 is formed above the source 152 and drain 154 regions of the high-voltage FET 120 in the FDSOI substrate 102. The trench can then be filled with a dielectric (e.g., silicon oxide). Overfilling and etch-back of the dielectric deposited in the trench may cause the buried insulating layer 106 (which typically comprises the same material as the TI) to extend over the finished TI 138, 170, 162, 164, 172. The SOI layer 104 and the buried insulating layer 106 can also be removed in other areas that are not needed during this process. Thus, the first high-voltage FET 120 is formed in the first region 122 of the FDSOI substrate 102 by forming a first TI 162 in the substrate semiconductor layer 108 and a second TI 164 spaced apart from the first TI 162. Figure 1 It can simultaneously form a second low-voltage FET 124. Figure 1 The TI 138 and the other TI 170 and 172.

[0032] Figure 3 Cross-sectional views are shown of various portions (e.g., wells and source / drains) of the doped substrate semiconductor layer 108 to form FETs 120 and 124. Doping may include any now-known or later-developed process for implanting dopants into the substrate semiconductor layer 108, such as ion implantation. The type of dopant and its concentration may be selected based on the desired polarity and performance characteristics. Any necessary mask may be used to guide the doping if needed. Any number of doping processes may be performed to achieve the desired doping distribution. For purposes of description, it will be assumed that FETs 120 and 124 are nFETs, i.e., source / drains with n-type doping. In the first region 122, the source 152 is formed around the first TI 162, and the drain 154 is formed around the second TI 164. Thus, the source 152 of the high-voltage FET 120 ( Figure 1 Around the first TI, the drain of the high-voltage FET 120 is 154 ( Figure 1 The second TI 164 can be surrounded therein. Other wells can also be formed during this step. For example, the doping process can also include doping the substrate semiconductor layer 108 beneath the buried insulating layer 106 in the second region 126 of the low-voltage FET 124. This process forms an n-well 140, for example, in the substrate semiconductor layer 108 in the second region 126. Other doping processes can form well connections 142, 174 in the first region 122 to contact the substrate semiconductor layer 108. For example, other wells (not shown) can be formed to provide an extended junction for better control of the threshold voltage of the high-voltage FET 120, for example, by applying a reverse bias. Thus, the well 140 and source / drain regions 152, 154 of the low-voltage FET 124 and the channel of the high-voltage FET 120 can be formed in the same process.

[0033] Figure 4 A cross-sectional view is shown of a gate electrode 134 formed over an SOI layer 104 between the source 130 and drain 132 of a low-voltage FET 124. As previously described, the gate electrode 134 may comprise any gate material now known or developed later. In one example, as previously described, the gate electrode 134 may comprise HKMG. The gate electrode material may also be formed over the SOI layer 104 in the first region 122 and then subsequently removed, for example, by etching (see the dashed box indicating the removed gate electrode 188). The gate material may be deposited using any suitable technique (e.g., atomic layer deposition) and may be patterned using any technique. Replacement metal gates or gate-first methods may be used.

[0034] Figure 5 A cross-sectional view is shown above the SOI layer 104 in the first region 122, showing an epitaxially grown semiconductor region 156. The terms “epitaxical growth” and “epitaxically formed and / or grown” mean growing a semiconductor material on a deposited surface of a semiconductor material, wherein the grown semiconductor material may have the same crystallinity characteristics as the semiconductor material on the deposited surface. Figure 5 Also shown is a gate dielectric 158 using a buried insulating layer 106 as a gate electrode 150, with the gate electrode 150 formed in a semiconductor region 156 and an SOI layer 104. The formation of the gate electrode 150 may include doping the semiconductor region 156 and / or the SOI layer 104 with appropriate dopants. (See also: Regarding...) Figure 4 The formation of the gate electrode 134 of the low-voltage FET 124 can occur before the formation of the gate electrode 150 of the high-voltage FET 120. In this case, the gate electrode 188 of the low-voltage FET 124 ( Figure 4 The dashed box in the figure can be removed from the semiconductor region 156 and SOI layer 104 in the first region 122 before the gate electrode 150 of the high-voltage FET 120 is formed. Figure 5 Also shown is a raised semiconductor region 133 epitaxially grown over an SOI layer 104 adjacent to the gate electrode 150. The raised semiconductor region 133 can be doped in any known manner to form raised source 130 and drain 132 for a low-voltage FET 124. The epitaxial process can also form source 152 and drain 154 for a high-voltage FET 120 in the first region 122. Figure 1 The raised semiconductor regions 178 and 180 for any of the various wells 140, 142, and 174. The raised semiconductor regions 133, 178, and 180 may include any suitable dopant. Any necessary spacers (not shown) may also be formed at this stage.

[0035] Then any now-known or later-developed semiconductor manufacturing process can be performed to form the interconnect layers to the first and second regions 122, 126 and the FETs 120, 124. For example... Figure 1 As shown, silicide 190 can be simultaneously formed above the source 152, drain 154, and gate electrode 150 of the high-voltage FET 120 and the source 130, drain 132, and gate electrode 134 of the low-voltage FET 124. Silicide 190 can be formed using any now-known or later-developed techniques, such as performing in-situ pre-cleaning, depositing metal (e.g., titanium, nickel, cobalt, etc.), annealing to react the metal with silicon, and removing unreacted metal. Any number of contacts 192 can be formed through the interlayer dielectric 194 to reach the necessary portions of the FETs 120 and 124.

[0036] Figure 6 A cross-sectional view of an alternative embodiment of a high-voltage FET 120 is shown, which can be used with the structure 100 described earlier herein. In this embodiment, the source 152 and drain 154 of the high-voltage FET 120 include p-type dopants, and additional wells are provided to control the threshold voltage of the FET 120. In this case, the high-voltage FET 120 includes n-type wells 210, 212 isolated by TI 170, 172 adjacent to each of the sources 152 and 154 of the high-voltage FET 120. Since the n-type wells 210, 212 cannot extend deep enough into the substrate semiconductor layer 108 to provide the required control, the high-voltage FET 120 may also include a deep n-type well 218 coupled in the substrate semiconductor layer 108 to the n-type wells 210, 212. In this embodiment, as formed Figure 2 The TI shown also includes the formation of: a (third) TI170 spaced apart from (first) TI 162 (within source 152), a (fourth) TI 214 spaced apart from (third) TI 170, a (fifth) TI 172 spaced apart from (second) TI 164 (within drain 154), and a (sixth) TI 216 spaced apart from (fifth) TI 172. Figure 3 The doping shown will include doping the substrate semiconductor layer 108 with an n-type dopant to form an n-type well 210 between TI 170 and TI 214, and an n-type well 212 between TI 172 and TI 216. The doping also includes performing doping to form a deep n-type well 218 in the substrate semiconductor layer 108 coupling the n-type wells 210, 212. Any suitable contact 192 of the various wells 210, 212 and / or p-type substrate semiconductor layer 108 can be added.

[0037] Figure 7A cross-sectional view of a structure 100 including a high-voltage FET 220 is shown. In this embodiment, a trench isolation layer 222 replaces the buried insulating layer 106 beneath the gate electrode 234 of the high-voltage FET 120 in the first region 122. Figure 1 The gate electrode 234 of the high-voltage FET 220 is in the form of an HKMG rather than... Figure 1 The semiconductor in the embodiment.

[0038] like Figure 7 As shown, structure 100 may include an SOI substrate 102, which includes an SOI layer 104 in a second region 126 above a buried insulator layer 106 located above a substrate semiconductor layer 108. A low-voltage FET 124 is described previously herein. The gate electrode 134 of the low-voltage FET 124 is located above the (semiconductor) SOI layer 104 above the buried insulator layer 106 above the substrate semiconductor layer 108. The source 130 and drain 132 of the low-voltage FET 124 are located within the (semiconductor) SOI layer 104 above the buried insulator layer 106. The gate electrode 134 of the low-voltage FET 124 may include a high-dielectric-constant metal gate (HKMG) located above the (semiconductor) SOI layer 104. In contrast, in the first region 122, the SOI layer 104 and the buried insulator layer 106 are removed during trench isolation formation. In the first region 122, a trench isolation layer 222 is located in the substrate semiconductor layer 108, with deep trench isolation (DTI) layers 240, 242 coupled thereto and extending into the source 152 and drain 154, respectively. The trench isolation layer 222 is formed in a shallow trench 235 such that its upper surface 236 is coplanar with the upper surface 237 of the substrate semiconductor layer 108, in contrast to the buried insulating layer located above the substrate semiconductor layer 108 in the second region 126. The trench isolation layer 222 and the DTI layers 240, 242 can be formed using any now-known or later-developed (dual) trench isolation formation process, such as trench formation, dielectric deposition, and planarization. The trench isolation layer 222 can have a thickness of, for example, from 20 nanometers (nm) to 50 nm, and may be referred to as "shallow trench isolation (sSTI)". Trench isolation layer 22 and DTI 240, 242 can be isolated from the trench (e.g., TI 138, 170, 172) Figure 2 They are formed together. DTIs 240 and 242 extend deeper into the substrate semiconductor layer 108 than trench isolation layer 222. DTIs 240 and 242 can also be referred to as “deep gate isolation”. DTIs 240 and 242 are located in the source 152 and drain 154, respectively, that is, the source 152 and drain 154 surround the corresponding DTIs 240 and 242 to create a longer drift region to support a higher drain voltage (V). DDThe relative positions of the junctions of the source 152 and drain 154 with the base semiconductor layer 108 below the gate electrode 234, as well as the relative positions of the DTIs 240 and 242 in the source 152 and drain 154, can be controlled to obtain the desired performance characteristics.

[0039] The high-voltage FET 220 is adjacent to the low-voltage FET 124 and has a source 152 and a drain 154 located in the substrate semiconductor layer 108 and below the trench isolation layer 222. Figure 1 Compared to structure 100, the gate electrode 234 of the high-voltage FET 220 may include an HKMG located above a trench isolation layer 222 above the substrate semiconductor layer 108. The gate electrode 226 of the high-voltage FET 220 includes a gate dielectric layer 226, which includes a trench isolation layer 222 and at least one dielectric layer 228 located above the trench isolation layer 222. That is, the gate dielectric layer 226 of the gate electrode 234 may include a trench isolation layer 222 and one or more dielectric layers 228 located above the trench isolation layer 222. The dielectric layer 228 may include one or more high-k layers as described herein with respect to HKMG, such as, but not limited to, hafnium oxide and titanium nitride. The gate electrode 234 may include other layers as described herein with respect to HKMG, such as a work function metal and a gate conductor. The gate dielectric layer 226 is located above the trench isolation layer 222 above the substrate semiconductor layer 108.

[0040] As mentioned above, Figure 7 Structure 100 also includes DTIs 240 and 242 in each of the source 152 and drain 154 of the high-voltage FET 220. The source 154 of the high-voltage FET 220 surrounds the DTI 240 therein, and the drain 154 of the high-voltage FET 220 surrounds the DTI 242 therein. The trench isolation layer 222 may include any suitable trench isolation dielectric, such as silicon oxide. The DTIs 240 and 242 are integral with the trench isolation layer 222 and may include the same material or another dielectric. The trench isolation layer 222 and the DTIs 240 and 242 may be formed in a manner similar to trench isolations 138, 170, and 172. The gate electrode 234 of the high-voltage FET 220 overlaps with both the DTIs 240 and 242 in the source 152 and drain 154 of the FET, respectively.

[0041] The embodiments of this disclosure utilize a process fully compatible with FDSOI technology and requiring no additional mask (meaning the structure is cost-neutral), providing both high-voltage FETs and high-performance low-voltage FETs. The high-voltage FETs can operate at, for example, 10 volts, where the gate-source voltage (Vgs) and gate-drain voltage (Vds) are greater than or equal to 10V. Due to the reduction in gate-source, gate-drain, and gate-gate capacitances (Cgs, Cgd, and Cgg), the high-voltage FETs also exhibit shorter switching times. This structure also simplifies analog circuit design for analog switches (e.g., reducing an eight-transistor device to a two-transistor or single-transistor device), certain high-voltage devices, such as, but not limited to, digital voltage level shifters (e.g., reducing an eight-transistor device to a four-transistor device), and operational amplifier applications.

[0042] The above-described structure and method are used for the manufacture of integrated circuit chips. The resulting integrated circuit chips can be distributed by the manufacturer in the form of raw wafers (i.e., as a single wafer with multiple unpackaged chips), as bare dies, or in packages. In the latter case, the chips are mounted in single-chip packages (e.g., plastic carriers with leads attached to a motherboard or other higher-level carriers) or multi-chip packages (e.g., ceramic carriers with surface interconnects and / or buried interconnects). In any case, the chips are then integrated with other chips, discrete circuit elements, and / or other signal processing devices as part of (a) an intermediate product (e.g., a motherboard) or (b) a final product. The final product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products with displays, keyboards or other input devices, and central processing units.

[0043] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. As used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It will be further understood that, when used in this specification, the terms “comprising” and / or “including” specify the presence of the stated features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof. “Optional” or “optionally” indicates that an event or condition subsequently described may or may not occur, and the description includes cases where the event occurs and cases where the event does not occur.

[0044] The approximate language used throughout the specification and claims can be used to modify any quantitative expression that allows for variation without causing a change in its associated essential function. Therefore, values ​​modified by one or more terms such as “about,” “approximate,” and “substantially” are not limited to the specified exact values. In at least some cases, approximate language may correspond to the precision of the instrument used to measure the value. In this document and throughout the specification and claims, range limitations can be combined and / or interchanged, such ranges being identified and including all subranges contained therein, unless the context or language indicates otherwise. The term “approximate” applied to a specific value within a range applies to both values ​​and, unless otherwise dependent on the precision of the instrument used to measure the value, may indicate + / - 10% of said value.

[0045] All the means or steps plus functional elements in the following claims are intended to include any structure, material, action, and equivalent that performs the function in combination with other claimed elements of the particular claim. The present disclosure has been described for purposes of illustration and description, but such description is not intended to be exhaustive or to limit the disclosure to the forms disclosed. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the disclosure. The embodiments were chosen and described in order to best explain the principles and practical application of the disclosure and to enable others skilled in the art to understand the various embodiments of the disclosure with various modifications suitable for the particular intended use.

Claims

1. A semiconductor structure, comprising: Semiconductor-on-insulator (SOI) substrate, comprising a semiconductor-on-insulator (SOI) layer above a buried insulator layer located above a substrate semiconductor layer; A first field-effect transistor (FET) is adjacent to a second FET, the first FET having a gate electrode on the buried insulator layer and a source and drain in the substrate semiconductor layer below the buried insulator layer, and the second FET having a source and drain above the buried insulator layer; as well as A trench isolation is provided, which is located in each of the source and drain of the first FET, with the source of the first FET surrounding the trench isolation therein.

2. The structure of claim 1, wherein, The buried insulating layer has the same composition and the same thickness in both the first FET and the second FET.

3. The structure of claim 1, wherein, The first FET operates at a higher voltage than the second FET.

4. The structure of claim 1, wherein, The gate electrode of the first FET overlaps with the trench isolation in the source and drain of the first FET.

5. The structure according to claim 1, wherein, The gate electrode of the first FET includes an epitaxial semiconductor layer located above the SOI layer.

6. The structure according to claim 5, wherein, The second FET includes a gate electrode located above the SOI layer, and wherein the source and drain of the second FET are at least partially located in the SOI layer.

7. The structure according to claim 1, wherein, The source and drain of the first FET include p-type dopants, and the structure further includes an n-type well isolated by trench isolation adjacent to each of the source and drain of the first FET, and a deep n-type well coupled in the substrate semiconductor layer.

8. A semiconductor structure, comprising: The trench isolation layer is located in the substrate semiconductor layer in the first region, and the semiconductor-on-insulator (SOI) substrate is located in the second region; A first field-effect transistor (FET) located in the first region is adjacent to a second FET located in the second region. The first FET has a source and a drain in the substrate semiconductor layer below the trench isolation layer and a gate electrode above the trench isolation layer above the substrate semiconductor layer. The second FET has a source and a drain in a semiconductor-on-insulator (SOI) layer above the buried insulator layer of the SOI substrate. as well as A deep trench isolation is located in each of the source and drain of the first FET, the deep trench isolation being integral with the trench isolation layer, and the source of the first FET surrounding the deep trench isolation therein.

9. The structure according to claim 8, wherein, The gate electrode of the first FET overlaps with the deep trench isolation in the source and drain of the first FET.

10. The structure according to claim 8, wherein, The gate electrode of the first FET includes a high-dielectric-constant metal gate (HKMG) located above the trench isolation layer.

11. The structure according to claim 8, wherein, The second FET includes a gate electrode comprising a high-dielectric-constant metal gate (HKMG) located above the SOI layer.

12. The structure according to claim 8, wherein, The gate electrode of the first FET includes a gate dielectric layer, the gate dielectric layer including the trench isolation layer and at least one dielectric layer located above the trench isolation layer.

13. A method for forming a semiconductor structure, comprising: In a fully depleted semiconductor-on-insulator (FDSOI) substrate, including a semiconductor-on-insulator (SOI) layer located above a buried insulator layer above a substrate semiconductor layer, a first field-effect transistor (FET) is formed in a first region of the FDSOI substrate in the following manner: A first trench isolation and a second trench isolation spaced apart from the first trench isolation are formed in the substrate semiconductor layer; The substrate semiconductor layer is doped to form a source isolated around the first trench and a drain isolated around the second trench, wherein the source of the first FET is isolated around the first trench therein; A semiconductor region is epitaxially grown above the SOI layer; as well as The buried insulating layer is used as the gate dielectric for the gate electrode, and the gate electrode is formed in the semiconductor region and the SOI layer.

14. The method of claim 13, further comprising forming a second FET in a second region of the SOI substrate that is adjacent to and electrically isolated from the first region, by means of: The SOI layer is doped to form the source and drain of the second FET therein, the source and drain of the second FET being located above the buried insulator layer; A gate electrode is formed above the SOI layer between the source and drain of the second FET.

15. The method according to claim 14, wherein, The formation of the gate electrode for the second FET occurs before the formation of the gate electrode for the first FET, and the method further includes: removing the gate electrode for the second FET from the semiconductor region in the first region and over the SOI layer before forming the gate electrode for the first FET.

16. The method of claim 14, wherein, Epitaxial growth of the semiconductor region over the SOI layer further includes epitaxial growth of a raised semiconductor region over each of the source and drain of the second FET.

17. The method of claim 14, wherein, Doping the substrate semiconductor layer to form the source isolated around the first trench and the drain isolated around the second trench in the first region for the first FET further includes: doping the substrate semiconductor layer beneath the buried insulator layer in the second region for the second FET.

18. The method of claim 14, further comprising: Simultaneously, silicide is formed above the source, drain, and gate electrodes of the first FET and the source, drain, and gate electrodes of the second FET.

19. The method according to claim 13, wherein, The source and drain of the first FET include a p-type dopant, and the formation of the first trench isolation and the second trench isolation further includes: forming a third trench isolation spaced apart from the first trench isolation, a fourth trench isolation spaced apart from the third trench isolation, a fifth trench isolation spaced apart from the second trench isolation, and a sixth trench isolation spaced apart from the fifth trench isolation, and the method further includes: doping the substrate semiconductor layer with an n-type dopant to form an n-type well between the third trench isolation and the fourth trench isolation and between the fifth trench isolation and the sixth trench isolation, and doping to form a deep n-type well coupled to the n-type well in the substrate semiconductor layer.

20. The method according to claim 13, wherein, Epitaxial growth of the semiconductor region over the SOI layer further includes epitaxial growth of a raised semiconductor region over each of the source and drain of the first FET.

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