Method for producing hexagonal boron nitride layer, iii-v epitaxial structure and method of fabrication

Abstract

The application discloses a preparation method of a hexagonal boron nitride layer, a III-V epitaxial structure and a manufacturing method. The preparation method comprises the following steps: performing pre-nitriding treatment on a substrate to form a nitriding layer; forming a first nucleation layer containing hexagonal boron nitride; performing first annealing treatment; alternately contacting a nitrogen source and a boron source to perform growth to obtain a hexagonal boron nitride layer. The manufacturing method comprises the following steps: growing a second nucleation layer on the surface of the hexagonal boron nitride layer; performing second annealing treatment on the second nucleation layer; and epitaxially growing a III-V semiconductor layer. The preparation method provided by the application can directly grow and form a hexagonal boron nitride layer on the surface of a non-copper substrate, without the need of performing stripping and bonding treatment, thereby improving the quality of epitaxial growth based on the hexagonal boron nitride layer, and significantly reducing the process complexity. The manufacturing method provided by the application does not need a stripping and bonding process and a special copper substrate, and the dislocation density of the formed III-V epitaxial layer is low, and the performance is excellent.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor epitaxial growth, and in particular to a preparation method of a hexagonal boron nitride layer, a III-V epitaxial structure and a manufacturing method. BACKGROUND

[0002] III-V semiconductor materials, such as GaN-based materials, have the characteristics of wide band gap, high saturated electron velocity, high thermal conductivity and stable chemical properties, which make them suitable for making electronic devices that work at high frequency, high power, high radiation resistance and high temperature. Using the polarization effect of GaN materials, a high-concentration two-dimensional electron gas (2DEG) can be formed at the non-doped heterojunction interface, which avoids impurity scattering and greatly improves the electron mobility. High electron mobility transistors (HEMTs) based on this two-dimensional electron gas have the characteristics of high power density, high breakdown field strength, high cutoff frequency and fast switching speed, and are very suitable for working under high frequency, high power and high voltage conditions, and have good application prospects in digital communication, new display and power electronics.

[0003] Unlike the first generation of semiconductor Si materials, GaN is mainly obtained by growing on a homogeneous or heterogeneous substrate through vapor phase epitaxy. The self-supporting substrate used for GaN homoepitaxy is generally prepared by HVPE (Hydride Vapor Phase Epitaxy), which has limited size and high price. GaN heteroepitaxy usually uses sapphire, silicon (111) or silicon carbide (SiC) substrates. SiC substrates have the best performance but are expensive. Sapphire substrates are difficult to process, have poor thermal and electrical conductivity, and it is difficult to obtain large-size substrates. In comparison, Si substrates have the advantages of low price, large size, good electrical and thermal conductivity, and easy processing, so epitaxial growth of GaN materials on Si substrates is an important choice to reduce process complexity and production cost.

[0004] Among them, the GaN materials prepared on sapphire and SiC substrates based on GaN and AlN nucleation layer method have the best quality, but the dislocation density is still as high as ~1E7 / cm2, which restricts the further performance of GaN-based devices.

[0005] The most commonly used GaN hetero-epitaxy substrates at present are mainly sapphire substrates, Si (111) substrates and SiC substrates. Among them, the sapphire substrate is also a hexagonal wurtzite structure. The GaN epitaxial on sapphire generally uses a two-step nucleation method, and the GaN nucleation layer is epitaxially grown at a low temperature, and then the GaN film is epitaxially grown again after high-temperature annealing. On the Si (111) substrate, the currently used buffer layer is a high-temperature AlN buffer layer, an AlGaN buffer layer, an AlGaN / GaN superlattice layer, a SiN amorphous insertion layer and a patterned Si surface treatment technology to further epitaxially grow a GaN thin film. On the SiC substrate, GaN and AlN buffer layers are also mainly used to further epitaxially grow GaN. Due to greater lattice mismatch, there is no direct report on epitaxial growth of GaN on Si (100) substrates at present.

[0006] However, the lattice mismatch and thermal mismatch inherent in hetero-epitaxy seriously affect the crystal quality of the epitaxial material. Although the emergence of the nucleation layer technology enables high-quality GaN material layers to be obtained on some substrates with greater lattice mismatch to GaN (especially, for example, Si (100)), the nucleation layer grown by the mainstream MOCVD method on the market still has certain dependence on the substrate, thereby making it difficult to obtain high-quality GaN material layers on some substrates with greater lattice mismatch (especially, for example, Si (100)), and in some existing situations, the dislocation density is still as high as 1E7 / cm 2 , which limits the further expansion of the application field of the GaN epitaxial layer.

[0007] In addition, due to the greater lattice mismatch between the Si (100) substrate and GaN, it is currently impossible to obtain high-quality GaN single crystal material on the Si (100) substrate by direct epitaxy. In order to make GaN compatible with the traditional Si MOS process, a complex substrate peeling and re-bonding to the Si (100) substrate is required. Therefore, the process flow is increased, the yield is reduced, and the cost is high.

[0008] The traditional Si-based process adopts a Si (100) substrate, and therefore, the GaN-based integrated circuit needs to be compatible with the mature Si-based process through a subsequent complex peeling and bonding process. Therefore, exploring a new epitaxy method is of great significance to solve the GaN large-mismatch hetero-epitaxy. SUMMARY

[0009] In view of the deficiencies of the prior art, the purpose of the present application is to provide a hexagonal boron nitride layer preparation method, a III-V epitaxial structure and a manufacturing method.

[0010] To achieve the foregoing purposes of the application, the technical solutions adopted by the present application include:

[0011] In a first aspect, the present application provides a method for preparing a hexagonal boron nitride layer, comprising:

[0012] 1) performing a pre-nitridation treatment on a substrate to form a nitrided layer on the surface of the substrate;

[0013] 2) contacting the nitrided layer with a nitrogen source and a boron source to form a first nucleation layer containing hexagonal boron nitride on the surface of the nitrided layer;

[0014] 3) performing a first annealing treatment on the first nucleation layer;

[0015] 4) alternately contacting the first nucleation layer with the nitrogen source and the boron source to grow the hexagonal boron nitride, thereby obtaining a hexagonal boron nitride layer.

[0016] In a second aspect, the present application also provides a method for preparing a III-V epitaxial structure, comprising:

[0017] forming a hexagonal boron nitride layer on a substrate by using the above method;

[0018] growing a second nucleation layer on the surface of the hexagonal boron nitride layer, wherein the second nucleation layer contains a III-V compound;

[0019] performing a second annealing treatment on the second nucleation layer;

[0020] epitaxially growing a III-V semiconductor layer on the surface of the second nucleation layer.

[0021] In a third aspect, the present application also provides a III-V epitaxial structure prepared by using the above method.

[0022] Based on the above technical solutions, compared with the prior art, the present application has the following beneficial effects:

[0023] The method for preparing a hexagonal boron nitride layer provided by the present application can directly grow a hexagonal boron nitride layer on the surface of a non-copper substrate, especially on the surface of a silicon (100) substrate with a large lattice mismatch, by pre-nitridation and forming a first nucleation layer, without the need for processes such as exfoliation bonding of the hexagonal boron nitride layer, thereby improving the quality of epitaxial growth based on the hexagonal boron nitride layer and significantly reducing the complexity of the process.

[0024] The method for preparing a III-V epitaxial structure based on the above hexagonal boron nitride layer provided by the present application does not require an exfoliation bonding process or a specific copper substrate, and the dislocation density of the III-V epitaxial layer formed is low, and the performance is excellent.

[0025] The above description is only a summary of the technical scheme of the present application, in order to enable those skilled in the art to more clearly understand the technical means of the present application, and can be implemented according to the content of the description, as follows. BRIEF DESCRIPTION OF DRAWINGS

[0026] Figure 1 is a flowchart of the manufacturing process of the III-V epitaxial structure provided by a typical embodiment of the present application;

[0027] Figure 2 is an AFM photo of the surface morphology of the h-BN film provided by a typical embodiment of the present application;

[0028] Figure 3a is an XRD test graph of the GaN semiconductor layer provided by a typical embodiment of the present application;

[0029] Figure 3b is an XRD test graph of the GaN semiconductor layer provided by a typical embodiment of the present application. DETAILED DESCRIPTION

[0030] In view of the deficiencies in the prior art, the present inventors have long studied and practiced to come up with the technical scheme of the present application. The technical scheme, its implementation process and principles will be further explained as follows.

[0031] h-BN is a hexagonal structure, consistent with the wurtzite structure of GaN, AlN, etc., and h-BN is a two-dimensional wide-bandgap insulating material, without dangling bonds in the vertical direction, which can effectively avoid the troubles caused by lattice mismatch, and thus solve the dependence on hetero-substrates in the process of GaN hetero-epitaxy. Therefore, we propose to use h-BN as a buffer layer to effectively solve the problems of non-epitaxy or poor epitaxy quality caused by lattice mismatch between Si(100) substrates and GaN, AlN films, etc.

[0032] In the following description, many specific details are set forth in order to provide a thorough understanding of the present application, however, the present application can be practiced in other manners different from those described herein, therefore, the scope of protection of the present application is not limited by the specific embodiments disclosed below.

[0033] Moreover, the relationship terms such as "first" and "second" are only used to distinguish one from another of the components or method steps with the same name, and do not necessarily require or imply any such actual relationship or sequence between the components or method steps.

[0034] The embodiment of the present application provides a preparation method of a hexagonal boron nitride layer, comprising the following steps:

[0035] 1) pre-nitridation treatment is performed on the substrate to form a nitrided layer on the surface of the substrate.

[0036] 2) the nitrided layer is contacted with a nitrogen source and a boron source to form a first nucleation layer containing hexagonal boron nitride on the surface of the nitrided layer.

[0037] 3) the first nucleation layer is subjected to a first annealing treatment.

[0038] 4) the first nucleation layer is alternately contacted with a nitrogen source and a boron source to grow hexagonal boron nitride, thereby obtaining a hexagonal boron nitride layer.

[0039] The inventors have found that in the above technical solution, by first forming a nitrided layer, and the nitrided layer is preferably an amorphous layer, the lattice mismatch between the substrate and the hexagonal boron nitride layer is blocked, and the corresponding first nucleation layer and the corresponding annealing process are used, and the nitrogen source and the boron source are alternately introduced, so that the subsequent hexagonal boron nitride layer has high growth quality, thereby forming a high-quality growth foundation that can cooperate with subsequent epitaxial growth, especially III-V semiconductor layer epitaxial growth.

[0040] However, the prior art provides some technical solutions for preparing semiconductor epitaxial layers using hexagonal boron nitride as an epitaxial growth foundation. However, the conventional method uses CVD to epitaxially grow h-BN on a Cu foil or the like, or uses h-BN on a Cu foil to be transferred to a substrate required for epitaxy, which is a relatively easy way to achieve h-BN epitaxy. This is because the conventional use of Cu substrate to epitaxially grow h-BN is because Cu has a certain catalytic effect on the epitaxy of h-BN on the upper layer, and it is easier to achieve h-BN epitaxy on a Cu foil.

[0041] The technical solution provided by the present application first uses MOCVD method, which can be used to epitaxially grow on some insulating substrates other than Cu foil substrate, especially Si(100), Si(111), SiC and the like. More importantly, Si(100) substrate can be directly compatible with the current Si integrated circuit process, while Cu foil cannot. However, due to the lattice mismatch between the substrate and GaN, it is also difficult to directly epitaxially grow GaN film on Si(100) substrate. Therefore, the substrate needs to be specially treated, such as pre-nitridation, and the requirement for the epitaxial process window of MOCVD is also higher. Therefore, h-BN can be epitaxially grown on Si substrate as a GaN buffer layer to shield the lattice mismatch between the substrate and GaN, thereby preparing a good GaN film, which is a unique advantage of the technical solution provided by the present application.

[0042] Secondly, the technical scheme provided by the embodiment of the present application uses pre-nitriding to process the substrate, forms an amorphous nitride layer on the surface, and relieves the lattice mismatch between the substrate and the h-BN, so as to facilitate the epitaxy of the h-BN crystal film. As analyzed above, it is difficult to epitaxially grow a GaN film on a Si(100) substrate directly due to the lattice mismatch with the substrate, but the lattice mismatch between GaN and h-BN is small, and the h-BN can effectively relieve the problem of lattice mismatch because it is a two-dimensional material and has no dangling bonds on the surface. However, this also brings a new problem, that is, it is difficult for GaN to nucleate on the surface of h-BN. Therefore, in the present application, through technical means, it is found that the MOCVD is used to epitaxially grow an AlN nucleation layer on the surface of h-BN under suitable conditions, so as to solve the problem that GaN cannot be epitaxially grown due to the absence of a nucleation layer. Compared with the scheme of providing an atomic layer deposition AlN layer in some prior art, the process of taking the substrate out of the MOCVD, putting the sample into the atomic layer deposition CVD to epitaxially grow the AlN, and then putting it back into the MOCVD to continue to epitaxially grow the upper GaN is avoided, the process is simplified, the time is saved, and the cost is reduced.

[0043] Throughout the prior art, there is no technology that can directly epitaxially grow h-BN on a non-copper substrate. Directly epitaxially growing h-BN on a non-copper substrate has the advantages of good uniformity and large area, and can be directly epitaxially grown to a size of 2, 4, 6, or 8 inches. In addition, in some prior art, graphene-h-BN composite layers are still needed. Because this is transferred from a Cu foil to a substrate, the process is more complicated than direct epitaxy, and the film is prone to breakage during the transfer process, and thus needs to be combined with graphene. The technical scheme provided by the embodiment of the present application obviously does not need to do so.

[0044] Therefore, the direct epitaxy method provided by the present application reduces the process steps, improves the yield, and reduces the cost.

[0045] In addition, the present application is significantly different from the technical solutions of the prior art in that the preparation method and the role of the AlN nucleation layer and the h-BN layer are different. For the h-BN layer, in addition to the different preparation method described above, the purpose of the h-BN layer in the technical solution provided by the present application is to shield the lattice mismatch between GaN and the substrate and to further epitaxially grow GaN and AlN by using the characteristics of the hexagonal phase of h-BN. The purpose of some prior art is to promote GaN nucleation and to protect the underlying AlN layer. The AlN nucleation layer prepared by the magnetron sputtering method used in the prior art is prepared on the substrate, while the AlN nucleation layer prepared by the MOCVD method used in the present application is prepared on the surface of the h-BN layer, which has the characteristics of high crystal quality and high temperature resistance. The AlN nucleation layer prepared by this method does not need to use the BN-graphene composite layer to protect the AlN layer as in the prior art. At the same time, the main role of the AlN nucleation layer is to promote the further island growth of the GaN layer, which plays a nucleation role, which is different from the lattice correction purpose of the AlN layer in the prior art. In addition, the direct use of MOCVD epitaxy also reduces the process procedure. The entire epitaxial process is directly completed in the MOCVD, which can reduce the negative effects caused by transfer.

[0046] Specifically, in some embodiments, step 1) can specifically include the following steps:

[0047] At the first temperature and the first pressure, nitrogen gas is introduced into the reaction chamber to contact the substrate with the nitrogen gas, and the pre-nitridation treatment is performed.

[0048] In some embodiments, the first temperature is 900-1000°C, and the first pressure is 90-101 kPa.

[0049] In some embodiments, the pre-nitridation treatment is performed for 5-10 min.

[0050] In some embodiments, the thickness of the nitrided layer is 5-10 nm.

[0051] In some embodiments, the substrate includes any one of a sapphire substrate, a silicon carbide substrate, and a silicon substrate, and in some embodiments, the substrate is further preferably a silicon (111) substrate or a silicon (100) substrate.

[0052] Specifically, in some embodiments, step 2) can specifically include the following steps:

[0053] At the second temperature and the second pressure, a nitrogen source and a boron source are simultaneously introduced into the reaction chamber to perform a nucleation reaction to generate the first nucleation layer.

[0054] In some embodiments, the second temperature is 900-1000°C, and the second pressure is 10-20 kPa.

[0055] In some embodiments, the nucleation reaction is performed for 5-10 min.

[0056] In some embodiments, the first nucleation layer has a thickness of 2-5 nm.

[0057] In some embodiments, the boron source is mixed with a carrier gas before being introduced into the reaction chamber.

[0058] In some embodiments, the carrier gas contains hydrogen. For example, pure hydrogen, or a mixture of hydrogen and argon or other inert gas, etc., in which the proportion of hydrogen is, for example, 30% or more, etc.

[0059] In some embodiments, the boron source is introduced at a flow rate of 10-20 sccm, and the nitrogen source is introduced at a flow rate of 5-15 slm.

[0060] In some embodiments, the first annealing process in step 3) is performed at a temperature of 1200-1250°C for 10-20 min.

[0061] In some embodiments, step 4) can specifically include the following steps:

[0062] Alternately introducing a nitrogen source and a boron source into the reaction chamber at a third temperature and a third pressure to grow a hexagonal boron nitride layer.

[0063] In some embodiments, the third temperature is 1150-1300°C, and the third pressure is 5-15 kPa.

[0064] In some embodiments, the hexagonal boron nitride layer is grown for 2-8 min.

[0065] In some embodiments, the hexagonal boron nitride layer has a thickness of 1-10 nm.

[0066] In some embodiments, the boron source is introduced at a flow rate of 5-12 sccm, and the nitrogen source is introduced at a flow rate of 8-15 slm.

[0067] In some embodiments, in each cycle, the boron source is introduced for 2-4 s, and the nitrogen source is introduced for 5-8 s.

[0068] In some embodiments, the boron source includes any one or a combination of triethylboron and diborane.

[0069] In some embodiments, the nitrogen source includes ammonia.

[0070] The embodiment of the present application also provides a method for manufacturing a III-V epitaxial structure, comprising the following steps:

[0071] The hexagonal boron nitride layer is formed on the substrate by using the manufacturing method in any of the above embodiments.

[0072] A second nucleation layer is grown on the surface of the hexagonal boron nitride layer, and the second nucleation layer comprises a III-V compound.

[0073] The second nucleation layer is subjected to a second annealing treatment.

[0074] A III-V semiconductor layer is epitaxially grown on the surface of the second nucleation layer.

[0075] In some embodiments, the growing of the second nucleation layer can specifically comprise: contacting a III source and a V source with the surface of the hexagonal boron nitride layer, and growing the second nucleation layer.

[0076] In some embodiments, the III source comprises an aluminum source, and is preferably trimethylaluminum, and the V source comprises ammonia.

[0077] In some embodiments, the growing temperature of the second nucleation layer is 800-950 ℃, the growing time is 2-5 min, and the pressure is 8-15 kPa.

[0078] In some embodiments, the temperature of the second annealing treatment is 1150-1250 ℃, and the time is 10-25 min.

[0079] In some embodiments, the atmosphere of the second annealing treatment is a nitrogen atmosphere.

[0080] In some embodiments, the material of the III-V semiconductor layer comprises any one or a combination of two or more of aluminum nitride or gallium nitride.

[0081] In some embodiments, the manufacturing of the hexagonal boron nitride layer, the growing of the second nucleation layer, the second annealing treatment, and the epitaxial growing of the III-V semiconductor layer are all performed in the same vapor deposition growth chamber.

[0082] The embodiment of the present application also provides a III-V epitaxial structure manufactured by the manufacturing method in any of the above embodiments.

[0083] In some embodiments, the III-V epitaxial structure comprises, in sequence, a substrate, a first nucleation layer, a hexagonal boron nitride layer, a second nucleation layer, and a III-V semiconductor layer.

[0084] In some embodiments, the dislocation density of the III-V semiconductor layer is less than 9E10 8 / cm 2 And generally can guarantee in 3E10 18 / cm 2 Below.

[0085] As some typical application examples of the above technical solutions, the preparation of the above hexagonal boron nitride layer and the preparation process of the device based thereon can be as follows:

[0086] As Figure 1 shown, taking the epitaxy of GaN-HEMT on Si(100) substrate as an example:

[0087] S1, clean the Si(100) substrate:

[0088] Put the substrate into acetone solution first, ultrasonic clean the Si substrate for 3 min, then ultrasonic clean in isopropyl alcohol solution for 5 min, and then put it into ultrapure water for ultrasonic cleaning for 5 min, repeatedly wash with ultrapure water to remove residual acetone and isopropyl alcohol solution, and finally blow dry with nitrogen.

[0089] Of course, as for the cleaning of the substrate, other cleaning methods different from this can also be selected, which can achieve the purpose of cleaning the surface of the substrate, and other related methods are well known in the prior art, which will not be described here.

[0090] S2, high-temperature hydrogen removal of the substrate surface oxide layer:

[0091] Put the cleaned wafer into the MOCVD reaction chamber, raise the temperature to about 1100℃, and introduce H2 gas into the reaction chamber for 5 min, while also introducing a certain amount of SiH4 into the reaction chamber to prevent the substrate from having large gullies, and remove the surface oxide layer of the substrate.

[0092] Of course, as for the removal of the oxide layer, other reduction or etching methods different from this can also be selected, which can achieve the purpose of removing the surface oxide layer, and other related methods are well known in the prior art, which will not be described here.

[0093] S3, substrate pre-nitriding treatment:

[0094] After the above step, reduce the temperature of the reaction chamber to about 900-1000℃, while pre-introducing N2 into the reaction chamber to pre-nitride the substrate for 5 min, to obtain a surface nitride layer of about 5-10 nm.

[0095] S4, h-BN low-temperature buffer nucleation layer (i.e. the first nucleation layer, same below) epitaxy:

[0096] The temperature of the reaction chamber is maintained at about 900-1000℃, the pressure of the reaction chamber is reduced to 10kpa, triethylboron (TEB) is introduced into the reaction chamber at about 15sccm, ammonia (NH3) is introduced into the reaction chamber at about 10slm, the introduction time is 5min, the carrier gas is H2or a mixed gas containing H2, and an epitaxial h-BN low-temperature buffer layer of about 2-5nm is formed.

[0097] S5, annealing of the h-BN low-temperature buffer nucleation layer:

[0098] The introduction of TEB and NH3 into the reaction chamber is stopped, the flow rate of N2 in the reaction chamber is increased, and the temperature is increased to 1200℃ for annealing for 10min.

[0099] S6, epitaxy of h-BN film:

[0100] The temperature of the reaction chamber is maintained at 1200℃, TEB is introduced into the reaction chamber at 8sccm, and NH3 is introduced into the reaction chamber at 10slm, i.e. NH3 and TEB are alternately introduced into the reaction chamber for epitaxy of h-BN, the introduction time of each source is TEB 3s and NH3 6s, about 5min, and an h-BN film of about 1-10nm is epitaxied.

[0101] S7, epitaxy of low-temperature AlN nucleation layer (i.e. the second nucleation layer, same below):

[0102] The temperature of the reaction chamber is reduced to 950℃, TMAl and NH3 are introduced into the reaction chamber, and a 50nm low-temperature AlN nucleation layer is epitaxied.

[0103] S8, annealing of the low-temperature AlN nucleation layer:

[0104] TMAl and NH3 are turned off, N2 is introduced into the reaction chamber, the temperature of the reaction chamber is increased to 1200℃, and annealing is performed for 15min.

[0105] S9, epitaxial growth of semiconductor layer:

[0106] Further epitaxy of GaN-based or AlN-based device structure.

[0107] In the above embodiments, the present application utilizes the epitaxy of h-BN buffer layer on a substrate such as Si(100) to perform epitaxial growth of semiconductor layer. Since h-BN is a two-dimensional material, it can be used to shield the problem of lattice mismatch that causes the device structure of GaN and AlN to be unable to be epitaxied on a substrate such as Si(100), so that GaN and AlN-based devices can be directly epitaxied on a Si(100) substrate, thereby being compatible with the traditional process of Si(100) in the current integrated circuit, and avoiding the problem of yield reduction and cost increase caused by flip-chip bonding and other processes.

[0108] At present, the GaN hetero-epitaxy on sapphire substrate, SiC substrate and Si(111) substrate mainly solves the problem of large lattice mismatch between the substrate and GaN by introducing GaN or AlN nucleation layer, but this method still cannot completely eliminate the influence of the substrate on the quality of GaN material, and at present, there is no ideal technical means to solve the problem of single crystal GaN growth on Si(100) substrate due to the larger lattice mismatch between Si(100) substrate and GaN. The present application utilizes the two-dimensional characteristics of h-BN material, and the vertical direction has no dangling bond, which can effectively avoid the lattice mismatch in the GaN epitaxy process, and the influence of the substrate on the growth of GaN is shielded by inserting two-dimensional h-BN between the substrate and GaN, and then a high-quality GaN epitaxial layer is prepared.

[0109] The technical solutions of the present application are further described in detail below through several embodiments in combination with the drawings. However, the selected embodiments are only used to illustrate the present application, and do not limit the scope of the present application.

[0110] Embodiment 1

[0111] This embodiment example 1 is a preparation case of GaN-HEMT layer epitaxial on Si(100) substrate, as shown below:

[0112] S1, cleaning the Si(100) substrate:

[0113] The substrate is first placed in an acetone solution and ultrasonically cleaned for 3 min, then ultrasonically cleaned in an isopropanol solution for 5 min, and then placed in ultrapure water and ultrasonically cleaned for 5 min. The residual acetone and isopropanol solution is removed by repeatedly washing with ultrapure water, and finally dried with nitrogen.

[0114] S2, high-temperature hydrogen removal of the substrate surface oxide layer:

[0115] The cleaned wafer is placed in a MOCVD reaction chamber, the temperature is raised to 1100 DEG C, H2 gas is introduced into the reaction chamber at a flow rate of 20 slm, and a certain amount of SiH4 is also introduced into the reaction chamber at a flow rate of 15 sccm to prevent the substrate from having large gullies, and the substrate surface oxide layer is removed.

[0116] S3, substrate pre-nitridation treatment:

[0117] After the above step, the temperature of the reaction chamber is reduced to 950 DEG C (pressure 101 kpa), N2 is pre-introduced into the reaction chamber at a flow rate of 15 slm, and the substrate is pre-nitrided for 5 min to obtain a substrate surface nitride layer of about 7.5 nm.

[0118] S4, h-BN low-temperature buffer nucleation layer epitaxy:

[0119] The temperature of the reaction chamber was maintained at 950℃, the pressure of the reaction chamber was reduced to 10kpa, triethylboron (TEB) 15sccm and ammonia (NH3) 10slm were introduced into the reaction chamber for 5min, wherein H2 was used as the carrier gas, and an epitaxial h-BN low-temperature buffer layer about 5nm was formed.

[0120] S5, annealing of the h-BN low-temperature buffer nucleation layer:

[0121] TEB and NH3 were stopped from being introduced into the reaction chamber, the flow rate of N2 in the reaction chamber was increased to 10slm, the pressure was 10kpa, and the temperature was increased to 1200℃ for annealing for 10min.

[0122] S6, epitaxy of the h-BN film:

[0123] The temperature of the reaction chamber was maintained at 1200℃, TEB 8sccm and NH3 10slm were introduced into the reaction chamber in a pulse mode, that is, NH3 and TEB were alternately introduced into the reaction chamber for epitaxy of h-BN, the time for each source was TEB 3s and NH3 6s, the pressure was 10kpa, the total introduction time was 2min, and an h-BN film about 2nm thick was epitaxied. The surface morphology thereof is shown in FIG. 4. Figure 2 As can be seen from FIG. 4, the h-BN film formed has a uniform and delicate morphology, and has no obvious dislocation and grain boundary defects.

[0124] S7, epitaxy of the low-temperature AlN nucleation layer:

[0125] The temperature of the reaction chamber was reduced to 950℃, TMAl 700sccm and NH3 0.6slm were introduced into the reaction chamber, the pressure was 10kpa, and an AlN low-temperature nucleation layer 50nm thick was epitaxied.

[0126] S8, annealing of the low-temperature AlN nucleation layer:

[0127] TMAl and NH3 were turned off, N2 was introduced into the reaction chamber at a flow rate of 7slm, the pressure was 10kpa, the temperature of the reaction chamber was increased to 1200℃, and annealing was performed for 15min.

[0128] S9, epitaxial growth of the semiconductor layer:

[0129] The temperature of the reaction chamber was reduced to 1070℃, TMGa 40sccm and NH3 20slm were introduced into the reaction chamber, and a GaN semiconductor layer was further epitaxied.

[0130] The XRD rocking curves of the grown GaN semiconductor layer at (002) and (102) are shown in FIGS. 5 and 6, respectively. Figure 3a Figure 3b ​As shown, the GaN therein forms a good crystal. The dislocation density of the GaN semiconductor layer grown in this example was tested, and the result was 9E10 8 / cm 2 .

[0131] Example 2

[0132] This example continues the case of growing a GaN-HEMT layer on a Si (100) substrate as in Example 1, and is basically the same as Example 1, except that:

[0133] In step S3, the pre-nitridation temperature was 900°C, the pressure was 101 KPa, the nitrogen flow was 15 slm, and the time was 8 min, thereby growing a 10 nm nitride layer.

[0134] In step S4, the growth temperature of the h-BN low-temperature buffer nucleation layer was 950°C, the pressure was 10 KPa, the triethylboron (TEB) was 15 sccm, the ammonia (NH3) was 10 slm, and the time was 10 min, thereby growing a 5 nm thick h-BN low-temperature buffer nucleation layer.

[0135] In step S5, the first annealing temperature was 1150°C, the pressure was 10 KPa, and the annealing time was 10 min.

[0136] In step S6, the h-BN film epitaxial growth temperature was 1200°C, the pressure was 10 KPa, the flow was TEB 15 sccm and NH3 10 slm, the time for each source was TEB 3 s and NH3 6 s, and the growth time was 2 min, thereby preparing a 2 nm h-BN film.

[0137] In step S7, the low-temperature AlN nucleation layer epitaxial growth temperature was 890°C, the pressure was 10 KPa, the flow was TMAl 700 sccm and NH3 0.6 slm, and a 25 nm thick AlN low-temperature nucleation layer was epitaxially grown.

[0138] In step S8, the second annealing temperature was 1200°C, the pressure was 10 KPa, and the annealing time was 18 min.

[0139] The dislocation density of the GaN semiconductor layer grown in this example was tested, and the result was 3*10 18 / cm 2 .

[0140] Example 3

[0141] This embodiment continues the preparation of GaN-HEMT layer on Si(100) substrate in Example 1, which is basically the same as Example 1, with the only difference being that:

[0142] In step S3, the pre-nitridation temperature is 1000℃, the pressure is 101KPa, the nitrogen flow is 15slm, and the time is 8min, and then a 10nm nitride layer is formed.

[0143] In step S4, the growth temperature of the h-BN low-temperature buffer nucleation layer is 1000℃, the pressure is 10KPa, the triethylboron (TEB) is 15sccm, the ammonia (NH3) is 10slm, and the flow time is 10min, and then a 5nm thick h-BN low-temperature buffer nucleation layer is grown.

[0144] In step S5, the first annealing temperature is 1250℃, the pressure is 10KPa, and the annealing time is 10min.

[0145] In step S6, the h-BN thin film epitaxial growth temperature is 1250℃, the pressure is 10KPa, the flow rate is TEB 15sccm and NH3 10slm, the source is introduced separately each time, the time is TEB 3s and NH3 6s, and the growth time is 2min, and then a 2nm h-BN thin film is prepared.

[0146] In step S7, the epitaxial growth temperature of the low-temperature AlN nucleation layer is 870℃, the pressure is 10KPa, the flow rate is TMAl 700sccm and NH3 0.6slm, and an AlN low-temperature nucleation layer with a thickness of 25nm is epitaxially grown.

[0147] In step S8, the second annealing temperature is 1250℃, the pressure is 10KPa, and the annealing time is 18min.

[0148] The dislocation density of the GaN semiconductor layer grown in this embodiment was tested, and the result was 9*10 8 / cm 2 .

[0149] Example 4

[0150] This embodiment continues the preparation of GaN-HEMT layer on Si(111) substrate in Example 1, which is basically the same as Example 1, with the only difference being that:

[0151] The substrate is replaced with a Si(111) substrate, and the rest of the steps and reaction conditions and reaction materials remain unchanged.

[0152] The dislocation density of the GaN semiconductor layer grown in this embodiment was tested, and the result was 3*10 8 / cm2 .

[0153] Example 5

[0154] This example continues the case of Example 1 of the preparation of a GaN-HEMT layer epitaxially grown on a silicon carbide substrate, and is generally the same as Example 1, except that:

[0155] The substrate is replaced with a silicon carbide substrate, and the remaining steps and reaction conditions and reaction materials are unchanged.

[0156] The GaN semiconductor layer grown in this example was tested for dislocation density, and the result was 1*10 18 / cm 2 .

[0157] Example 6

[0158] This example continues the case of Example 1 of the preparation of a GaN-HEMT layer epitaxially grown on a sapphire substrate, and is generally the same as Example 1, except that:

[0159] The substrate is replaced with a sapphire substrate, and the remaining steps and reaction conditions and reaction materials are unchanged.

[0160] The GaN semiconductor layer grown in this example was tested for dislocation density, and the result was 1*10 18 / cm 2 .

[0161] Example 7

[0162] This example continues the case of Example 1 of the preparation of an AlN layer epitaxially grown on a Si(111) substrate, and is generally the same as Example 1, except that:

[0163] In step S9, the gallium source is replaced with an aluminum source, triethylaluminum, and the remaining steps and reaction conditions are unchanged.

[0164] The AlN semiconductor layer grown in this example was tested for dislocation density, and the result was 9E10 8 / cm 2 .

[0165] Comparative Example 1

[0166] This comparative example illustrates the case of Example 1 of the preparation of a GaN-HEMT layer epitaxially grown on a Si(100) substrate, and is generally the same as Example 1, except that:

[0167] Steps S3-S6 are omitted, and instead, steps S7-S9 are used to directly grow a second nucleation layer, anneal, and epitaxially grow a semiconductor layer on the surface of the substrate after cleaning and removal of the oxide layer, with the growth conditions and materials unchanged.

[0168] In this embodiment, since the effect of hexagonal boron nitride is missing, there is a large mismatch between the substrate and gallium nitride, and the growth quality of the gallium nitride semiconductor layer is very poor. The GaN semiconductor layer grown in this comparative example is significantly inferior to that of Example 1.

[0169] Comparative Example 2

[0170] The preparation of a GaN-HEMT layer epitaxially grown on a Si(100) substrate in this comparative example is basically the same as that of Example 1, except that:

[0171] Step S3 is omitted, and instead, steps S4-S9 are directly performed on the substrate surface after cleaning and removing the oxide layer, and the same subsequent growth of each layer and annealing treatment are performed.

[0172] In this embodiment, since the effect of the nitride layer is missing, the growth quality of the boron nitride layer is very poor, which further leads to poor film quality of each layer epitaxially grown subsequently. The dislocation density of the GaN semiconductor layer grown in this comparative example is tested, and the result is about 10 20 / cm 2 , which is significantly larger than that of Example 1.

[0173] Comparative Example 3

[0174] The preparation of a GaN-HEMT layer epitaxially grown on a Si(100) substrate in this comparative example is basically the same as that of Example 1, except that:

[0175] In step S6, the alternating introduction of boron source and nitrogen source is replaced by simultaneous introduction of boron source and nitrogen source, and the total amount of each source introduced and the total time of introduction remain unchanged.

[0176] In this embodiment, since the alternating introduction is not performed, the boron nitride layer has poor quality and a rough surface, and single-crystal gallium nitride cannot be epitaxially grown

[0177] Comparative Example 4

[0178] The preparation of a GaN-HEMT layer epitaxially grown on a Si(100) substrate in this comparative example is basically the same as that of Example 1, except that:

[0179] Steps S7-S8 are omitted, and gallium nitride is directly grown on the surface of hexagonal boron nitride, and the growth conditions and raw materials of the gallium nitride layer remain unchanged.

[0180] In this embodiment, since there is no AlN nucleation layer to promote further island growth of the GaN layer, it plays a nucleation role, and thus the growth quality of the GaN layer is still greatly affected by the hexagonal boron nitride. Single-crystal gallium nitride cannot be epitaxially grown, which is significantly inferior to Example 1.

[0181] Based on the above examples and comparative examples, it can be clear that the preparation method of the hexagonal boron nitride layer provided by the embodiments of the present application can directly grow and form a hexagonal boron nitride layer on the surface of a non-copper substrate through pre-nitridation and the formation of a first nucleation layer, especially can form a hexagonal boron nitride layer on the surface of a substrate such as silicon (100) with a larger lattice mismatch, and does not need to perform a stripping bonding process of the hexagonal boron nitride layer, thereby improving the quality of the epitaxial growth based on the hexagonal boron nitride layer and significantly reducing the process complexity.

[0182] In addition, the manufacturing method of the III-V group epitaxial structure based on the above hexagonal boron nitride layer provided by the embodiments of the present application does not need a stripping bonding process and a specific copper substrate, the dislocation density of the formed III-V group epitaxial layer is low, and the performance is excellent.

[0183] It should be understood that the above examples are only for illustrating the technical concepts and characteristics of the present application, and the purpose is to enable those skilled in the art to understand the content of the present application and to implement it, and cannot limit the protection scope of the present application. Any equivalent changes or modifications made according to the spirit and principle of the present application should be covered within the protection scope of the present application.

Claims

1. A method for fabricating a group III-V epitaxial structure, characterized in that, include: 1) The substrate is pre-nitrided to form a nitrided layer on the substrate surface, wherein the substrate is selected from Si (100) substrate; 2) The nitrided layer is brought into contact with a nitrogen source and a boron source to form a first nucleation layer containing hexagonal boron nitride on the surface of the nitrided layer; 3) Perform a first annealing treatment on the first nucleation layer; 4) The first nucleation layer is alternately contacted with a nitrogen source and a boron source to grow hexagonal boron nitride and obtain a hexagonal boron nitride layer; 5) A second nucleation layer is grown on the surface of the hexagonal boron nitride layer, the second nucleation layer comprising a group III-V compound; 6) Perform a second annealing treatment on the second nucleation layer; 7) Epitaxially grow a group III-V semiconductor layer on the surface of the second nucleation layer.

2. The manufacturing method according to claim 1, characterized in that, Step 1) specifically includes: Nitrogen gas is introduced into the reaction chamber at a first temperature and a first pressure to bring the substrate into contact with the nitrogen gas for the pre-nitriding treatment. The first temperature is 900-1000°C, the first pressure is 90-101 kPa, the pre-nitriding treatment time is 5-10 min, and the thickness of the nitrided layer is 5-10 nm.

3. The manufacturing method according to claim 2, characterized in that, Step 2) specifically includes: Under a second temperature and a second pressure, a nitrogen source and a boron source are simultaneously introduced into the reaction chamber to carry out a nucleation reaction and generate the first nucleation layer. The second temperature is 900-1000℃, the second pressure is 10-20kPa, the nucleation reaction time is 5-10min, and the thickness of the first nucleation layer is 2-5nm.

4. The manufacturing method according to claim 3, characterized in that, The boron source is mixed with the carrier gas and enters the reaction chamber. The carrier gas contains hydrogen. In step 2), the flow rate of the boron source is 10-20 sccm and the flow rate of the nitrogen source is 5-15 slm. In step 3), the temperature of the first annealing treatment is 1200-1250℃ and the time is 10-20 min.

5. The manufacturing method according to claim 2, characterized in that, Step 4) specifically includes: Under a third temperature and a third pressure, nitrogen and boron sources are alternately introduced into the reaction chamber to grow hexagonal boron nitride. The third temperature is 1150-1300℃, the third pressure is 5-15kPa, the growth time of the hexagonal boron nitride layer is 2-8min, and the thickness of the hexagonal boron nitride layer is 1-10nm. In step 4), the flow rate of the boron source is 5-12 sccm and the flow rate of the nitrogen source is 8-15 slm. In each cycle, the boron source is introduced for 2-4 s and the nitrogen source is introduced for 5-8 s.

6. The manufacturing method according to claim 5, characterized in that, The boron source includes any one or a combination of two of triethylborane and diborane, and the nitrogen source includes ammonia.

7. The manufacturing method according to claim 1, characterized in that, include: The group III source and the group V source are brought into contact with the surface of the hexagonal boron nitride layer to grow the second nucleation layer. The group III source includes an aluminum source, which is trimethylaluminum. The group V source includes ammonia. The growth temperature of the second nucleation layer is 800-950℃, the growth time is 2-5 min, and the pressure is 8-15 kPa.

8. The manufacturing method according to claim 1, characterized in that, The second annealing treatment is performed at a temperature of 1150-1250℃ for 10-25 minutes, and the atmosphere for the second annealing treatment is a nitrogen atmosphere. The material of the III-V semiconductor layer includes any one or a combination of two of aluminum nitride and gallium nitride.

9. The manufacturing method according to claim 1, characterized in that, The preparation of the hexagonal boron nitride layer, the growth of the second nucleation layer, the second annealing treatment, and the epitaxial growth of the III-V group semiconductor layer are all performed in the same vapor deposition growth chamber.

10. The III-V group epitaxial structure prepared by the method according to any one of claims 1-9 is characterized in that, The group III-V epitaxial structure comprises a substrate, a first nucleation layer, a hexagonal boron nitride layer, a second nucleation layer, and a group III-V semiconductor layer stacked sequentially, wherein the dislocation density of the group III-V semiconductor layer is less than 9 × 10⁻⁶. 8 / cm 2 .

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