Circuit structure and switching method for realizing MCU low-power power management

Abstract

The present invention relates to a circuit structure for implementing low-power power management of an MCU, wherein the circuit structure comprises: a first low-voltage difference linear regulator unit (LDOA), which is used to start the circuit and operate after receiving a high-level signal sent by an external digital logic unit (logic), and output a large current to enable the circuit structure to enter a high-performance mode; and a second low-voltage difference linear regulator unit (LDOB), which is used to start the circuit and operate after receiving a low-level signal sent by an external digital logic unit (logic), and output a low current to enable the circuit structure to enter an ultra-low power mode. The present invention also relates to a corresponding switching method. The circuit structure and switching method for implementing low-power power management of an MCU of the present invention are simple in structure, require fewer circuit components, save chip area, and the switching process is simple and easy to implement, which can effectively improve the chip yield.

Description

Technical Field

[0001] The present invention relates to the field of electronic technology, in particular to the field of power management technology, and specifically to a circuit structure and a switching method thereof for realizing low-power power management of an MCU. Background Art

[0002] Achieving high performance and low power consumption has always been a challenge in MCU (microcontroller unit) design. This is especially true as MCU circuits grow larger and larger, making power consumption an increasingly prominent issue. Low-power design has become both a hot topic and a challenge in MCU design. Implementing low-power MCU design not only significantly increases device life in battery-powered applications, but also reduces MCU operating temperatures, extending the device's lifespan.

[0003] In existing MCU designs, most use low-power mode to reduce the power consumption current when the MCU is in sleep mode. Specifically, the MCU's operating frequency is switched to low-frequency mode when the device has few or no tasks, and some digital modules are turned off at the same time to reduce the power consumption current when the MCU is in standby mode. However, this method still has the defect of high power consumption and cannot meet the more demanding ultra-low power requirements. In addition, the mode switching process is complicated. Therefore, there is an urgent need to find a circuit structure and switching method that can achieve low-power power management of MCU. Summary of the Invention

[0004] The purpose of the present invention is to overcome the shortcomings of the above-mentioned prior art and provide a circuit structure and switching method thereof for realizing low-power power management of MCU with simple structure and low power consumption.

[0005] In order to achieve the above-mentioned object, the circuit structure and switching method for realizing MCU low-power power management of the present invention are as follows:

[0006] The circuit structure for implementing MCU low-power management has the following main features:

[0007] a first low voltage difference linear voltage regulator unit, configured to start the circuit and operate after receiving a high level signal sent by an external digital logic unit, and output a large current so that the circuit structure enters a high performance mode; and

[0008] A second low voltage difference linear voltage regulator unit is used to start the circuit to work after receiving a low level signal sent by the external digital logic unit, and output a low current so that the circuit structure enters an ultra-low power consumption mode;

[0009] The output end of the first low voltage difference linear voltage regulator unit and the output end of the second low voltage difference linear voltage regulator unit are both connected to the back-end digital circuit, which is used to control the light load and / or heavy load working state of the digital circuit.

[0010] Preferably, it further comprises a central processing unit, wherein the central processing unit comprises the external digital logic unit, wherein:

[0011] The first enable input terminal of the external digital logic unit is used to input a low power mode signal;

[0012] The second enable input terminal of the external digital logic unit is used to input a linear voltage regulation signal;

[0013] The first enable output terminal of the external digital logic unit is used to input a first logic control signal to the second low voltage difference linear voltage regulator unit through the central processing unit;

[0014] The second enable output terminal of the external digital logic unit is used to input a second logic control signal to the first low voltage difference linear voltage regulator unit through the central processing unit.

[0015] Preferably, the first low voltage difference linear voltage stabilizing unit specifically includes:

[0016] an operational amplifier, wherein a first terminal of the operational amplifier is used to receive a first reference voltage output by a bandgap reference circuit;

[0017] a third PMOS field-effect transistor, wherein the gate of the third PMOS field-effect transistor is connected to the output terminal of the operational amplifier, and the drain of the third PMOS field-effect transistor is used to access the power supply voltage;

[0018] a first adjustable resistor and a second resistor;

[0019] The second resistor is connected between the second terminal of the operational amplifier and the source of the third PMOS field effect transistor;

[0020] The first adjustable resistor is connected between the second resistor and the ground.

[0021] Preferably, the circuit structure is further provided with a control signal, and the control signal is used to set the resistance value of the first adjustable resistor.

[0022] Preferably, the second low voltage difference linear voltage stabilizing unit specifically includes:

[0023] a first PMOS field effect transistor, wherein a gate of the first PMOS field effect transistor is used to receive the first logic control signal, and a drain of the first PMOS field effect transistor is used to output a bias current;

[0024] a second PMOS field effect transistor, wherein the gate of the second PMOS field effect transistor is grounded, and the drain of the second PMOS field effect transistor is used to access a power supply voltage;

[0025] a second NMOS field effect transistor, wherein the gate and the drain of the second NMOS field effect transistor are both connected to the source of the first PMOS field effect transistor;

[0026] a first NMOS field effect transistor, wherein the gate and the drain of the first NMOS field effect transistor are both connected to the source of the second NMOS field effect transistor; and

[0027] a third NMOS field effect transistor, wherein the drain of the third NMOS field effect transistor is connected to the source of the second PMOS field effect transistor, the gate of the third NMOS field effect transistor is connected to the gate and drain of the second NMOS field effect transistor, and the source of the third NMOS field effect transistor is connected between the third PMOS field effect transistor and the second resistor.

[0028] Preferably, the resistance of the first adjustable resistor is adjusted by the control signal so that the second low voltage difference linear voltage stabilization unit outputs the required low power consumption voltage driving current.

[0029] The method for realizing low-power switching of a dual LDO structure using the above circuit structure is mainly characterized in that the method comprises the following steps:

[0030] (1) The chip enters the first working cycle, the circuit structure is in the high-performance mode, and the first low-voltage difference linear regulator unit and the second low-voltage difference linear regulator unit perform circuit processing in this mode;

[0031] (2) determining whether the microcontroller unit receives a low power mode switching command sent from the outside, if yes, proceeding to step (3), otherwise, continuing the processing of step (1);

[0032] (3) The microcontroller unit issues a low power switching command;

[0033] (4) The chip enters the second working cycle, and the second low voltage difference linear voltage regulator unit enters the ultra-low power consumption mode according to the received low power consumption command and executes the circuit processing in this mode.

[0034] Preferably, the step (1) specifically includes the following steps:

[0035] (1.1) The microcontroller unit sets the low power mode signal to an off state and sets the linear voltage regulation signal to an on state;

[0036] (1.2) After being processed by the external digital logic unit, the first logic control signal outputs a low-level signal, and the second logic control signal outputs a high-level signal;

[0037] (1.3) The operational amplifier receives the high-level signal output by the second logic control signal, and the first low-voltage difference linear voltage regulator unit starts to work;

[0038] (1.4) The first PMOS field effect transistor receives the low level signal output by the first logic control signal, and the second low voltage difference linear voltage regulator unit starts to work.

[0039] Preferably, the step (4) specifically includes the following steps:

[0040] (4.1) The second low-voltage-dropout linear regulator unit receives a low-power-consumption command sent by the microcontroller unit;

[0041] (4.2) The microcontroller unit sets the low power command to a low level and turns off the large load circuit that does not maintain the basic functions of the chip, and then enters the delay state;

[0042] (4.3) After the delay ends, the micro control unit sets the low power mode signal and the linear voltage regulation signal to the on state;

[0043] (4.4) After being processed by the external digital logic unit, the first logic control signal outputs a low-level signal, and the second logic control signal outputs a low-level signal;

[0044] (4.5) After the operational amplifier receives the low-level signal output by the second logic control signal, the first low-voltage difference linear regulator unit turns off the circuit;

[0045] (4.6) The first PMOS field effect transistor receives the low level signal output by the first logic control signal, and the second low voltage difference linear voltage regulator unit continues to maintain the working state.

[0046] Preferably, the driving current output by the first low voltage difference linear voltage regulator unit and the second low voltage difference linear voltage regulator unit is at the uA level, so that the circuit structure meets the requirement of ultra-low power consumption.

[0047] The circuit structure and switching method for implementing low-power MCU power management employ the present invention. When the circuit operating frequency decreases and enters low-power mode, a low-power LDO structure is used to further reduce power consumption. The low-power LDO structure is simple and easy to implement, requires few additional circuit components, and does not require additional bias voltages. Only five MOS transistors are required, and integration within the chip significantly reduces chip area. The new low-power LDO structure can operate simultaneously with a high-performance LDO without interfering with each other. Compared to existing technologies, the switching process is simpler and easier to implement, effectively improving chip yield. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] Figure 1 The figure is a schematic diagram of the circuit structure for realizing low-power consumption power management of MCU according to the present invention.

[0049] Figure 2 Schematic diagram of the method for realizing low power consumption switching of dual LDO structure of the present invention.

[0050] Figure 3 This is a timing diagram of low-power switching of the dual LDO structure of the present invention.

[0051] Reference numerals

[0052] LDOA first low dropout linear regulator unit

[0053] LDOB Second low dropout linear regulator unit

[0054] logic digital logic unit

[0055] CPU Central Processing Unit

[0056] STANDBY_ENH low power mode signal

[0057] LDO15_PDN linear regulated signal

[0058] PDN first logic control signal

[0059] STANDBY second logic control signal

[0060] AMP Operational Amplifier

[0061] BGR Bandgap Reference Circuit

[0062] VBG first reference voltage

[0063] VDDD50 supply voltage

[0064] mp1 first PMOS field effect transistor

[0065] mp2 second PMOS field effect tube

[0066] mp3 The third PMOS field effect tube

[0067] mn1 The first NMOS field effect transistor

[0068] mn2 Second NMOS field effect transistor

[0069] Native_mn3 The third NMOS field effect transistor

[0070] R1 first adjustable resistor

[0071] R2 Second resistor

[0072] LDO15_TRIM<4:0> control signal

[0073] MCU Microcontroller Unit

[0074] ENZ low power command

[0075] STANDBY_ENH low power mode signal DETAILED DESCRIPTION

[0076] In order to more clearly describe the technical content of the present invention, further description is given below in conjunction with specific embodiments.

[0077] Before describing in detail embodiments according to the present invention, it should be noted that, hereinafter, relational terms such as first and second are used merely to distinguish one entity or action from another entity or action, and do not necessarily require or imply any actual such relationship or order between such entities or actions. The terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, whereby a process, method, article, or apparatus comprising a list of elements includes not only those elements, but also other elements not expressly listed or inherent to such process, method, article, or apparatus.

[0078] See also Figure 1 As shown, the circuit structure for implementing MCU low-power power management, wherein the circuit structure includes:

[0079] a first low-dropout linear voltage regulator unit LDOA, configured to start the circuit and operate after receiving a high-level signal from an external digital logic unit Logic, and output a large current so that the circuit structure enters a high-performance mode; and

[0080] The second low-dropout linear voltage regulator unit LDOB is used to start the circuit and work after receiving a low-level signal sent by the external digital logic unit logic, outputting a low current so that the circuit structure enters an ultra-low power consumption mode;

[0081] The output end of the first low voltage difference linear regulator unit LDOA and the output end of the second low voltage difference linear regulator unit LDOB are both connected to the back-end digital circuit, which is used to control the small load and / or large load working state of the digital circuit.

[0082] As a preferred embodiment of the present invention, it also includes a central processing unit CPU, and the central processing unit CPU includes the external digital logic unit logic, wherein,

[0083] The first enable input terminal of the external digital logic unit logic is used to input the low power mode signal STANDBY_ENH;

[0084] The second enable input terminal of the external digital logic unit logic is used to input the linear voltage regulation signal LDO15_PDN;

[0085] The first enable output terminal of the external digital logic unit Logic is used to input a first logic control signal PDN to the second low voltage difference linear regulator unit LDOB through the central processing unit CPU;

[0086] The second enable output terminal of the external digital logic unit Logic is used to input a second logic control signal STANDBY to the first low voltage difference linear voltage regulator unit LDOA through the central processing unit CPU.

[0087] As a preferred embodiment of the present invention, the first low-dropout linear voltage regulator unit LDOA specifically includes:

[0088] An operational amplifier AMP, wherein a first terminal of the operational amplifier AMP is used to receive a first reference voltage VBG output by a bandgap reference circuit BGR;

[0089] a third PMOS field effect transistor mp3, wherein the gate of the third PMOS field effect transistor mp3 is connected to the output end of the operational amplifier AMP, and the drain of the third PMOS field effect transistor mp3 is used to access the power supply voltage VDDD50;

[0090] A first adjustable resistor R1 and a second resistor R2;

[0091] The second resistor R2 is connected between the second terminal of the operational amplifier AMP and the source of the third PMOS field effect transistor mp3;

[0092] The first adjustable resistor R1 is connected between the second resistor R2 and the ground.

[0093] In practical applications, LDOA consists of an operational amplifier AMP, a MOS transistor mp3, and resistors R2 and R1. R1 is an adjustable resistor. By setting LDO15_TRIM<4:0>, the resistance value can be set to change the output voltage of VDDD15. AMP can be turned on by a high level on the signal line STANDBY. In addition, LDOA requires a bias voltage VBG, which is generally generated by a bandgap reference circuit BRG. Figure 1 The working principle of LDOA is that under the feedback of the operational amplifier AMP, Vp=VBG=V bias , so the voltage at VDDD15 is:

[0094] VDDD15=V bias ×(R2+R1) / R1;

[0095] By adjusting the resistance of R2 and R1, the voltage of VDDD15 can be adjusted to 1.5V.

[0096] As a preferred embodiment of the present invention, the circuit structure is further provided with a control signal LDO15_TRIM<4:0>, and the control signal LDO15_TRIM<4:0> is used to set the resistance value of the first adjustable resistor R1.

[0097] As a preferred embodiment of the present invention, the second low-dropout linear voltage regulator unit LDOB specifically includes:

[0098] a first PMOS field effect transistor mp1, wherein a gate of the first PMOS field effect transistor mp1 is used to receive the first logic control signal PDN, and a drain of the first PMOS field effect transistor mp1 is used to output a bias current IBIAS0;

[0099] a second PMOS field effect transistor mp2, wherein the gate of the second PMOS field effect transistor mp2 is grounded, and the drain of the second PMOS field effect transistor mp2 is used to access the power supply voltage VDDD50;

[0100] a second NMOS field effect transistor mn2, wherein the gate and drain of the second NMOS field effect transistor mn2 are both connected to the source of the first PMOS field effect transistor mp1;

[0101] a first NMOS field effect transistor mn1, wherein the gate and the drain of the first NMOS field effect transistor mn1 are both connected to the source of the second NMOS field effect transistor mn2; and

[0102] a third NMOS field-effect transistor Native_mn3, wherein the drain of the third NMOS field-effect transistor Native_mn3 is connected to the source of the second PMOS field-effect transistor mp2, the gate of the third NMOS field-effect transistor Native_mn3 is connected to the gate and drain of the second NMOS field-effect transistor mn2, and the source of the third NMOS field-effect transistor Native_mn3 is connected between the third PMOS field-effect transistor mp3 and the second resistor R2.

[0103] As a preferred embodiment of the present invention, the resistance of the first adjustable resistor R1 is adjusted by the control signal LDO15_TRIM<4:0> so that the second low-dropout linear regulator unit LDOB outputs the required low-power voltage drive current.

[0104] In practical applications, LDOB consists of two P-type MOS transistors mp1 and mp2 and three N-type MOS transistors mn1, mn2, and Native_mn3. Its operating principle is that under the bias current IBIAS0, mn1 and mn2 are connected in a diode configuration, generating a 1.5V voltage at point Vp. mn3 is a native transistor, normally open, with a 1.5V voltage at its source terminal (V15). LDOB requires a bias current, which is derived from a low-frequency oscillator. All MCU chips have a low-frequency oscillator, eliminating the need for additional bias circuitry, unlike LDOA structures that require a separate bandgap reference circuit. The LDOB circuit structure is very simple, requiring only a few basic components (resistors, capacitors, and MOS transistors). When integrated into the chip, it occupies a very small area, which translates to lower costs. The 1.5V voltage generated by this structure drives a current in the microamp range, resulting in low power consumption for the entire circuit, meeting ultra-low power requirements.

[0105] The method for implementing low-power switching of a dual LDO structure using the above-mentioned circuit structure includes the following steps:

[0106] (1) The chip enters the first working cycle, the circuit structure is in the high-performance mode, and the first low-voltage difference linear regulator unit LDOA and the second low-voltage difference linear regulator unit LDOB perform circuit processing in this mode;

[0107] (2) determining whether the microcontroller unit MCU receives a low power mode switching command sent from an external source, if so, proceeding to step (3), otherwise, continuing with the processing of step (1);

[0108] (3) The microcontroller unit MCU issues a low power switching command ENZ;

[0109] (4) The chip enters the second working cycle, and the second low voltage difference linear regulator unit LDOB enters the ultra-low power mode according to the received low power command ENZ and executes the circuit processing in this mode.

[0110] As a preferred embodiment of the present invention, the step (1) specifically includes the following steps:

[0111] (1.1) The microcontroller unit MCU sets the low power mode signal STANDBY_ENH to the off state and sets the linear voltage regulation signal LDO15_PDN to the on state;

[0112] (1.2) After being processed by the external digital logic unit Logic, the first logic control signal PDN outputs a low-level signal, and the second logic control signal STANDBY outputs a high-level signal;

[0113] (1.3) The operational amplifier AMP receives the high level signal output by the second logic control signal STANDBY, and the first low voltage difference linear regulator unit LDOA starts to work;

[0114] (1.4) The first PMOS field effect transistor mp1 receives the low level signal output by the first logic control signal PDN, and the second low voltage difference linear regulator unit LDOB starts to work.

[0115] As a preferred embodiment of the present invention, the step (4) specifically includes the following steps:

[0116] (4.1) The second low-dropout linear voltage regulator unit LDOB receives the low-power command ENZ sent by the microcontroller unit MCU;

[0117] (4.2) The microcontroller unit MCU sets the low power command ENZ to a low level, and turns off the large load circuit that does not maintain the basic functions of the chip, and then enters the delay state;

[0118] (4.3) After the delay ends, the microcontroller unit MCU sets the low power mode signal STANDBY_ENH and the linear voltage regulation signal LDO15_PDN to the on state;

[0119] (4.4) After being processed by the external digital logic unit Logic, the first logic control signal PDN outputs a low-level signal, and the second logic control signal STANDBY outputs a low-level signal;

[0120] (4.5) After the operational amplifier AMP receives the low-level signal output by the second logic control signal STANDBY, the first low-dropout linear voltage regulator unit LDOA turns off the circuit;

[0121] (4.6) The first PMOS field effect transistor mp1 receives the low level signal output by the first logic control signal PDN, and the second low voltage difference linear regulator unit LDOB continues to maintain the working state.

[0122] As a preferred embodiment of the present invention, the driving current output by the first low voltage difference linear regulator unit LDOA and the second low voltage difference linear regulator unit LDOB is at the uA level, so that the circuit structure meets the requirements of ultra-low power consumption.

[0123] In actual applications, when the MCU enters its first operating cycle and the chip is in high-performance mode, the digital circuitry requires high current. At this time, STANDBY_ENH = 0 and LDO15_PDN = 1. After processing by the digital logic, PDN outputs a low level, while STANDBY outputs a high level. The AMP receives this high level, turning on the circuit and LDOA, which begins operating and outputs a high current. mp1 is a P-type MOS transistor. Upon receiving a low level from PDN, it turns on, and the LDOB circuit also begins operating. Because the LDOA output current is larger than the LDOB current, LDOB's contribution to the VDDD15 supply current is minimal, so LDOB can be considered inoperative at this point.

[0124] In actual applications, when the MCU enters the second operating cycle and the chip enters ultra-low power mode, the MCU issues the ENZ command to shut down large load circuits that do not maintain the basic functions of the chip. After a delay (to ensure the smooth switching of the dual LDO structure, this delay time must be as long as possible), the MCU then sets STANDBY_ENH = 1 and LDO15_PDN = 1. After the digital unit logic processes, PDN outputs a low level, STANDBY outputs a low level, and the AMP shuts down the circuit after receiving the low level. Since PDN is still low, the LDOB circuit continues to operate, outputting a small current to ensure the chip's low power operation.

[0125] See also Figure 2As shown, in a specific embodiment of the present invention, during the low-power switching process, since LDOB can only output uA-level current, if the switch is made directly without considering the change in load, VDDD15 will be powered off and the chip will fail and reset. Therefore, a switching sequence is required when switching from normal operation to low-power mode. When the MCU receives the command to switch to low-power mode, the MCU will first issue a low-power command ENZ, setting ENZ to a low level. The large load circuit module of the digital circuit will be turned off immediately, but the small load circuit involved cannot be turned off immediately and requires a delay time. After the MCU delays for a period of time, there are only some small load circuit modules in the digital circuit that maintain the operation of the chip, which only require a very small current. Then the MCU pulls STANDBY to a low level, LDOA is turned off, and the MCU enters low-power mode.

[0126] As can be seen, the LDOB is always active in both normal and low-power modes, making the switching process very simple. When the MCU needs to resume normal operation, it only needs to turn on the LDOA first, wait for a period of stabilization, and then turn on all digital circuits.

[0127] See also Figure 3 As shown, in a specific embodiment of the present invention, the timing diagram of the low power switching of the dual LDO structure is as follows Figure 3 As shown:

[0128] When the circuit structure receives the low-power command ENZ issued by the MCU, it will be immediately placed in a low-level state, and then enter a delay state. During this process, the first logic control signal PDN always maintains a low-level state, that is, the second low-voltage difference linear voltage regulator unit LDOB is in a working state regardless of whether it is in normal working mode or low-power mode; and the second logic control signal STANDBY switches from the original high-level state to a low-level state after the same delay time, that is, the current circuit enters the low-power mode, and the first low-voltage difference linear voltage regulator unit LDOA stops working.

[0129] It's important to note that in a dual-LDO configuration, switching between the two LDOs must occur after the circuit is already in low-power mode and stable. This is beneficial because, since the drive current of LDOB is very low, the high-current-consuming modules in the digital circuit must be turned off before shutting down LDOA. Wait until the digital circuit is in sleep mode and stable before shutting down LDOA. Therefore, certain requirements must be placed on the switching timing of the two LDOs.

[0130] Any process or method description in a flowchart or otherwise described herein may be understood to represent a module, segment or portion of code comprising one or more executable instructions for implementing the steps of a specific logical function or process, and the scope of the preferred embodiments of the present invention includes alternative implementations in which functions may be performed out of the order shown or discussed, including performing functions in a substantially simultaneous manner or in the reverse order depending on the functions involved, which should be understood by those skilled in the art to which the embodiments of the present invention pertain.

[0131] It should be understood that each part of the present invention can be implemented by hardware, software, firmware or a combination thereof. In the above embodiments, multiple steps or methods can be implemented by software or firmware stored in a memory and executed by a suitable instruction execution device.

[0132] Those skilled in the art will understand that all or part of the steps of the method for implementing the above-mentioned embodiment can be completed by instructing the relevant hardware through a program, and the program can be stored in a computer-readable storage medium. When the program is executed, it includes one of the steps of the method embodiment or a combination thereof.

[0133] Furthermore, the functional units in the various embodiments of the present invention may be integrated into a single processing module, each unit may exist physically separately, or two or more units may be integrated into a single module. The aforementioned integrated modules may be implemented in the form of hardware or software functional modules. If the integrated modules are implemented in the form of software functional modules and sold or used as independent products, they may also be stored in a computer-readable storage medium.

[0134] The storage medium mentioned above can be a read-only memory, a magnetic disk or an optical disk, etc.

[0135] Throughout this specification, references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "embodiment" indicate that the specific features, structures, materials, or characteristics described in conjunction with that embodiment or example are included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

[0136] Although the embodiments of the present invention have been shown and described above, it will be understood that the above embodiments are illustrative and are not to be construed as limitations on the present invention. A person skilled in the art may change, modify, replace and modify the above embodiments within the scope of the present invention.

[0137] The circuit structure and switching method for implementing low-power MCU power management employ the present invention. When the circuit operating frequency decreases and enters low-power mode, a low-power LDO structure is used to further reduce power consumption. The low-power LDO structure is simple and easy to implement, requires few additional circuit components, and does not require additional bias voltages. Only five MOS transistors are required, and integration within the chip significantly reduces chip area. The new low-power LDO structure can operate simultaneously with a high-performance LDO without interfering with each other. Compared to existing technologies, the switching process is simpler and easier to implement, effectively improving chip yield.

[0138] In this specification, the present invention has been described with reference to specific embodiments thereof. However, it will be apparent that various modifications and variations may be made without departing from the spirit and scope of the present invention. Accordingly, the specification and drawings are to be regarded as illustrative rather than restrictive.

Claims

1. A circuit structure for realizing low-power power management of MCU, characterized in that: The circuit structure includes: a first low-dropout linear voltage regulator (LDOA) ​​configured to start the circuit and output a large current to enable the circuit structure to enter a high-performance mode after receiving a high-level signal from an external digital logic unit (logic); and a second low-dropout linear voltage regulator (LDOB) unit, configured to start the circuit and operate after receiving a low-level signal sent by an external digital logic unit (logic), outputting a low current so that the circuit structure enters an ultra-low power consumption mode; The output end of the first low-dropout linear voltage regulator unit (LDOA) ​​and the output end of the second low-dropout linear voltage regulator unit (LDOB) are both connected to the back-end digital circuit, for controlling the light-load and / or heavy-load working state of the digital circuit; It also includes a central processing unit (CPU), the central processing unit (CPU) includes the external digital logic unit (logic), wherein, The first enable input terminal of the external digital logic unit (logic) is used to input a low power mode signal (STANDBY_ENH); The second enable input terminal of the external digital logic unit (logic) is used to input a linear voltage regulation signal (LDO15_PDN); The first enable output terminal of the external digital logic unit (logic) is used to input a first logic control signal (PDN) to the second low-dropout linear voltage regulator unit (LDOB) through the central processing unit (CPU); The second enable output terminal of the external digital logic unit (logic) is used to input a second logic control signal (STANDBY) to the first low-dropout linear voltage regulator unit (LDOA) ​​through the central processing unit (CPU); The first low dropout voltage regulator unit (LDOA) ​​includes: an operational amplifier (AMP), wherein a first terminal of the operational amplifier (AMP) is configured to receive a first reference voltage (VBG) output by a bandgap reference circuit (BGR); a third PMOS field effect transistor (mp3), wherein a gate of the third PMOS field effect transistor (mp3) is connected to the output end of the operational amplifier (AMP), and a drain of the third PMOS field effect transistor (mp3) is used to access a power supply voltage (VDDD50); a first adjustable resistor (R1) and a second resistor (R2); The second resistor (R2) is arranged between the second end of the operational amplifier (AMP) and the source of the third PMOS field effect transistor (mp3); the first adjustable resistor (R1) is arranged between the second resistor (R2) and the ground; The second low-dropout linear voltage regulator unit (LDOB) includes: a first PMOS field effect transistor (mp1), wherein a gate of the first PMOS field effect transistor (mp1) is used to receive the first logic control signal (PDN), and a drain of the first PMOS field effect transistor (mp1) is used to output a bias current (IBIAS0); a second PMOS field effect transistor (mp2), wherein the gate of the second PMOS field effect transistor (mp2) is grounded, and the drain of the second PMOS field effect transistor (mp2) is used to access a power supply voltage (VDDD50); a second NMOS field effect transistor (mn2), wherein the gate and the drain of the second NMOS field effect transistor (mn2) are both connected to the source of the first PMOS field effect transistor (mp1); a first NMOS field effect transistor (mn1), wherein the gate and the drain of the first NMOS field effect transistor (mn1) are both connected to the source of the second NMOS field effect transistor (mn2); and a third NMOS field effect transistor (Native_mn3), wherein the drain of the third NMOS field effect transistor (Native_mn3) is connected to the source of the second PMOS field effect transistor (mp2), the gate of the third NMOS field effect transistor (Native_mn3) is connected to the gate and drain of the second NMOS field effect transistor (mn2), and the source of the third NMOS field effect transistor (Native_mn3) is arranged between the third PMOS field effect transistor (mp3) and the second resistor (R2).

2. The circuit structure for realizing low-power consumption power management of MCU according to claim 1, characterized in that: The circuit structure is further provided with a control signal (LDO15_TRIM<4:0>), and the control signal (LDO15_TRIM<4:0>) is used to set the resistance value of the first adjustable resistor (R1).

3. The circuit structure for realizing low-power consumption power management of MCU according to claim 2, characterized in that: The resistance of the first adjustable resistor (R1) is adjusted by the control signal (LDO15_TRIM<4:0>) so that the second low-dropout linear voltage regulator unit (LDOB) outputs the required low-power voltage driving current.

4. A method for realizing low-power switching of a dual LDO structure using the circuit structure according to any one of claims 1 to 3, characterized in that: The following steps are involved: (1) The chip enters the first working cycle, the circuit structure is in the high-performance mode, and the first low-dropout linear regulator unit (LDOA) ​​and the second low-dropout linear regulator unit (LDOB) perform circuit processing in this mode; (2) determining whether the microcontroller unit (MCU) receives a low power mode switching command sent from an external source, if so, proceeding to step (3); otherwise, continuing with step (1); (3) The microcontroller unit (MCU) issues a low power switching command (ENZ); (4) The chip enters the second working cycle, and the second low-dropout linear regulator unit (LDOB) enters the ultra-low power mode according to the received low-power command (ENZ) and executes circuit processing in this mode.

5. The method for realizing low power consumption switching of dual LDO structure according to claim 4, characterized in that: The step (1) comprises the following steps: (1.1) The microcontroller unit (MCU) sets the low power mode signal (STANDBY_ENH) to the off state and sets the linear voltage regulation signal (LDO15_PDN) to the on state; (1.2) After being processed by the external digital logic unit (logic), the first logic control signal (PDN) outputs a low-level signal, and the second logic control signal (STANDBY) outputs a high-level signal; (1.3) The operational amplifier (AMP) receives the high level signal output by the second logic control signal (STANDBY), and the first low-dropout linear voltage regulator unit (LDOA) ​​starts to operate; (1.4) The first PMOS field effect transistor (mp1) receives the low level signal output by the first logic control signal (PDN), and the second low voltage difference linear regulator unit (LDOB) starts to work.

6. The method for realizing low power consumption switching of dual LDO structure according to claim 5, characterized in that: The step (4) comprises the following steps: (4.1) The second low-dropout linear regulator unit (LDOB) receives a low-power command (ENZ) sent by the microcontroller unit (MCU); (4.2) The microcontroller unit (MCU) sets the low power command (ENZ) to a low level and turns off the large load circuits that are not required to maintain the basic functions of the chip, and then enters a delay state; (4.3) After the delay ends, the microcontroller unit (MCU) sets the low power mode signal (STANDBY_ENH) and the linear voltage regulation signal (LDO15_PDN) to the on state; (4.4) After being processed by the external digital logic unit (logic), the first logic control signal (PDN) outputs a low-level signal, and the second logic control signal (STANDBY) outputs a low-level signal; (4.5) After the operational amplifier (AMP) receives the low-level signal output by the second logic control signal (STANDBY), the first low-dropout linear regulator unit (LDOA) ​​turns off the circuit; (4.6) The first PMOS field effect transistor (mp1) receives the low level signal output by the first logic control signal (PDN), and the second low voltage difference linear regulator unit (LDOB) continues to maintain the working state.

7. The method for realizing low power consumption switching of dual LDO structure according to claim 4, characterized in that: The driving current output by the first low-voltage-dropout linear regulator unit (LDOA) ​​and the second low-voltage-dropout linear regulator unit (LDOB) is at the uA level, so that the circuit structure meets the requirements of ultra-low power consumption.

Images