Electronic device, method of determining memory access efficiency, and storage medium

Abstract

The present disclosure provides an electronic device, relates to the technical field of computers, and particularly relates to the technical field of chips, memories, processors, and the like. The device comprises a memory configured to store executable instructions and to-be-processed data, wherein the to-be-processed data is divided into a plurality of data blocks; and a processor configured to execute the executable instructions so as to: read a to-be-tested data block in the plurality of data blocks from the memory; determine memory access description information according to size information of the to-be-tested data block, wherein the memory access description information comprises read period information and a data read interval; and determine a memory access efficiency of the processor reading the to-be-tested data block according to the memory access description information and channel description information, wherein the channel description information describes a plurality of channels of the processor reading the to-be-processed data from the memory. The present disclosure also provides a storage medium for determining a memory access efficiency.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of computer technology, and more particularly to the technical field of chips, memories, and processors. More specifically, the present disclosure provides an electronic device, a method for determining memory access efficiency, and a storage medium. BACKGROUND

[0002] With the development of artificial intelligence technology and computer technology, an operator based on an artificial intelligence (AI) chip can be developed. In order to improve the performance of the operator, the hardware utilization rate of the operator can be improved. SUMMARY

[0003] The present disclosure provides an electronic device, a method for determining memory access efficiency, and a storage medium.

[0004] According to an aspect of the present disclosure, an electronic device is provided, the device comprising: a memory configured to store executable instructions and to-be-processed data, wherein the to-be-processed data is divided into a plurality of data blocks; and a processor configured to execute the executable instructions so as to: read a to-be-tested data block in the plurality of data blocks from the memory; determine access description information according to size information of the to-be-tested data block, wherein the access description information comprises read period information and a data read interval; and determine access efficiency of the processor reading the to-be-tested data block according to the access description information and channel description information, wherein the channel description information describes a plurality of channels of the processor reading the to-be-processed data from the memory.

[0005] According to another aspect of the present disclosure, a method for determining memory access efficiency is provided, the method comprising: reading a to-be-tested data block in a plurality of data blocks from a memory; determining access read description information according to a size of the to-be-tested data block, wherein the access description information comprises read period information and a data read interval; and determining access efficiency of reading the to-be-tested data block according to the access description information and channel description information, wherein the channel description information describes a plurality of channels of reading to-be-processed data from the memory.

[0006] According to another aspect of the present disclosure, an electronic device is provided, comprising: at least one processor; and a memory in communication connection with the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the method provided by the present disclosure.

[0007] According to another aspect of the present disclosure, a non-transitory computer readable storage medium having computer instructions stored therein is provided, the computer instructions being used to cause a computer to execute the method provided by the present disclosure.

[0008] According to another aspect of the present disclosure, there is provided a computer program product comprising a computer program which, when executed by a processor, implements the method provided by the present disclosure.

[0009] It should be understood that the matters described herein are intended to be illustrative rather than limiting. For example, while the application is illustrated and described in relation to a computer program product, the application is not limited to a computer program product. The application can be implemented in any suitable hardware, software, firmware, or combination thereof. The application can be implemented in one or more computer programs or code that can be executable, interpreted or compiled programs and can be implemented in the module or component level or in a higher level of abstraction. The application can be implemented in one or more modules or components. BRIEF DESCRIPTION OF DRAWINGS

[0010] The accompanying drawings are included to provide a further understanding of the application, and are incorporated in and constitute a part of this specification. Illustrations in the drawings are for purposes of illustrating an implementation of the application and are not intended to limit the application.

[0011] Figure 1 is a schematic diagram of an electronic device according to one embodiment of the present disclosure;

[0012] Figure 2A is a function image schematic diagram of a memory access description function according to one embodiment of the present disclosure;

[0013] Figure 2B is a schematic diagram of a periodic square wave according to one embodiment of the present disclosure;

[0014] Figure 2C is a schematic diagram of a data read interval according to one embodiment of the present disclosure;

[0015] Figure 3A is a distribution schematic diagram of a plurality of channels according to one embodiment of the present disclosure;

[0016] Figure 3B is a function image schematic diagram of a channel description function according to one embodiment of the present disclosure;

[0017] Figure 4A is a function image schematic diagram of an adjusted target channel description function according to one embodiment of the present disclosure.

[0018] Figure 4B is a schematic diagram of an adjusted periodic square wave according to one embodiment of the present disclosure;

[0019] Figure 4C is a schematic diagram of an adjusted data read interval according to one embodiment of the present disclosure

[0020] Figure 5 is a flowchart of a method for determining memory access efficiency according to one embodiment of the present disclosure; and

[0021] Figure 6 is a block diagram of an electronic device to which the method for determining memory access efficiency can be applied according to one embodiment of the present disclosure. DETAILED DESCRIPTION

[0022] Exemplary embodiments of the present disclosure are described herein below with reference to the accompanying drawings, in which various specific details are set forth to assist in a thorough understanding of these embodiments. It should be understood, however, that various changes and modifications can be made to the embodiments described herein, without departing from the scope and spirit of the present disclosure. Also, descriptions of well-known functions and constructions can be omitted for clarity and conciseness.

[0023] The memory-intensive operator can include a general matrix multiplication (GEMM) operator and a convolution (conv) operator. The bandwidth utilization of the memory by the memory-intensive operator can be improved to optimize the operator. In the case of limited internal cache, the data to be processed can be blocked. The memory access time of different matrix blocking methods can be determined before the operator is started. In some cases, channel conflicts can affect the overall memory access time of the data. For example, in the case of channel conflicts, the bandwidth efficiency can be the inverse of the number of channels (cn), i.e., 1 / cn.

[0024] In some embodiments, the way of blocking the data to be processed can be optimized so that each memory access falls on more channels as much as possible to effectively utilize the bandwidth of the multi-channel. However, in the case of limited internal cache, if the bandwidth of the read operation is increased, the bandwidth of the write operation can be reduced. If the memory efficiency of a specific memory width cannot be quantitatively evaluated, it is difficult to determine a better data blocking method.

[0025] In some embodiments, a specific data read offset (1d) can be processed. For example, the specific data read offset can be the product of the number of channels and the channel width (ig). When determining the blocking method, the bandwidth efficiency penalty can be increased for the specific data read offset, so that the final blocking method can utilize the bandwidth of the multi-channel as much as possible. However, if the difference between the data read offset and the specific data read offset is small, it is difficult to determine a suitable blocking method. In addition, if the data read offset is an integer multiple or 0.5 times the specific data read offset, it is also difficult to determine a suitable blocking method.

[0026] To improve data processing efficiency, the present disclosure provides an electronic device, which will be described below.

[0027] Figure 1 is a schematic diagram of an electronic device according to an embodiment of the present disclosure.

[0028] As shown in Figure 1 The electronic device 100 can include a memory 110 and a processor 120.

[0029] The memory 110 can be configured to store executable instructions and to-be-processed data.

[0030] In the embodiments of the present disclosure, the to-be-processed data can be divided into a plurality of data blocks. For example, the to-be-processed data can be divided into a plurality of data blocks in any block division manner.

[0031] In the embodiments of the present disclosure, the memory can be a double data rate synchronous dynamic random access memory (DDR) or a graphics double data rate (GDDR).

[0032] The processor 120 can be configured to execute the executable instructions to read a to-be-tested data block in the plurality of data blocks from the memory. The memory access description information is determined according to the size information of the to-be-tested data block. The memory access efficiency of the processor reading the to-be-tested data block is determined according to the memory access description information and the channel description information.

[0033] In the embodiments of the present disclosure, any data block in the plurality of data blocks can be taken as the to-be-tested data block.

[0034] In the embodiments of the present disclosure, the memory access description information can include read period information and data read range. For example, the to-be-tested data block can be implemented as a matrix. The size information of the to-be-tested data block can include the number of rows and the number of columns. The read period information can be determined according to the number of columns. The data read range can be determined according to the number of rows. In an example, the read period information can indicate that one row of data of the matrix is read in each read period. The row of data includes the number of column values. The data read range is related to all values of the matrix.

[0035] In the embodiments of the present disclosure, the channel description information describes a plurality of channels through which the processor reads the to-be-processed data from the memory. For example, the processor can read one or more data blocks of the to-be-processed data from the memory via the plurality of channels. The channel description information can describe the plurality of channels.

[0036] Through the embodiments of the present disclosure, the memory access description information is established, and the memory access efficiency is determined according to the memory access description information and the channel description information. Thus, in the case where the memory access efficiency is determined, if the memory access efficiency is low, the data block division manner can be adjusted to improve the memory access efficiency, which helps to improve the data processing capability of the electronic device.

[0037] It can be understood that the electronic device of the present disclosure is described above, and the memory access description information of the present disclosure will be further described below.

[0038] In some embodiments, the size information of the to-be-tested data block can include a data read offset, the number of rows, and the number of columns. The memory access description information can be determined according to the data read offset, the number of rows, and the number of columns. The memory access description information can be implemented as a memory access description function, which will be combined with the followingFigure 2A Further description will be made.

[0039] Figure 2A is a function image diagram of a memory access description function according to one embodiment of the present disclosure.

[0040] As Figure 2A shown, the memory access description function can be a periodic function, and the function period can be determined according to a data read offset. For example, the memory access description function x(t) can be:

[0041]

[0042] k can be an integer greater than or equal to 0 and less than or equal to row-1. row can be the number of rows. col can be the number of columns. ld can be the data read offset.

[0043] It can be understood that the memory access description function shown in Formula One can be regarded as the product of a periodic function and a data interval. For example, the periodic function can correspond to the read period information, and the data interval can correspond to the data read interval.

[0044] In some embodiments, the read period information can be characterized as a periodic square wave. Further description will be made below in conjunction with Figure 2B

[0045] Figure 2B is a diagram of a periodic square wave according to one embodiment of the present disclosure.

[0046] In the embodiments of the present disclosure, the effective width of the square wave can be the number of columns, and the period of the periodic square wave is determined according to the read offset. As Figure 2B shown, the read period function l(t) corresponding to the periodic square wave can be:

[0047]

[0048] In some embodiments, the data read interval can be determined according to the data read offset and the number of rows. Further description will be made below in conjunction with Figure 2C

[0049] Figure 2C is a diagram of a data read interval according to one embodiment of the present disclosure.

[0050] As Figure 2C shown, the first interval endpoint value corresponding to the data read interval can be 0, and the second interval endpoint value corresponding to the data read interval can be the product of the data read offset ld and the number of rows row, i.e., row*ld. For example, the function i(t) corresponding to the data read interval can be:

[0051] ​​

[0052] According to the embodiments of the present disclosure, the memory access description information is determined, the modeling of the memory access behavior is implemented, and the memory access efficiency is accurately and quantitatively determined.

[0053] It can be understood that the memory access description information of the present disclosure is described above, and the channel description information of the present disclosure will be described below. Figure 3A and Figure 3B The channel description information of the present disclosure is described.

[0054] Figure 3A is a distribution diagram of a plurality of channels according to an embodiment of the present disclosure.

[0055] As shown in Figure 3A , the number of channels can be cn, and the channel width of the channel can be ig.

[0056] In some embodiments, the channel description information can include the channel bandwidth of the channel. For example, the channel description information can be implemented as a channel description function. For a channel channel0 in the plurality of channels, the function image of the channel description function of the channel channel0 is as shown in Figure 3B .

[0057] Figure 3B is a function image diagram of a channel description function according to an embodiment of the present disclosure.

[0058] As shown in Figure 3B , the channel width of the channel channel_0 can also be ig. For example, the channel description function of the channel channel0 can be:

[0059]

[0060] k can be an integer greater than or equal to 0.

[0061] According to the embodiments of the present disclosure, the channel description information is determined, the modeling of the channel is implemented, and the memory access efficiency is accurately and quantitatively determined.

[0062] It can be understood that the channel description information and the memory access description information of the present disclosure are described above, and some ways of determining the memory access efficiency will be further described below.

[0063] In the embodiments of the present disclosure, the processor can be configured to determine the memory access time of any channel according to the integral result of the memory access description information and the channel description information, the number of channels, and a first preset parameter. The first preset parameter can be related to the bandwidth of the channel. For example, for the i-th channel in the cn channels, the memory access time ci t may be:

[0064]

[0065] The bw can be a first preset parameter. The c_i(t) can be a channel description function of the i-th channel. The i can be an integer greater than or equal to 0 and less than or equal to cn-1.

[0066] As described above, the memory access description information can include the read period information and the data read interval. In the embodiments of the present disclosure, the processor can also be configured to determine the memory access time of any channel according to the read period information, the integral value of the data read interval, the number of channels, and the first preset parameter. For example, for the i-th channel in the cn channels, the memory access time c_i can be determined according to the following formula seven: t Also can be:

[0067]

[0068] Through the embodiments of the present disclosure, the data read interval can be used as the integral interval, which is beneficial to determine the memory access time.

[0069] In some embodiments, the processor can also be configured to determine a target channel in the plurality of channels. In the embodiments of the present disclosure, in the case of reading the to-be-tested data block from the memory in parallel by using the plurality of channels, the target channel can be the channel with the largest data transmission load. For example, in the case of reading the to-be-tested data block from the memory in parallel by using the cn channels, if the data transmission load of the channel channel_0 is the largest, the channel channel_0 can be used as the target channel.

[0070] In some embodiments, the processor can also be configured to determine the target channel description information of the target channel. For example, in the case of the target channel being the channel channel_0, the channel description information of the channel channel_0 can be used as the target channel description information.

[0071] In some embodiments, the processor can also be configured to determine the memory access efficiency of the processor reading the to-be-tested data block according to the number of columns, the number of rows of the to-be-tested data block, the first preset parameter, and the target channel. For example, the memory access efficiency η can be determined by the following formula:

[0072]

[0073] max(c0 t , c1 t ... c{cn-1} t ) is a function of determining the target channel in the plurality of channels. In the case of the target channel being the channel channel_0, the formula seven can be converted into:

[0074]

[0075] Next, formula eight and formula six can be combined. That is, in the embodiments of the present disclosure, the processor can be further configured to determine the memory access efficiency of the processor reading the to-be-tested data block according to the integral value of the data read interval and the target channel description information. For example, the memory access efficiency of the processor reading the to-be-tested data block can be determined according to the number of channels, the size information of the to-be-tested data block and the integral value. If T = row * ld, the memory access efficiency can be determined by the following formula:

[0076]

[0077] As shown in formula nine, formula two and formula four, c_0(t) and l(t) can both be periodic functions. To determine the integral value, the correlation function can be converted to the frequency domain. The conversion method can include Fourier series expansion, Fourier transform, wavelet transform, etc. When Fourier series expansion is performed, if the correlation function is an even function, only cosine terms can exist in the overall series to reduce the operation cost. Thus, in the embodiments of the present disclosure, the processor can be configured to adjust the read period function, the target channel description function and the data read interval respectively to obtain an adjusted read period function, an adjusted target channel description function. The following will be described in detail in combination with Figures 4A to 4C .

[0078] Figure 4A is a function image schematic diagram of the adjusted target channel description function according to one embodiment of the present disclosure. As shown in Figure 4A , the target channel description function can be translated by 1 / 2 channel width along the horizontal axis direction to obtain the adjusted target channel function. The adjusted target channel function can be an even function.

[0079] Figure 4B is a schematic diagram of the adjusted periodic square wave according to one embodiment of the present disclosure. The read period function can be translated by 1 / 2 column data along the horizontal axis direction to obtain the adjusted read period function. The adjusted read period function can be an even function. The adjusted read period function can be characterized as the adjusted periodic square wave as shown in Figure 4B .

[0080] Figure 4C is a schematic diagram of the adjusted data read interval according to one embodiment of the present disclosure. As shown in Figure 4C , the data read interval can be translated by 1 / 2 of the product (row * ld) along the horizontal axis direction to obtain the adjusted data read interval.

[0081] Next, after adjusting the read period function, the target channel description function and the data read interval respectively, in the embodiments of the present disclosure, the processor can also be configured to: determine the memory access efficiency of the processor reading the to-be-tested data block according to the number of the plurality of channels, the size information of the to-be-tested data block, and the integral value of the adjusted data read interval according to the adjusted read period information and the adjusted target channel description information. For example, the memory access efficiency can be determined by the following formula:

[0082]

[0083] Next, the processor can be configured to: determine a plurality of first frequency domain components of the read period information and a plurality of second frequency domain components of the target channel description information. For example, the processor can also be configured to: perform Fourier series expansion on the read period information to obtain the plurality of first frequency domain components. Perform Fourier series expansion on the target channel description information to obtain the plurality of second frequency domain components.

[0084] For another example, if the function f(t) is an even function and a periodic function, the n-level Fourier expansion of the function f(t) can be:

[0085]

[0086] The period of the function f(t) can be Tf. ω can be a frequency corresponding to the period. n The nth-level expansion parameter can be an. n The frequency ω, the 0th-level expansion parameter a0, and the nth-level expansion parameter an can be respectively:

[0087]

[0088] a0=r (Formula Thirteen)

[0089]

[0090] r can be the duty cycle of the function f(t).

[0091] Therefore, the n c th Fourier expansion of the target channel description function c_0(t) can be:

[0092]

[0093] The period of the target channel description function c_0(t) can be cn*ig. ω c can be a frequency corresponding to the period. The nth-level expansion parameter can be an. c The frequency ω, the 0th-level expansion parameter a0, and the nth-level expansion parameter an can be respectively: ​

[0094]

[0095]

[0096]

[0097] The duty cycle corresponding to the target channel description function c 0 (t) can be described. It can be understood that the plurality of first frequency domain components can include n c first frequency domain components. The n c th first frequency domain component can be

[0098] In addition, the n l th Fourier expansion of the read cycle function l(t) can be:

[0099]

[0100] The period of the read cycle function l(t) can be ld. The frequency corresponding to the period can be ω l The n l th expansion parameter can be. The frequency ω l , the 0th expansion parameter al 0, and the n l th expansion parameter may be respectively:

[0101]

[0102]

[0103]

[0104] The duty cycle corresponding to the read cycle function l(t) can be described. It can be understood that the plurality of second frequency domain components can include n l second frequency domain components. The n l th second frequency domain component can be

[0105] After Fourier expansion of the read cycle information and the target channel description information respectively, a plurality of first frequency domain components and a plurality of second frequency domain components can be obtained. Next, in some embodiments, the processor can be configured to: determine the memory access efficiency of the processor reading the to-be-tested data block according to the plurality of first frequency domain components and the plurality of second frequency domain components.

[0106] For example, according to the plurality of first frequency domain components and the plurality of second frequency domain components, an integral value The integral value ​may be set as:

[0107]

[0108] For another example, an intermediate parameter p(n c , n l ) can be set as: c l may be set as:

[0109]

[0110] sinc( ) can be a sinc function.

[0111] Therefore, based on Equation Twenty-Three and Equation Twenty-Four, the integral value can be determined as:

[0112]

[0113] Next, the processor can determine the memory access efficiency according to the number of the plurality of channels, the size information of the data block to be measured, and the integral value. For example, the memory access efficiency can be determined according to Equation Twenty-Five and Equation Ten. In an example, n c may be 5, and n l may also be 5.

[0114] In the embodiments of the present disclosure, the memory access efficiency of the processor reading the data block to be measured can represent the data transmission load uniformity in the plurality of channels when the processor reads the data block to be measured from the memory in parallel via the plurality of channels. Through the embodiments of the present disclosure, the degree of conflict between the channels can be accurately determined when the size information (data read offset, number of columns, and number of rows) of the data block to be measured is determined. In addition, the memory access efficiency is determined according to the size information, which has good generalization ability, can adapt to data blocks of different sizes, and can accurately determine the memory access efficiency in the case of various values of the data read offset. Furthermore, the blocking manner can be adjusted to improve the memory access efficiency and reduce the channel conflict.

[0115] It can be understood that the electronic device of the present disclosure is described above, and the method for determining the memory access efficiency of the present disclosure will be described below.

[0116] Figure 5 is a flowchart of a method for determining the memory access efficiency according to an embodiment of the present disclosure.

[0117] As shown in Figure 5 , the method 500 can include operation S510 to operation S530.

[0118] In operation S510, a data block to be measured in a plurality of data blocks is read from a memory.​

[0119] In operation S520, memory access reading description information is determined according to the size of the data block to be measured.

[0120] In the embodiments of the present disclosure, the memory access description information includes reading period information and data reading interval.

[0121] In operation S530, memory access efficiency of reading the data block to be measured is determined according to the memory access description information and the channel description information.

[0122] In the embodiments of the present disclosure, the channel description information describes a plurality of channels for reading the data to be processed from the memory.

[0123] It can be understood that the method 500 can be executed by the processor 120 described above. It can also be understood that the method 500 can determine the memory access efficiency related to the memory 110.

[0124] In some embodiments, the data to be processed reading size information includes a data reading offset, a number of rows and a number of columns. The reading period information is characterized as a periodic square wave, and the effective width of the square wave is the number of columns. The period of the periodic square wave is determined according to the data reading offset. The data reading interval is determined according to the data reading offset and the number of rows.

[0125] In some embodiments, determining the memory access efficiency of the processor reading the data block to be measured according to the memory access description information and the channel description information includes: determining a target channel in the plurality of channels. For example, the target channel is the channel with the largest data transmission load in the case of reading the data block to be measured from the memory in parallel using the plurality of channels. The target channel description information of the target channel is determined. For example, the target channel description information includes the channel bandwidth of the target channel. The memory access efficiency of the processor reading the data block to be measured is determined according to the integral value of the data reading interval of the reading period information and the target channel description information.

[0126] In some embodiments, determining the memory access efficiency of the processor reading the data block to be measured according to the integral value of the data reading interval of the reading period information and the target channel description information includes: determining the memory access efficiency of the processor reading the data block to be measured according to the number of the plurality of channels, the size of the data block to be measured and the integral value.

[0127] In some embodiments, determining the memory access efficiency of the processor reading the data block to be measured according to the integral value of the data reading interval of the reading period information and the target channel description information includes: determining a plurality of first frequency domain components of the reading period information and a plurality of second frequency domain components of the target channel description information. The memory access efficiency of the processor reading the data block to be measured is determined according to the plurality of first frequency domain components and the plurality of second frequency domain components.

[0128] In some embodiments, determining the plurality of first frequency domain components of the read period information and determining the plurality of second frequency domain components of the target channel description information comprises: performing Fourier series expansion on the read period information to obtain the plurality of first frequency domain components; and performing Fourier series expansion on the target channel description information to obtain the plurality of second frequency domain components.

[0129] In some embodiments, the memory access efficiency of the processor reading the to-be-tested data block is used to represent: in the case that the processor reads the to-be-tested data block from the memory in parallel via the plurality of channels, data transmission load uniformity in the plurality of channels.

[0130] In the technical solutions of the present disclosure, the collection, storage, use, processing, transmission, provision and disclosure of user personal information involved in the technical solutions comply with relevant laws and regulations and do not violate public order and good customs.

[0131] According to embodiments of the present disclosure, the present disclosure further provides an electronic device, a readable storage medium and a computer program product.

[0132] Figure 6 A schematic block diagram of an example electronic device 600 that can be used to implement embodiments of the present disclosure is shown. The electronic device is intended to represent various forms of digital computers, such as laptops, desktops, tablets, personal digital assistants, servers, blade servers, mainframes, and other appropriate computers. The electronic device can also represent various forms of mobile devices, such as personal digital processors, cellular telephones, smart phones, wearable devices, and other similar computing devices. The components shown here, their connections and relationships, and their functions, are meant to be examples only, and are not meant to limit implementations of the present disclosure described and / or claimed in this document.

[0133] As shown in Figure 6 The device 600 includes a computing unit 601 that can perform various appropriate actions and processes in accordance with a computer program stored in a read-only memory (ROM) 602 or a computer program loaded from a storage unit 608 into a random access memory (RAM) 603. Various programs and data required for the operation of the device 600 can also be stored in the RAM 603. The computing unit 601, the ROM 602, and the RAM 603 are connected to each other through a bus 604. An input / output (I / O) interface 605 is also connected to the bus 604.

[0134] A number of components in the device 600 are connected to the I / O interface 605, including: an input unit 606, such as a keyboard, a mouse, etc.; an output unit 607, such as various types of displays, speakers, etc.; a storage unit 608, such as a magnetic disk, an optical disk, etc.; and a communication unit 609, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 609 allows the device 600 to exchange information / data with other devices over a computer network, such as the Internet, and / or various telecommunication networks.

[0135] The computing unit 601 can be various general and / or special purpose processing components with processing and computing capabilities. Some examples of the computing unit 601 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various specialized artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, a digital signal processor (DSP), and any appropriate processor, controller, microcontroller, etc. The computing unit 601 performs various methods and processes described above, such as the method of determining memory access efficiency. For example, in some embodiments, the method of determining memory access efficiency can be implemented as a computer software program, which is tangibly embodied in a machine-readable medium, such as the storage unit 608. In some embodiments, part or all of the computer program can be loaded and / or installed onto the device 600 via the ROM 602 and / or the communication unit 609. When the computer program is loaded onto the RAM 603 and executed by the computing unit 601, one or more steps of the method of determining memory access efficiency described above can be performed. Alternatively, in other embodiments, the computing unit 601 can be configured to perform the method of determining memory access efficiency by other any appropriate means, such as by means of firmware.

[0136] Various implementations of the systems and techniques described above herein can be realized in digital electronic circuitry, integrated circuitry, a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), a system on a chip (SOC), a complex programmable logic device (CPLD), computer hardware, firmware, software, and / or combinations thereof. These various implementations can include implementation in one or more computer programs that are executable and / or interpretable on a programmable system including at least one programmable processor, which can be special or general purpose, coupled to receive data and instructions from, and to transmit data and instructions to, a storage system, at least one input device, and at least one output device.

[0137] Program code for carrying out methods of the present disclosure can be written in any combination of one or more programming languages. The program code can be provided to a processor or controller of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the program code, when executed by the processor or controller, produces the functions / operations specified in the flowcharts and / or block diagrams. The program code can be executed entirely on a machine, partially on a machine, partially on a machine as a standalone software package, or entirely on a remote machine or server.

[0138] In the context of the present disclosure, a machine-readable medium can be a tangible medium that contains or stores a program for use by or in connection with an instruction execution system, apparatus, or device. The machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium can include but is not limited to an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. More specific examples of the machine-readable storage medium will include one or more lines of electrical connections, portable computer disks, hard disk drives, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or Flash memory), optical fibers, portable compact disc read-only memories (CD-ROMs), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0139] To provide for interaction with a user, the systems and techniques described here can be implemented on a computer having a display device (e.g., a CRT (cathode ray tube) monitor or LCD (liquid crystal display) monitor) for displaying information to the user and a keyboard and a pointing device (e.g., a mouse or a trackball) by which the user can provide input to the computer. Other kinds of devices can be used to provide for interaction with a user as well; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form, including acoustic, speech, or tactile input.

[0140] The systems and techniques described here can be implemented in a computing system that includes a back end component (e.g., as a data server), or that includes a middleware component (e.g., an application server), or that includes a front end component (e.g., a user computer having a graphical user interface or a Web browser through which a user can interact with an implementation of the systems and techniques described here), or any combination of such back end, middleware, or front end components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include a local area network (LAN), a wide area network (WAN), and the Internet.

[0141] The computer system can include clients and servers. This relationship can be

[0142] It should be understood that the procedures shown above can be re-ordered, added to, or removed from, while still being within the scope of the present disclosure. For example, the steps recited in the present disclosure can be performed in parallel, in series, or in a different order, as long as the desired results of the technology disclosed in the present disclosure are achieved, and are not limited herein.

[0143] The specific embodiments described above are not intended to be limiting, and persons skilled in the art will appreciate that various modifications, combinations, sub-combinations and alternatives can be made to the specific embodiments without departing from the spirit and principles of the disclosure. Accordingly, the disclosure is not limited to the specific embodiments described above.

Claims

1. An electronic device, comprising: a memory configured to store executable instructions and to-be-processed data, wherein the to-be-processed data is divided into a plurality of data blocks; and a processor configured to execute the executable instructions so as to: read a to-be-tested data block from the plurality of data blocks from the memory; determine memory access description information according to size information of the to-be-tested data block, wherein the memory access description information comprises read period information and a data read interval, the size information of the to-be-tested data block comprises a data read offset, a number of rows and a number of columns, the read period information is characterized as a periodic square wave, an effective width of the square wave is the number of columns, a period of the periodic square wave is determined according to the data read offset, and the data read interval is determined according to the data read offset and the number of rows; and determine memory access efficiency of the processor reading the to-be-tested data block according to the memory access description information and channel description information, wherein the channel description information describes a plurality of channels of the processor reading the to-be-processed data from the memory, the processor is further configured to determine a target channel from the plurality of channels, wherein the target channel is a channel with the largest data transmission load in a case that the to-be-tested data block is read from the memory in parallel using the plurality of channels; determine target channel description information of the target channel, wherein the target channel description information comprises channel bandwidth of the target channel.

2. The electronic device of claim 1, wherein, the processor is further configured to: determine the memory access efficiency of the processor reading the to-be-tested data block according to an integral value of the read period information and the target channel description information in the data read interval.

3. The electronic device of claim 2, wherein, the processor is further configured to: determine the memory access efficiency of the processor reading the to-be-tested data block according to the number of the plurality of channels, the size information of the to-be-tested data block and the integral value.

4. The electronic device of claim 2, wherein, the processor is further configured to: determine a plurality of first frequency domain components of the read period information and a plurality of second frequency domain components of the target channel description information; and determine the memory access efficiency of the processor reading the to-be-tested data block according to the plurality of first frequency domain components and the plurality of second frequency domain components. the processor is further configured to:

5. The electronic device of claim 4, wherein, perform Fourier series expansion on the read period information to obtain the plurality of first frequency domain components; and perform Fourier series expansion on the target channel description information to obtain the plurality of second frequency domain components. The memory access efficiency of the processor reading the to-be-tested data block is used to represent data transmission load uniformity in the plurality of channels in a case that the to-be-tested data block is read from the memory in parallel by the processor via the plurality of channels.

6. The electronic device of any of claims 1-5, wherein, 7.A method for determining memory access efficiency, comprising: reading a to-be-tested data block from a plurality of data blocks of to-be-processed data from a memory; ​ determining memory access description information according to the size information of the data block to be measured, wherein the memory access description information comprises read cycle information and a data read interval, the size information of the data block to be measured comprises a data read offset, a number of rows and a number of columns, the read cycle information is characterized as a periodic square wave, an effective width of the square wave is the number of columns, and a period of the periodic square wave is determined according to the data read offset, and the data read interval is determined according to the data read offset and the number of rows; and determining memory access efficiency of reading the data block to be measured according to the memory access description information and channel description information, wherein the channel description information describes a plurality of channels for reading the data to be processed from the memory, the determining memory access efficiency of reading the data block to be measured according to the memory access description information and channel description information comprises: determining a target channel in the plurality of channels, wherein the target channel is a channel with the largest data transmission load in a case of reading the data block to be measured from the memory in parallel by using the plurality of channels; determining target channel description information of the target channel, wherein the target channel description information comprises a channel bandwidth of the target channel.

8. The method of claim 7, wherein, the determining memory access efficiency of reading the data block to be measured according to the memory access description information and channel description information further comprises: determining memory access efficiency of a processor reading the data block to be measured according to an integral value of the read cycle information and the target channel description information in the data read interval.

9. The method of claim 8, wherein, the determining memory access efficiency of the processor reading the data block to be measured according to the integral value of the read cycle information and the target channel description information in the data read interval comprises: determining memory access efficiency of the processor reading the data block to be measured according to a number of the plurality of channels, a size of the data block to be measured and the integral value.

10. The method of claim 9, wherein, the determining memory access efficiency of the processor reading the data block to be measured according to the integral value of the read cycle information and the target channel description information in the data read interval comprises: determining a plurality of first frequency domain components of the read cycle information and a plurality of second frequency domain components of the target channel description information; and determining memory access efficiency of the processor reading the data block to be measured according to the plurality of first frequency domain components and the plurality of second frequency domain components.

11. The method of claim 10, wherein, the determining the plurality of first frequency domain components of the read cycle information and the plurality of second frequency domain components of the target channel description information comprises: performing Fourier series expansion on the read cycle information to obtain a plurality of first frequency domain components; and performing Fourier series expansion on the target channel description information to obtain a plurality of second frequency domain components.

12. The method of any one of claims 7 to 11, wherein, the memory access efficiency of reading the data block to be measured is used to represent data transmission load uniformity in the plurality of channels in a case of reading the data block to be measured from the memory in parallel by the processor via the plurality of channels.

13. An electronic device comprising: at least one processor; and a memory connected to the at least one processor in communication; wherein, The memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor to enable the at least one processor to perform the method of any one of claims 7 to 12.

14. A non-transitory computer readable storage medium having stored thereon computer instructions, wherein, The computer instructions are for causing the computer to perform the method of any one of claims 7 to 12.

15. A computer program product comprising a computer program which, when executed by a processor, implements the method of any one of claims 7 to 12.

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