Low-power wake-up driving method

Abstract

This invention discloses a low-power wake-up driving method, comprising the following steps: In the second stage of the preparation mode, the voltages of the first, second, third, fourth, and fifth signals are preprocessed to standard voltage levels; In the first stage of the LPWG mode, the first and second signals are driven to output pulse signals based on the standard voltage levels, and the third, fourth, and fifth signals are driven to output pulse signals based on low voltage levels; In the second stage of the LPWG mode, the third, fourth, and fifth signals are driven to output high voltage levels based on the pulse signal voltages; In the third stage of the LPWG mode, the high voltage levels of the third, fourth, and fifth signals are adjusted back to low levels. By adjusting the output signal voltages in the LPWG mode, not only is the standby power consumption of the LPWG mode reduced, but also the problem of micro-short circuits in the pull-up and pull-down modules of some GOA circuits is avoided.

Description

Technical Field

[0001] This invention relates to the field of display panel technology, and in particular to a low-power wake-up driving method. Background Technology

[0002] Smartphones often perform scans even when the screen is off, using gestures to wake up certain functions or related software; this is known as LPWG (Low Power Wake-up Gesture). This mode requires minimal power consumption and eliminates abnormal phenomena such as screen flickering.

[0003] To eliminate screen flicker, a black screen is typically inserted when entering and exiting LPWG mode. This enables the GOA signal, turning on all gate drive lines of the panel. To reduce power consumption, the voltage range in this mode is usually set to a lower range. However, in amorphous silicon or some low-temperature polycrystalline silicon display panels, the transistor type is usually N-type TFT. The voltage can cause micro-short circuits in the pull-up and pull-down modules of the GOA unit, resulting in higher power consumption.

[0004] Therefore, an LPWG mode that can adapt to most smartphone displays is needed to reduce power consumption. Summary of the Invention

[0005] In LPWG mode, existing smartphone displays are prone to micro-short circuits in the pull-up and pull-down modules of the GOA unit in amorphous silicon or partially low-temperature polycrystalline silicon display panels, resulting in high power consumption.

[0006] To address the above issues, a low-power wake-up driver method is proposed.

[0007] A low-power wake-up driving method includes the following steps:

[0008] In the second stage of the preparation mode, the voltages of the first signal, the second signal, the third signal, the fourth signal, and the fifth signal are preprocessed into standard voltage levels.

[0009] In the first stage of LPWG mode: the first signal and the second signal are driven to output pulse signals based on the standard voltage level, and the third signal, the fourth signal and the fifth signal are driven to output pulse signals based on the low voltage level.

[0010] In the second stage of LPWG mode, the third, fourth, and fifth signals are driven to output a high-level voltage based on the voltage of the pulse signal;

[0011] In the third stage of LPWG mode, the high-level voltages of the third, fourth, and fifth signals are adjusted back to the low-level.

[0012] In conjunction with the low-power wake-up driving method described in the first aspect of the present invention, in a first possible implementation, the step of: in the second stage of the preparation mode, preprocessing the voltages of the first signal, the second signal, the third signal, the fourth signal, and the fifth signal into standard voltage levels includes:

[0013] The voltages of the first signal and the fourth signal are adjusted to higher values ​​respectively to obtain the standard voltage level;

[0014] The voltage of the second signal and the standard voltage level of the third signal are obtained respectively.

[0015] In conjunction with the first possible embodiment of the first aspect of the present invention, in the second possible embodiment, the step of: in the first stage of LPWG mode: driving the first signal and the second signal to output pulse signals based on the standard voltage level, and driving the third signal, the fourth signal, and the fifth signal to output the pulse signals based on the low voltage level, includes:

[0016] After entering LPWG mode, in the first stage: the standard voltage bits of the third, fourth, and fifth signals are adjusted to the lower bits respectively to obtain the low-bit voltage;

[0017] After entering LPWG mode, in the first stage: after driving the third signal, fourth signal and fifth signal to output the low voltage T time respectively, the pulse signal is output.

[0018] In conjunction with the second possible implementation of the first aspect of the present invention, in the third possible implementation, the step of: driving the third signal, the fourth signal, and the fifth signal to output a high-level voltage based on the voltage of the pulse signal in the second stage of the LPWG mode includes:

[0019] After entering LPWG mode, in the second stage: the pulse signals of the third, fourth, and fifth signals are adjusted to a higher level to obtain the high-level voltage;

[0020] After entering LPWG mode, in the second stage: the third signal, the fourth signal, and the fifth signal are driven to output the high voltage throughout the second stage.

[0021] In conjunction with the third possible implementation of the first aspect of the present invention, and in the fourth possible implementation, the step of: driving the third signal, the fourth signal, and the fifth signal to output a high-level voltage based on the voltage of the pulse signal in the second stage of the LPWG mode, further includes:

[0022] After entering LPWG mode, in the second stage: the voltages of the pulse signals of the first signal and the second signal are adjusted to the standard voltage level respectively;

[0023] After entering LPWG mode, in the second stage: the first signal and the second signal are driven to output the standard voltage level throughout the second stage.

[0024] In conjunction with the fourth possible implementation of the first aspect of the present invention, in the fifth possible implementation, the step of: adjusting the high-order voltages of the third, fourth, and fifth signals back to low-order values ​​in the third stage of the LPWG mode includes:

[0025] In the third stage of LPWG mode, the high-level voltages of the third, fourth, and fifth signals are adjusted to the low-level voltages again, until they reach the standard voltage level.

[0026] In the third stage of LPWG mode, the third signal, the fourth signal, and the fifth signal are driven to output the standard voltage level throughout the third stage.

[0027] In conjunction with the fourth possible implementation of the first aspect of the present invention, in the sixth possible implementation, the step of: adjusting the high-order voltages of the third, fourth, and fifth signals back to low-order values ​​in the third stage of the LPWG mode, further includes:

[0028] In the third stage of LPWG mode, the high-level voltages of the third, fourth, and fifth signals are adjusted to the low-level voltages again.

[0029] In the third stage of LPWG mode, the third signal, the fourth signal, and the fifth signal are driven to output the low-level voltage throughout the third stage.

[0030] In conjunction with the sixth possible implementation of the first aspect of the present invention, and in the seventh possible implementation, the driving method further includes:

[0031] In the first stage of recovery mode, the first signal and the second signal are driven to be output at a standard voltage level;

[0032] In the second stage of the recovery mode, the voltages of the third, fourth, and fifth signals are adjusted to the standard voltage level and output at the standard voltage level.

[0033] In conjunction with the low-power wake-up driving method described in the first aspect of the present invention, in an eighth possible implementation, the third signal is the gate driving signal of the display screen GOA circuit, the fourth signal is the VGL signal of the GOA circuit, and the fifth signal is the VGH signal of the GOA circuit.

[0034] In conjunction with the low-power wake-up driving method described in the first aspect of the present invention, in a ninth possible implementation, the low voltage is -6V, the high voltage is 6V, and the standard voltage is 3.5V.

[0035] By implementing the low-power wake-up driving method described in this invention, the standby power consumption of LPWG mode is reduced by adjusting the output signal voltage at different stages of LPWG mode. Furthermore, by adjusting the signal driving timing voltage in the third stage of LPWG mode, the problem of micro-short circuits in the pull-up and pull-down modules in the GOA unit of amorphous silicon or partially low-temperature polycrystalline silicon display panels is avoided. Attached Figure Description

[0036] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0037] Figure 1 This is a first timing diagram of the driving method of the present invention;

[0038] Figure 2 This is a second timing diagram of the driving method of the present invention;

[0039] Figure 3 This is a schematic diagram of the GOA circuit in this invention;

[0040] Figure 4 This is a first schematic diagram of the driving method of the present invention;

[0041] Figure 5 This is a second schematic diagram of the driving method of the present invention;

[0042] Figure 6 This is a third schematic diagram of the driving method of the present invention;

[0043] Figure 7 This is a fourth schematic diagram of the driving method of the present invention;

[0044] Figure 8 This is a fifth schematic diagram of the driving method of the present invention;

[0045] Figure 9 This is the sixth schematic diagram of the driving method of the present invention;

[0046] Figure 10 This is the seventh schematic diagram of the driving method of the present invention;

[0047] Figure 11 This is the eighth schematic diagram of the driving method of the present invention; Detailed Implementation

[0048] The technical solutions of this invention will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this invention, and not all of them. Other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are all within the scope of protection of this invention.

[0049] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0050] It should be noted that when a component is referred to as being "fixed to" or "set on" another component, it can be directly on or indirectly on that other component. When a component is referred to as being "connected to" another component, it can be directly connected to or indirectly connected to that other component.

[0051] It should be understood that the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0052] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0053] In LPWG mode, existing smartphone displays are prone to micro-short circuits in the pull-up and pull-down modules of the GOA unit in amorphous silicon or partially low-temperature polycrystalline silicon display panels, resulting in high power consumption.

[0054] Example 1

[0055] A low-power wake-up driving method, such as Figure 4 , Figure 4 This is a first schematic diagram of the driving method of the present invention; it includes the following steps:

[0056] In the second stage of the preparation mode (IN mode), the voltages of the first signal (VCOM / RX signal), the second signal (Source signal), the third signal (GOA signal), the fourth signal (VGL signal), and the fifth signal (VGH signal) are preprocessed into standard voltage bits (GND voltage bits).

[0057] In the first stage of LPWG mode: the first signal (VCOM / RX signal) and the second signal (Source signal) are driven to output pulse signals based on the standard voltage level (GND voltage level), and the third signal (GOA signal), the fourth signal (VGL signal), and the fifth signal (VGH signal) are driven to output pulse signals based on the low voltage level (AVEE voltage level).

[0058] In the second stage of LPWG mode, the third signal (GOA signal), the fourth signal (VGL signal), and the fifth signal (VGH signal) are driven to output a high-level voltage (AVDD voltage level) based on the voltage of the pulse signal.

[0059] In the third stage of LPWG mode, the high-order voltage (AVDD voltage level) of the third signal (GOA signal), the fourth signal (VGL signal), and the fifth signal (VGH signal) are adjusted back to the low-order level.

[0060] Smartphone displays typically include display mode, ready mode, LPWG mode, and display recovery mode. In display mode, all signals are output normally according to the display requirements. The gate of the GOA circuit drives Gout to output a high-level pulse GOA signal to drive the pixel transistor to turn on and off.

[0061] In this embodiment, the first signal (VCOM / RX signal) is the VCOM / RX signal, the second signal (Source signal) is the Source signal, the third signal (GOA signal) is the GOA signal, the fourth signal (VGL signal) is the VGL signal, and the fifth signal (VGH signal) is the VGH signal.

[0062] In this embodiment, the LPWG mode includes three stages: the first stage (gesture sensing stage), the second stage (All gate on stage), and the third stage (interval stage).

[0063] The first stage (gesture sensing stage) of LPWG mode: The first signal (VCOM / RX signal) and the second signal (Source signal) are output based on the standard voltage level (GND voltage level).

[0064] GOA signal, VGH, VGL in AVEE

[0065] (Usually -6V) is used to apply the same drive signal.

[0066] The second stage of LPWG mode (All gate on stage): The third signal (GOA signal), the fourth signal (VGL signal), and the fifth signal (VGH signal) output high-level voltage (AVDD voltage level) (AVDD voltage, typically 6V), while the first signal (VCOM / RX signal) and the second signal (Source signal) output quasi-voltage levels (GND voltage level). Figure 3 In the GOA circuit unit, the P-point potential outputs a high level. The high level of the clock level terminal CK passes through the main transistor M7, and at the same time, the high level of CKB turns on the sixth transistor M6. That is, at this time, Gout outputs a high level, which releases the accumulated charge in the previous stage and avoids the display failure caused by residual charge after the screen is turned on.

[0067] The third stage (interval stage) of LPWG mode: the first signal (VCOM / RX signal) and the second signal (Source signal) output standard voltage bit (GND voltage bit), and the third signal (GOA signal), the fourth signal (VGL signal), and the fifth signal (VGH signal) output low bit voltage (AVEE voltage bit).

[0068] If no gesture touch wake-up is performed, the first to third stages of LPWG mode will cycle through. If gesture touch wake-up is performed, the system will enter recovery mode (OUT mode).

[0069] OUT mode: First, all signals are pulled to the standard voltage level (GND voltage level), and then the normal display mode (Display mode) is restored.

[0070] In the preparation mode (IN mode), the normal display mode is switched to prepare to enter the LPWG mode. In the preparation mode, all signals are pulled to the standard voltage level (GND voltage level) (GND level). In this embodiment, the GOA signal includes the CK signal, CKB signal, STV signal, FW signal, BW signal, and RST signal in the GOA circuit, but does not include the VGL signal and VGH signal.

[0071] like Figure 3 , Figure 3This is a schematic diagram of the GOA circuit in this invention; the GOA circuit in this application can be implemented as including:

[0072] Clock level terminal CK, start level terminal STV, forward scan signal terminal FW, reverse scan signal terminal BW, first transistor M1, second transistor M2.

[0073] The set level terminal RST, the input level terminal CLB, the low level terminal VGL, the third transistor M3, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, and the first capacitor C1.

[0074] The main transistor M7, the output terminal Gout, and the second capacitor C2.

[0075] Its specific circuit structure can be implemented as follows:

[0076] The clock level terminal CK is electrically connected to the first terminal of the first capacitor C1 and the source of the main transistor M7;

[0077] The start-up level terminal STV is electrically connected to the gate of the first transistor M1;

[0078] The forward scan signal terminal FW is electrically connected to the drain of the first transistor M1;

[0079] The reverse scan signal terminal BW is electrically connected to the source of the second transistor M2;

[0080] The set level terminal RST is electrically connected to the gate of the second transistor M2;

[0081] The source of the first transistor M1, the drain of the second transistor M2, the drain of the third transistor M3, the gate of the main transistor M7, the gate of the fourth transistor M4, and the first terminal of the second capacitor C2 are all connected to point P.

[0082] The second terminal of the first capacitor C1, the gate of the third transistor M3, the drain of the fourth transistor M4, and the gate of the fifth transistor M5 are all connected to point A.

[0083] The source of the third transistor M3, the source of the fourth transistor M4, the drain of the fifth transistor M5, and the drain of the sixth transistor M6 are all connected to the low-level terminal VGL.

[0084] The input level terminal CLB is electrically connected to the gate of the sixth transistor M6;

[0085] The source of the sixth transistor M6, the source of the fifth transistor M5, the second terminal of the second capacitor C2, and the drain of the main transistor M7 are all connected to the output terminal Gout.

[0086] Here Figure 1 The GOA signal contains Figure 2All GOA control signals except those mentioned above (i.e., the same applies below).

[0087] Example 2

[0088] In this embodiment, as Figure 1 , Figure 1 This is a first timing diagram of the driving method of the present invention; based on embodiment 1, it is preferably further implemented as follows: Figure 5 , Figure 5 This is a second schematic diagram of the driving method of the present invention, including the following steps:

[0089] The voltages of the first signal (VCOM / RX signal) and the fourth signal (VGL signal) are adjusted to higher values ​​to obtain the standard voltage level (GND voltage level);

[0090] Obtain the voltage of the second signal (Source signal) and the standard voltage level (GND voltage level) of the third signal (GOA signal) respectively.

[0091] In the second phase of the preparation mode, all signals are pulled to the standard voltage level.

[0092] Example 3

[0093] In this embodiment, based on Embodiment 2, to transition from the second stage of the preparation mode to the first stage of the LPWG mode, it is necessary to adjust the standard voltage levels (GND voltage levels) of the third, fourth, and fifth signals to a lower value. Preferably, as follows: Figure 6 , Figure 6 The third schematic diagram of the driving method of the present invention includes the following steps:

[0094] After entering LPWG mode, in the first stage: the standard voltage level (GND voltage level) of the third signal (GOA signal), the fourth signal (VGL signal), and the fifth signal (VGH signal) are adjusted to the lower level to obtain the low voltage level (AVEE voltage level).

[0095] Simultaneously, after driving the third signal (GOA signal), the fourth signal (VGL signal), and the fifth signal (VGH signal) to output a low-level voltage (AVEE voltage level) for a time T, a pulse signal is output.

[0096] After being adjusted to a low voltage, the third signal (GOA signal), the fourth signal (VGL signal), and the fifth signal (VGH signal) output the same pulse signal.

[0097] In the second phase of the LPWG model, preferably, a step is implemented as follows: Figure 7 , Figure 7 This is a fourth schematic diagram of the driving method of the present invention, including the following steps:

[0098] After entering the second stage of LPWG mode: the pulse signals of the third signal (GOA signal), the fourth signal (VGL signal), and the fifth signal (VGH signal) are adjusted to the higher level to obtain the high level voltage (AVDD voltage level).

[0099] Then, the third signal (GOA signal), the fourth signal (VGL signal), and the fifth signal (VGH signal) are driven respectively to output high-level voltage (AVDD voltage bit) throughout the second stage.

[0100] In the second phase of the LPWG model: such as Figure 8 , Figure 8 This is a fifth schematic diagram of the driving method of the present invention; the voltages of the pulse signals of the first signal (VCOM / RX signal) and the second signal (Source signal) are also adjusted to the standard voltage level (GND voltage level).

[0101] Then, the first signal (VCOM / RX signal) and the second signal (Source signal) are driven respectively to output the standard voltage level (GND voltage level) throughout the second stage.

[0102] Preferably, such as Figure 9 , Figure 9 This is the sixth schematic diagram of the driving method of the present invention; in the third stage of LPWG mode, the high-order voltage (AVDD voltage level) of the third signal (GOA signal), the fourth signal (VGL signal), and the fifth signal (VGH signal) are adjusted to the low-order level again to the standard voltage level (GND voltage level), and the third signal (GOA signal), the fourth signal (VGL signal), and the fifth signal (VGH signal) are respectively driven to output the standard voltage level (GND voltage level) throughout the third stage.

[0103] Example 4

[0104] In this embodiment, as Figure 2 , Figure 2 This is a second timing diagram of the driving method of the present invention; based on embodiment 2, the difference from embodiment 3 is as follows: Figure 10 , Figure 10 This is the seventh schematic diagram of the driving method of the present invention; it includes the following steps:

[0105] In the third stage of LPWG mode, the high-level voltage (AVDD voltage level) of the third signal (GOA signal), the fourth signal (VGL signal), and the fifth signal (VGH signal) is adjusted to the low level again, adjusted to the low-level voltage (AVEE voltage level).

[0106] The third signal (GOA signal), the fourth signal (VGL signal), and the fifth signal (VGH signal) are driven respectively to output low-level voltage (AVEE voltage bit) throughout the third stage.

[0107] Example 5

[0108] In this embodiment, based on the foregoing embodiments, as follows: Figure 11 , Figure 11 This is the eighth schematic diagram of the driving method of the present invention. The driving method further includes the following steps:

[0109] In the first stage of recovery mode (OUT mode), the first signal (VCOM / RX signal) and the second signal (Source signal) are driven to be output at the standard voltage level (GND voltage level).

[0110] In the second stage of recovery mode (OUT mode), the voltages of the third signal (GOA signal), the fourth signal (VGL signal), and the fifth signal (VGH signal) are adjusted to the standard voltage level (GND voltage level) and output at the standard voltage level (GND voltage level).

[0111] If no gesture touch wake-up is performed, the first to third stages of LPWG mode will cycle through. If gesture touch wake-up is performed, the system will enter recovery mode (OUT mode).

[0112] OUT mode: First, all signals are pulled to the standard voltage level (GND voltage level), and then the normal display mode is restored.

[0113] In this embodiment, the third signal is the gate drive signal of the display screen GOA circuit, the fourth signal is the VGL signal of the GOA circuit, and the fifth signal is the VGH signal of the GOA circuit. The low-level voltage (AVEE voltage level) is -6V, the high-level voltage (AVDD voltage level) is 6V, and the standard voltage level (GND voltage level) is 3.5V.

[0114] The low-power wake-up driving method of the present invention reduces the standby power consumption of LPWG mode by adjusting the output of signal voltages at different stages of LPWG mode, and avoids the problem of micro-short circuits in the pull-up and pull-down modules of the GOA unit in amorphous silicon or partially low-temperature polycrystalline silicon display panels by adjusting the signal driving timing voltage in the third stage of LPWG mode.

[0115] The above are merely preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A low-power wake-up driving method, characterized in that, Including the following steps: In the second stage of the preparation mode, the voltages of the first signal, the second signal, the third signal, the fourth signal, and the fifth signal are preprocessed into standard voltage levels. In the first stage of LPWG mode: the first signal and the second signal are driven to output pulse signals based on the standard voltage level, and the third signal, the fourth signal and the fifth signal are driven to output pulse signals based on the low voltage level. In the second stage of LPWG mode, the third, fourth, and fifth signals are driven to output a high-level voltage based on the voltage of the pulse signal; In the third stage of LPWG mode, the high-level voltages of the third, fourth, and fifth signals are adjusted back to the low-level. The first signal is the VCOM / RX signal, the second signal is the Source signal, the third signal is the GOA signal, the fourth signal is the VGL signal, and the fifth signal is the VGH signal.

2. The low-power wake-up driving method according to claim 1, characterized in that, The steps include: In the second stage of the preparation mode, preprocessing the voltages of the first signal, the second signal, the third signal, the fourth signal, and the fifth signal into standard voltage levels, including: The voltages of the first signal and the fourth signal are adjusted to higher values ​​respectively to obtain the standard voltage level; The voltage of the second signal and the standard voltage level of the third signal are obtained respectively.

3. The low-power wake-up driving method according to claim 2, characterized in that, The steps are as follows: In the first stage of LPWG mode: drive the first signal and the second signal to output pulse signals based on the standard voltage level, and drive the third signal, the fourth signal, and the fifth signal to output pulse signals based on the low voltage level, including: After entering LPWG mode, in the first stage: the standard voltage bits of the third, fourth, and fifth signals are adjusted to the lower bits respectively to obtain the low-bit voltage; After entering LPWG mode, in the first stage: after driving the third signal, fourth signal and fifth signal to output the low voltage T time respectively, the pulse signal is output.

4. The low-power wake-up driving method according to claim 3, characterized in that, The steps are as follows: In the second stage of LPWG mode, the third, fourth, and fifth signals are driven to output a high-level voltage based on the voltage of the pulse signal, including: After entering LPWG mode, in the second stage: the pulse signals of the third, fourth, and fifth signals are adjusted to a higher level to obtain the high-level voltage; After entering LPWG mode, in the second stage: the third signal, the fourth signal, and the fifth signal are driven to output the high voltage throughout the second stage.

5. The low-power wake-up driving method according to claim 4, characterized in that, The steps, including driving the third, fourth, and fifth signals to output a high-level voltage based on the voltage of the pulse signal in the second stage of LPWG mode, further include: After entering LPWG mode, in the second stage: the voltages of the pulse signals of the first signal and the second signal are adjusted to the standard voltage level respectively; After entering LPWG mode, in the second stage: the first signal and the second signal are driven to output the standard voltage level throughout the second stage.

6. The low-power wake-up driving method according to claim 5, characterized in that, The steps are as follows: In the third stage of LPWG mode, the high-order voltages of the third, fourth, and fifth signals are adjusted back to low-order values, including: In the third stage of LPWG mode, the high-level voltages of the third, fourth, and fifth signals are adjusted to the low-level voltages again, until they reach the standard voltage level. In the third stage of LPWG mode, the third signal, the fourth signal, and the fifth signal are driven to output the standard voltage level throughout the third stage.

7. The low-power wake-up driving method according to claim 5, characterized in that, The step, in the third stage of LPWG mode, further includes adjusting the high-order voltages of the third, fourth, and fifth signals back to the low-order voltages, and also includes: In the third stage of LPWG mode, the high-level voltages of the third, fourth, and fifth signals are adjusted to the low-level voltages again. In the third stage of LPWG mode, the third signal, the fourth signal, and the fifth signal are driven to output the low-level voltage throughout the third stage.

8. The low-power wake-up driving method according to claim 7, characterized in that, The driving method further includes: In the first stage of recovery mode, the first signal and the second signal are driven to be output at a standard voltage level; In the second stage of the recovery mode, the voltages of the third, fourth, and fifth signals are adjusted to the standard voltage level and output at the standard voltage level.

9. The low-power wake-up driving method according to claim 8, characterized in that, The low voltage is -6V, the high voltage is 6V, and the standard voltage is 3.5V.

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