Cpu scheduling method and device, electronic equipment and readable storage medium

Abstract

The application discloses a CPU scheduling method and device, electronic equipment and a readable storage medium, and belongs to the field of artificial intelligence. The method comprises the following steps: determining a target CPU from a plurality of CPUs, wherein the target CPU is a CPU with the lowest load of all tasks meeting a preset condition running on the plurality of CPUs, and the important level corresponding to the task meeting the preset condition is greater than or equal to the important level corresponding to a first task; in the case that the important level corresponding to the first task is greater than the important level corresponding to a second task running in the target CPU, the second task is paused, and the first task is run through the target CPU.

Description

Technical Field

[0001] This application belongs to the field of artificial intelligence, and specifically relates to a CPU scheduling method, apparatus, electronic device, and readable storage medium. Background Technology

[0002] With the continuous development of internet and hardware technologies, electronic devices are becoming increasingly powerful, and more and more applications are running in the background, resulting in a greater number of tasks running simultaneously. This can lead to situations where foreground tasks cannot be scheduled by the CPU in a timely manner, causing delays and resulting in system lag. Summary of the Invention

[0003] The purpose of this application is to provide a CPU scheduling method, apparatus, electronic device, and readable storage medium that can solve the problem of system lag caused by task delays due to untimely CPU scheduling.

[0004] In a first aspect, embodiments of this application provide a CPU scheduling method, which includes: determining a target CPU from multiple CPUs, wherein the target CPU is the CPU with the lowest load among all tasks running on the multiple CPUs that meet preset conditions, and the importance level of the task that meets the preset conditions is greater than or equal to the importance level of a first task; if the importance level of the first task is greater than the importance level of a second task currently running on the target CPU, pausing the second task and running the first task through the target CPU.

[0005] Secondly, embodiments of this application provide a CPU scheduling device, which includes: a determining module and a processing module; the determining module is used to determine a target CPU from multiple CPUs, wherein the target CPU is the CPU with the lowest load among all tasks running on the multiple CPUs that meet preset conditions, and the importance level corresponding to the task that meets the preset conditions is greater than or equal to the importance level corresponding to a first task; the processing module is used to pause the second task and run the first task through the target CPU if the importance level corresponding to the first task is greater than the importance level corresponding to the second task running on the target CPU determined by the determining module.

[0006] Thirdly, embodiments of this application provide an electronic device including a processor and a memory, wherein the memory stores programs or instructions executable on the processor, and the programs or instructions, when executed by the processor, implement the steps of the method described in the first aspect.

[0007] Fourthly, embodiments of this application provide a readable storage medium on which a program or instructions are stored, which, when executed by a processor, implement the steps of the method described in the first aspect.

[0008] Fifthly, embodiments of this application provide a chip, the chip including a processor and a communication interface, the communication interface being coupled to the processor, the processor being used to run programs or instructions to implement the method as described in the first aspect.

[0009] In a sixth aspect, embodiments of this application provide a computer program product stored in a storage medium, which is executed by at least one processor to implement the method described in the first aspect.

[0010] In this embodiment, a target CPU is determined from multiple CPUs. The target CPU is the CPU with the lowest load among all tasks running on the multiple CPUs that meet preset conditions. The importance level of the tasks meeting the preset conditions is greater than or equal to the importance level of the first task. If the importance level of the first task is greater than the importance level of the second task currently running on the target CPU, the second task is paused, and the first task runs on the target CPU. Through this scheme, since the CPU scheduling device can set a corresponding importance level for a task and, based on the current task's importance level, determines the CPU with the lowest task load whose importance level is greater than or equal to the importance level of the first task, and performs CPU scheduling, the current task can run in a timely manner. This reduces the probability of background tasks preempting the CPU of foreground tasks, improves the response speed of foreground applications, and thus reduces system lag. Attached Figure Description

[0011] Figure 1 This is a flowchart of a CPU scheduling method provided in an embodiment of this application;

[0012] Figure 2 This is a schematic diagram illustrating an example of a CPU scheduling method provided in an embodiment of this application;

[0013] Figure 3 This is a schematic diagram of the structure of a CPU scheduling device provided in an embodiment of this application;

[0014] Figure 4 This is one of the hardware structure diagrams of an electronic device provided in the embodiments of this application;

[0015] Figure 5 This is a second schematic diagram of the hardware structure of an electronic device provided in an embodiment of this application. Detailed Implementation

[0016] The technical solutions of the embodiments of this application will be clearly described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application are within the scope of protection of this application.

[0017] The terms "first," "second," etc., used in the specification and claims of this application are used to distinguish similar objects and not to describe a specific order or sequence. It should be understood that such terms can be used interchangeably where appropriate so that embodiments of this application can be implemented in orders other than those illustrated or described herein, and the objects distinguished by "first," "second," etc., are generally of the same class and the number of objects is not limited; for example, a first object can be one or more. Furthermore, in the specification and claims, "and / or" indicates at least one of the connected objects, and the character " / " generally indicates that the preceding and following objects are in an "or" relationship.

[0018] The following explains some terms / nouns used in the embodiments of this application.

[0019] 1. Completely Fair Scheduler (CFS Scheduler)

[0020] This is a basic scheduler in the Linux operating system kernel. The core principle of the CFS scheduler is to ensure that each process receives running time as fairly as possible. Therefore, it always selects the process that has run the least in the past to run, which means that it achieves ideal, precise, and completely fair multi-task scheduling on real hardware.

[0021] The CFS scheduler uses dynamic priority as weight to schedule CPUs and run all tasks.

[0022] 2. Relative time units

[0023] The system's relative time unit, also known as the system's time base, originates from the periodic interrupts of the timer. One interrupt represents one tick, hence it is also called a Tick interrupt.

[0024] The Tick interrupt is a periodic clock interrupt, serving as the heartbeat of the operating system (OS).

[0025] The CPU scheduling method, apparatus, electronic device, and readable storage medium provided in this application will be described in detail below with reference to the accompanying drawings and through specific embodiments and application scenarios.

[0026] Currently, electronic devices (such as mobile phones and tablets) are becoming increasingly powerful, with larger memory capacities and more applications running in the background. This means that more and more programs are running simultaneously. On the one hand, when using electronic devices, the system runs various tasks concurrently, including foreground tasks, background tasks, and system service tasks. For example, while using an electronic device, video software can play videos in the foreground, while communication software can receive messages in the background, and download software can download movies in the background. Therefore, this poses a significant challenge to the system's concurrency capabilities. On the other hand, because many electronic devices have 120Hz high refresh rate screens, the response time requirements for foreground tasks are extremely high; even slight delays in response can result in stuttering.

[0027] In related technologies, the Linux kernel's CFS scheduler can schedule CPUs according to task priorities, so that the system does not lag and meets the requirements for smooth performance.

[0028] However, on the one hand, since the CFS scheduler is a completely fair scheduler that schedules CPUs based on task priority, in high-concurrency scenarios, it will place multiple important tasks on the same CPU to run. This can easily lead to multiple tasks competing for CPU time, which means that background tasks may preempt the foreground tasks. As a result, the foreground tasks may experience delays in running because they cannot get CPU scheduling in time, ultimately leading to system lag.

[0029] On the other hand, due to the high frame rate screens used in electronic devices, the response time requirements for foreground tasks are very high, and Linux's CFS scheduler can no longer meet the current system performance requirements.

[0030] In the CPU scheduling method provided in this application embodiment, a target CPU is determined from multiple CPUs. The target CPU is the CPU with the lowest load among all tasks running on the multiple CPUs that meet preset conditions. The importance level of the task meeting the preset conditions is greater than or equal to the importance level of the first task. If the importance level of the first task is greater than the importance level of the second task currently running on the target CPU, the second task is paused, and the first task runs on the target CPU. Through this scheme, since the CPU scheduling device can set a corresponding importance level for a task and determine the CPU with the lowest task load based on the current task's importance level (greater than or equal to the importance level of the first task), CPU scheduling can be performed. Therefore, the current task can be run on the CPU in a timely manner, thereby reducing the probability of background tasks preempting the CPU of foreground tasks, improving the response speed of foreground applications, and thus reducing system lag.

[0031] The CPU scheduling method provided in this application can be executed by a CPU scheduling device. Exemplarily, the CPU scheduling device can be an electronic device or a component within that electronic device, such as an integrated circuit or a chip. The CPU scheduling method provided in this application will be described below using a CPU scheduling device as an example.

[0032] This application provides a CPU scheduling method. Figure 1 A flowchart of a CPU scheduling method provided in an embodiment of this application is shown. Figure 1 As shown, the CPU scheduling method provided in this application embodiment may include the following steps 101 to 102.

[0033] Step 101: The CPU scheduling device determines the target CPU from multiple CPUs.

[0034] Among them, the target CPU is the CPU with the lowest load among all tasks that meet the preset conditions running on the multiple CPUs, and the importance level of the task that meets the preset conditions is greater than or equal to the importance level of the first task.

[0035] Optionally, the importance level corresponding to the above tasks can indicate the degree of importance of the tasks.

[0036] For example, the higher the importance of the first task, the higher its corresponding importance level; conversely, the lower the importance of the first task, the lower its corresponding importance level.

[0037] Optionally, the importance of a task can be determined by factors such as whether the task is in the foreground or background, whether it is a critical link thread for rendering and displaying video or audio, or whether it is an important service task.

[0038] It should be noted that the importance level of a task can be dynamically set based on the importance of the task it corresponds to. In other words, the importance level of a task can change as the status of the task changes.

[0039] For example, a CPU contains four tasks: Task 1, Task 2, Task 3, and Task 4. Task 1 is a background task with an importance level of 0; Task 2 is a foreground task with an importance level of 2; Task 3 serves the foreground task with an importance level of 1; and Task 4 is a critical task with an importance level of 3. When a foreground task switches to a background task—that is, when Task 1 becomes a foreground task and Task 2 becomes a background task—the importance level of Task 1 can change to 2, and the importance level of Task 2 can change to 0.

[0040] It is understandable that CPU load can indicate the sum of the number of processes that the CPU is processing and waiting to be processed over a period of time.

[0041] In this embodiment of the application, the CPU scheduling device can schedule multiple CPUs.

[0042] In this embodiment, the "target CPU with the lowest load" can be understood as the CPU with the fewest task processes running that meet preset conditions among multiple CPUs. That is, the CPU scheduling device can determine the CPU with the lowest load as the target CPU based on the importance level corresponding to the first task and the load of tasks running on the multiple CPUs with an importance level greater than or equal to the importance level corresponding to the first task. Specifically, it obtains all tasks on each CPU with an importance level higher than or equal to the first task. If some CPUs do not have any tasks with an importance level higher than or equal to the first task, then the load of these CPUs is considered 0, and further, the CPU with the lowest load is determined as the target CPU. It is understood that the target CPU is the CPU running the fewest important tasks.

[0043] Optionally, step 101 may include steps 101a and 101b described below.

[0044] Step 101a: The CPU scheduling device obtains the first load of each CPU among the multiple CPUs.

[0045] Optionally, the first load of the CPU can be the load of the target task running on the CPU, that is, the load of the task running on the CPU with an importance level greater than or equal to the importance level corresponding to the first task.

[0046] For example, the CPU scheduler can calculate the number of processes running on the CPU with an importance level greater than or equal to the importance level corresponding to the first task, as the first load of the CPU. Generally, the higher the first load of the CPU, the more processes running important tasks are running on the CPU, and vice versa.

[0047] Step 101b: The CPU scheduling device determines the CPU with the lowest load among multiple CPUs as the target CPU.

[0048] When multiple tasks that meet preset conditions are running in the first CPU, the first load of the first CPU is the total load of all tasks that meet preset conditions running in the first CPU. When no tasks that meet preset conditions are running in the first CPU, the first load of the first CPU is 0.

[0049] Optionally, the first CPU mentioned above can be any one of a plurality of CPUs.

[0050] In this embodiment of the application, "the CPU with the lowest load among multiple CPUs" can be understood as: the target CPU with the fewest processes running the target task among multiple CPUs.

[0051] For example, the CPU scheduler can schedule CPU1, CPU2, and CPU3. Assume the importance level of the first task is 1; CPU1 runs task 1 with an importance level of 0; CPU2 runs task 2 with an importance level of 2 and task 3 with an importance level of 1; and CPU3 runs task 4 with an importance level of 3. Then, the sum of the number of task processes with an importance level greater than or equal to the importance level of the first task in CPU1 is 0; the sum of the number of task processes with an importance level greater than or equal to the importance level of the first task in CPU2 is 2; and the sum of the number of task processes with an importance level greater than or equal to the importance level of the first task in CPU3 is 1. Therefore, the CPU scheduler can determine the CPU with the lowest workload among tasks with an importance level greater than or equal to the importance level of the first task, i.e., CPU1, as the target CPU.

[0052] In this way, since the CPU scheduling device can identify the CPU with the lowest load among all CPUs whose importance level is greater than or equal to that of the first task as the target CPU, it can ensure that important tasks, that is, tasks with high importance levels, are assigned to different CPUs. This ensures that important tasks will not compete for CPU time, thereby reducing system lag.

[0053] Step 102: If the importance level of the first task is greater than the importance level of the second task currently running on the target CPU, the CPU scheduling device will suspend the second task and run the first task through the target CPU.

[0054] In this embodiment of the application, "pausing the second task and running the first task through the target CPU" can be understood as the first task preempting the CPU occupied by the second task to run.

[0055] It should be noted that after the second task is paused, the second task can enter the queue of tasks waiting to be run and wait for the CPU to execute it.

[0056] In this embodiment, since the CPU scheduling device can set a corresponding importance level for a task and determine the CPU with the lowest task load whose importance level is greater than or equal to the importance level of the first task based on the current task's importance level, the current task can be run on the CPU in a timely manner, thereby reducing the probability of background tasks preempting the CPU of foreground tasks, improving the response speed of foreground applications, and thus reducing system lag.

[0057] Optionally, after step 101 above, the CPU scheduling method provided in this application embodiment may further include step 103 below.

[0058] Step 103: If the importance level of the first task is lower than the importance level of all tasks currently running on the target CPU, the CPU scheduling device continues to run the tasks on the target CPU.

[0059] It should be noted that at this point, the first task can enter the queue of tasks waiting to be run and wait for the CPU to execute it.

[0060] Thus, since the CPU scheduler can continue to run tasks on the target CPU even if the importance level of the first task is lower than the importance level of all tasks currently running on the target CPU, the CPU scheduler can determine the tasks to be run on the target CPU based on the importance level of the tasks, thereby reducing the response time of important tasks and reducing system lag.

[0061] Optionally, after step 101 above, the CPU scheduling method provided in this application embodiment may further include step 104 below.

[0062] Step 104: If the importance level of the first task is equal to the importance level of the second task currently running on the target CPU, the CPU scheduling device will run the target task through the target CPU.

[0063] Among them, the aforementioned target task can be the higher priority task among the first and second tasks.

[0064] In the embodiments of this application, the priority of any task can be used to indicate the priority of the operating system for the use of runtime resources for that task.

[0065] It is understandable that, if the importance level of the first task is equal to the importance level of the second task currently running on the target CPU, the CPU scheduler will run the higher-priority task between the first and third tasks through the target CPU.

[0066] Thus, since the CPU scheduler can run the higher-priority task between the first and third tasks through the target CPU when the importance level of the first task is equal to the importance level of the second task currently running on the target CPU, the CPU scheduler can determine the task to be run on the target CPU based on the importance level of the task and the priority of the task, thereby reducing the response time of important tasks and reducing system lag.

[0067] Optionally, if the task currently running on the target CPU has finished running, the CPU scheduling method provided in this application embodiment may further include the following step 201.

[0068] Step 201: If there are no tasks to be run on the target CPU, the CPU scheduling device will select the task with the highest priority on the second CPU as the next task to be executed by the target CPU.

[0069] The second CPU mentioned above is a CPU among the plurality of CPUs that has at least two tasks.

[0070] For example, after the current task of the target CPU has finished running, and there are no other tasks in the queue of tasks waiting to be run, the CPU scheduling device can select the task with the highest importance from other CPUs with at least two tasks as the next task to be executed by the target CPU.

[0071] For example, a CPU scheduler can select the highest priority task from CPUs containing two or more tasks as the next task to be executed by the target CPU.

[0072] Optionally, the CPU scheduling device may select the CPU with the heaviest load from the multiple CPUs mentioned above, and select the task with the highest importance level on that CPU as the next task to be executed by the target CPU.

[0073] Optionally, when there are other tasks in the queue of tasks waiting to be executed, the CPU scheduler can select the task with the highest importance level from the queue of tasks waiting to be executed as the next task to be executed by the target CPU.

[0074] In this embodiment of the application, if there are multiple tasks with the highest importance level in the queue of tasks waiting to be run, the CPU scheduling device can select the task with the highest priority from these multiple tasks with the highest importance level as the next task to be executed by the target CPU.

[0075] For example, in a queue of tasks waiting to be executed, there are five tasks: Task 5, Task 6, Task 7, Task 8, and Task 9. Task 5 has an importance level of 1, Task 6 has an importance level of 2, Task 7 has an importance level of 3, Task 8 has an importance level of 3, and Task 9 has an importance level of 1. The CPU scheduler can then select Task 7 (the highest importance level) and Task 8 (the highest priority task) as the next task to be executed by the target CPU.

[0076] It should be noted that if there are not at least two tasks in the second CPU, the CPU scheduler can control the target CPU to enter a sleep state.

[0077] Thus, since the CPU scheduler can select the highest priority task from at least one task to be run as the next task to be executed by the target CPU, the high priority task can be run by the CPU in a timely manner, thereby shortening the response time of important tasks and reducing system lag.

[0078] Optionally, the CPU scheduling method provided in this application embodiment may further include the following step 301.

[0079] Step 301: During the CPU's task execution, if the execution time of the third task exceeds the task time corresponding to the importance level of the third task within a unit of time, the CPU scheduling device will pause the third task and select the next task to run according to priority.

[0080] Understandably, each importance level corresponds to a task time. Once a task of a certain importance level exceeds its corresponding time, the task will be paused.

[0081] Optionally, after a Tick interrupt occurs, the CPU scheduler can determine whether the running time of the third task exceeds the task time corresponding to the importance level of the third task, that is, the CPU scheduler can determine whether the third task has timed out.

[0082] Optionally, the task time corresponding to the task can indicate the runnable time of the task.

[0083] Optionally, different importance levels can correspond to different task durations.

[0084] For example, the higher the importance level of a task, the longer its corresponding task time. That is, the more important the task, the longer its run time.

[0085] For example, Task 1 has an importance level of 1 and a task time of 30 milliseconds; Task 11 has an importance level of 2 and a task time of 50 milliseconds.

[0086] Optionally, if the execution time of a task exceeds its corresponding task time, the CPU scheduler can determine that the task has timed out, i.e., the task's execution time is too long. The CPU scheduler can then forcibly pause the task and select the next task to be executed for the CPU.

[0087] It should be noted that the method by which the CPU scheduler selects the next task to be executed by the CPU can be found in step 201 above, and will not be repeated here.

[0088] It should be noted that the third task that was forcibly suspended can be added to the queue of tasks waiting to be executed, based on its priority.

[0089] It should be noted that if the execution time of a task does not exceed its corresponding task time, the CPU scheduler can exit the timeout detection and the CPU can continue to run the third task.

[0090] Thus, since the CPU scheduler can perform timeout detection on tasks running on the CPU, it can prevent high-priority tasks, i.e., important tasks, from running for too long, thereby avoiding starving other tasks and preventing a decrease in system stability.

[0091] The following specific examples illustrate the CPU scheduling method provided in the embodiments of this application.

[0092] like Figure 2 As shown, the CPU scheduling method provided in this application embodiment may include the following steps 401 to 411.

[0093] Step 401: The CPU scheduler determines the wake-up task to be run.

[0094] Optionally, the wake-up task can be the same as the first task mentioned above.

[0095] Step 402: The CPU scheduler selects the CPU with the lowest workload for tasks of importance level or above corresponding to the current task.

[0096] Step 403: If the importance level of the wake-up task is higher than the importance level of the task currently running on the CPU, the CPU scheduler will preempt the CPU currently occupied by the task and run the wake-up task.

[0097] Step 404: If the priority level of the wake-up task is less than or equal to the priority level of the task currently running on the CPU, the CPU scheduler continues to run the current task or determines the task to be run based on priority.

[0098] Step 405: After the current task is completed, the CPU scheduler selects the next task to run.

[0099] Step 406: The CPU scheduler determines the task list of the highest priority tasks.

[0100] Step 407: The CPU scheduler determines the tasks to be run from the task list based on their priority.

[0101] Optionally, the highest priority task in the task list can be run first.

[0102] Step 408: After the task to be run, determined in step 407, is completed, if there are still other tasks in the list of tasks waiting to be run, the CPU scheduling device selects the task with the highest importance level from the CPU with the heaviest load and runs it on the current CPU.

[0103] Step 409: After the task to be run, determined in step 407, is completed, if there are no other tasks in the list of tasks waiting to be run, the CPU scheduling device determines whether there are more than two tasks running on other CPUs.

[0104] Step 410: When there are more than two tasks running on other CPUs, the CPU scheduling device selects the task with the highest importance from the CPU with the heaviest load and sends it to the current CPU for execution.

[0105] Step 411: If there are no more than two tasks running on other CPUs, the CPU scheduling device controls the current CPU to enter a sleep state.

[0106] In this embodiment, a target CPU is determined from multiple CPUs. The target CPU is the CPU with the lowest load among all tasks running on the multiple CPUs that meet preset conditions. The importance level of the tasks meeting the preset conditions is greater than or equal to the importance level of the first task. If the importance level of the first task is greater than the importance level of the second task currently running on the target CPU, the second task is paused, and the first task runs on the target CPU. Through this scheme, since the CPU scheduling device can set a corresponding importance level for a task and, based on the current task's importance level, determines the CPU with the lowest load whose importance level is greater than or equal to the importance level of the first task, and performs CPU scheduling, the current task can be run on the CPU in a timely manner. This reduces the probability of background tasks preempting the CPU of foreground tasks, improves the response speed of foreground applications, and thus reduces system lag.

[0107] The CPU scheduling method provided in this application can be executed by a CPU scheduling device. This application uses the execution of the CPU scheduling method by a CPU scheduling device as an example to illustrate the CPU scheduling device provided in this application.

[0108] Figure 3 A schematic diagram of a possible structure of the CPU scheduling device involved in an embodiment of this application is shown. For example... Figure 3 As shown, the CPU scheduling device 30 may include a determination module 31 and a processing module 32.

[0109] The determining module 31 is used to determine the target CPU from multiple CPUs. The target CPU is the CPU with the lowest load among all tasks running on the multiple CPUs that meet preset conditions. The importance level of the task that meets the preset conditions is greater than or equal to the importance level of the first task. The processing module 32 is used to pause the second task and run the first task through the target CPU if the importance level of the first task is greater than the importance level of the second task running on the target CPU determined by the determining module 31.

[0110] In one possible implementation, the aforementioned determining module 31 is specifically used for:

[0111] Get the first load of each CPU in a multi-CPU system;

[0112] The CPU with the lowest load among multiple CPUs is identified as the target CPU;

[0113] Where multiple tasks that meet preset conditions are running in the first CPU, the first load of the first CPU is the total load of all tasks that meet preset conditions running in the first CPU; where no tasks that meet preset conditions are running in the first CPU, the first load of the first CPU is 0.

[0114] The first CPU can be any one of the multiple CPUs.

[0115] In one possible implementation, the processing module 32 is further configured to continue running the tasks in the target CPU after the determining module 31 determines the target CPU from multiple CPUs, provided that the importance level of the first task is lower than the importance level of all tasks currently running in the target CPU.

[0116] In one possible implementation, the processing module 32 is further configured to, after the determining module 31 determines the target CPU from multiple CPUs, run the target task through the target CPU if the importance level corresponding to the first task is equal to the importance level corresponding to the second task currently running on the target CPU. The target task is the highest priority task among the first and second tasks, wherein the priority of any task is used to indicate the priority level of the operating system for using running resources for any task.

[0117] In one possible implementation, the processing module 32 is further configured to, when the task currently running on the target CPU has finished running and there are no tasks to be run on the target CPU, select the task with the highest importance level among the tasks of the second CPU as the next task to be executed by the target CPU; wherein the second CPU is a CPU with at least two tasks among multiple CPUs.

[0118] In one possible implementation, the processing module 32 is further configured to, during the CPU's task execution, if the execution time of the third task exceeds the task time corresponding to the importance level of the third task within a unit of time, pause the third task and select the next task to run according to priority.

[0119] This application provides a CPU scheduling device that determines a target CPU from multiple CPUs. The target CPU is the CPU with the lowest load among all tasks running on the multiple CPUs that meet preset conditions. The importance level of the tasks meeting the preset conditions is greater than or equal to the importance level of a first task. If the importance level of the first task is greater than the importance level of a second task currently running on the target CPU, the second task is paused, and the first task runs on the target CPU. Through this scheme, since the CPU scheduling device can set a corresponding importance level for a task and, based on the current task's importance level, determines the CPU with the lowest task load whose importance level is greater than or equal to the importance level of the first task, and performs CPU scheduling, the current task can be run on the CPU in a timely manner. This reduces the probability of background tasks preempting the CPU of foreground tasks, improves the response speed of foreground applications, and thus reduces system lag.

[0120] The CPU scheduling device in this application embodiment can be an electronic device or a component within an electronic device, such as an integrated circuit or a chip. The electronic device can be a terminal or other devices besides a terminal. For example, the electronic device can be a mobile phone, tablet computer, laptop computer, PDA, in-vehicle electronic device, mobile internet device (MID), augmented reality (AR) / virtual reality (VR) device, robot, wearable device, ultra-mobile personal computer (UMPC), netbook, or personal digital assistant (PDA), etc. It can also be a server, network attached storage (NAS), personal computer (PC), television (TV), ATM, or self-service machine, etc. This application embodiment does not specifically limit the scope of the device.

[0121] The CPU scheduling device in this application embodiment can be a device with an operating system. This operating system can be Android, iOS, or other possible operating systems; this application embodiment does not specifically limit it.

[0122] The CPU scheduling device provided in this application embodiment can implement the various processes implemented in the method embodiments of Figures N to N+x, achieving the same technical effect. To avoid repetition, it will not be described again here.

[0123] Optionally, such as Figure 4 As shown, this application embodiment also provides an electronic device 400, including a processor 401 and a memory 402. The memory 402 stores a program or instructions that can run on the processor 401. When the program or instructions are executed by the processor 401, they implement the various steps of the CPU scheduling method embodiment described above and can achieve the same technical effect. To avoid repetition, they will not be described again here.

[0124] It should be noted that the electronic devices in the embodiments of this application include the mobile electronic devices and non-mobile electronic devices described above.

[0125] Figure 5 A schematic diagram of the hardware structure of an electronic device to implement an embodiment of this application.

[0126] The electronic device 500 includes, but is not limited to, components such as: radio frequency unit 501, network module 502, audio output unit 503, input unit 504, sensor 505, display unit 506, user input unit 507, interface unit 508, memory 509, and processor 510.

[0127] Those skilled in the art will understand that the electronic device 500 may also include a power supply (such as a battery) for supplying power to various components. The power supply may be logically connected to the processor 510 through a power management system, thereby enabling functions such as managing charging, discharging, and power consumption through the power management system. Figure 5 The electronic device structure shown does not constitute a limitation on the electronic device. The electronic device may include more or fewer components than shown, or combine certain components, or have different component arrangements, which will not be elaborated here.

[0128] The processor 510 is used to determine a target CPU from multiple CPUs. The target CPU is the CPU with the lowest load among all tasks running on the multiple CPUs that meet preset conditions. The importance level of the task that meets the preset conditions is greater than or equal to the importance level of the first task. The processor 510 is used to pause the second task and run the first task through the target CPU if the importance level of the first task is greater than the importance level of the second task currently running on the target CPU.

[0129] Optionally, the processor 510 described above is specifically used for:

[0130] Get the first load of each CPU in a multi-CPU system;

[0131] The CPU with the lowest load among multiple CPUs is identified as the target CPU;

[0132] Where multiple tasks that meet preset conditions are running in the first CPU, the first load of the first CPU is the total load of all tasks that meet preset conditions running in the first CPU; where no tasks that meet preset conditions are running in the first CPU, the first load of the first CPU is 0.

[0133] The first CPU can be any one of the multiple CPUs.

[0134] Optionally, the processor 510 is further configured to continue running the tasks in the target CPU after determining the target CPU from multiple CPUs, provided that the importance level of the first task is lower than the importance level of all tasks currently running in the target CPU.

[0135] Optionally, the processor 510 is further configured to, after determining the target CPU from multiple CPUs, run the target task through the target CPU if the importance level corresponding to the first task is equal to the importance level corresponding to the second task currently running on the target CPU. The target task is the highest priority task among the first and second tasks, wherein the priority of any task is used to indicate the priority level of using running resources assigned by the operating system for any task.

[0136] Optionally, the processor 510 is further configured to, when the task currently running on the target CPU has finished running and there are no tasks to be run on the target CPU, select the task with the highest importance level among the tasks of the second CPU as the next task to be executed by the target CPU; wherein the second CPU is a CPU that has at least two tasks among multiple CPUs.

[0137] Optionally, the processor 510 is further configured to, during the CPU's task execution, if the execution time of the third task exceeds the task time corresponding to the importance level of the third task within a unit time, pause the third task and select the next task to run according to priority.

[0138] This application provides an electronic device that determines a target CPU from multiple CPUs. The target CPU is the CPU with the lowest load among all tasks running on the multiple CPUs that meet preset conditions. The importance level of the tasks meeting the preset conditions is greater than or equal to the importance level of a first task. If the importance level of the first task is greater than the importance level of a second task currently running on the target CPU, the second task is paused, and the first task is run on the target CPU. Through this scheme, since the CPU scheduling device can set a corresponding importance level for a task and, based on the current task's importance level, determines the CPU with the lowest task load whose importance level is greater than or equal to the importance level of the first task, and performs CPU scheduling, the current task can be run on the CPU in a timely manner. This reduces the probability of background tasks preempting the CPU of foreground tasks, improves the response speed of foreground applications, and thus reduces system lag.

[0139] It should be understood that, in this embodiment, the input unit 504 may include a graphics processing unit (GPU) 5041 and a microphone 5042. The GPU 5041 processes image data of still images or videos obtained by an image capture device (such as a camera) in video capture mode or image capture mode. The display unit 506 may include a display panel 5061, which may be configured in the form of a liquid crystal display, an organic light-emitting diode, or the like. The user input unit 507 includes at least one of a touch panel 5071 and other input devices 5072. The touch panel 5071 is also called a touch screen. The touch panel 5071 may include a touch detection device and a touch controller. Other input devices 5072 may include, but are not limited to, physical keyboards, function keys (such as volume control buttons, power buttons, etc.), trackballs, mice, and joysticks, which will not be described in detail here.

[0140] The memory 509 can be used to store software programs and various data. The memory 509 may primarily include a first storage area for storing programs or instructions and a second storage area for storing data. The first storage area may store the operating system, application programs or instructions required for at least one function (such as sound playback, image playback, etc.). Furthermore, the memory 509 may include volatile memory or non-volatile memory, or both. The non-volatile memory may be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. Volatile memory can be random access memory (RAM), static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDRSDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous link dynamic random access memory (SLDRAM), and direct memory bus RAM (DRRAM). The memory 509 in this embodiment includes, but is not limited to, these and any other suitable types of memory.

[0141] Processor 510 may include one or more processing units; optionally, processor 510 integrates an application processor and a modem processor, wherein the application processor mainly handles operations involving the operating system, user interface, and applications, and the modem processor mainly handles wireless communication signals, such as a baseband processor. It is understood that the aforementioned modem processor may also not be integrated into processor 510.

[0142] This application also provides a readable storage medium storing a program or instructions. When the program or instructions are executed by a processor, they implement the various processes of the CPU scheduling method embodiments described above and achieve the same technical effect. To avoid repetition, they will not be described again here.

[0143] The processor is the processor in the electronic device described in the above embodiments. The readable storage medium includes computer-readable storage media, such as computer read-only memory (ROM), random access memory (RAM), magnetic disk, or optical disk.

[0144] This application embodiment also provides a chip, which includes a processor and a communication interface. The communication interface is coupled to the processor. The processor is used to run programs or instructions to implement the various processes of the CPU scheduling method embodiment described above, and can achieve the same technical effect. To avoid repetition, it will not be described again here.

[0145] It should be understood that the chip mentioned in the embodiments of this application may also be referred to as a system-on-a-chip, system chip, chip system, or system-on-a-chip, etc.

[0146] This application provides a computer program product that is stored in a storage medium and executed by at least one processor to implement the various processes of the CPU scheduling method embodiment described above, and can achieve the same technical effect. To avoid repetition, it will not be described again here.

[0147] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element. Furthermore, it should be noted that the scope of the methods and apparatuses in the embodiments of this application is not limited to performing functions in the order shown or discussed, but may also include performing functions substantially simultaneously or in the reverse order, depending on the functions involved. For example, the described methods may be performed in a different order than described, and various steps may be added, omitted, or combined. Additionally, features described with reference to certain examples may be combined in other examples.

[0148] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a computer software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) and includes several instructions to cause a terminal (which may be a mobile phone, computer, server, or network device, etc.) to execute the methods described in the various embodiments of this application.

[0149] The embodiments of this application have been described above with reference to the accompanying drawings. However, this application is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of this application without departing from the spirit and scope of the claims, and all of these forms are within the protection scope of this application.

Claims

1. A CPU scheduling method, characterized by, The method comprises: determining a target CPU from a plurality of CPUs, the target CPU being a CPU with the lowest load of all tasks meeting preset conditions running on the plurality of CPUs, the tasks meeting the preset conditions corresponding to an importance level greater than or equal to an importance level corresponding to a first task; in a case where the importance level corresponding to the first task is greater than an importance level corresponding to a second task running on the target CPU, pausing the second task and running the first task through the target CPU; wherein the determining of the target CPU from the plurality of CPUs comprises: obtaining a first load of each CPU in the plurality of CPUs; determining a CPU with the lowest first load in the plurality of CPUs as the target CPU; wherein, in a case where a plurality of the tasks meeting the preset conditions are running on a first CPU, the first load of the first CPU is a total load of all the tasks meeting the preset conditions running on the first CPU, and in a case where no task meeting the preset conditions is running on the first CPU, the first load of the first CPU is 0; wherein the first CPU is any CPU in the plurality of CPUs.

2. The method of claim 1, wherein, After the determining of the target CPU from the plurality of CPUs, the method further comprises: in a case where the importance level corresponding to the first task is less than an importance level corresponding to all tasks running on the target CPU, continuing to run the tasks in the target CPU.

3. The method of claim 1, wherein, After the determining of the target CPU from the plurality of CPUs, the method further comprises: in a case where the importance level corresponding to the first task is equal to an importance level corresponding to a second task running on the target CPU, running a target task through the target CPU, the target task being a task with a higher priority in the first task and the second task, wherein the priority of any task indicates a priority level of a running resource specified by an operating system for the any task.

4. The method of claim 1, wherein, in a case where a task currently running on the target CPU ends, the method further comprises: in a case where there is no task to be run on the target CPU, a task with the highest importance level among tasks of a second CPU is executed as a next task of the target CPU; wherein the second CPU is a CPU with at least two tasks in the plurality of CPUs.

5. The method of claim 1, characterized in that, The method further comprises: in a case where, in a process of running a task on a CPU, a running time of a third task exceeds a task time corresponding to an importance level corresponding to the third task in a unit time, pausing the third task and selecting a next task to be run according to a priority.

6. A CPU scheduling apparatus characterized by comprising: The apparatus comprises a determining module and a processing module; the determining module is configured to determine a target CPU from a plurality of CPUs, the target CPU being a CPU with the lowest load of all tasks meeting preset conditions running on the plurality of CPUs, the tasks meeting the preset conditions corresponding to an importance level greater than or equal to an importance level corresponding to a first task; The processing module is configured to pause a second task running in the target CPU and run the first task through the target CPU, if the importance level corresponding to the first task is greater than the importance level corresponding to the second task determined by the determining module. The determining module is specifically configured to: obtain a first load of each CPU in a plurality of CPUs; determine a CPU with the lowest first load in the plurality of CPUs as the target CPU; if the first CPU is running a plurality of tasks satisfying the preset condition, the first load of the first CPU is a total load of all the tasks satisfying the preset condition running in the first CPU, and if the first CPU is not running the task satisfying the preset condition, the first load of the first CPU is 0. The first CPU is any CPU in the plurality of CPUs.

7. The apparatus of claim 6, wherein the processing module is further configured to continue running tasks in the target CPU, if the importance level corresponding to the first task is less than the importance level corresponding to all the tasks running in the target CPU after the determining module determines the target CPU from the plurality of CPUs.

8. The apparatus of claim 6, wherein the processing module is further configured to run a target task through the target CPU, if the importance level corresponding to the first task is equal to the importance level corresponding to a second task running in the target CPU after the determining module determines the target CPU from the plurality of CPUs, the target task being a task with a higher priority in the first task and the second task, wherein the priority of any task indicates a priority level of using a running resource specified by an operating system for the any task.

9. The apparatus of claim 6, wherein the processing module is further configured to select a task with the highest importance level in a second CPU as a next task executed by the target CPU, if the target CPU is not running any task after a task currently running in the target CPU ends, wherein the second CPU is a CPU in the plurality of CPUs having at least two tasks.

10. The apparatus of claim 6, wherein the processing module is further configured to pause a third task and select a next task to run according to a priority, if a running time of the third task exceeds a task time corresponding to the importance level corresponding to the third task in a unit of time during a process of running a task in a CPU. A processor and a memory, the memory stores programs or instructions executable on the processor, and the programs or instructions are executed by the processor to implement steps of the CPU scheduling method in any one of claims 1 to 5.

11. An electronic device, comprising: The readable storage medium stores programs or instructions, and the programs or instructions are executed by the processor to implement steps of the CPU scheduling method in any one of claims 1 to 5.

12. A readable storage medium, characterized by, ​

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