A 3D Processor Array Reconfiguration Method Based on Switch Structure
Through the three-dimensional processor array reconstruction method based on switch structure, the problem of failure units affecting reliability during the manufacturing process of the three-dimensional processor array is solved, the reconstruction efficiency and array scale are improved, and hardware cost and delay are reduced.
Patent Information
- Application Number
- CN202310306017.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2023-03-27
- Publication Date
- 2025-07-25
- Estimated Expiration
- 2043-03-27
AI Technical Summary
Existing three-dimensional processor arrays are prone to defects during manufacturing, resulting in high failure probability and affecting system reliability. The existing fault-tolerant technology has shortcomings in hardware cost, delay and failure possibility.
A three-dimensional processor array reconstruction method based on switch structure is adopted, and the bottleneck surface exclusion and compensation priority rules are used to generate a logical array using a logical array construction algorithm, limiting the routing distance to 1, and improving the utilization rate of trouble-free processor units.
It improves the reconstruction efficiency and reliability of the processor array, increases the scale of the reconstruction array, reduces the waste of faultless units, and reduces hardware costs and delays.
Smart Images
Figure CN116302657B_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of processor arrays, and particularly to a method for reconfiguring a three-dimensional processor array based on a switch structure. Background Art
[0002] With the increase in the array density of three-dimensional processor arrays of very large scale integrated circuits (VLSIs), the possibility of defects occurring in three-dimensional processor arrays during the manufacturing process also increases, thereby significantly increasing the probability of defects occurring during the manufacturing of electronic systems based on three-dimensional processor arrays and the probability of failures occurring during operation. Therefore, it is necessary to use effective fault tolerance technologies to reconfigure three-dimensional processor arrays containing faulty processor units in order to improve yield and reliability, thereby ensuring the reliability of the system.
[0003] Currently, the most commonly used fault tolerance architectures for studying mesh processor arrays are router-based architectures and switch-based architectures. The router-based architecture consists of interconnected network nodes, and each network node contains a traditional router wrapped by a topological switch. The topological switch is used to connect links and routers, and together they allow different logical topologies to be configured on the same physical architecture. The router-based architecture is easier to reconfigure in terms of algorithms, but the complexity of router circuits not only increases the hardware cost and power consumption, but also increases the probability of router failures, and the routing process on the router causes a huge time delay. In the switch-based architecture, single-rail switches are placed between adjacent processor units (PEs), and the switches are also interconnected with each other. In this architecture, once a connection is established, data can be transmitted without any control information. Since no routing or arbitration is required, the time delay can be ignored. Therefore, the switch-based architecture has advantages in terms of hardware cost, time delay, power consumption, and the possibility of hardware failures, but the biggest challenge lies in designing an efficient reconfiguration algorithm. Summary of the Invention
[0004] The problem to be solved by the present invention is that faulty processor units in existing processor arrays will affect the reliability of the entire system, and a method for reconfiguring a three-dimensional processor array based on a switch structure is provided.
[0005] To solve the above problems, the present invention is realized through the following technical solutions:
[0006] A method for reconfiguring a three-dimensional processor array based on a switch structure includes the following steps:
[0007] Step 1, initialize the bottleneck surface marking array flag, the sub-logical array layer number array adj, and the logical array scale array scale; set the maximum number of iterations K, where K > 1;
[0008] Step 2: Form a sub-physical array from every two adjacent xz physical planes of the current physical array, generate a sub-logical array for each sub-physical array using a logical array generation algorithm, and record the layer height of each sub-logical array in the sub-logical array layer number array adj; where adj = {V i}, V i is the number of layers of the i-th sub-logical array formed by the i-th xz physical plane and the (i + 1)-th xz physical plane in the y-axis direction of the current physical array, where i = 1, 2, …, n - 1, and n is the number of columns of the current physical array;
[0009] Step 3: Select the layer number V c of the smallest sub-logical array in the sub-logical array layer number array adj, and compare the layer number V c of the smallest sub-logical array with the layer number V c of the previous sub-logical array in the sub-logical array layer number array adj; c-1 If V
[0010] ≥ V c-1 or c = 1, then mark the c-th xz physical plane in the y-axis direction of the current physical array as the bottleneck plane, record it in the current bottleneck plane marking array flag, then exclude all the processor units on this bottleneck plane from the current physical array, and update the current physical array; c If V
[0011] c-1 <V c c , then mark the (c + 1)-th xz physical plane in the y-axis direction of the current physical array as the bottleneck plane, record it in the current bottleneck plane marking array flag, then exclude all the processor units on this bottleneck plane from the current physical array, and update the current physical array;
[0012] where, V c is the number of layers of the c-th sub-logical array formed by the c-th xz physical plane and the (c + 1)-th xz physical plane in the y-axis direction of the current physical array, and V c-1 is the number of layers of the (c - 1)-th sub-logical array formed by the (c - 1)-th xz physical plane and the c-th xz physical plane in the y-axis direction of the current physical array;
[0013] Step 4: According to the compensation priority rule, for the bottleneck planes in the current bottleneck plane marking array flag, in the current physical array, use each fault-free processor unit e on each bottleneck plane to replace the faulty physical column predecessor processor unit u or the faulty physical column predecessor processor unit v of this fault-free processor unit e, and update the current physical array;
[0014] Step 5: Generate a logical array for the current physical array using the logical array generation algorithm, record the scale of this logical array in the logical array scale array scale, and initialize the sub-logical array layer number array adj;
[0015] Step 6: Increment the current iteration count by 1, and determine whether the current iteration count has reached the maximum iteration count K. If it has not reached, return to Step 2; if it has reached, output the logical array corresponding to the maximum scale in the logical array scale array scale to complete the reconstruction.
[0016] In the above Steps 2 and 5, the process of the logical array generation algorithm is the greedy planar routing algorithm, and its specific process is as follows:
[0017] S1: Construct each logical plane in the xy direction in the form of logical rows, that is, start constructing from the first logical row of the current logical plane, along the positive x-axis direction, and keep constructing until the last logical row of the current logical plane; when constructing each logical row, perform the following operations:
[0018] S1.1: For the first logical column of the current logical row:
[0019] S1.1.1: Take the unit cluster of the physical row corresponding to the current logical row and the first physical column in the current physical array as the first unit cluster;
[0020] S1.1.2: Select an unmarked processor unit with the smallest physical layer coordinates from the first unit cluster as the alternative unit, and determine whether this alternative unit is faulty:
[0021] If the alternative unit is not faulty, take this alternative unit as the processor unit e1 of the first logical column of the current logical row;
[0022] If the alternative unit is faulty, select the first fault-free processor unit in the positive z-axis direction of the alternative unit in the first unit cluster as the processor unit e1 of the first logical column of the current logical row;
[0023] S1.1.3: Mark the processor unit e1 selected as the first logical column of the current logical row as used in the current physical array;
[0024] S1.2: For the j-th logical column of the current logical row:
[0025] S1.2.1: Take the unit cluster of the physical row corresponding to the current logical row and the j-th column in the current physical array as the j-th unit cluster; take the physical layer coordinates of the processor unit e of the (j - 1)-th logical column of the current logical row as the current reference layer unit; j-1 as the current reference layer unit;
[0026] S1.2.2 In the j-th unit cluster, select the processor unit whose physical layer coordinates are equal to those of the current reference layer unit as the candidate unit;
[0027] S1.2.3 Determine whether there is at least one unmarked fault-free processor unit among the candidate unit, the layer-predecessor processor unit of the candidate unit, and the layer-successor processor unit of the candidate unit:
[0028] If so, select a processor unit with the smallest physical layer coordinates from these unmarked fault-free processor units as the processor unit of the j-th logical column of the current logical row e j , and go to S1.2.5
[0029] Otherwise, go to S1.2.4;
[0030] S1.2.4 Mark the processor unit of the (j - 1)-th logical column of the current logical row e j-1 as unavailable, and let j = j - 1. If j = 1 at this time, go to S1.1; otherwise, go to S1.2;
[0031] S1.2.5 In the current physical array, mark the processor unit selected as the j-th logical column of the current logical row e j as used;
[0032] where j = 2, 3,..., n, and n is the number of columns of the physical array;
[0033] S2 Repeat S1 to construct the logical plane in the xy direction until there are no unmarked processor units in the unit cluster of the first physical row and the first physical column in the current physical array, then the construction of all logical planes is completed;
[0034] S3 Link all the constructed logical planes to form a logical array.
[0035] In the above step 4, the compensation priority rule is: compensate according to the recording order of the bottleneck planes in the current bottleneck plane marking array flag;
[0036] For each fault-free processor unit e on the current bottleneck plane, determine whether the physical column-predecessor processor unit u of the fault-free processor unit e is a faulty processor unit:
[0037] If the physical column-predecessor processor unit u is a faulty processor unit, use the fault-free processor unit e to replace the faulty physical column-predecessor processor unit u;
[0038] If the predecessor processor unit u is a fault-free processor unit, further determine whether the physical column-successor processor unit v of the fault-free processor unit e is a faulty processor unit:
[0039] If the physical column predecessor processor unit v is a faulty processor unit, then use the fault-free processor unit e to replace the faulty physical column successor processor unit v;
[0040] If the physical column predecessor processor unit u is a fault-free processor unit, no compensation processing is performed.
[0041] Compared with the prior art, the present invention has the following characteristics:
[0042] 1. Adopt a bottleneck surface exclusion method not used in the existing three-dimensional array reconstruction technology. Use the logic array construction algorithm to construct each adjacent surface, count the constructible logic layer height between them, and then compare and judge to select the bottleneck that blocks the construction of a larger-scale sub-array, and mark and exclude its bottleneck surface.
[0043] 2. Use its fault-free units to compensate for the faulty units in the adjacent construction areas, reducing the situation where the fault-free units with lower heights cannot be utilized due to backtracking operations during the construction process, thereby improving the reconstruction efficiency of the processor array;
[0044] 3. Considering that reselecting processor units with higher heights to continue constructing the logic plane will inevitably generate longer and more tortuous connection routes, which require more switches and are bound to occupy the switches near other fault-free units, resulting in some fault-free processor units not being utilized. When constructing the logic array, the present invention does not use the scheme in the prior art that does not limit the routing distance, but limits the routing distance to 1 (predecessor and successor), thereby increasing the utilization rate of the fault-free processor units in the array and increasing the scale of the reconstructed array. BRIEF DESCRIPTION OF THE DRAWINGS
[0045] Figure 1 It is an example of a physical array structure with a scale of 3×3×2.
[0046] Figure 2 It is a schematic diagram of each plane in the three-dimensional array structure. DETAILED DESCRIPTION OF THE INVENTION
[0047] To make the objectives, technical solutions, and advantages of the present invention clearer and more understandable, the present invention will be further described in detail below with reference to specific examples.
[0048] In a given very large scale integrated circuit, the physical array produced by lithography-related technologies is called the physical array, also known as the main array, denoted as H. The processor array usually consists of processor elements (PEs), routing switches, communication links, etc., as Figure 1As shown. When the processor unit is unable to process data or read and write information from its surrounding units, the processor unit has failed and is defined as a faulty unit. A processor unit that has not failed, that is, can work properly, is called a normal unit or a fault-free unit. A processor array that can operate normally and has no faulty units is called a fault-free array. It should be noted that in the research of the present invention, faulty units only include arithmetic units, that is, processor units. The routing switches and communication links are assumed to be fault-free. The sub-array of fault-free units reconstructed on the main array is called a logical array, also called a target array, denoted as T.
[0049] Rows, columns, and layers on the physical array (main array) are respectively defined as physical rows, physical columns, and physical layers. Rows, columns, and layers on the logical array (target array) are respectively defined as physical rows, physical columns, and physical layers. For a certain processor unit e x,y,z , its position in the three-dimensional processor array can be represented by three-dimensional coordinates, that is, the row coordinate X(e x,y,z ) = x, the column coordinate Y(e x,y,z ) = y, and the layer coordinate Z(e x,y,z ) = z. Except for boundary processor units, each processor unit e x,y,z has corresponding predecessor and successor processor units. Processor units e x-1,y,z and e x+1,y,z are respectively called the row predecessor and row successor of e x,y,z ; processor units e x,y-1,z and e x,y+1,z are respectively called the column predecessor and column successor of e x,y,z ; processor units e x,y,z-1 and e x,y,z+1 are respectively called the layer predecessor and layer successor of e x,y,z . In the physical array, if a series of processor units have the same row coordinate x and column coordinate y, then the set of these processor units is called a unit cluster H x,y , that is, H x,y = {e|X(e) = x, Y(e) = y}.
[0050] The processor plane in the physical array is called the physical plane, and the processor plane in the logical array is called the logical plane. In the three-dimensional processor array, the plane in the column-layer direction, that is, the yz plane ( Figure 2 the yz-plane in Figure 2 ), the plane in the row-layer direction, that is, the xz plane ( Figure 2 the xz-plane inThe xy-plane) represents the planes in three directions of a three-dimensional processor array, where the yz-plane represents the plane composed of processor units with the same x-axis coordinate, the xz-plane represents the plane composed of processor units with the same y-axis coordinate, and the xy-plane represents the plane composed of processor units with the same z-axis coordinate.
[0051] Based on the above knowledge, a method for reconstructing a three-dimensional processor array based on a switching structure proposed by the present invention includes the following steps:
[0052] Step 1: Initialize the bottleneck plane marking array flag, the sub-logical array layer number array adj, and the logical array scale array scale; set the maximum number of iterations K, where K > 1;
[0053] Step 2: Form a sub-physical array by every two adjacent xz physical planes of the current physical array, and generate a sub-logical array for each sub-physical array using a logical array generation algorithm, and record the layer height of each sub-logical array in the sub-logical array layer number array adj; where adj = {V i}, V i is the number of layers of the i-th sub-logical array formed by the i-th xz physical plane and the (i + 1)-th xz physical plane in the y-axis direction of the current physical array, where i = 1, 2,..., n - 1, and n is the number of columns of the current physical array;
[0054] The process of generating a sub-logical array for a sub-physical array using a logical array generation algorithm is as follows:
[0055] S1: Construct each logical plane in the xy direction in the form of logical rows, that is, start constructing from the first logical row of the current logical plane, and construct along the positive x-axis direction until the last logical row of the current logical plane; when constructing each logical row, perform the following operations:
[0056] S1.1: For the first logical column of the current logical row:
[0057] S1.1.1: Take the unit cluster of the physical row and the first physical column corresponding to the current logical row in the current sub-physical array as the first unit cluster;
[0058] S1.1.2: Select an unmarked processor unit with the smallest physical layer coordinate from the first unit cluster as an alternative unit, and determine whether the alternative unit has a fault:
[0059] If the alternative unit has no fault, then take the alternative unit as the processor unit e1 of the first logical column of the current logical row;
[0060] If the alternative unit fails, select the first fault-free processor unit in the positive z-axis direction of the alternative unit in the first unit cluster as the processor unit e1 of the first logical column of the current logical row;
[0061] S1.1.3 Mark the processor unit e1 selected as the first logical column of the current logical row in the current sub-physical array as used;
[0062] S1.2 For the j-th logical column of the current logical row:
[0063] S1.2.1 Take the unit cluster corresponding to the physical row of the current logical row and the j-th column in the current sub-physical array as the j-th unit cluster; Take the physical layer coordinates of the processor unit e j-1 as the current reference layer unit;
[0064] S1.2.2 In the j-th unit cluster, select the processor unit with physical layer coordinates equal to those of the current reference layer unit as the candidate unit;
[0065] S1.2.3 Determine whether there is at least one unmarked fault-free processor unit among the candidate unit, the layer-predecessor processor unit of the candidate unit, and the layer-successor processor unit of the candidate unit:
[0066] If so, select a processor unit with the smallest physical layer coordinates among these unmarked fault-free processor units as the processor unit e j of the j-th logical column of the current logical row, and go to S1.2.5
[0067] Otherwise, go to S1.2.4;
[0068] S1.2.4 Mark the processor unit e j-1 of the (j - 1)-th logical column of the current logical row as unavailable, and let j = j - 1. If j = 1, go to S1.1; otherwise, go to S1.2;
[0069] S1.2.5 Mark the processor unit e j selected as the j-th logical column of the current logical row in the current sub-physical array as used;
[0070] where j = 2, 3,..., n, and n is the number of columns of the sub-physical array;
[0071] S2 Repeat S1 to construct the logical plane in the xy direction until there are no unmarked processor units in the unit cluster of the first physical row and the first physical column of the current sub-physical array, then complete the construction of all logical planes;
[0072] S3 Link all the constructed logical planes to form a sub-logical array.
[0073] Step 3: Select the number of layers V of the smallest sub-logic array in the sub-logic array layer number array adj c , and use the number of layers V of the smallest sub-logic array c to compare with the number of layers V of the previous sub-logic array of this smallest sub-logic array in the sub-logic array layer number array adj c ; c-1 Make a comparison;
[0074] If V c-1 ≥ V c or c = 1, then mark the c-th xz physical plane in the y-axis direction of the current physical array as a bottleneck plane, record it in the current bottleneck plane marking array flag, then exclude all the processor units on this bottleneck plane from the current physical array, and update the current physical array;
[0075] If V c-1 <V c , then mark the (c + 1)-th xz physical plane in the y-axis direction of the current physical array as a bottleneck plane, record it in the current bottleneck plane marking array flag, then exclude all the processor units on this bottleneck plane from the current physical array, and update the current physical array;
[0076] Among them, V c is the number of layers of the c-th sub-logic array formed by the c-th xz physical plane and the (c + 1)-th xz physical plane in the y-axis direction of the current physical array, and V c-1 is the number of layers of the (c - 1)-th sub-logic array formed by the (c - 1)-th xz physical plane and the c-th xz physical plane in the y-axis direction of the current physical array;
[0077] Step 4: According to the compensation priority rule, for the bottleneck planes in the current bottleneck plane marking array flag, in the current physical array, use each fault-free processor unit e on each bottleneck plane to replace the faulty physical column predecessor processor unit u or the faulty physical column predecessor processor unit v of this fault-free processor unit e, and update the current physical array;
[0078] Compensate according to the recording order of the bottleneck planes in the current bottleneck plane marking array flag, that is, first process the bottleneck plane marked first in the current bottleneck plane marking array flag, and finally process the bottleneck plane marked last in the current bottleneck plane marking array flag;
[0079] For each fault-free processor unit e on the current bottleneck plane, determine whether the physical column predecessor processor unit u of the fault-free processor unit e is a faulty processor unit:
[0080] If the physical column predecessor processor unit u is a faulty processor unit, use the fault-free processor unit e to replace the faulty physical column predecessor processor unit u;
[0081] If the predecessor processor unit u is a fault-free processor unit, further determine whether the physical column successor processor unit v of the fault-free processor unit e is a faulty processor unit:
[0082] If the physical column successor processor unit v is a faulty processor unit, use the fault-free processor unit e to replace the faulty physical column successor processor unit v;
[0083] If the physical column predecessor processor unit u is a fault-free processor unit, no compensation process is performed.
[0084] Step 5: Generate a logical array for the current physical array using the logical array generation algorithm, record the scale of the logical array in the logical array scale array scale, and initialize the sub-logical array layer number array adj;
[0085] The process of generating a logical array for the current physical array using the logical array generation algorithm is as follows:
[0086] S1: Construct each xy-direction logical plane in the form of logical rows, that is, start constructing from the first logical row of the current logical plane, along the positive x-axis direction, and keep constructing until the last logical row of the current logical plane; when constructing each logical row, perform the following operations:
[0087] S1.1: For the first logical column of the current logical row:
[0088] S1.1.1: Use the unit cluster of the physical row and the first physical column corresponding to the current logical row in the current physical array as the first unit cluster;
[0089] S1.1.2: Select an unmarked processor unit with the smallest physical layer coordinate in the first unit cluster as the alternative unit, and determine whether the alternative unit is faulty:
[0090] If the alternative unit is fault-free, use the alternative unit as the processor unit e1 of the first logical column of the current logical row;
[0091] If the alternative unit is faulty, select the first fault-free processor unit in the positive z-axis direction of the alternative unit in the first unit cluster as the processor unit e1 of the first logical column of the current logical row;
[0092] S1.1.3: Mark the processor unit e1 selected as the first logical column of the current logical row as used in the current physical array;
[0093] S1.2: For the j-th logical column of the current logical row:
[0094] S1.2.1 Take the physical row corresponding to the current logical row in the current physical array and the cell cluster in the j-th column as the j-th cell cluster; take the physical layer coordinates of the processor unit e in the j-1 logical column of the current logical row as the current reference layer unit; j-1
[0095] S1.2.2 In the j-th cell cluster, select the processor unit whose physical layer coordinates are equal to those of the current reference layer unit as the candidate unit;
[0096] S1.2.3 Determine whether there is at least one unmarked fault-free processor unit among the candidate unit, the layer-predecessor processor unit of the candidate unit, and the layer-successor processor unit of the candidate unit:
[0097] If so, select a processor unit with the smallest physical layer coordinates among these unmarked fault-free processor units as the processor unit e in the j-th logical column of the current logical row, j and go to S1.2.5;
[0098] Otherwise, go to S1.2.4;
[0099] S1.2.4 Mark the processor unit e in the j-1 logical column of the current logical row as unavailable, and let j = j - 1. If the updated j = 1, then go to S1.1; otherwise, go to S1.2; j-1
[0100] S1.2.5 Mark the processor unit e selected as the j-th logical column of the current logical row as used in the current physical array; j
[0101] where j = 2, 3,..., n, and n is the number of columns of the physical array;
[0102] S2 Repeat S1 to construct the logical plane in the xy direction until there are no unmarked processor units in the cell cluster of the first physical row and the first physical column in the current physical array, then complete the construction of all logical planes;
[0103] S3 Link all the constructed logical planes to form a logical array.
[0104] Step 6: Increment the current iteration count by 1, and determine whether the current iteration count has reached the maximum iteration count K. If not, return to Step 2; if so, output the logical array corresponding to the largest scale in the logical array scale array to complete the reconstruction.
[0105] It should be noted that although the embodiments described above of the present invention are illustrative, they are not limitations of the present invention. Therefore, the present invention is not limited to the above specific embodiments. Without departing from the principle of the present invention, any other embodiments obtained by those skilled in the art under the inspiration of the present invention are deemed to be within the protection scope of the present invention.
Claims
1. A three-dimensional processor array reconstruction method based on a switching structure, characterized in that It includes the following steps: Step 1: Initialize the bottleneck surface marking array flag, the sub-logical array layer number array adj, and the logical array scale array scale; set the maximum number of iterations K, where K > 1; Step 2: Form a sub-physical array by taking every two adjacent xz physical planes of the current physical array, generate a sub-logical array for each sub-physical array using a logical array generation algorithm, and record the layer height of each sub-logical array in the sub-logical array layer number array adj; where adj = {V i}, V i is the number of layers of the i-th sub-logical array formed by the i-th xz physical plane and the (i + 1)-th xz physical plane in the y-axis direction of the current physical array, where i = 1, 2,..., n - 1, and n is the number of columns of the current physical array; Step 3: Select the number of layers V of the smallest sub-logic array in the sub-logic array layer number array adj c , and compare the number of layers V of the smallest sub-logic array c with the number of layers V of the previous sub-logic array c of this smallest sub-logic array in the sub-logic array layer number array adj c-1 ; If V c-1 ≥ V c or c = 1, mark the c-th xz physical plane in the y-axis direction of the current physical array as a bottleneck plane, record it in the current bottleneck plane marking array flag, then exclude all the processor units on this bottleneck plane from the current physical array, and update the current physical array; If V c-1 <V c , then mark the (c + 1)-th xz physical plane in the y-axis direction of the current physical array as the bottleneck plane, record it in the current bottleneck plane marking array flag, then exclude all the processor units on this bottleneck plane from the current physical array, and update the current physical array; Among them, V c is the number of layers of the c-th sub-logical array formed by the c-th xz physical plane and the (c + 1)-th xz physical plane in the y-axis direction of the current physical array, and V c-1 is the number of layers of the (c - 1)-th sub-logical array formed by the (c - 1)-th xz physical plane and the c-th xz physical plane in the y-axis direction of the current physical array; Step 4: According to the compensation priority rule, for the bottleneck surfaces in the current bottleneck surface marking array flag, in the current physical array, use each fault-free processor unit e on each bottleneck surface to replace the faulty physical column predecessor processor unit u or the faulty physical column predecessor processor unit v of the fault-free processor unit e, and update the current physical array; Step 5: Use the logical array generation algorithm to generate a logical array for the current physical array, record the scale of this logical array in the logical array scale array scale, and initialize the sub-logical array layer number array adj; Step 6: Increment the current iteration number by 1, and determine whether the current iteration number has reached the maximum number of iterations K. If not, return to Step 2; if so, output the logical array corresponding to the maximum scale in the logical array scale array scale to complete the reconstruction.
2. The three-dimensional processor array reconstruction method based on a switching structure according to claim 1, wherein In Steps 2 and 5, the process of the logical array generation algorithm is the greedy plane routing algorithm, and its specific process is as follows: S1: Construct each xy-direction logical plane in the form of logical rows, that is, start constructing from the first logical row of the current logical plane, along the positive x-axis direction, and keep constructing until the last logical row of the current logical plane; when constructing each logical row, perform the following operations: S1.1 For the first logical column of the current logical row: S1.1.1 Take the unit cluster of the physical row and the first physical column corresponding to the current logical row in the current physical array as the first unit cluster; S1.1.2 Select an unmarked processor unit with the smallest physical layer coordinate from the first unit cluster as the alternative unit, and determine whether the alternative unit is faulty: If the alternative unit is fault-free, then take this alternative unit as the processor unit e1 of the first logical column of the current logical row; If the alternative unit is faulty, then select the first fault-free processor unit in the positive z-axis direction of the alternative unit in the first unit cluster as the processor unit e1 of the first logical column of the current logical row; S1.1.3 Mark the processor unit e1 selected as the first logical column of the current logical row as used in the current physical array; S1.2 For the j-th logical column of the current logical row: S1.2.1 Take the physical row corresponding to the current logical row in the current physical array and the cell cluster in the j-th column as the j-th cell cluster; take the physical layer coordinates of the processor unit e j-1 in the (j - 1)-th logical column of the current logical row as the current reference layer unit; S1.2.2 In the j-th unit cluster, select the processor unit with the physical layer coordinate equal to the physical layer coordinate of the current reference layer unit as the candidate unit; S1.2.3 Determine whether there is at least one unmarked fault-free processor unit among the candidate unit, the layer predecessor processor unit of the candidate unit, and the layer successor processor unit of the candidate unit: If so, select a processor unit with the smallest physical layer coordinate among these unmarked fault-free processor units as the processor unit of the j-th logical column of the current logical row e j , and go to S1.2.5 Otherwise, go to S1.2.4; S1.2.4 Mark the processor unit e in the (j - 1)-th logical column of the current logical row as unavailable, and after setting j = j - 1, if j = 1, go to S1.1; otherwise, go to S1.2; j-1 S1.2.5 Mark the processor unit e that is the j-th logical column selected as the current logical row in the current physical array as used; j Mark as used; where j = 2, 3,..., n, and n is the number of columns of the physical array; S2: Repeat S1 to construct the xy-direction logical plane until there are no unmarked processor units in the unit cluster of the first physical row and the first physical column in the current physical array, then complete the construction of all logical planes; S3: Link all the constructed logical planes to form a logical array.
3. A three-dimensional processor array reconstruction method based on a switch structure according to claim 1, characterized in that In step 4, the compensation priority rule is: compensation is performed according to the recording order of bottleneck faces in the current bottleneck face marking array flag; For each fault-free processor unit e on the current bottleneck face, determine whether the physical column predecessor processor unit u of the fault-free processor unit e is a faulty processor unit: If the physical column predecessor processor unit u is a faulty processor unit, use the fault-free processor unit e to replace the faulty physical column predecessor processor unit u; If the predecessor processor unit u is a fault-free processor unit, further determine whether the physical column successor processor unit v of the fault-free processor unit e is a faulty processor unit: If the physical column predecessor processor unit v is a faulty processor unit, use the fault-free processor unit e to replace the faulty physical column successor processor unit v; If the physical column predecessor processor unit u is a fault-free processor unit, no compensation processing is performed.