Verification circuit and verification device for frame buffer compression

Abstract

The application provides a frame buffer compression verification circuit and a verification device. The frame buffer compression verification circuit is used for function verification of a compression module and a decompression module. The compression verification circuit is used for generating a compression address and a first enable signal of a to-be-processed image frame, and configuring the compression module based on the compression address and the first enable signal before the to-be-processed image frame is input into the compression module. The decompression verification circuit is used for generating a decompression address and a second enable signal of a compressed image frame processed by the compression module, and configuring the decompression module based on the decompression address and the second enable signal before the compressed image frame is input into the decompression module. The application can verify the compression and decompression modules before a software system is built, can find possible problems early, can accelerate the verification of the modules, can save time cost and labor cost, and can improve the development and verification speed of a chip.

Description

Technical Field

[0001] This invention relates to the field of image compression technology, and in particular to a verification circuit and verification device for frame buffer compression. Background Technology

[0002] In complex System-on-Chips (SoCs), frame buffer compression and decompression modules are typically added to improve bandwidth utilization during frame buffering and reading operations. Verification of these compression and decompression modules generally requires software intervention to ensure the correct address is configured and enabled for each arriving frame.

[0003] Current methods require the CPU system to monitor the status of the compression and decompression modules in real time to ensure that they do not access the same address at the same time upon startup. However, such real-time monitoring inevitably increases CPU load and impacts efficiency. Furthermore, in the early stages of SOC development, the CPU system is often not fully deployed, making it impossible to perform field-programmable gate array (FPGA) prototyping of the compression and decompression modules via software. Waiting for the complete deployment of the necessary software before verification will consume more time than other methods, affecting the overall chip development speed. Summary of the Invention

[0004] This invention provides a frame buffer compression verification circuit and verification device to solve the defect in the prior art that FPGA prototype verification requires software deployment. By implementing verification through hardware circuit, verification is accelerated and development time is shortened.

[0005] The present invention provides a frame buffer compression verification circuit, which is used to perform functional verification on the compression module and the decompression module. The frame buffer compression verification circuit includes a compression verification circuit and a decompression verification circuit.

[0006] The compression verification circuit is used to generate a compression address and a first enable signal for the image frame to be processed, and to configure the compression module based on the compression address and the first enable signal before the image frame to be processed is input to the compression module.

[0007] The decompression verification circuit is used to generate a decompression address and a second enable signal for the compressed image frame after compression processing by the compression module, and to configure the decompression module based on the decompression address and the second enable signal before the compressed image frame is input to the decompression module.

[0008] According to the present invention, a frame buffer compression verification circuit is provided, wherein the compression module verification circuit includes a first address calculation circuit and a first configuration circuit;

[0009] The first address calculation circuit is used to obtain the compressed address of the image frame to be processed based on the frame compression result of the compression module and the frame decompression result of the decompression module.

[0010] The first configuration circuit is used to configure the compression address of the image frame to be processed and the first enable signal to the compression module through a communication interface that communicates with the compression module.

[0011] According to a frame buffer compression verification circuit provided by the present invention, obtaining the compressed address of the image frame to be processed based on the frame compression result of the compression module and the frame decompression result of the decompression module includes:

[0012] Based on the frame compression result of the compression module and the frame decompression result of the decompression module, a first count value is calculated;

[0013] The compressed address of the image frame to be processed is generated based on the base address of the compression module, the first offset address, and the first count value.

[0014] According to a frame buffer compression verification circuit provided by the present invention, the first count value is positively correlated with the number of frames compressed by the compression module, and the first count value is negatively correlated with the number of frames decompressed by the decompression module.

[0015] Specifically, if the first count value exceeds the total number of memory addresses, the first enable signal is set to 0.

[0016] According to a frame buffer compression verification circuit provided by the present invention, the decompression module verification circuit includes a second address calculation circuit and a second configuration circuit;

[0017] The second address calculation circuit is used to obtain the decompression address of the compressed image frame based on the frame compression result of the compression module and the frame decompression result of the decompression module;

[0018] The second configuration circuit is used to configure the decompression address of the compressed image frame and the second enable signal to the decompression module through a communication interface that communicates with the decompression module.

[0019] According to a frame buffer compression verification circuit provided by the present invention, obtaining the decompression address of the compressed image frame based on the frame compression result of the compression module and the frame decompression result of the decompression module includes:

[0020] A second count value is obtained based on the frame compression result of the compression module and the frame decompression result of the decompression module;

[0021] The decompression address of the image frame to be processed is generated based on the base address of the decompression module, the second offset address, the initial decompression threshold, and the second count value.

[0022] According to a frame buffer compression verification circuit provided by the present invention, when the second count value is 0, the second enable signal is set to 1.

[0023] According to a frame buffer compression verification circuit provided by the present invention, the compression verification circuit includes a first state machine, and the compression verification circuit is further used to perform functional verification on the compression module in the configuration state of the first state machine;

[0024] The decompression verification circuit includes a second state machine, and the decompression verification circuit is further used to perform functional verification on the decompression module in the configuration state of the second state machine.

[0025] According to a frame buffer compression verification circuit provided by the present invention, when the first count value is less than the total number of memory addresses, the first state machine is determined to be in a configuration state;

[0026] If the second count value is greater than or equal to the initial decompression threshold, the second state machine is determined to be in a configuration state.

[0027] The present invention also provides a verification device, comprising: any of the frame buffer compression verification circuits described above, wherein the verification circuit comprises: a compression verification circuit and a decompression verification circuit;

[0028] The verification device is provided with a first interface for connecting to a host computer, a second interface for connecting the compression verification circuit and an external compression module, and a third interface for connecting the decompression verification circuit and an external decompression module.

[0029] The frame buffer compression verification circuit and verification device provided by this invention, at the hardware level, through the compression verification circuit and the decompression verification circuit, is equivalent to simulating the effect of software intervention outside the compression and decompression modules. Before each frame of image arrives, the correct DDR address is calculated and this address and the enable signal are sent to the compression and decompression modules. This allows the early FPGA prototype verification of the compression and decompression modules to be independent of software intervention, thereby accelerating the verification process and shortening the development time. Attached Figure Description

[0030] To more clearly illustrate the technical solutions in this invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0031] Figure 1 This is one of the structural schematic diagrams of the frame buffer compression verification circuit provided in the embodiments of the present invention;

[0032] Figure 2 This is a schematic diagram of the compression verification circuit provided in an embodiment of the present invention;

[0033] Figure 3 This is a schematic diagram of the decompression verification circuit provided in an embodiment of the present invention;

[0034] Figure 4 This is a schematic diagram of the DDR addresses accessed by the compression module and decompression module in each frame at a frame rate of 1:1, provided in an embodiment of the present invention.

[0035] Figure 5 This is a schematic diagram of the DDR addresses accessed by the compression module and decompression module in each frame at a frame rate of 2:1, as provided in this embodiment of the invention.

[0036] Figure 6 This is a schematic diagram of the DDR addresses accessed by the compression module and decompression module in each frame at a frame rate of 1:2, provided in an embodiment of the present invention.

[0037] Figure 7 This is a second schematic diagram of the structure of the verification circuit for frame buffer compression provided in this embodiment of the invention;

[0038] Figure 8 This is a schematic diagram of the structure of the verification device provided in an embodiment of the present invention. Detailed Implementation

[0039] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0040] The following is combined Figures 1-6 This invention describes a verification circuit for frame buffer compression, which is used to perform functional verification on the compression and decompression modules, such as... Figure 1As shown, the frame buffer compression verification circuit includes: compression verification circuit 101 and decompression verification circuit 102;

[0041] The compression verification circuit 101 is used to generate a compression address and a first enable signal for the image frame to be processed, and to configure the compression module based on the compression address and the first enable signal before the image frame to be processed is input to the compression module.

[0042] The decompression verification circuit 102 is used to generate a decompression address and a second enable signal for the compressed image frame after compression processing by the compression module, and to configure the decompression module based on the decompression address and the second enable signal before the compressed image frame is input to the decompression module.

[0043] It's important to note that in complex SOC systems, to reduce DDR (double data rate SDRAM) data throughput and improve bandwidth utilization, frame buffer compression (encoder) and decompression (decoder) modules are typically added during frame buffering and read operations. If software configuration is used, the CPU needs to continuously monitor the encoder and decoder to ensure they are complete. Each time the encoder and decoder are detected as finished, the correct address must be assigned to them, and the CPU must be re-triggered to ensure that the encoder and decoder do not access the same DDR address simultaneously upon startup. This real-time monitoring of the encoder and decoder status increases CPU load.

[0044] Therefore, this embodiment of the invention designs a hardware circuit that only needs to set the addresses of the encoder and decoder once before the encoder and decoder start for the first time. After the encoder and decoder start, the hardware circuit will automatically calculate and configure the addresses required for the next startup of the encoder and decoder without the need for the CPU to intervene again.

[0045] A communication interface is provided between the compression verification circuit 101 and the decompression verification circuit 102. The compression verification circuit 101 is provided with a communication interface for communicating with the encoder to be verified, and the decompression verification circuit 102 is provided with a communication interface for communicating with the decoder to be verified. Through the communication interface, the verification circuit of this embodiment can send the verified configuration information to the compression module and the decompression module before the compression module and the decompression module actually perform their respective operations, so as to improve the verification efficiency.

[0046] The frame buffer compression verification circuit of this invention, through the compression verification circuit and the decompression verification circuit, is equivalent to simulating the effect of software intervention outside the compression and decompression module. Before each frame of image arrives, the correct DDR address is calculated and this address and the enable signal are sent to the compression and decompression module. This allows the early FPGA verification of the compression and decompression module to be independent of software intervention, thereby accelerating the verification and shortening the development time.

[0047] In one embodiment, such as Figure 2 As shown, the compression module verification circuit includes a first address calculation circuit and a first configuration circuit;

[0048] The first address calculation circuit is used to obtain the compressed address of the image frame to be processed based on the frame compression result of the compression module and the frame decompression result of the decompression module.

[0049] The first configuration circuit is used to configure the compression address of the image frame to be processed and the first enable signal to the compression module through the communication interface with the compression module.

[0050] It should be noted that, in this embodiment of the invention, the compression module verification circuit needs to perform two functions to verify the encoder. The first part is to calculate the compression address of each image frame to be processed by the encoder. The second part is to configure the calculated compression address and enable signal to the encoder, so that the encoder performs frame compression operation according to the configuration.

[0051] Specifically, firstly, through the first address calculation circuit, the compression module verification circuit calculates the compression address of the current image frame entering the compression module. The compression address is generally determined by the base address and the offset address (frame_offset), i.e., compression address = address + frame_offset. In this embodiment of the invention, the base address and offset address are determined by the initial configuration of the compression module verification circuit. During the operation of the compression module verification circuit, the compression address may change depending on the compression processing result.

[0052] In addition, the compression module verification circuit can also set the initial parameters and initial enable signal of the encoder. That is, when the first frame of the image to be processed arrives, the encoder will compress it according to its own initial configuration parameters and enable signal. In each subsequent frame, the encoder will calculate a new compression address and enable signal according to the first address calculation circuit to determine the behavior of the encoder in the current frame.

[0053] In another embodiment, based on the frame compression result of the compression module and the frame decompression result of the decompression module, the compressed address of the image frame to be processed is obtained, including:

[0054] The first count value is calculated based on the frame compression result of the compression module and the frame decompression result of the decompression module;

[0055] The compressed address of the image frame to be processed is generated based on the base address of the compression module, the first offset address, and the first count value.

[0056] It should be noted that, for the first address calculation circuit, firstly, it needs to obtain the compressed DDR address of each image frame to be processed. Specifically, it determines the compressed address of the (n+1)th image frame to be processed based on the frame compression result and decompression result of the nth image frame to be processed, where n≥1. Secondly, the encoder parameters are configured by the first configuration circuit when processing the (n+1)th image frame to be processed.

[0057] The first address calculation circuit receives the frame compression processing result from the compression module through the second communication interface, and obtains the decompression processing result from the decompression verification circuit through the first communication interface. The processing result of the compression module is represented as `encoder_done`, which is the flag bit at the end of each encoder operation. The processing result of the decompression module is represented as `decoder_done`, which is the flag bit at the end of each decoder operation. The first count value is the value of the encoder's bufferwater counter; the counter increments by 1 after each frame is compressed, and decrements by 1 after each `decoder_done` is received.

[0058] Before startup, the first configuration circuit will set parameters such as the base address, offset address, and number of memory addresses (addr_num) of the compression module through the host computer or CPU. For example, if 3 memory addresses (buffer) are needed, then addr_num equals 3.

[0059] In one embodiment, the first count value is positively correlated with the number of frames compressed by the compression module and negatively correlated with the number of frames decompressed by the decompression module.

[0060] Specifically, if the first count value exceeds the total number of memory addresses, the first enable signal is set to 0.

[0061] It should be noted that, in this embodiment of the invention, the first enable signal is set to 0 when the encoder's first count value exceeds the total number of allocated memory addresses, i.e., the number of buffers. This means that the encoder does not process the current frame at this time, skipping the current frame and dropping it. This is done to handle fast-to-slow frame rate conversion.

[0062] In the three frame rate scenarios of 1:1, 2:1, and 1:2, the DDR addresses accessed by the encoder and decoder in each frame are as follows: Figures 4 to 6 As shown, if three DDR addresses are allocated to the encoder and decoder, with DDR addresses being buffer0, buffer1, and buffer2 respectively, then in the diagram, input vsync is the frame synchronization signal for the input image, and encoder_done is the flag bit that appears after each encoder operation. Output vsync is the frame synchronization signal for the output image, and decoder_done is the flag bit that appears after each decoder operation.

[0063] like Figure 4 The image shows the case where the frame rate is 1:1. In this case, there is no frame rate conversion involved, nor is it necessary to compare the size relationship between the first count value and the total number of memory addresses. Under normal operation, there will be no address conflict between the two.

[0064] like Figure 5 As shown, with Figure 5 Taking the first drop as an example, if the encoder is triggered in the frame that should be dropped (i.e., the first enable signal is not set to 0), the encoder will write data to buffer1. At the same time, the decoder needs to read data from buffer1, resulting in a conflict where reading and writing access the same address. Therefore, this embodiment of the invention, by judging the relationship between the first count value and the total number of memory addresses, can disable the encoder when reading and writing access the same address value, avoiding address conflicts caused by the encoder and decoder accessing the same DDR address at the same time. It also implements the fast-to-slow frame rate conversion function.

[0065] The frame buffer compression verification circuit in this embodiment of the invention avoids address conflicts by calculating and comparing the relationship between the first count value and the total number of memory addresses before configuring the first enable signal. Furthermore, the above method also implements frame rate conversion. Whether it's 1:1, fast to slow, or slow to fast, it can correctly calculate and trigger the encoder and decoder addresses each time they start.

[0066] In one embodiment, such as Figure 3 As shown, the decompression module verification circuit includes a second address calculation circuit and a second configuration circuit;

[0067] The second address calculation circuit is used to obtain the decompression address of the compressed image frame based on the frame compression result of the compression module and the frame decompression result of the decompression module.

[0068] The second configuration circuit is used to configure the decompression address of the compressed image frame and the second enable signal to the decompression module through the communication interface that communicates with the decompression module.

[0069] It should be noted that, in this embodiment of the invention, similar to the compression module verification circuit, the decompression module verification circuit needs to implement two functions to verify the decoder. The first part is to calculate the decompression address for each compressed image frame. The second part is to configure the calculated decompression address and enable signal to the decoder, so that the decoder performs the decompression operation according to the configuration.

[0070] In another embodiment, based on the frame compression result of the compression module and the frame decompression result of the decompression module, the decompression address of the compressed image frame is obtained, including:

[0071] The second count value is obtained based on the frame compression result of the compression module and the frame decompression result of the decompression module;

[0072] The decompression address of the image frame to be processed is generated based on the base address of the decompression module, the second offset address, the initial decompression threshold, and the second count value.

[0073] It should be noted that the decompression module verification circuit mainly has two functions. First, it obtains the decompression DDR address of each compressed image frame through the second address calculation circuit. Specifically, it determines the decompression address of the (n+1)th compressed image frame based on the compression result of the nth image frame to be processed and the decompression result of the nth compressed image frame. Second, it configures the various parameters of the decoder when processing the (n+1)th compressed image frame through the second configuration circuit.

[0074] The second address calculation circuit receives the decompression processing result from the decompression module through the third communication interface, and obtains the frame compression processing result from the compression verification circuit through the first communication interface. Each time encoder_done is received from the encoder, the counter of the second count value is incremented by 1, and the counter of the second count value is decremented by 1 after each frame is decompressed.

[0075] The behavior of the second configuration circuit is similar to that of the first configuration circuit. Before startup, it sets itself according to the instructions of the CPU system, including the initial decompression threshold init_thr, which specifies how many frames to compress before starting decompression, the base address accessed by the decompression module for the first time, the offset address of the decompression module, and other parameters.

[0076] Understandably, when the second count value is 0, the second enable signal is set to 1.

[0077] It should be noted that, in this embodiment of the invention, the second enable signal is set to 1 when the second count value is 0. This is to prevent the decompression module from being idle, and to ensure that it can continue to perform decompression operations using the address of the previous frame when the current frame is repeated with the previous frame. This avoids address conflicts where the decompression module directly accesses the address of the next frame when the current frame is repeated with the previous frame. Specifically, when the second count value counter of the decompression module is set to 0, the decompression module is instructed to repeatedly perform the decompression action on the current frame, i.e., repeat.

[0078] like Figure 6 As shown, the frame rate is 2:1, which is the case of slow to fast. Taking the decoder repeatedly accessing buffer0 in the figure as an example, if buffer1 is accessed at this time, the encoder is writing data into buffer1. Therefore, repeatedly accessing buffer0 can avoid the encoder and decoder accessing the same DDR address at the same time, so as to avoid address conflict.

[0079] In one embodiment, according to a frame buffer compression verification circuit provided by the present invention, the compression verification circuit includes a first state machine, and the compression verification circuit is further configured to perform functional verification on the compression module in the configuration state of the first state machine;

[0080] The decompression verification circuit includes a second state machine, and the decompression verification circuit is further used to perform functional verification on the decompression module in the configuration state of the second state machine.

[0081] Both the first and second state machines contain four states: idle state, waiting state, configuration state, and configuration complete state.

[0082] Specifically, if the first count value is less than the total number of memory addresses, the first state machine is determined to be in a configuration state;

[0083] If the second count value is greater than or equal to the initial decompression threshold, the second state machine is determined to be in a configuration state.

[0084] It should be noted that the state machine configures the compression verification circuit and the decompression verification circuit in different states to obtain the parameters of the encoder or decoder when each frame arrives, namely the address and first enable signal required by the encoder, and the address and second enable signal required by the decoder. The state machine in this embodiment of the invention consists of a state register and combinational logic circuits, and can perform state transitions according to pre-set states based on control signals. It is the control center that coordinates related signal actions and completes specific operations. When determining the corresponding different states of the encoder or decoder, the state machine configures the address and enable signal of the encoder or decoder respectively through the first configuration circuit and the second configuration circuit, realizing the corresponding behavior of the encoder or decoder for the current frame in the corresponding state.

[0085] As an example, for the encoder, upon initial power-up, the state machine is in the "idle" state. If the current frame is being compressed, it enters the "waiting" state. At this time, if the bufferwatercounter corresponding to the compression verification circuit is less than addr_num, it will enter the "configuration" state. At this time, the first address calculation circuit will configure the calculated address and enable signal to the encoder in sequence. After the configuration is completed, it enters the "configuration completed" state. When the compression of the next frame begins, it returns to the "waiting" state, waiting for the next configuration.

[0086] As an example, for the decoder, upon initial power-up, the state machine is in the "IDLE" state. When the bufferwater counter corresponding to the decompression verification circuit is detected to be greater than or equal to init_thr, it enters the "CONFIG" state. At this time, the decoder's enable signal is configured to enable the decoder to perform the first decompression action. During the first decompression action, the decoder's address is its pre-configured address. After the enable signal configuration is complete, it enters the "CONFIG_DONE" state. When it is detected that the decoder is performing an action, it enters the "WAITING" state. After the current frame decompression action is completed, it enters the "CONFIG" state again, configures the address calculated by the second address calculation circuit and the second enable signal, and then repeats the process from "CONFIG_DONE" to "WAITING" to "CONFIG".

[0087] The frame buffer compression verification circuit of this invention, by setting up a state machine, can configure different states of the database configuration module and configure fixed operations for each state, ensuring that it proceeds according to predetermined logic. This improves the circuit's automated configuration capabilities and enhances the maintainability and scalability of the process. Furthermore, the state machine's display function allows for real-time monitoring of the operating states of the compression and decompression modules, improving the productization capability of the verification circuit.

[0088] In one embodiment, such as Figure 7 As shown, the frame buffer compression verification circuit includes a compression verification circuit and a decompression verification circuit.

[0089] The compression verification circuit includes: an encoder state detection unit, a first count value calculation unit, and an encoder parameter configuration unit; the decompression verification circuit includes: a decoder state detection unit, a second count value calculation unit, and a decoder parameter configuration unit.

[0090] It should be noted that the compression verification circuit operates as follows: First, the encoder status detection unit determines the current encoder's working state in real time. Encoder working states include: idle state, waiting state, configuration state, and configuration complete state. Second, the first count value calculation unit calculates the first count value based on different working states. Specifically, the first count value is determined by the bufferwater counter. Combined with the compression address = base address + offset address * bufferwatercounter, the compression address is obtained. Then, the enable signal value is determined based on addr_num. Finally, the encoder parameter configuration unit configures the current frame's compression address and enable signal to the encoder, completing the compression module's verification process. The first enable signal can be configured to be 0 or 1, representing whether the compression module performs a compression operation or not.

[0091] The decompression verification circuit operates as follows: First, the decoder status detection unit continuously determines the current working state of the decoder, which includes: idle state, waiting state, configuration state, and configuration complete state. Second, the first counter value calculation unit calculates a second counter value based on different working states. Specifically, the second counter value is determined by the bufferwater counter. Combined with the decompression address (base address + offset address * bufferwater counter), the compression address is obtained. Then, the enable signal value is determined based on addr_num. Finally, the decoder parameter configuration unit configures the decompression address and enable signal of the current frame to the decoder, completing the verification process of the decompression module. The second enable signal can be configured to 0 or 1, representing whether the decompression module performs a decompression operation or not. Normally, the enable signal of the decompression module is set to 1.

[0092] The frame buffer compression verification circuit of this invention, compared with the traditional verification method that relies on software intervention, uses hardware-level means to wrap a hardware wrapper around the compression and decompression modules to simulate the effect of software intervention. Before each frame of image arrives, the correct DDR address is calculated and this address and the enable signal are sent to the compression and decompression modules. This allows the early FPGA verification of the compression and decompression modules to be independent of software intervention, thereby accelerating the verification process and shortening the overall chip development speed.

[0093] The verification device provided by the present invention is described below. The verification device described below includes a frame buffer compression verification circuit as described above. The verification circuit includes a compression verification circuit and a decompression verification circuit, such as... Figure 8 As shown:

[0094] The verification device is equipped with a first interface 201 for connecting to a host computer, a second interface 202 for connecting the compression verification circuit and an external compression module, and a third interface 203 for connecting the decompression verification circuit and an external decompression module. The compression verification circuit generates a compression address and a first enable signal for the image frame to be processed, and configures the compression module based on the compression address and the first enable signal. The image output by the host computer serves as the image frame to be processed. After the compression module is configured, the host computer starts outputting the image, thereby verifying the compression module through the compression verification circuit.

[0095] The decompression verification circuit is used to generate a decompression address and a second enable signal for the compressed image frame after compression by the compression module, and to configure the decompression module based on the decompression address and the second enable signal. After the configuration is completed, the compressed image frame is input into the decompression module, thereby verifying the decompression module through the decompression verification circuit.

[0096] The verification device of this invention can implement the configuration of the software system through hardware circuitry. Only the addresses of the encoder and decoder need to be set once via the first interface before the encoder and decoder start for the first time. After the encoder and decoder start, the circuitry of the verification device will automatically calculate and configure the addresses required for the next startup of the encoder and decoder, without the need for CPU intervention, thus achieving rapid configuration. Since the chip to be verified contains compression and decompression modules, the device can directly connect to the host computer and the chip to be verified through different interfaces and can be plugged in and out at any time. This achieves the effect of rapid verification of different chips containing compression and decompression modules without the need to build a corresponding software environment.

[0097] Understandably, indicator lights are also installed on the verification equipment;

[0098] Indicator lights are used to indicate the working status of the compression module and the decompression module to be verified. The indicator lights have two states: green and red.

[0099] It should be noted that when the indicator light is red, it means that both the compression and decompression modules are performing compression and decompression normally. Do not plug or unplug the device at this time, as this may cause data loss. The indicator light will turn green when all image data from the data source has been transmitted or when both the compression and decompression modules are idle and no longer working, indicating that the device can be plugged or unplugged at this time.

[0100] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A verification circuit for frame buffer compression, characterized in that, The frame buffer compression verification circuit is used to perform functional verification on the compression module and the decompression module. The frame buffer compression verification circuit includes a compression verification circuit and a decompression verification circuit. The compression verification circuit is used to generate a compression address of the image frame to be processed and set a first enable signal, and configure the compression module before the image frame to be processed is input to the compression module based on the compression address and the first enable signal. The compression address is determined based on the base address and the first offset address of the compression module. The decompression verification circuit is used to generate a decompression address for the compressed image frame after compression by the compression module and set a second enable signal. Based on the decompression address and the second enable signal, the circuit configures the decompression module before the compressed image frame is input to the decompression module. The decompression address is determined based on the base address and the second offset address of the decompression module.

2. The verification circuit for frame buffer compression according to claim 1, characterized in that, The compression module verification circuit includes a first address calculation circuit and a first configuration circuit; The first address calculation circuit is used to obtain the compressed address of the image frame to be processed based on the frame compression result of the compression module and the frame decompression result of the decompression module. The first configuration circuit is used to configure the compression address of the image frame to be processed and the first enable signal to the compression module through a communication interface that communicates with the compression module.

3. The frame buffer compression verification circuit according to claim 2, characterized in that, The process of obtaining the compressed address of the image frame to be processed based on the frame compression result of the compression module and the frame decompression result of the decompression module includes: Based on the frame compression result of the compression module and the frame decompression result of the decompression module, a first count value is calculated; The compressed address of the image frame to be processed is generated based on the base address of the compression module, the first offset address, and the first count value.

4. The frame buffer compression verification circuit according to claim 3, characterized in that, The first count value is positively correlated with the number of frames that the compression module has completed compression, and the first count value is negatively correlated with the number of frames that the decompression module has completed decompression. Specifically, if the first count value exceeds the total number of memory addresses, the first enable signal is set to 0.

5. The frame buffer compression verification circuit according to claim 4, characterized in that, The decompression module verification circuit includes a second address calculation circuit and a second configuration circuit; The second address calculation circuit is used to obtain the decompression address of the compressed image frame based on the frame compression result of the compression module and the frame decompression result of the decompression module; The second configuration circuit is used to configure the decompression address of the compressed image frame and the second enable signal to the decompression module through a communication interface that communicates with the decompression module.

6. The verification circuit for frame buffer compression according to claim 5, characterized in that, The process of obtaining the decompression address of the compressed image frame based on the frame compression result of the compression module and the frame decompression result of the decompression module includes: A second count value is obtained based on the frame compression result of the compression module and the frame decompression result of the decompression module; The decompression address of the image frame to be processed is generated based on the base address of the decompression module, the second offset address, the initial decompression threshold, and the second count value.

7. The frame buffer compression verification circuit according to claim 6, characterized in that, When the second count value is 0, the second enable signal is set to 1.

8. The verification circuit for frame buffer compression according to claim 6, characterized in that, The compression verification circuit includes a first state machine, and the compression verification circuit is further used to perform functional verification on the compression module in the configuration state of the first state machine; The decompression verification circuit includes a second state machine, and the decompression verification circuit is further used to perform functional verification on the decompression module in the configuration state of the second state machine.

9. The verification circuit for frame buffer compression according to claim 8, characterized in that, If the first count value is less than the total number of memory addresses, the first state machine is determined to be in a configuration state; If the second count value is greater than or equal to the initial decompression threshold, the second state machine is determined to be in a configuration state.

10. A verification device, characterized in that, include: The verification circuit for frame buffer compression according to any one of claims 1-9, the verification circuit includes: a compression verification circuit and a decompression verification circuit; The verification device is provided with a first interface for connecting to a host computer, a second interface for connecting the compression verification circuit and an external compression module, and a third interface for connecting the decompression verification circuit and an external decompression module.

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