An Adaptive SPI Interface Device and an Adaptive Timing Calibration Method

Abstract

The present invention discloses an adaptive SPI interface device and an adaptive timing calibration method, which include a master device interface and a slave device interface; the master device interface and / or the slave device interface include a data buffer, a clock source, an interface controller, a training check sequence, a training reception register, and an interface timing circuit; the training check sequence is interconnected with the training reception register, the training reception register is interconnected with the data buffer, the data buffer is interconnected with the interface timing circuit, and the output end of the interface controller is respectively connected to the data buffer, the interface timing circuit, and the input end of the clock source. Adaptive timing is achieved, timing debugging is avoided, and the debugging efficiency is high.

Description

Technical Field

[0001] The present invention belongs to the field of SPI communication, and relates to an adaptive SPI interface device and an adaptive timing calibration method. Background Art

[0002] SPI is a high-speed full-duplex, synchronous communication bus, generally composed of 3 or 4 wires. The SPI interface is widely used in communication between chips / devices (in this article, "chip" and "device" can be interchanged), such as: MCU, FLASH, EEPROM, ADC, etc.

[0003] SPI works in a master-slave mode, and data transmission is initiated by the master chip. One master chip can be connected to one or more slave chips.

[0004] In practical applications, the master chip needs to configure the working mode of its own SPI interface according to the working mode of the slave chip's SPI interface. Only when the working modes of the master and slave chips are the same can the two communicate normally and stably. Since the working modes of different types of chips or the same type of chips from different manufacturers may be different, the master chip needs to manually modify the program to re-adapt to the slave chip mode, which has low debugging efficiency and is prone to errors. In addition, a more concealed failure mode is that when the SPI modes of the master and slave chips do not match and the bus timing is close to the critical state of the standard timing, the bus may also communicate normally, but due to the very small timing margin, the reliability of the system is very poor. For example, communication data may be incorrect at different ambient temperatures, and the problems caused by this unstable state are also difficult to troubleshoot in actual engineering. Summary of the Invention

[0005] The purpose of the present invention is to overcome the above-mentioned shortcomings of the prior art, and provide an adaptive SPI interface device and an adaptive timing calibration method, which achieve adaptive timing, timing-free debugging, and high debugging efficiency.

[0006] To achieve the above purpose, the present invention adopts the following technical solutions:

[0007] An adaptive SPI interface device includes a master device interface and a slave device interface;

[0008] The master device interface and / or the slave device interface includes a data buffer, a clock source, an interface controller, a training check sequence, a training receive register, and an interface timing circuit; the training check sequence is interconnected with the training receive register, the training receive register is interconnected with the data buffer, the data buffer is interconnected with the interface timing circuit, and the output end of the interface controller is respectively connected to the data buffer, the interface timing circuit, and the input end of the clock source.

[0009] Preferably, when the master device interface and the slave device interface are connected in a four-wire system, the clock source inputs or outputs a clock signal, and the interface timing circuit inputs or outputs a chip select signal, a master out slave in signal, and a master in slave out signal.

[0010] Preferably, when the master device interface and the slave device interface are connected in a three-wire system, the clock source inputs or outputs a clock signal, and the interface timing circuit inputs or outputs a chip select signal and a bidirectional data signal.

[0011] Preferably, the master device interface is connected to a master device, and the slave device interface is connected to a slave device;

[0012] The master device and the slave device adopt FPGA, MCU, DSP, CPU, GPU, CPLD, FLASH, PLL, ADC, DAC, amplifier, attenuator, transceiver or sensor.

[0013] An adaptive timing calibration method based on the above device includes the following processes:

[0014] After the master device interface and the slave device interface are connected, when the master device interface is used as the adaptive end:

[0015] S1. The master and slave device interfaces enter the calibration mode. The master device interface initiates calibration, and the slave device interface responds to the calibration;

[0016] S2. The master device interface sequentially configures multiple SPI modes;

[0017] S3. The master device interface configures the clock phase to the standard phase, that is, the clock edge is aligned with the data change;

[0018] S4. The master device interface writes data to the slave device interface and receives the data from the slave device interface;

[0019] S5. The master device interface judges the consistency of the written and read data. If they are inconsistent, return to S2 and switch to the next SPI mode. If they are consistent, continue to the next step;

[0020] S6. The master device interface sequentially configures the clock phase to be advanced and lagged, that is, the clock edge is advanced or lagged by a certain phase relative to the data change edge;

[0021] S7. The master device interface writes data to the slave device interface and receives the data from the slave device interface;

[0022] S8. The master device interface judges the consistency of the written and read data. If they are inconsistent, return to S2 and switch to the next SPI mode. If they are consistent, end the adaptive mode;

[0023] S9. The master device interface is configured with standard phase parameters for normal SPI communication;

[0024] When the slave device interface is used as the adaptive end, the adaptation process is the same as that of the master device interface.

[0025] Preferably, the SPI modes are 0, 1, 2, and 3.

[0026] Preferably, the time of leading or lagging is 1 / 8 or 1 / 4 clock.

[0027] Preferably, the specific process of S4 is as follows: In the first frame, the master device interface sends a training verification sequence to the slave device interface, and the slave device interface writes the received sampled sequence into the training reception register of the slave device interface according to the set timing sequence. In the second frame, the master device interface reads the received sampled sequence from the slave device interface, and the slave device interface transmits the data in the training reception register to the master device interface according to the set timing sequence, and the master device interface receives the data according to the SPI mode and stores it in the training reception register of the master device interface.

[0028] Furthermore, the specific process of S5 is as follows: After the reception is completed, the interface controller of the master device interface compares the training reception register with the previously sent training verification sequence. If the sent data and the received data are the same, the timing configuration is considered valid.

[0029] Preferably, if the written and read data are inconsistent in all SPI modes, the master device interface is replaced.

[0030] Compared with the prior art, the present invention has the following beneficial effects:

[0031] By configuring multiple SPI modes, the present invention performs consistency comparison of written and read data under normal clock phases, leading, and lagging. If the sent data and the received data are the same under the normal clock phase, the timing configuration is considered valid. If both the leading and lagging clock offsets are configured validly, the current SPI timing mode configuration is considered correct. The present invention realizes adaptive timing, eliminates the need for timing debugging, and has high debugging efficiency; measures and uses the best signal timing, with strong stability; and the invented interface has good compatibility, can adapt to the timings of various manufacturers' chips, and does not require modification and maintenance of the software for later hardware replacement, reducing the system cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 is a schematic diagram of the interface composition of the present invention;

[0033] Figure 2 is a schematic diagram of the four-wire connection of the present invention;

[0034] Figure 3 is a schematic diagram of the three-wire connection of the present invention;

[0035] Figure 4 is a schematic diagram of the adaptive timing calibration process of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0036] Next, in combination with the accompanying drawings in the embodiments of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without making creative efforts belong to the scope of protection of the present invention.

[0037] It should be noted that the terms "front", "rear", "left", "right", "up" and "down" used in the following description refer to the directions in the accompanying drawings, and the terms "inner" and "outer" respectively refer to the directions towards or away from the geometric center of a specific component.

[0038] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the technical field to which the present invention belongs. The terms used in the specification of the present invention herein are only for the purpose of describing specific embodiments, and are not intended to limit the present invention. The term "and / or" used herein includes any and all combinations of one or more of the related listed items.

[0039] As Figure 1 shown, the adaptive SPI interface device described in the present invention includes a master device interface and a slave device interface.

[0040] Only one of the master device interface and the slave device interface can be the adaptive device described in the present invention, or both can be adaptive devices, and both are applicable to adaptive timing calibration.

[0041] The master device interface and / or the slave device interface of the adaptive device includes a data buffer, a clock source, an interface controller, a training verification sequence, a training reception register, and an interface timing circuit; the training verification sequence is connected to the training reception register in an interactive manner, the training reception register is connected to the data buffer in an interactive manner, the data buffer is connected to the interface timing circuit in an interactive manner, and the output end of the interface controller is respectively connected to the data buffer, the interface timing circuit, and the input end of the clock source.

[0042] The interface timing circuit: is responsible for generating corresponding normal, early, or late transmission signal timings according to the requirements of the interface controller, and sampling the received signals.

[0043] The data buffer: is responsible for caching the sampled data of the interface timing circuit when receiving. When sending, it is responsible for caching the sending data (training sequence or data to be sent).

[0044] The training transceiver register: is used to work only in the calibration mode. When sending, it reads the training verification sequence from the training verification sequence, and when receiving, it compares the received training sequence with the read training verification sequence.

[0045] Training verification sequence: responsible for saving the set training calibration sequence.

[0046] Clock source: responsible for generating the clock.

[0047] Interface controller: responsible for controlling the state of the entire calibration process, generating the corresponding SPI signal waveform, and controlling the interface timing circuit to generate the corresponding signal phase.

[0048] According to the bus data direction, it can be divided into an adaptive 4-wire or 3-wire SPI system.

[0049] Such as Figure 2 As shown, when the master device interface and the slave device interface are connected in a four-wire system, the clock source inputs or outputs a clock signal, and the interface timing circuit inputs or outputs a chip select signal, a master out slave in signal, and a master in slave out signal.

[0050] Such as Figure 3 As shown, when the master device interface and the slave device interface are connected in a three-wire system, the clock source inputs or outputs a clock signal, and the interface timing circuit inputs or outputs a chip select signal and a bidirectional data signal.

[0051] Among them, CS: represents the chip select signal. SCLK: represents the clock signal. MOSI: represents the master out slave in signal. MISO: represents the master in slave out signal. IO: represents the bidirectional data bus.

[0052] The master device interface is connected to the master device, and the slave device interface is connected to the slave device.

[0053] The master device and the slave device adopt FPGA, MCU, DSP, CPU, GPU, CPLD, FLASH, PLL, ADC, DAC, amplifier, attenuator, transceiver or sensor, etc.

[0054] The basic working process is as follows:

[0055] After power-on startup, enter the adaptive timing calibration mode.

[0056] After calibration is passed, switch to the normal communication mode (i.e., SPI communication in an existing certain mode).

[0057] When the master device interface is used as the adaptive end, the process of adaptive timing calibration is as Figure 4 shown:

[0058] 1. The master and slave device interfaces enter the calibration mode. The master device interface initiates calibration, and the slave device interface responds to the calibration.

[0059] 2. The master device interface configures SPI modes 0, 1, 2, and 3 in sequence.

[0060] 3. The master device interface configures the clock phase to the standard phase, i.e., the clock edge is aligned with the data change.

[0061] 4. The master device interface writes data to the slave device interface and receives data from the slave device interface.

[0062] 5. The master device interface judges the consistency of the written and read data. If they are inconsistent, go back to step 2, switch to the next SPI mode. If they are consistent, continue to the next step.

[0063] 6. The master device interface configures the clock phase to be advanced and lagged in sequence, i.e., the clock edge is advanced or lagged by a certain phase relative to the data change edge.

[0064] 7. The device writes data to the slave device interface and receives data from the slave device interface.

[0065] 8. The master device interface judges the consistency of the written and read data. If they are inconsistent, go back to step 2, switch to the next SPI mode. If they are consistent, end the adaptive mode.

[0066] 9. The master device interface is configured with standard phase parameters for normal SPI communication.

[0067] If the written and read data are inconsistent in all SPI modes, it proves that there is a problem with the master device interface, and replace the master device interface.

[0068] The advanced or lagged time is 1 / 8 or 1 / 4 of the clock.

[0069] The master device interface controller sets the clock source and the interface timing circuit to SPI mode 0. In the first frame, the master device interface sends a training verification sequence to the slave device interface. The slave device interface writes the received sampled sequence into the training receive register of the slave device according to the set timing. In the second frame, the master device interface reads the received sampled sequence from the slave device interface. The slave device interface transmits the data in the training receive register to the master device interface according to the set timing. The master device interface receives the data according to SPI mode 0 and stores it in the training receive register of the master device interface. After the reception is completed, the master device interface compares the training receive register with the previously sent training verification sequence. If the sent data and the received data are the same, the timing configuration is considered valid.

[0070] If the current mode configuration is valid, the master device interface controller sets the clock source to be offset by a certain time (such as advanced or lagged by 1 / 8 of the clock), and repeats the above timing calibration process. If both the advanced and lagged clock offsets are configured validly, it is considered that the current SPI timing mode configuration is correct, and enter the normal communication mode.

[0071] If there is a training sequence error in any one of the configurations of the standard / advance / lag clock phase, it is considered that the current SPI timing mode configuration is incorrect. The master device interface controller sets the clock source and the interface timing circuit to enter SPI timing modes 1, 2, and 3 in sequence, and advances / lags the clock in each mode until the correct timing configuration mode (selecting the standard SCLK phase) is found, and then enters the normal communication mode.

[0072] When only one end of the master device interface and the slave device interface is an adaptive device, the adaptive device end adjusts according to the above process to find the best timing mode. When both the master device interface and the slave device interface are adaptive devices, they are adjusted in chronological order, that is, after power-on, the master (or slave) device first performs timing adjustment, and after a certain agreed preset time, the slave (or master) device then performs timing adjustment.

[0073] Embodiment 1:

[0074] 1. Instantiate the master device as an FPGA, the slave device as a FLASH, the training sequence as a PRBS sequence, and the training register as a certain storage space of the FLASH.

[0075] 2. The master device interface sends the PRBS sequence to the slave device interface, and then receives the PRBS sequence returned by the slave device interface, and compares whether the sent and received data are consistent.

[0076] 3. The master device interface sequentially configures the clock sampling points as standard, and configures the sampling points to be advanced and lagged by 1 / 8 to 1 / 4 of the data line hold time, and tests data sending and receiving.

[0077] 4. Refer to the process in the solution for the detailed steps.

[0078] 5. If the master device interface cannot adjust the best time slot after traversing each timing mode, after 1 s, the slave device interface performs the above adjustment process.

[0079] Embodiment 2:

[0080] The master device interface is an adaptive master device interface, and the slave device interface is an existing non-adaptive slave device interface.

[0081] In this case, the system working mode is as follows:

[0082] 1. The master device interface configures its own training register according to the parameters of a specific register (such as: chip ID register, or a freely readable and writable register in the chip) of the slave device interface.

[0083] 2. The master device interface uses the training sequence in the training register and performs adaptive actions according to the process in the solution.

[0084] 3. The process of the master device interface reading and writing the slave device interface register can traverse different command control words (such as the length being divided into 1 Byte, 2 Byte, etc., and the read / write bit being before or after the address) so as to adapt to more types of non - adaptive slave device interfaces.

[0085] Embodiment 3:

[0086] The master device interface is an existing non - adaptive SPI master device interface, and the slave device interface is an adaptive SPI slave device interface. In this case, the working mode is as follows:

[0087] 1. The master device interface cyclically reads and writes the content in the slave device interface training register.

[0088] 2. The slave device interface responds to the training sequence.

[0089] 3. The master device interface compares the content read and written. If they are the same, it sets the slave device interface calibration complete register, and then ends the adaptive mode. If they are different, it continues to read and write the slave device interface training register.

[0090] 4. The slave device interface reads its own calibration complete register. If it is set, it ends the adaptive mode. Otherwise, it maintains the adaptive mode.

[0091] It should be noted that in this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non - exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not expressly listed, or elements inherent to such process, method, article or device.

[0092] It should be understood that the above description is for illustrative purposes rather than for limitation. By reading the above description, many embodiments and many applications other than the provided examples will be obvious to those skilled in the art. Therefore, the scope of this teaching should not be determined by reference to the above description, but should be determined by reference to the full scope of the foregoing claims and the equivalents of these claims. For the sake of completeness, all articles and references including patent applications and published announcements are incorporated herein by reference. The omission of any aspect of the subject matter disclosed herein in the foregoing claims is not intended to abandon such subject matter, nor should it be considered that the applicant has not considered such subject matter as part of the disclosed inventive subject matter.

Claims

1. An adaptive timing calibration method based on an adaptive SPI interface device, characterized in that, The adaptive SPI interface device includes a master device interface and a slave device interface; The master device interface and / or the slave device interface includes a data buffer, a clock source, an interface controller, a training verification sequence, a training reception register, and an interface timing circuit; The training verification sequence is interconnected with the training reception register, the training reception register is interconnected with the data buffer, the data buffer is interconnected with the interface timing circuit, and the output end of the interface controller is respectively connected to the data buffer, the interface timing circuit, and the input end of the clock source; Adaptive timing calibration method Includes the following Process: After the master device interface and the slave device interface are connected, when the master device interface is used as the adaptive end: S1. The master and slave device interfaces enter the calibration mode. The master device interface initiates calibration, and the slave device interface responds to the calibration; S2. The master device interface sequentially configures multiple SPI modes; S3. The master device interface configures the clock phase to the standard phase, that is, the clock edge is aligned with the data change; S4. The master device interface writes data to the slave device interface and receives the data from the slave device interface; S5. The master device interface determines the consistency of the written and read data. If they are inconsistent, return to S2 and switch to the next SPI mode. If they are consistent, continue to the next step; S6. The master device interface sequentially configures the clock phase to be advanced and delayed, that is, the clock edge is advanced or delayed by a certain phase relative to the data change edge; S7. The master device interface writes data to the slave device interface and receives the data from the slave device interface; S8. The master device interface determines the consistency of the written and read data. If they are inconsistent, return to S2 and switch to the next SPI mode. If they are consistent, end the adaptive mode; S9. The master device interface is configured with standard phase parameters for normal SPI communication; When the slave device interface is used as the adaptive end, the adaptive process is the same as that of the master device interface.

2. The adaptive timing calibration method according to claim 1, wherein When the master device interface and the slave device interface are connected in a four-wire system, the clock source inputs or outputs a clock signal, and the interface timing circuit inputs or outputs a chip select signal, a master out slave in signal, and a master in slave out signal.

3. The adaptive timing calibration method according to claim 1, wherein When the master device interface and the slave device interface are connected in a three-wire system, the self-clock source inputs or outputs a clock signal, and the interface timing circuit inputs or outputs a chip select signal and a bidirectional data signal.

4. The adaptive timing calibration method according to claim 1, wherein The master device interface is connected to a master device, and the slave device interface is connected to a slave device; The master device and the slave device adopt an FPGA, an MCU, a DSP, a CPU, a GPU, a CPLD, a FLASH, a PLL, an ADC, a DAC, an amplifier, an attenuator, a transceiver, or a sensor.

5. The adaptive timing calibration method according to claim 1, characterized in that The SPI modes are 0, 1, 2, and 3.

6. The adaptive timing calibration method according to claim 1, wherein The advanced or delayed time is 1 / 8 or 1 / 4 clock.

7. The adaptive timing calibration method according to claim 1, wherein The specific process of S4 is as follows: In the first frame, the master device interface sends a training verification sequence to the slave device interface. The slave device interface writes the received and sampled sequence into the training reception register of the slave device interface according to its set timing. In the second frame, the master device interface reads the received and sampled sequence from the slave device interface. The slave device interface transmits the data in the training reception register to the master device interface according to its set timing. The master device interface receives the data according to the SPI mode and stores it in the training reception register of the master device interface.

8. The adaptive timing calibration method according to claim 7, wherein The specific process of S5 is as follows: After receiving is completed, the interface controller of the master device interface compares the training receive register with the previously transmitted training check sequence. If the transmitted data and the received data are the same, the timing configuration is considered valid.

9. The adaptive timing calibration method according to claim 1, wherein If the written and read data are inconsistent in all SPI modes, replace the master device interface.

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