Chip unit layout optimization method, device and equipment and readable storage medium

Abstract

The application discloses a chip unit layout optimization method, device and equipment and a readable storage medium. The method comprises the following steps: obtaining overall layout data of a chip unit; determining a plurality of unit regions where the chip unit is located according to the overall layout data, and determining the pin density of each unit region; determining whether the pin density is greater than a preset density; if yes, diffusing the chip unit in the unit region with the pin density greater than the preset density to other unit regions, and returning to the step of determining whether the pin density is greater than the preset density until the pin density of each unit region is less than or equal to the preset density. The application realizes the following: starting from the overall situation of the chip unit layout, respectively determining the pin density in each unit region, diffusing the chip unit in the unit region with the pin density greater than the preset density to other unit regions, reducing the pin density of the unit region, and reducing the wiring cost.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of chip integrated circuit design, in particular to a chip unit layout optimization method, device and equipment and readable storage medium. BACKGROUND

[0002] The development of integrated circuits follows Moore's Law, that is, the scale of integrated circuits in chips increases over time. In the electronic design automation of modern high-performance chips, the Pin Access (connection between pins of units) problem becomes more difficult and important with the significant increase in the scale of integrated circuits in chips, especially in the detailed routing link of the entire physical implementation process.

[0003] The Pin Access problem may cause many design rule violations (DRC) and increase the routing cost that should not have occurred. However, since the business of different links in the entire physical design process is different and relatively independent, the position of the chip unit is fixed in the subsequent routing stage, so this problem cannot be completely solved by the routing tool. At the same time, the optimization of Pin Access capability is a very detailed problem, so it is a very good choice to adjust and optimize this problem in the detailed layout link.

[0004] However, the existing chip unit layout optimization scheme almost all optimizes the position and direction of the chip unit by designing a dynamic programming algorithm in a single row to minimize the target cost function designed in the scheme, and does not consider the Pin Access problem from a global perspective. There will still be situations where additional connections are needed due to conflicts between pins when connecting lines, or there will be too many conflicts between pins, resulting in high routing costs. SUMMARY

[0005] Therefore, the present application provides a chip unit layout optimization method, device, equipment and readable storage medium, which aims to improve the optimization effect of chip pin connection to reduce the routing cost and design rule violation.

[0006] To achieve the above-mentioned purpose, the present application provides a chip unit layout optimization method, which comprises the following steps:

[0007] Obtain the overall layout data of the chip unit;

[0008] According to the overall layout data, determine a plurality of unit regions in which the chip unit is located, and determine the pin density of each unit region;

[0009] Determine whether the pin density is greater than a preset density;

[0010] If greater, then diffusing the chip units in the unit region with the pin density greater than the preset density to other unit regions, and returning to the step of determining whether the pin density is greater than the preset density until each pin density is less than or equal to the preset density.

[0011] For example, the step of, if greater, then diffusing the chip units in the unit region with the pin density greater than the preset density to other unit regions, comprises:

[0012] If greater, then taking the unit region with the pin density greater than the preset density as a supply node, and taking the unit region with the pin density less than or equal to the preset density as a demand node;

[0013] According to a preset path algorithm, determining a traffic diffusion path for reducing the pin density between the supply node and the demand node;

[0014] According to the traffic diffusion path, diffusing the chip units in the unit region with the pin density greater than the preset density to other unit regions.

[0015] For example, the preset path algorithm comprises a breadth search algorithm and a depth search algorithm, and the step of, according to a preset path algorithm, determining a traffic diffusion path for reducing the pin density between the supply node and the demand node, comprises:

[0016] Generating a traffic network from the supply node to the demand node, and adding a virtual source node and a virtual sink node in the traffic network to obtain a network flow graph;

[0017] According to a breadth search algorithm, determining same-layer nodes in the network flow graph, and according to the same-layer nodes, performing layered processing on the network flow graph to obtain a multi-layer network;

[0018] According to a depth search algorithm, layer by layer searching for the path of the traffic from the virtual source node to the virtual sink node in the multi-layer network, if searching to the virtual sink node, then determining the path as an augmented path, and adding a reverse edge of the path to backtrack from the virtual node to the virtual source node;

[0019] After backtracking, returning to the step of, layer by layer searching for the path of the traffic from the virtual source node to the virtual sink node, until no new path can be found after backtracking;

[0020] When no new path can be found after backtracking, performing secondary layered processing on the multi-layer network, if a virtual sink node in the network layer after the secondary layered processing cannot be determined according to the depth search algorithm, then taking the augmented path that has been found as a traffic diffusion path.

[0021] Exemplarily, if the pin density is greater than the preset density, the chip units in a unit region with the pin density greater than the preset density are diffused to other unit regions, and the step of determining whether the pin density is greater than the preset density is returned to until the step of determining whether the pin density is greater than the preset density is performed after each pin density is less than or equal to the preset density, and the step of determining whether the pin density is greater than the preset density is performed again.

[0022] The chip units distributed in the same row are determined, and a conflict region in which the chip units exist is determined.

[0023] According to the conflict region, a position of a chip unit causing a conflict or an arrangement order of pins of the chip unit causing the conflict is adjusted.

[0024] The influence degree of the conflict between the adjusted chip units is calculated, and a probability of causing a conflict between all the chip units is counted.

[0025] If the probability does not meet a preset requirement or a current adjustment number is less than or equal to a preset iteration threshold, the step of determining the chip units distributed in the same row and determining the conflict region in which the chip units exist is returned to until the probability meets the preset requirement or the current adjustment number is equal to the preset iteration number.

[0026] Exemplarily, the step of calculating the influence degree of the conflict between the adjusted chip units includes:

[0027] The distance between adjacent chip units and the conflict regions of the adjacent chip units are determined to determine an overlapping area of the conflict regions between the adjacent chip units.

[0028] The number of pin connection points corresponding to adjacent edges between the adjacent chip units is determined.

[0029] According to the number of pin connection points, the distance and the overlapping area, the influence of the connection pins between the adjacent chip units is calculated.

[0030] Exemplarily, the step of obtaining the overall layout data of the chip units includes:

[0031] Position information of the chip units is obtained, and distribution information of pins arranged on the chip units is obtained.

[0032] The position information and the distribution information are input to the router, so that the router determines a connection point position of the pins according to the position information and the distribution information, and determines a conflict region between the chip units according to the connection point position, wherein the overall layout data includes the position information, the distribution information, the connection point position and the conflict region.

[0033] Exemplarily, the method further includes:

[0034] In the updating of the positions of the chip units, position coordinates of the chip units updated in sequence are determined, and a conflict area of the chip units is determined;

[0035] According to the position coordinates and the conflict area, a movement of the conflict area of the chip units updated in sequence is calculated, and a movement distance of the chip units is calculated;

[0036] If the movement and the movement distance satisfy a preset constraint condition, it is determined that the current update is legal.

[0037] Exemplarily, to achieve the above-mentioned purpose, the present application further provides a chip unit layout optimization device, which comprises:

[0038] An acquisition module is configured to acquire overall layout data of chip units;

[0039] A determination module is configured to determine a plurality of unit areas where the chip units are located according to the overall layout data, and determine a pin density of each unit area;

[0040] A judgment module is configured to determine whether the pin density is greater than a preset density;

[0041] A diffusion module is configured to diffuse the chip units in the unit area with the pin density greater than the preset density to other unit areas if the pin density is greater than the preset density, and return to the step of determining whether the pin density is greater than the preset density until each pin density is less than or equal to the preset density.

[0042] Exemplarily, to achieve the above-mentioned purpose, the present application further provides a chip unit layout optimization device, which comprises a memory, a processor and a chip unit layout optimization program stored in the memory and executable on the processor, and the chip unit layout optimization program is configured to implement the steps of the chip unit layout optimization method as described above.

[0043] Exemplarily, to achieve the above-mentioned purpose, the present application further provides a computer readable storage medium, which stores a chip unit layout optimization program, and the chip unit layout optimization program is executable on a processor to implement the steps of the chip unit layout optimization method as described above.

[0044] Compared with the related art, the pin access problem is not considered globally, and the conflict of pins when connecting lines still needs to be additionally connected, or there are too many conflicts between pins, resulting in high wiring cost. In the present application, the overall layout data of the chip unit is obtained; according to the overall layout data, a plurality of unit regions where the chip unit is located are determined, and the pin density of each unit region is determined; it is determined whether the pin density is greater than the preset density; if it is greater than, the chip unit in the unit region with pin density greater than the preset density is diffused to other unit regions, and the step of determining whether the pin density is greater than the preset density is returned, until each pin density is less than or equal to the preset density, that is, starting from the overall layout data of the chip unit, the pin density of the plurality of unit regions where the chip unit is located is calculated, and it is judged whether the pin density meets the preset density, the distribution position of the chip unit in the plurality of unit regions is adjusted, that is, the unit in the unit region with pin density greater than the preset density is diffused to other unit regions, until each pin density is less than or equal to the preset density, so as to reduce the density of each chip unit in each unit region, and then realize the reduction of the pin density in each unit region, that is, according to the size of the pin density of each unit region, the distribution position of each chip unit is adaptively controlled to avoid the conflict between the chip units, so as to realize the effect of adaptively adjusting the distribution position of the chip unit according to the overall layout of the chip unit, and then reduce the conflict existing between the chip units and the pins, avoid additional wiring mode, and thus realize the effect of reducing the wiring cost. BRIEF DESCRIPTION OF DRAWINGS

[0045] Figure 1 The flowchart of the first embodiment of the chip unit layout optimization method of the present application;

[0046] Figure 2 The overall layout data diagram of the chip unit of the chip unit layout optimization method of the present application;

[0047] Figure 3 The adjustment diagram of the in-line chip unit of the chip unit layout optimization method of the present application;

[0048] Figure 4 The flowchart of the second embodiment of the chip unit layout optimization method of the present application;

[0049] Figure 5 The node conversion diagram of the chip unit layout optimization method of the present application;

[0050] Figure 6 The schematic diagram of the network flow graph of the chip unit layout optimization method of the present application;

[0051] Figure 7A structural schematic diagram of a hardware running environment involved in an embodiment of the present application.

[0052] The implementation, functional features and advantages of the present application will be further described with reference to the embodiments and the accompanying drawings. DETAILED DESCRIPTION

[0053] It should be understood that the specific embodiments described herein are merely illustrative of the present application and do not limit the present application.

[0054] The present application provides a chip unit layout optimization method, with reference to Figure 1 , Figure 1 A flowchart of a first embodiment of the chip unit layout optimization method of the present application.

[0055] Embodiments of the chip unit layout optimization method are provided in the present application. It should be noted that although a logical order is shown in the flowchart, in some cases, the steps shown or described herein can be performed in an order different from that shown herein. In order to facilitate description, the following omits the description of the execution subject of each step of the chip unit layout optimization method, and the chip unit layout optimization method includes:

[0056] Step S110: obtaining overall layout data of a chip unit;

[0057] Since the conflict problem of Pin Access can be accurately located only in the routing process, if Pin Access is considered in the detailed layout stage, a suitable Pin Access conflict model and Pin Access point identification strategy are needed, therefore, the overall layout data of the chip unit can be obtained in advance to establish the corresponding Pin Access conflict model, and the layout and routing are designed to optimize the level.

[0058] Illustratively, the step of obtaining the overall layout data of the chip unit includes:

[0059] Step a: obtaining position information of the chip unit and distribution information of pins arranged on the chip unit;

[0060] The position information of the chip unit and the distribution information of the pins arranged on the chip unit can be obtained from the manufacturer of the chip. The positions of the units and pins distributed on the chip are known data when the chip is shipped.

[0061] Step b: inputting the position information and the distribution information into the router, so that the router determines the via point positions of the pins according to the position information and the distribution information, and determines the conflict areas between the chip units according to the via point positions, wherein the overall layout data comprises the position information, the distribution information, the via point positions and the conflict areas.

[0062] After obtaining the position information and the distribution information, the pin via information of the current chip unit can be analyzed and evaluated by the router, for example, the current pin distribution is determined, the positions of the via points are determined, or the position information and the distribution information of the current chip unit are determined, and the difficulty of the current pin via is determined.

[0063] For example, when the position information and the distribution information are input into the router, the router can determine the specific positions of the routing tracks and the relative positions of the routing tracks between the chip units according to the routing tracks specified by the LEF file. The distance between the tracks is strongly related to the advancement of the process node. The LEF file is a data file, which is a layout parameter for defining the specific positions of the routing tracks.

[0064] For example, the intersection of the pins in the chip unit and the routing tracks is considered as a connectable point. The cost of via is the highest at these points, and the cost of routing is less. The Pin Access analysis in the routing link will preferentially consider these points and the surrounding conditions to determine the legality and select accurate via points.

[0065] For example, the conflict area is prone to occur around the chip unit. The size of this area is set according to the information provided by the router engine. If the router believes that the shape of the pins in a certain type of chip unit is difficult to connect, the conflict area will be larger, and vice versa. The conflict area will be used as a constraint throughout the optimization process and will be used for cost function calculation.

[0066] For example, in high-performance chip physical design, there are some pins in some chip units that do not have any intersection with the routing tracks. Therefore, a wire mesh patch needs to be added to these pins to enhance the connectivity of these pins and further improve the accuracy of Pin Access point selection.

[0067] The specific conditions of the overall layout data of the chip unit determined by the router can refer to Figure 2 .

[0068] Step S120: determining a plurality of unit areas in which the chip units are located according to the overall layout data, and determining the pin density of each unit area;

[0069] In the overall layout data, the layout of the chip unit is optimized, and the position of the chip unit is classified, for example, the area involved in the same chip is divided into multiple chip unit areas, and the specific situation of the divided area needs to be combined with the actual position information of the chip unit to limit the specific size of each divided unit area.

[0070] The conflict between the chip units is negatively related to the distance between the chip units, for example, the closer the positions of two chip units, the greater the possibility of conflict, therefore, in order to avoid the probability of conflict, it is necessary to consider reducing the distance between the chip units, and from the overall layout consideration, that is, the layout density of the chip unit needs to be considered from a macro perspective, for example, the more chip units in the same size unit area, the greater the probability of conflict, therefore, the number of chip units in each unit area can be adaptively reduced, thereby reducing the density (chip unit area divided by unit area), further, the number of pins on the chip unit can be considered, the greater the pin area, the more the number of contact points distributed on it, the more the number of contact points, the more the wiring needed, the greater the possibility of conflict, therefore, the pin density (pin area divided by unit area) is considered to reduce the conflict probability of the chip unit.

[0071] Step S130: if the pin density is greater than the preset density, the chip units in the unit area with pin density greater than the preset density are diffused to other unit areas, and the step of determining whether the pin density is greater than the preset density is returned, until each pin density is less than or equal to the preset density.

[0072] When the pin density is greater than the preset density, it can be proved that the area of the pin in the unit area corresponding to the pin density is too large, therefore, the pin density in the corresponding unit area needs to be adjusted, that is, the chip unit needs to be adjusted (the pin is arranged on the chip unit), that is, the pin density of each unit area is controlled to be less than or equal to the preset density.

[0073] The preset density can be determined according to the number of chip units on the actual chip and the number of unit areas.

[0074] And in the process of spreading the chip units in the unit area to other unit areas, since the essence of reducing the density is to reduce the density of pins, and in order to reduce the density of pins, the chip units need to be spread (moved or adjusted position), therefore, there will be a certain conflict, that is, the density of pins that need to be reduced (which can be determined according to the area of the pins, and the area of the pins needs to be converted into a certain number of pins), that is, a certain number of pins need to be finally determined to be moved, and there may not be a chip unit that meets the moving requirements in terms of both area and number, so there will be a certain deviation.

[0075] In order to avoid the deviation of pins and chip units due to movement, the spreading effect needs to be evaluated after each spread, that is, after each spread, it is determined whether the pin density of each unit area after spreading is less than or equal to the preset density, if it is less than or equal to, the spreading and judgment action can be stopped, and the optimization action is completed.

[0076] For example, if it is greater than, the chip units in the unit area with pin density greater than the preset density are spread to other unit areas, and the step of determining whether the pin density is greater than the preset density is returned, until each pin density is less than or equal to the preset density, including:

[0077] Step c: determining the chip units distributed in the same row, and determining the conflict area where the chip units exist;

[0078] For example, a local search algorithm is designed, a sliding window is specifically set, and the corresponding chip units distributed in the same row are determined through the sliding window, and the conflict area where the chip units exist is further determined, that is, the position or layout of the chip units can be adjusted according to the conflict area, where the overlap of the conflict area or the distance between the conflict areas is too small can cause the conflict between the chip units, and the position or layout of the chip units can be adjusted by adjusting the left and right positions of the chip units in the row, or adjusting the layout order of the pins in the chip.

[0079] Step d: adjusting the position of the chip units corresponding to the conflict area or adjusting the pin arrangement order of the chip units corresponding to the conflict area;

[0080] The chip cell reordering and flipping in a single row, "perturbation" in a sliding window of a specified size, reduces the area of the overlapping conflict region, minimizes the probability of pin conflict, optimizes the cell position, and further converges the results of global optimization. Among them: (1) cell reordering: by reordering the cells, the relative order between the cells is changed to reduce the conflict probability of the cells; (2) cell flipping: by flipping the cells left and right without changing the coordinates of the cells, the positions of the pins in the mirrored cells are changed, which indirectly alleviates the conflict between the left and right regions of the cells, which will be described in detail with reference to Figure 3 .

[0081] Step e: Calculate the conflict impact degree between the adjusted chip cells, and count the probability of conflict between all chip cells;

[0082] The conflict impact degree of the chip cells can be designed according to the distance between the chip cells and the pin contact points on the chip cells to design a corresponding objective function, so as to determine the specific conflict impact degree between the chip cells by solving the objective function. The closer the distance, the greater the impact degree, and the greater the number of pin contact points, the greater the impact degree.

[0083] After calculating the conflict impact degree, the probability of conflict between all chip cells can be further calculated, that is, the greater the conflict impact degree, the greater the conflict probability.

[0084] For example, the step of calculating the conflict impact degree between the adjusted chip cells includes:

[0085] Step f: Determine the distance between adjacent chip cells and the conflict regions of the adjacent chip cells, respectively, to determine the overlapping area of the conflict regions between the adjacent chip cells;

[0086] Step g: Determine the number of pin contact points corresponding to the adjacent edges between the adjacent chip cells;

[0087] Step h: According to the number of pin contact points, the distance and the overlapping area, calculate the conflict impact of the pin contact between the adjacent chip cells.

[0088] The objective function is specifically: used to calculate the cost of Pin Access between adjacent cells, which indirectly describes the influence degree of the Pin Access ability of the chip cells by the adjacent cells.

[0089]

[0090] Among them:

[0091] (1) The number of Pin Access points representing the boundary of the adjacent chiplet close to the current chiplet;

[0092] (2) area CRO The area of the conflict region of two adjacent chiplets, which is usually greater than 0;

[0093] (3) dist i，i+1 The distance between chiplets c i , c i+1 , where the probability of Pin Access conflict is negatively correlated with the distance between the two adjacent units c i , c i+1 The specific distribution example can refer to Figure 2 .

[0094] Step i: If the probability does not meet the preset requirement or the current adjustment number is less than or equal to the preset iteration threshold, return to the step of determining the chiplets distributed in the same row and determining the conflict region of the chiplets, until the probability meets the preset requirement or the current adjustment number is equal to the preset iteration number.

[0095] The single-row design local search algorithm optimizes the position and direction of the chiplets, so that the probability of conflict between adjacent chiplets when performing Pin Access is minimized:

[0096] (1) Construct an initial solution S: according to the constraints of the conflict region, form a better initial solution S = {x1, x2, …, x i , …, x n};

[0097] (2) Define the neighborhood δ(S) of S: in a given sliding window, select an i-th unit for unit flipping or modification of the order, and perform perturbation, i.e.: x i → x′ i ;

[0098] (3) Search for a new solution S' = {x1, x2, …, x i , …, x n} in the neighborhood δ(S);

[0099] (4) Let S = S', repeat the above steps until the termination condition is met: when the iteration number reaches the upper limit, or the unit position of the single row meets the minimum conflict probability, then terminate.

[0100] Compared with the related art, the pin access problem is not considered globally, and the conflict of pins in the connection line still needs to be additionally connected, or there are too many conflicts between the pins, resulting in a high wiring cost. In the present application, the overall layout data of the chip unit is obtained; according to the overall layout data, a plurality of unit regions in which the chip unit is located are determined, and the pin density of each unit region is determined; it is determined whether the pin density is greater than the preset density; if it is greater, the chip unit in the unit region with the pin density greater than the preset density is diffused to other unit regions, and the step of determining whether the pin density is greater than the preset density is returned, until each pin density is less than or equal to the preset density, that is, starting from the overall layout data of the chip unit, the pin density of the plurality of unit regions in which the chip unit is located is calculated, and it is judged whether the pin density meets the preset density, the distribution position of the chip unit in the plurality of unit regions is adjusted, that is, the unit in the unit region with the pin density greater than the preset density is diffused to other unit regions, until each pin density is less than or equal to the preset density, thereby reducing the density of each chip unit in each unit region, and further realizing the reduction of the pin density in each unit region, that is, according to the size of the pin density of each unit region, the distribution position of each chip unit is adaptively controlled to avoid the conflict between the chip units, thereby realizing the effect of adaptively adjusting the distribution position of the chip unit according to the overall layout of the chip unit, and further reducing the conflict between the chip units and the pins, avoiding additional wiring mode, and thus realizing the effect of reducing the wiring cost.

[0101] For example, referring to Figure 4 , Figure 4 is a flowchart of the second embodiment of the chip unit layout optimization method of the present application, based on the first embodiment of the chip unit layout optimization method of the present application, the second embodiment is proposed, the method further comprises:

[0102] Step S210: If it is greater, the unit region with the pin density greater than the preset density is taken as a supply node, and the unit region with the pin density less than or equal to the preset density is taken as a demand node;

[0103] When diffusing the chip unit in the unit region with the pin density greater than the preset density, the overall diffusion trend is to diffuse the chip unit in the unit region with the pin density greater than the preset density to the unit region with the pin density less than or equal to the preset density, at the same time, the cost required when diffusing is also considered, the chip unit can be first diffused to the unit region with the pin density greater than the preset density, and further diffused to the unit region with the pin density less than or equal to the preset density.

[0104] Therefore, the unit region with the pin density greater than the preset density can be taken as a supply node, and the unit region with the pin density less than or equal to the preset density can be taken as a demand node, and a diffusion trend is set to be from the supply node to other supply nodes or to the demand node, wherein, according to the diffusion direction, an edge between the supply node and other supply nodes or the demand node can be connected, and the flow is provided from the supply node outwardly, and details can be referred to Figure 5 .

[0105] For example, the probability of conflict occurring when the pin is connected is positively correlated with the number of pins in a unit area (i.e., the density of the pins), so that the units in the region with high density can be moved to the region with low density, thereby indirectly optimizing the pin connection capability. The pin positions in the chip units are analyzed and mapped, and here, the supply node (high density) and the demand node (low density) are set according to the different connection point numbers of each pin, and a minimum cost maximum flow problem is formed.

[0106] Step S220: determining a flow diffusion path for reducing the pin density between the supply node and the demand node according to a preset path algorithm.

[0107] According to the solution mode of the minimum cost maximum flow problem, the flow and the cost (expense) in the diffusion of the chip units need to be determined, therefore, the diffusion cost of the chip units is usually calculated first, and the corresponding flow is formed, that is, when the flow is calculated, the cost corresponding to the current flow is known, so that the flow diffusion path in the case of the maximum flow under the minimum cost condition can be further determined, and the flow diffusion path is the path of the minimum cost maximum flow in the diffusion of the chip units between the nodes.

[0108] The cost is calculated according to the number of moved chip units and the conflict probability after the chip units are moved.

[0109] The preset path algorithm is a path augmentation algorithm suitable for the current minimum cost maximum flow.

[0110] For example, the preset path algorithm includes a breadth-first search algorithm and a depth-first search algorithm, and the step of determining the flow diffusion path for reducing the pin density between the supply node and the demand node according to the preset path algorithm includes:

[0111] Step j: generating a flow network from the supply node to the demand node, and adding a virtual source node and a virtual sink node in the flow graph to obtain a network flow graph;

[0112] Before using the preset path algorithm, the graph composed of the supply node and the demand node needs to be abstracted into a network flow graph as Figure 6The network flow diagram is shown, and then an improved algorithm based on DINIC+SPFA is adopted to improve the processing of the flow of the edge, to give priority to the unit, and to convert the flow from the pin number to the chip unit number.

[0113] Wherein, the essence of DINIC is to solve the process by BFS (breadth-first search) and DFS (depth-first search), BFS is used for layering and DFS is used for augmentation, and DINIC (maximum flow) + SPFA (cost flow) is to replace the original simple BFS in DINIC with SPFA (Shortest Path Faster Algorithm), and in fact, SPFA is a queue implementation of Bellman-Ford (processing negative weight edge unit shortest path problem) algorithm, which reduces unnecessary redundant calculation.

[0114] In order to obtain the solution of the minimum cost maximum flow, a corresponding source node and sink node are added outside the supply node and demand node, and the source node and sink node are virtual nodes.

[0115] Step k: according to the breadth search algorithm, the same layer nodes in the network flow diagram are determined, and the network flow diagram is processed by layering according to the same layer nodes, to obtain a multi-layer network;

[0116] The preset path algorithm includes a breadth search algorithm and a depth search algorithm, that is, first, the BFS is used to layer the residual network, and the depth of a node is the number of edges from the source point to the node.

[0117] The BFS is used to layer the residual network (converted from the network flow diagram), and after layering, a multi-layer network is obtained, and then the DFS is used to repeatedly find an augmented path from the previous layer to the next layer.

[0118] Step l: according to the depth search algorithm, the path of the flow is found in the multi-layer network from the virtual source node to the virtual sink node layer by layer in the direction, if the virtual sink node is found, the path is determined as an augmented path, and the reverse edge of the path is increased to trace back from the virtual node to the virtual source node;

[0119] After layering, the DFS is used to repeatedly find an augmented path from the previous layer to the next layer from the source point (that is, each step of the DFS must reach the node of the next layer). Therefore, when layering, the number of layers to the sink node is calculated and the layering is stopped, because according to the DFS rule, the node of the sink node layer or the next layer is impossible to reach the sink node.

[0120] In the process of DFS, if a sink is encountered, it means that an augmenting path is found. At this time, the total flow value is increased, the capacities of the edges in the path are reduced, and the reverse edges are added, i.e., the so-called augmenting.

[0121] Step m: after backtracking, return to the step of finding the path of the flow layer by layer from the virtual source node to the virtual sink node, until a new path cannot be found after backtracking;

[0122] After DFS finds an augmenting path, it does not end immediately, but continues to find the next augmenting path after backtracking. If it backtracks to the source point and cannot continue to walk down, DFS ends. Therefore, in one DFS process, multiple augmenting paths can be found.

[0123] Step n: when a new path cannot be found after backtracking, the multi-layer network is processed for secondary layering, and if the virtual sink node in the network layer after secondary layering cannot be determined according to the depth search algorithm, the augmenting path that has been found is taken as the flow diffusion path.

[0124] The capacity on the tree edge (u, v) of the DFS search tree has become 0. That is, the flow added on the augmenting path just found is equal to the capacity of (u, v) before this augmentation (in the process of DFS, it is from u to the lower layer v).

[0125] After DFS ends, the residual network is layered again, and then DFS is performed. When the layering operation of the residual network cannot calculate the level of the sink (i.e., BFS cannot reach the sink), the algorithm ends, the maximum flow is calculated, and the augmenting path that has been found is taken as the flow diffusion path. Further, before determining the flow diffusion path, the corresponding cost is calculated in advance, thereby forming the flow. Therefore, the flow diffusion path of the maximum flow is calculated, and according to the path, the corresponding chip unit can be diffused.

[0126] Step S230: according to the flow diffusion path, diffusing the chip units in the unit area with a pin density greater than the preset density to other unit areas.

[0127] After determining the flow diffusion path, the chip units in the unit area with a pin density greater than the preset density are diffused to other unit areas, and the pin density of each unit area is ensured to be less than or equal to the preset density, i.e., the pin density converges, and the optimization process of diffusing the chip units is completed.

[0128] In the embodiment, if the pin density is greater than the preset density, the unit region with the pin density greater than the preset density is taken as a supply node, and the unit region with the pin density less than or equal to the preset density is taken as a demand node; a traffic diffusion path for reducing the pin density between the supply node and the demand node is determined according to a preset path algorithm; and the chip units in the unit region with the pin density greater than the preset density are diffused to other unit regions according to the traffic diffusion path, that is, by converting the problem of diffusing the chip units into the problem of calculating the minimum cost maximum flow, and according to the nodes corresponding to each unit region, the traffic diffusion path is calculated, so that the diffusion effect and accuracy of the chip units are improved according to the diffusion manner of the chip units according to the traffic diffusion path, the conflict probability between the chip units is reduced, and the wiring cost is further reduced.

[0129] For example, based on the first embodiment and the second embodiment of the chip unit layout optimization method, a third embodiment is provided, and the method further includes:

[0130] Step o: when the positions of the chip units are updated, the position coordinates of the chip units updated in sequence are determined, and the conflict region of the chip units is determined;

[0131] Step p: according to the position coordinates and the conflict region, the movement of the conflict region of the chip units updated in sequence is calculated, and the movement distance of the chip units is calculated;

[0132] In the whole Pin Access detailed layout optimization process, in order to ensure the effectiveness or reliability of the optimization process, a legality judgment needs to be performed on each optimization process (adjusting or diffusing the distribution position of the chip units), that is, by designing a corresponding constraint formula, whether the data information of each optimization process is reasonable is judged, and an inequality constraint must be followed in the whole optimization process.

[0133] Constraints:

[0134]

[0135]

[0136] Wherein:

[0137] (1) x′ i , y′ i The initial coordinates of the chip units in the input legalization result, x i , y i represent the coordinates of the chip units after the movement optimization;

[0138] (2) Displacement is the moving amount of the chip cell, that is, the Manhattan distance between the new coordinates and the initial coordinates of the cell during the Pin Access optimization process;

[0139] (3) represents the width of the Pin Access conflict region on the right side of the chip cell c i ; represents the width of the Pin Access conflict region on the right side of the chip cell c i ; represents the width of the Pin Access conflict region on the left side of the chip cell c i ; represents the width of the Pin Access conflict region on the left side of the chip cell c i+1 ;

[0140] Step q: if the moving condition and the moving distance satisfy the preset constraint condition, it is determined that the current update is legal.

[0141] In the optimization process, if the moving condition and the moving distance satisfy the preset constraint condition, it is determined that the current update process is legal, that is, each adjustment process needs to follow the constraint inequality.

[0142] In addition, in addition to controlling the legalization of the optimization process by the constraint inequality, adaptive global legalization needs to be added. The global legalization eliminates the overlap of all chip cells in the entire layout and keeps the chip cells aligned with the power rail, while minimizing the total moving amount of the chip cells in the legalization process. Legalization not only needs to be applied after the global layout, but also needs to be applied after incremental optimization steps such as detailed layout, gate size adjustment, and buffer insertion. However, applying global legalization after such incremental optimization is too time-consuming and is not conducive to protecting the optimized results, so after these incremental optimizations are completed, we need to incrementally legalize, that is, by locally adjusting the position of the chip cell to eliminate the overlap after each chip cell transformation, and finally keep it legal.

[0143] In the embodiment, the legalization constraint limit is designed for the actual optimization process, so that the corresponding inequality judgment is performed for each optimization process, thereby ensuring the legalization of updating the position information of the chip cell or adjusting the layout information of the pins on the chip cell each time, avoiding new conflicts caused by the update process, thereby reducing the conflict probability, and thus avoiding the cost demand during wiring.

[0144] In addition, the application also provides a chip cell layout optimization device, which comprises:

[0145] an acquisition module configured to acquire overall layout data of chip cells;

[0146] determining a plurality of cell regions where the chip units are located according to the overall layout data, and determining a pin density of each cell region;

[0147] determining whether the pin density is greater than a preset density;

[0148] spreading the chip units in the cell region with the pin density greater than the preset density to other cell regions if greater, and returning to the step of determining whether the pin density is greater than the preset density until each pin density is less than or equal to the preset density.

[0149] Exemplarily, the spreading module comprises:

[0150] determining a cell region with the pin density greater than the preset density as a supply node, and a cell region with the pin density less than or equal to the preset density as a demand node if greater;

[0151] determining a traffic spreading path between the supply node and the demand node for reducing the pin density according to a preset path algorithm;

[0152] spreading the chip units in the cell region with the pin density greater than the preset density to other cell regions according to the traffic spreading path.

[0153] Exemplarily, the determining module comprises:

[0154] generating a traffic network from the supply node to the demand node, and adding a virtual source node and a virtual sink node in the traffic graph to obtain a network flow graph;

[0155] determining same-layer nodes in the network flow graph according to a breadth search algorithm, and performing layered processing on the network flow graph according to the same-layer nodes to obtain a multi-layer network;

[0156] finding a path of the traffic from the virtual source node to the virtual sink node in the multi-layer network layer by layer according to a depth search algorithm, determining the path as an augmented path if the virtual sink node is found, and adding a reverse edge of the path to backtrack from the virtual node to the virtual source node;

[0157] returning to the step of finding the path of the traffic from the virtual source node to the virtual sink node layer by layer until a new path cannot be found after backtracking;

[0158] A hierarchical unit is configured to perform secondary hierarchical processing on the multi-layer network when no new path can be found after backtracking, and if the virtual sink node in the network layer after secondary hierarchical processing cannot be determined according to the depth search algorithm, the found augmented path is taken as a traffic diffusion path.

[0159] The device further includes, for example:

[0160] A chip unit determination module is configured to determine chip units distributed in the same row and determine a conflict area where the chip units exist;

[0161] An adjustment module is configured to adjust the positions of the chip units that cause conflicts or adjust the pin arrangement order of the chip units that cause conflicts according to the conflict area;

[0162] A first calculation module is configured to calculate the conflict influence degree between the adjusted chip units and count the probability of conflicts between all chip units;

[0163] A loop module is configured to return to the step of determining the chip units distributed in the same row and determining the conflict area where the chip units exist if the probability does not meet a preset requirement or the current adjustment number is less than or equal to a preset iteration threshold, until the probability meets the preset requirement or the current adjustment number is equal to the preset iteration number;

[0164] An update module is configured to determine the position coordinates of the chip units in the order of updating when updating the positions of the chip units and determine the conflict area of the chip units;

[0165] A second calculation module is configured to calculate the movement of the conflict area of the chip units in the order of updating according to the position coordinates and the conflict area and calculate the movement distance of the chip units;

[0166] A constraint judgment module is configured to determine that the current update is legal if the movement and the movement distance meet a preset constraint condition.

[0167] The first calculation module includes, for example:

[0168] A second determination submodule is configured to determine the distance between adjacent chip units and the conflict areas of the adjacent chip units to determine the overlapping area of the conflict areas between the adjacent chip units;

[0169] A third determination submodule is configured to determine the number of pin connection points corresponding to adjacent edges between the adjacent chip units;

[0170] The calculating sub-module is configured to calculate the conflict influence of the pin connection points between the adjacent chip units according to the pin connection point quantity, the distance and the overlapping area.

[0171] The acquisition module includes, for example:

[0172] The acquisition sub-module is configured to acquire position information of the chip units and distribution information of pins arranged on the chip units.

[0173] The processing sub-module is configured to input the position information and the distribution information into the router, so that the router determines the pin connection point positions according to the position information and the distribution information, and determines the conflict areas between the chip units according to the pin connection point positions, wherein the overall layout data includes the position information, the distribution information, the pin connection point positions and the conflict areas.

[0174] The chip unit layout optimization device embodiment of the present application is basically the same as the above chip unit layout optimization method embodiments, and will not be repeated here.

[0175] In addition, the present application also provides a chip unit layout optimization device. As shown in Figure 7 , Figure 7 is a structural diagram of a hardware running environment related to the embodiment of the present application.

[0176] For example, Figure 7 , that is, the structural diagram of the hardware running environment of the chip unit layout optimization device.

[0177] As shown in Figure 7 , the chip unit layout optimization device can include a processor 701, a communication interface 702, a memory 703 and a communication bus 704, wherein the processor 701, the communication interface 702 and the memory 703 complete mutual communication through the communication bus 704, the memory 703 is used to store computer programs, and the processor 701 is used to execute the programs stored in the memory 703 to realize the steps of the chip unit layout optimization method.

[0178] The communication bus 704 mentioned above can be a peripheral component interconnect (PCI) bus or an extended industry standard architecture (EISA) bus, etc. The communication bus 704 can be divided into an address bus, a data bus and a control bus, etc. For the convenience of representation, only one thick line is shown in the figure, but it does not mean that there is only one bus or one type of bus.

[0179] The communication interface 702 is configured to communicate between the chip unit layout optimization device and other devices.

[0180] The memory 703 can include a random access memory (RAM) and can also include a non-volatile memory (NVM), such as at least one disk memory. Optionally, the memory 703 can also be at least one storage device located away from the aforementioned processor 701.

[0181] The aforementioned processor 701 can be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), etc. It can also be a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic device, discrete gate or transistor logic device, discrete hardware component.

[0182] The chip unit layout optimization device embodiment of the present application is basically the same as the aforementioned chip unit layout optimization method embodiments, and thus will not be described here again.

[0183] In addition, the present application also proposes a computer readable storage medium, and the computer readable storage medium stores a chip unit layout optimization program. When the chip unit layout optimization program is executed by a processor, the steps of the chip unit layout optimization method described above are implemented.

[0184] The computer readable storage medium embodiment of the present application is basically the same as the aforementioned chip unit layout optimization method embodiments, and thus will not be described here again.

[0185] It should be noted that in this document, the terms "comprising", "including", or any other variant thereof are intended to cover non-exclusive inclusion, so that processes, methods, articles, or systems including a series of elements not only include those elements, but also include other elements not explicitly listed, or inherent to such processes, methods, articles, or systems. Without more limitations, the element defined by the statement "including a" does not exclude the presence of other identical elements in the process, method, article, or system including the element.

[0186] The above application embodiment serial numbers are only for description, and do not represent the advantages and disadvantages of the embodiments.

[0187] Through the above description of the embodiments, those skilled in the art can clearly understand that the above-mentioned embodiment method can be realized by means of software and the necessary general hardware platform, of course, it can also be realized by hardware, but in many cases the former is a better embodiment. Based on such understanding, the technical solutions of the present application can be embodied in the form of a software product, which is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) as described above, and includes a plurality of instructions for making a terminal device (which can be a mobile phone, computer, server, or network device, etc.) execute the methods described in various embodiments of the present application.

[0188] The above is only the preferred embodiment of the present application, and does not limit the patent scope of the present application, and any equivalent structure or equivalent process transformation using the content of the present application specification and drawings, or direct or indirect application in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A chip unit layout optimization method, characterized in that: The chip unit layout optimization method comprises the following steps: Obtaining overall layout data of chip units; Determining, based on the overall layout data, a plurality of unit regions in which the chip unit is located, and determining a pin density of each unit region; Determining whether the pin density is greater than a preset density; If it is greater than, the chip units in the unit area where the pin density is greater than the preset density are diffused to other unit areas, and the process returns to the step of determining whether the pin density is greater than the preset density until each pin density is less than or equal to the preset density; If the pin density is greater than the preset density, the chip units in the unit area where the pin density is greater than the preset density are diffused to other unit areas, and the process returns to the step of determining whether the pin density is greater than the preset density until each pin density is less than or equal to the preset density, including: Determining chip units distributed in the same row and determining conflicting areas where the chip units exist; According to the conflicting area, adjusting the position of the chip unit corresponding to the conflict or adjusting the pin arrangement order of the chip unit generating the conflict; Calculate the impact of conflicts between the adjusted chip units and calculate the probability of conflicts between all chip units; If the probability does not meet the preset requirements or the current number of adjustments is less than or equal to the preset iteration threshold, return to the step of determining the chip units distributed in the same row and determining the conflicting areas where the chip units exist, until the probability meets the preset requirements or the current number of adjustments is equal to the preset iteration threshold.

2. The chip unit layout optimization method according to claim 1, wherein: If the density is greater than the preset density, the step of diffusing the chip units in the unit area where the pin density is greater than the preset density to other unit areas includes: If it is greater than, the unit area with a pin density greater than the preset density is used as a supply node, and the unit area with a pin density less than or equal to the preset density is used as a demand node; Determining, according to a preset path algorithm, a flow diffusion path between the supply node and the demand node that reduces the pin density; According to the flow diffusion path, the chip units in the unit area with a pin density greater than the preset density are diffused to other unit areas.

3. The chip unit layout optimization method according to claim 2, wherein: The preset path algorithm includes a width search algorithm and a depth search algorithm. The step of determining a flow diffusion path between the supply node and the demand node that reduces the pin density according to the preset path algorithm includes: generating a flow network from the supply node to the demand node, and adding a virtual source node and a virtual sink node to the flow network graph to obtain a network flow graph; Determine the same-layer nodes in the network flow graph according to a breadth search algorithm, and perform layered processing on the network flow graph based on the same-layer nodes to obtain a multi-layer network; According to a depth search algorithm, searching for a path of the traffic layer by layer in the multi-layer network from the virtual source node to the virtual sink node, and if the virtual sink node is found, determining that the path is an augmenting path, and adding a reverse edge to the path to trace back from the virtual node to the virtual source node; After backtracing, returning to the step of searching for a path for the traffic layer by layer from the virtual source node to the virtual sink node until no new path can be found after backtracing; When a new path cannot be found after backtracking, the multi-layer network is subjected to secondary layering processing. If the virtual sink node in the network layer after the secondary layering processing cannot be determined according to the deep search algorithm, the augmented path that has been found is used as the traffic diffusion path.

4. The chip unit layout optimization method according to claim 1, wherein: The step of calculating the conflict impact degree between the adjusted chip units includes: Determining the distance between adjacent chip units and the respective conflicting regions of the adjacent chip units to determine the overlapping areas of the conflicting regions between the adjacent chip units; Determining the number of pin connection points corresponding to adjacent sides between the adjacent chip units; The conflict impact of connecting pins between adjacent chip units is calculated based on the number, distance and overlapping area of ​​the pin connection points.

5. The chip unit layout optimization method according to claim 1, wherein: The step of obtaining the overall layout data of the chip unit includes: Obtaining location information of a chip unit and obtaining distribution information of pins provided on the chip unit; The position information and the distribution information are input into a router so that the router can determine the connection point position of the pin based on the position information and the distribution information, and determine the conflict area between the chip units based on the connection point position, wherein the overall layout data includes the position information, the distribution information, the connection point position and the conflict area.

6. The chip unit layout optimization method according to claim 1, wherein: The method further comprises: When updating the position of the chip unit, determining the updated position coordinates of the chip unit and determining the conflicting area of ​​the chip unit; Calculating the movement of the conflicting areas of the chip units before and after the update according to the position coordinates and the conflicting areas, and calculating the movement distance of the chip units; If the movement condition and the movement distance meet the preset constraint conditions, it is determined that the current update is legal.

7. A chip unit layout optimization device, characterized in that: The chip unit layout optimization device comprises: An acquisition module, used to obtain the overall layout data of the chip unit; a determination module, configured to determine, based on the overall layout data, a plurality of unit regions in which the chip unit is located, and determine a pin density of each unit region; A judgment module, used to determine whether the pin density is greater than a preset density; A diffusion module, configured to diffuse the chip units in the unit area with a pin density greater than a preset density to other unit areas if the pin density is greater than the preset density, and return to the step of determining whether the pin density is greater than the preset density until each pin density is less than or equal to the preset density; The chip unit layout optimization device is also used to achieve: Determining chip units distributed in the same row and determining conflicting areas where the chip units exist; According to the conflicting area, adjusting the position of the chip unit corresponding to the conflict or adjusting the pin arrangement order of the chip unit generating the conflict; Calculate the impact of conflicts between the adjusted chip units and calculate the probability of conflicts between all chip units; If the probability does not meet the preset requirements or the current number of adjustments is less than or equal to the preset iteration threshold, return to the step of determining the chip units distributed in the same row and determining the conflicting areas where the chip units exist, until the probability meets the preset requirements or the current number of adjustments is equal to the preset iteration threshold.

8. A chip unit layout optimization device, characterized in that: The device includes: a memory, a processor, and a chip unit layout optimization program stored in the memory and executable on the processor, wherein the chip unit layout optimization program is configured to implement the steps of the chip unit layout optimization method according to any one of claims 1 to 6.

9. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a chip unit layout optimization program, which, when executed by a processor, implements the steps of the chip unit layout optimization method according to any one of claims 1 to 6.

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