Display panel, driving method thereof, and display device

Abstract

The embodiment of the application discloses a display panel and a driving method thereof, and a display device. The display panel comprises N types of display areas, the N types of display areas comprise an i-th type of display area and a j-th type of display area, the display panel comprises M display parts, the M display parts comprise a first display part and a second display part, the first display part comprises at least one i-th type of display area, the second display part comprises at least one i-th type of display area, and at least one j-th type of display area is arranged between the i-th type of display area comprised by the first display part and the i-th type of display area comprised by the second display part. The light-emitting time periods of the i-th type of display area and the j-th type of display area at least partially do not overlap, so that the number of sub-pixels driven by a power supply voltage line in the display panel is reduced in the same time period, and when each sub-pixel emitting light in the same time period emits light with the same brightness, the rising amplitude of transient current on the power supply voltage line is reduced, the voltage drop on the power supply voltage line is reduced, and the uniformity of a display picture is improved.

Description

[0001] This application claims priority to the Chinese patent application No. 202111671753.1, filed on December 31, 2021, and entitled "Display panel, driving method thereof, and display device", the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0002] The present application relates to the technical field of display, in particular to a display panel, a display device comprising the display panel, and a driving method of the display panel. BACKGROUND

[0003] With the development of display technology, display panels are increasingly used, and users have more and more requirements for the display quality of display panels. In order to meet the increasing requirements of users for the display quality of display panels, the number of display units included in the display panel is increasing under the same size, so that the resolution of the display panel is higher and higher, so as to improve the richness of the display picture of the display panel.

[0004] At present, pulse width modulation (PWM) driving circuit is widely used in display panels to control the duration of the driving current of the light emitting element in the display unit, so as to control the light emitting state of the light emitting element. However, with the increase of the number of display units included in the display panel, the voltage drop on the power line in the display panel is also increasing, which makes the display uniformity of the display panel poor. SUMMARY

[0005] To solve the above problems, the embodiments of the present application provide a display panel, a display device and a driving method of the display panel to improve the uniformity of the display picture.

[0006] Specifically, the embodiments of the present application provide the following technical solutions:

[0007] A display panel, comprising N types of display areas, wherein the N types of display areas comprise an i-th type of display area and a j-th type of display area, the light emitting period of the i-th type of display area and the j-th type of display area at least partially do not overlap, wherein N≥2 and N is an integer, 0

[0008] The display panel comprises M display parts, M≥2 and M is an integer, the M display parts comprise a first display part and a second display part, the first display part comprises at least one i-th type of display area, the second display part comprises at least one i-th type of display area, and at least one j-th type of display area is included between the i-th type of display area included in the first display part and the i-th type of display area included in the second display part.

[0009] The display device comprises the display panel.

[0010] The display panel is applied to the display panel, and the driving method comprises the following steps of:

[0011] In the first time period, the sub-pixels included in the i-th display area are controlled to emit light, and in the second time period, the sub-pixels included in the j-th display area are controlled to emit light.

[0012] The first time period and the second time period at least partially do not overlap.

[0013] In the technical scheme provided by the embodiment of the present application, the light-emitting time periods of the i-th display area and the j-th display area at least partially do not overlap, so that the number of sub-pixels driven by the power voltage line in the display panel in the same time period is reduced, and when each sub-pixel emitting light in the same time period emits light with the same brightness, the rising amplitude of the instantaneous current on the power voltage line is reduced, the voltage drop on the power voltage line is reduced, and the uniformity of the display picture is improved. BRIEF DESCRIPTION OF DRAWINGS

[0014] In order to more clearly illustrate the technical scheme in the embodiments of the present application or the prior art, the drawings needed in the embodiment or the prior art description will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application, and those skilled in the art can also obtain other drawings according to these drawings without creative labor.

[0015] Figure 1 The schematic diagram of the display panel provided by an embodiment of the present application;

[0016] Figure 2 In the display panel provided by an embodiment of the present application, the light-emitting time periods of the i-th display area and the j-th display area partially overlap.

[0017] Figure 3 The schematic diagram of the display panel provided by another embodiment of the present application;

[0018] Figure 4 In the display panel provided by an embodiment of the present application, the light-emitting time periods of the i-th display area and the j-th display area do not overlap.

[0019] Figure 5 In the display panel provided by another embodiment of the present application, the light-emitting time periods of the i-th display area and the j-th display area do not overlap.

[0020] Figure 6 The schematic diagram of the display panel provided by another embodiment of the present application;

[0021] Figure 7 A schematic diagram of a display panel according to another embodiment of the application;

[0022] Figure 8 A schematic diagram of a display panel according to another embodiment of the application;

[0023] Figure 9 A schematic diagram of a display panel according to another embodiment of the application;

[0024] Figure 10 A schematic diagram of a display panel according to another embodiment of the application;

[0025] Figure 11 A schematic diagram of a display panel according to another embodiment of the application;

[0026] Figure 12 A schematic diagram of a display panel according to another embodiment of the application;

[0027] Figure 13 A schematic diagram of a display panel according to another embodiment of the application;

[0028] Figure 14 A schematic diagram of a display panel according to another embodiment of the application;

[0029] Figure 15 A schematic diagram of a display panel according to another embodiment of the application;

[0030] Figure 16 A schematic diagram of a display panel according to another embodiment of the application;

[0031] Figure 17 A schematic diagram of a display panel according to another embodiment of the application;

[0032] Figure 18 A schematic diagram of a display panel according to another embodiment of the application;

[0033] Figure 19 A schematic diagram of a display panel according to another embodiment of the application;

[0034] Figure 20 A schematic diagram of a pixel driving circuit in a display panel according to an embodiment of the application;

[0035] Figure 21 A timing diagram of a pixel driving circuit in operation in a display panel according to an embodiment of the application;

[0036] Figure 22A timing diagram of the scan signals of the hth display area and the kth display area in the display panel provided by one embodiment of the present application;

[0037] Figure 23 A schematic diagram of a display panel provided by another embodiment of the present application;

[0038] Figure 24 A schematic diagram of a display panel provided by another embodiment of the present application;

[0039] Figure 25 A schematic diagram of a display device provided by one embodiment of the present application;

[0040] Figure 26 A schematic diagram of a driving method of a display panel provided by one embodiment of the present application;

[0041] Figure 27 A schematic diagram of a driving method of a display panel provided by another embodiment of the present application;

[0042] Figure 28 A schematic diagram of a driving method of a display panel provided by another embodiment of the present application;

[0043] Figure 29 A schematic diagram of a driving method of a display panel provided by another embodiment of the present application;

[0044] Figure 30 A schematic diagram of a display area of a display panel provided by one embodiment of the present application;

[0045] Figure 31 A schematic diagram of a display area of a display panel provided by one embodiment of the present application; Figure 30 A schematic diagram of a display area of a display panel provided by one embodiment of the present application;

[0046] Figure 32 A schematic diagram of a display area of a display panel provided by one embodiment of the present application; Figure 33 A schematic diagram of a pixel circuit in the display panel provided by one embodiment of the present application; Figure 31 A schematic diagram of a pixel circuit in the display panel provided by one embodiment of the present application;

[0047] Figure 34 A driving timing diagram of a pixel circuit in the display panel provided by one embodiment of the present application; Figure 32 Figure 33 A driving timing diagram of a pixel circuit in the display panel provided by one embodiment of the present application;

[0048] Figure 35 A driving timing diagram of a pixel circuit in the display panel provided by one embodiment of the present application; Figure 32 Figure 33 A driving timing diagram of a pixel circuit in the display panel provided by one embodiment of the present application;

[0049] Figure 36 Figure 30 A driving timing diagram of a pixel circuit in the display panel provided by one embodiment of the present application;

[0050] Figure 37 A driving timing diagram of a pixel circuit in the display panel provided by one embodiment of the present application; Figure 30 ​​​Another driving timing diagram of the display area shown in FIG. 1;

[0051] Figure 38 is a schematic diagram of a display state when the display area is in a first light-emitting stage E1 or in a control light-emitting process E11, E21, E31 and E41; Figure 36 Figure 37

[0052] Figure 39 is another driving timing diagram of the display area shown in FIG. 1; Figure 30

[0053] Figure 40 is still another driving timing diagram of the display area shown in FIG. 1. Figure 30 DETAILED DESCRIPTION

[0054] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work fall within the scope of protection of the present application.

[0055] In the following description, many specific details are set forth in order to provide a thorough understanding of the present application. However, the present application can be practiced according to other embodiments that deviate from the specific details described herein, and the skilled in the art will recognize that the present application is not limited to the embodiments described herein.

[0056] As described in the background section, with the increase of the number of display units included in the display panel, the voltage drop on the power supply voltage line in the display panel is also increasing, which makes the display uniformity of the display panel poor.

[0057] This is because in the display panel using a pulse width modulation (PWM) circuit to control the driving current of the light-emitting element, the driving of the light-emitting element is current driving, and in the light-emitting stage, each light-emitting element emits light at the same time, so that in the light-emitting stage, in order to make each light-emitting element emit light with the same brightness, the instantaneous current on the power supply voltage line will be significantly increased, thereby causing a large voltage drop on the power supply voltage line, which affects the uniformity of the display picture.

[0058] Moreover, the more light-emitting elements driven by the same power supply voltage line, the more the instantaneous current on the power supply voltage line will be increased in order to make each light-emitting element emit light with the same brightness in the light-emitting period, and the larger the voltage drop on the power supply voltage line, and the poorer the uniformity of the display picture.

[0059] Therefore, the embodiments of the present application provide a display panel, as shown in​​​​Figure 1 As shown in the figure, the display panel comprises N types of display areas, the N types of display areas comprise an i-th type of display area and a j-th type of display area, as shown in the figure Figure 2 As shown in the figure, the i-th type of display area and the j-th type of display area are at least partially non-overlapping in the light-emitting period, so as to reduce the number of sub-pixels driven by the power voltage line in the display panel in the same time period, thereby reducing the rising amplitude of the instantaneous current on the power voltage line when each sub-pixel emitting light in the same time period emits light with the same brightness, reducing the driving current transmitted on the power voltage line, and further reducing the voltage drop on the power voltage line, and improving the uniformity of the display picture. Wherein, N≥2 and N is an integer, 0

[0060] Optionally, the light-emitting periods of any two types of display areas in the N types of display areas are at least partially non-overlapping, further reducing the number of sub-pixels driven by the power voltage line in the display panel in the same time period, thereby reducing the rising amplitude of the instantaneous current on the power voltage line when each sub-pixel emitting light in the same time period emits light with the same brightness, reducing the driving current transmitted on the power voltage line, and further reducing the voltage drop on the power voltage line, and improving the uniformity of the display picture. However, the present application does not limit this, and the specific conditions are determined accordingly.

[0061] It should be noted that in the embodiments of the present application, the display panel comprises N types of display areas, which are divided into N types of display areas according to the light-emitting time of the display panel, wherein the light-emitting period of the sub-pixels in the same type of display area is the same, i.e. the starting light-emitting time and the ending light-emitting time of the sub-pixels in the same type of display area are the same. It should also be noted that in the embodiments, the display panel comprises at least two i-th type of display areas, and the j-th type of display area can have one or more, which is not limited by the present application, and the specific conditions are determined accordingly.

[0062] Specifically, in the embodiments of the present application, the display panel comprises M display parts, M≥2 and M is an integer, and continues as shown in the figure Figure 1 As shown in the figure, the M display parts comprise a first display part 10 and a second display part 20, the first display part 10 comprises at least one i-th type of display area, the second display part 20 comprises at least one i-th type of display area, and there is at least one j-th type of display area between the i-th type of display area comprised by the first display part 10 and the i-th type of display area comprised by the second display part 20, i.e. in the embodiments of the present application, the i-th type of display area between different display parts is at least separated by one j-th type of display area; Similarly, as shown in the figure Figure 3As shown, the first display part 10 also includes the jth display area, and the second display part 10 also includes the jth display area, the first display part 10 includes at least one ith display area between the jth display area included by the first display part 10 and the jth display area included by the second display part 20, that is, in the embodiment of the present application, at least one ith display area is arranged between the jth display areas located in different display parts.

[0063] It should be noted that in the embodiment of the present application, the plurality of ith display areas are arranged in at least the first display part and the second display part, and at least one jth display area is arranged between the ith display area included by the first display part and the ith display area included by the second display part, so that when the ith display area emits light, the display areas emitting light are not concentrated in one area, but are arranged in at least two display parts, so as to further improve the uniformity of the display picture.

[0064] Similarly, when the N display areas include a plurality of jth display areas, the plurality of jth display areas are arranged in at least the first display part and the second display part, and at least one ith display area is arranged between the jth display area included by the first display part and the jth display area included by the second display part, so that when the jth display area emits light, the display areas emitting light are not concentrated in one area, but are arranged in at least two display parts, so as to further improve the uniformity of the display picture.

[0065] It should be noted that in the embodiment, the first display part can include N display areas, or can include some of the N display areas; the second display part can also include N display areas, or can include some of the N display areas, which are not limited in the present application, and are determined according to the situation.

[0066] It should also be noted that the number of the same type of display area included in the first display part can be one or more; similarly, the number of the same type of display area included in the second display part can also be one or more; and when the number of the same type of display area included in the same display part is more than one, the same type of display area located in the same display part can be arranged adjacently or not adjacently, which is not limited in the present application, and is determined according to the situation.

[0067] The display panel provided by the embodiment of the present application is described below, taking the first display part including N display areas, the second display part including N display areas, and the same type of display area located in the same display part being arranged adjacently as an example.

[0068] Optionally, in an embodiment of the present application, the i-th type display region is uniformly distributed in the display panel, and the j-th type display region is uniformly distributed in the display panel, so as to further improve the uniformity of the display picture, but the present application is not limited thereto, and the specific arrangement is subject to the actual situation.

[0069] Specifically, in an embodiment of the present application, as shown in Figure 2 , the starting time of the light-emitting period of the i-th type display region does not overlap with that of the j-th type display region, so that the light-emitting periods of the i-th type display region and the j-th type display region at least partially do not overlap, thereby reducing the rising amplitude of the instantaneous current on the power voltage line when each sub-pixel emitting light of the same brightness at the same time period, reducing the voltage drop on the power voltage line, and improving the uniformity of the display picture.

[0070] In an embodiment of the present application, as shown in Figure 4 , the light-emitting periods of the i-th type display region and the j-th type display region do not overlap, so as to further reduce the number of sub-pixels driven by the power voltage line in the display panel at the same time period, thereby reducing the rising amplitude of the instantaneous current on the power voltage line when each sub-pixel emitting light of the same brightness at the same time period, reducing the voltage drop on the power voltage line, and improving the uniformity of the display picture.

[0071] Optionally, in an embodiment of the present application, when N is an integer greater than 2, the light-emitting periods of different types of display regions in the N types of display regions do not overlap, so as to further reduce the number of sub-pixels driven by the power voltage line in the display panel at the same time period, thereby reducing the rising amplitude of the instantaneous current on the power voltage line when each sub-pixel emitting light of the same brightness at the same time period, reducing the voltage drop on the power voltage line, and improving the uniformity of the display picture, but the present application is not limited thereto, and at least two types of display regions in the N types of display regions can have non-overlapping light-emitting periods.

[0072] Specifically, in an embodiment of the present application, in a display frame (i.e., in the display process of one frame of display picture), as shown in Figure 4 , the i-th type display region emits light first, and the j-th type display region emits light later, and the starting time of the light-emitting period of the j-th type display region is not earlier than the ending time of the light-emitting period of the i-th type display region, so that the light-emitting periods of the i-th type display region and the j-th type display region completely do not overlap; in another embodiment of the present application, in a display frame, as shown in Figure 5 , the j-th type display region emits light first, and the i-th type display region emits light later, and the starting time of the light-emitting period of the i-th type display region is not earlier than the ending time of the light-emitting period of the j-th type display region, so that the light-emitting periods of the i-th type display region and the j-th type display region completely do not overlap. The present application is not limited thereto, and the specific arrangement is subject to the actual situation.

[0073] Optionally, in an embodiment of the present application, when the light-emitting time periods of the i-th type display area and the j-th type display area are completely non-overlapping, the time gap t between the light-emitting time periods of the two types of display areas adjacent in the light-emitting time periods satisfies: 1 microsecond ≤ t ≤ T / 2, and the display panel continues to be as shown in Figure 4 As shown in the figure, the i-th type display area and the j-th type display area are two types of display areas adjacent in the light-emitting time periods, and the time gap between the light-emitting time periods of the i-th type display area and the j-th type display area is t, i.e., the time gap between the end time of the light-emitting time period of the i-th type display area and the start time of the light-emitting time period of the j-th type display area is t, wherein T represents the length of one light-emitting time period, so that in one display frame, the light-emitting time periods of the two types of display areas successively emitting light are non-overlapping, reducing the voltage drop on the power supply voltage line and improving the uniformity of the display picture, while avoiding the gap between the light-emitting time periods of the two types of display areas successively starting to emit light being too long, resulting in flickering of the display picture and affecting the user experience.

[0074] It should be noted that the light-emitting time periods of the two types of display areas adjacent in the light-emitting time periods are at least partially non-overlapping, which means that in the two types of display areas, the start time of the light-emitting time period of the one type of display area emitting light first and the start time of the light-emitting time period of the one type of display area emitting light later are not separated by the light-emitting time period of the other type of display area; the light-emitting time periods of the two types of display areas adjacent in the light-emitting time periods are completely non-overlapping, which means that in the two types of display areas, the end time of the light-emitting time period of the one type of display area emitting light first and the start time of the light-emitting time period of the one type of display area emitting light later are not separated by the light-emitting time period of the other type of display area.

[0075] Optionally, in an embodiment of the present application, the first display part and the second display part include the same types and numbers of N types of display areas, i.e., when the first display part includes R types of display areas, the second display part also includes R types of display areas, wherein R is any integer not less than 1 and not greater than N; when the first display part includes S display areas, the second display part also includes S display areas. As shown in Figure 6 For example, as shown in the figure, when N is 2, the first display part includes two types of display areas, i.e., the i-th type display area and the j-th type display area, and the second display part also includes two types of display areas, i.e., the i-th type display area and the j-th type display area; the first display part includes two display areas, i.e., one i-th type display area and one j-th type display area, and the second display part also includes two display areas, i.e., one i-th type display area and one j-th type display area. However, the present application does not limit this, and the specific implementation is determined as appropriate.

[0076] In the following, the display panel provided by the embodiment of the present application is described by taking the first display part including N types of display areas and the second display part also including N types of display areas as an example.

[0077] Specifically, in one embodiment of this application, the various display areas in the first display unit and the second display unit are arranged in the same order in the column direction. For example... Figure 7 As shown, taking N as 4 as an example, the first display unit 10 includes four types of display areas: a first type of display area A, a second type of display area B, a third type of display area C, and a fourth type of display area D. The arrangement order of the various types of display areas in the first display unit 10 is ABCD. The second display unit 20 also includes four types of display areas: a first type of display area A, a second type of display area B, a third type of display area C, and a fourth type of display area D. The arrangement order of the various types of display areas in the second display unit 20 is also ABCD.

[0078] like Figure 8 As shown, in one embodiment of this application, the display panel includes a plurality of pixel rows 30 arranged along the column direction Y1, and sub-pixels 31 in the pixel rows 30 are arranged along the row direction X1. The row direction X1 intersects the column direction Y1. Optionally, the row direction X1 is perpendicular to the column direction Y1, but this application does not limit this and it depends on the specific situation.

[0079] The following description continues with an example of the row direction being perpendicular to the column direction, to further illustrate the display panel provided in the embodiments of this application.

[0080] Optionally, in one embodiment of this application, each of the N types of display areas includes one pixel row 30 to further improve the uniformity of the display screen. Continuing with N=4 as an example, as... Figure 9 As shown, the first display unit includes four types of display areas: a first type of display area A, a second type of display area B, a third type of display area C, and a fourth type of display area D. Each type of display area includes one pixel row 30.

[0081] In another embodiment of this application, each of the N types of display areas includes at least two pixel rows to reduce the number of gate drive lines in the pixel rows of the display panel, thus facilitating the layout of signal lines in the display panel. Continuing with N=4 as an example, in this embodiment, each type of display area may include two pixel rows, such as... Figure 10 As shown, it can also include three pixel rows, or even more pixel rows. This application does not limit this; it depends on the specific circumstances.

[0082] Specifically, in one embodiment of this application, each of the M display units includes the N types of display areas. Taking M as 2 and N as 4 as an example, the following continues... Figure 10As shown in FIG. 1, each of the first display part 10 and the second display part 20 includes four types of display areas, i.e., the first type of display area A, the second type of display area B, the third type of display area C, and the fourth type of display area D. However, the present application is not limited thereto, and in other embodiments of the present application, the number of types of display areas included in different display parts can be different. For example, if M is 2 and N is 4, the first display part 10 and the second display part 20 can include three types of display areas, i.e., the first type of display area A, the second type of display area B, and the third type of display area C, and the first display part 10 and the second display part 20 can include four types of display areas, i.e., the first type of display area A, the second type of display area B, the third type of display area C, and the fourth type of display area D. Figure 11 As shown in FIG. 1, the M display parts include the first display part 10 and the second display part 20. The first display part 10 includes three types of display areas, i.e., the first type of display area A, the second type of display area B, and the third type of display area C. The second display part 20 includes four types of display areas, i.e., the first type of display area A, the second type of display area B, the third type of display area C, and the fourth type of display area D. The specific number of types of display areas included in the first display part 10 and the second display part 20 can be determined as appropriate.

[0083] As shown in FIG. 1, the M display parts include the first display part 10 and the second display part 20. The first display part 10 includes three types of display areas, i.e., the first type of display area A, the second type of display area B, and the third type of display area C. The second display part 20 includes four types of display areas, i.e., the first type of display area A, the second type of display area B, the third type of display area C, and the fourth type of display area D. The specific number of types of display areas included in the first display part 10 and the second display part 20 can be determined as appropriate. Figure 12 As shown in FIG. 1, in an embodiment of the present application, the display panel includes a third display part 40. The third display part 40 includes at least one ith type of display area and at least one jth type of display area. The ith type of display area and the jth type of display area in the third display part 40 are arranged along a first direction X2. The first direction X2 is the extension direction of the scanning lines in the display panel. That is, in the embodiment of the present application, among the plurality of sub-pixels arranged along the extension direction of the scanning lines, part of the sub-pixels are located in the ith type of display area, and part of the sub-pixels are located in the jth type of display area. In this way, the number of sub-pixels driven by the scanning lines in the same time period is reduced, thereby reducing the load on the scanning lines. Optionally, the first direction X2 is the same as the row direction X1. However, the present application is not limited thereto, and the specific direction can be determined as appropriate.

[0084] It should be noted that in any of the above embodiments, the sub-pixels in the N types of display areas can be driven by the same gate drive circuit or by different gate drive circuits. The present application is not limited thereto, and the specific manner can be determined as appropriate.

[0085] Optionally, in an embodiment of the present application, different types of display areas in the N types of display areas are driven by different gate drive circuits. Specifically, in the embodiment, the display panel includes a gate drive module. The gate drive module includes N gate drive circuits. The N gate drive circuits correspond to the N types of display areas one by one, and provide scanning drive signals for the sub-pixels in the corresponding display areas. In this way, the driving mode of the gate drive circuit is compatible with the existing gate drive circuit driving mode, thereby reducing the cost of the display panel. Figure 13As shown, taking N=4 as an example, the N types of display areas include four types of display areas, i.e., a first type of display area A, a second type of display area B, a third type of display area C, and a fourth type of display area D. Correspondingly, the gate drive module includes four gate drive circuits, i.e., a first gate drive circuit, a second gate drive circuit, a third gate drive circuit, and a fourth gate drive circuit. The first gate drive circuit provides a gate drive signal for the first type of display area A, the second gate drive circuit provides a gate drive signal for the second type of display area B, the third gate drive circuit provides a gate drive signal for the third type of display area C, and the fourth gate drive circuit provides a gate drive signal for the fourth type of display area D. The N types of display areas are located in the display area 100 of the display panel, and the gate drive module is located in the non-display area 200 of the display panel.

[0086] It should be noted that although Figure 13 As shown in the display panel, the N gate drive circuits are located on the same side of the display area 100, but the present application does not limit this, and in other embodiments of the present application, the N gate drive circuits can also be located on different sides of the display area 100, such as Figure 14 As shown, the specific arrangement is determined according to the situation.

[0087] In an embodiment of the present application, the M display parts are arranged along a preset direction, and in the preset direction, the gate drive module provides scanning drive signals for the sub-pixels of each type of display area in the N types of display areas in a first order. Specifically, in an embodiment of the present application, when the N types of display areas include four types of display areas, i.e., a first type of display area A, a second type of display area B, a third type of display area C, and a fourth type of display area D, the first order can be A-B-C-D, or B-A-C-D, or C-A-B-D, or other orders, and the present application does not limit this, and the specific arrangement is determined according to the situation.

[0088] Optionally, in an embodiment of the present application, in a display part, in the preset direction, the sub-pixels of each type of display area are arranged in a second order, and the first order and the second order are the same.

[0089] Specifically, in an embodiment of the present application, the preset direction includes a column direction, and taking the N types of display areas including four types of display areas, i.e., a first type of display area A, a second type of display area B, a third type of display area C, and a fourth type of display area D as an example, in this embodiment, the driving order of the four types of display areas, i.e., the first type of display area A, the second type of display area B, the third type of display area C, and the fourth type of display area D in a display part is A-B-C-D, and continuing as Figure 10 As shown, in the column direction Y1, the arrangement order of the four types of display areas, i.e., the first type of display area A, the second type of display area B, the third type of display area C, and the fourth type of display area D included in the display part is also A-B-C-D.

[0090] In another embodiment of the present application, the preset direction includes a row direction and a column direction, and continuing to take an example in which the N types of display areas include a first type of display area A, a second type of display area B, a third type of display area C and a fourth type of display area D, in this embodiment, the driving sequence of the four types of display areas A, B, C and D in one display part is A-B-C-D, in one implementation manner of this embodiment, as shown in Figure 15 the display part includes two types of display areas A and B arranged in sequence in the row direction X1, and two types of display areas C and D arranged in sequence in the row direction X1, and in the column direction Y1, the display part includes two types of display areas A and C arranged in sequence, and two types of display areas B and D arranged in sequence. Figure 16 In another implementation manner of this embodiment, as shown in the display part includes two types of display areas A and C arranged in sequence in the row direction X1, and two types of display areas B and D arranged in sequence in the row direction X1, and in the column direction Y1, the display part includes two types of display areas A and B arranged in sequence, and two types of display areas C and D arranged in sequence.

[0091] In another embodiment of the present application, in one display part, in the preset direction, the sub-pixels of each type of display area are arranged in a second sequence.

[0092] Specifically, in one embodiment of the present application, the preset direction includes a column direction, and continuing to take an example in which the N types of display areas include a first type of display area A, a second type of display area B, a third type of display area C and a fourth type of display area D, in this embodiment, the driving sequence of the four types of display areas A, B, C and D in one display part can be A-B-C-D, in one implementation manner of this embodiment, as shown in Figure 17As shown in FIG. 6, in the column direction Y1, the display part includes the first type display area A, the second type display area B, the third type display area C and the fourth type display area D arranged in the order of D-A-C-B; in another implementation manner of the embodiment, in the column direction Y1, the display part includes the first type display area A, the second type display area B, the third type display area C and the fourth type display area D arranged in the order of D-C-A-B or other arrangement order, which is not limited in the application and is determined according to the actual situation.

[0093] In another embodiment of the application, the preset direction includes the row direction and the column direction, and the N type display areas include the first type display area A, the second type display area B, the third type display area C and the fourth type display area D. In the embodiment, the driving order of the four type display areas in a display part is A-B-C-D. In one implementation manner of the embodiment, as shown in FIG. 7, in the row direction X1, the display part includes the second type display area B and the fourth type display area D arranged in sequence, and the third type display area C and the first type display area A arranged in sequence. In the column direction Y1, the display part includes the second type display area B and the third type display area C arranged in sequence, and the fourth type display area D and the first type display area A arranged in sequence. Figure 18 As shown in FIG. 8, in the row direction X1, the display part includes the second type display area B and the third type display area C arranged in sequence, and the first type display area A and the fourth type display area D arranged in sequence. In the column direction Y1, the display part includes the second type display area B and the first type display area A arranged in sequence, and the third type display area C and the fourth type display area D arranged in sequence. In another implementation manner of the embodiment, the first type display area A, the second type display area B, the third type display area C and the fourth type display area D in a display part can have other arrangement order, which is not limited in the application and is determined according to the actual situation. Figure 19 As shown in FIG. 8, in the row direction X1, the display part includes the second type display area B and the third type display area C arranged in sequence, and the first type display area A and the fourth type display area D arranged in sequence. In the column direction Y1, the display part includes the second type display area B and the first type display area A arranged in sequence, and the third type display area C and the fourth type display area D arranged in sequence. In another implementation manner of the embodiment, the first type display area A, the second type display area B, the third type display area C and the fourth type display area D in a display part can have other arrangement order, which is not limited in the application and is determined according to the actual situation.

[0094] As shown in FIG. 9, in one embodiment of the application, the display panel includes the pixel driving circuit in addition to the sub-pixel 101. Specifically, as shown in FIG. 10, the pixel driving circuit includes a first driving transistor 102, a second driving transistor 103 and a third driving transistor 104. Figure 20 As shown in FIG. 9, in one embodiment of the application, the display panel includes the pixel driving circuit in addition to the sub-pixel 101. Specifically, as shown in FIG. 10, the pixel driving circuit includes a first driving transistor 102, a second driving transistor 103 and a third driving transistor 104. Figure 20As shown, the pixel driving circuit comprises a pulse width modulation (PWM) module 102, a light-emitting control module 103, and a driving transistor T0, wherein the pulse width modulation module 102 outputs a pulse width setting signal to a first end of the light-emitting control module 103 based on a sweep signal SWEEP, and the driving transistor T0 is configured to output a driving current according to a signal at a gate of the driving transistor T0 and a signal at a first end of the driving transistor T0; the light-emitting control module 103 is configured to control the sub-pixel 101 to emit light in response to the driving current under the control of a light-emitting control signal, and output the pulse width setting signal to the gate of the driving transistor T0 to control the light-emitting time of the sub-pixel. It should be noted that in the present embodiment, in the N types of display areas, the sub-pixels of the same type of display area share the sweep signal and the light-emitting control signal, so that the sub-pixels of the same type of display area emit light at the same time, improve the light-emitting synchronization of the sub-pixels of the same display area, and reduce the number of control signals in the display panel.

[0095] Optionally, in one embodiment of the present application, the process continues as follows Figure 20 As shown, the pixel driving circuit further comprises an amplitude modulation module 104 and a reset module 105, wherein the amplitude modulation module 104 is configured to output an amplitude setting signal to the gate of the driving transistor T0, and the reset module 105 is electrically connected to the first electrode of the sub-pixel 101 to reset the first electrode of the sub-pixel.

[0096] Specifically, in one embodiment of the present application, the light-emitting control module 103 comprises a first transistor T1, a second transistor T2, and a third transistor T3.

[0097] The first electrode of the first transistor T1 is electrically connected to a power voltage input end to input a power voltage signal VDD; the second electrode of the first transistor T1 is electrically connected to the first electrode of the driving transistor T0; the gate of the first transistor T1 is electrically connected to a first light-emitting control end to input a first light-emitting control signal PAM_EM, and the first light-emitting control signal PAM_EM is configured to control the transmission of the power voltage signal to the first electrode of the driving transistor T0;

[0098] The first electrode of the second transistor T2 is electrically connected to the pulse width modulation module 102 to input the pulse width setting signal; the second electrode of the second transistor T2 is electrically connected to the gate of the driving transistor T0; the gate of the second transistor T2 inputs a second light-emitting control signal, and the second light-emitting control signal PWM_EM is configured to control the transmission of the pulse width setting signal to the gate of the driving transistor T0;

[0099] The first terminal of the second transistor T3 is electrically connected to the second terminal of the driving transistor T0, and the second terminal is electrically connected to the first terminal of the sub-pixel 101. The gate is electrically connected to the first light-emitting control terminal, and the first light-emitting control signal PAM_EM is input. Under the control of the first light-emitting control signal PAM_EM, the driving current output by the driving transistor T0 is transmitted to the sub-pixel 101.

[0100] Optionally, in one embodiment of this application, the reset module 105 includes a fourth transistor, the first terminal of the fourth transistor is electrically connected to a reference signal terminal to input a reference signal VREF, the second terminal of the fourth transistor is electrically connected to the first terminal of the sub-pixel 101, and the gate of the fourth transistor is electrically connected to a second scan signal. Under the control of the second scan signal, the reference signal VREF is transmitted to the first terminal of the sub-pixel 101 to reset the first terminal of the sub-pixel 101.

[0101] It should be noted that in the above embodiments, each transistor in the pixel driving circuit can be a P-type transistor, or all of them can be N-type transistors, or some can be P-type transistors and some can be N-type transistors. This application does not limit this, and it depends on the specific situation.

[0102] The following description, assuming that all transistors in the pixel driving circuit are P-type transistors, illustrates the operation of the pixel driving circuit provided in this application embodiment. Figure 21 As shown, Figure 21 for Figure 20 The timing diagram during operation shows that, in this embodiment, the operation of the pixel circuit includes a data writing stage and a light emission stage.

[0103] During the data writing phase, when the first scan signal S1 is low and the second scan signal S2 is high, the amplitude modulation module 104 resets the gate of the driving transistor T0, and the driving transistor T0 is turned on. When the first scan signal S1 switches to high and the second scan signal S2 switches to low, the amplitude modulation module 104 pulls the gate voltage of the driving transistor T0 high until the voltage across capacitor C is the voltage corresponding to the amplitude setting signal. The second scan signal S2 switches to high again. At this time, the gate of the driving transistor T0 is the amplitude setting signal.

[0104] During the light-emitting stage, the first scan signal S1 and the second scan signal S2 are at high levels, and the first light-emitting control signal PAM_EM is at low level. The driving transistor T0, the first transistor T1, and the third transistor T3 are turned on, forming a path between VDD and VEE. When the second light-emitting control signal PWM_EM is at low level, the second transistor T2 is turned on, forming a path between the pulse width modulation module 102 and the driving transistor T0. The driving transistor T0 outputs a corresponding driving current to the first pole of the sub-pixel 101 according to the signal of its gate and the signal of its first terminal. The sub-pixel 101 emits light in response to the driving current. When the scan signal SWEEP decreases linearly, the driving transistor T0 is turned off according to the signal provided by the pulse width modulation module 102, and the sub-pixel is turned off, ending the display of one display frame.

[0105] Optionally, the first light-emitting control signal may switch to a low level later than the second light-emitting control signal may switch to a low level, but this application does not limit this and it depends on the specific circumstances.

[0106] In one embodiment of this application, the N-type display area includes an h-th type display area and a k-th type display area, where 0 < h ≤ N, 0 < k ≤ N, h and k are integers, and h ≠ k; in this embodiment, as Figure 22 As shown, in the same display frame, the start time of the effective period of the sweep frequency signal SWEEP of the sub-pixel in the h-th display area is earlier than the start time of the effective period of the sweep frequency signal SWEEP of the sub-pixel in the k-th display area.

[0107] Optionally, in one embodiment of this application, such as Figure 23 As shown, the M display units include a fourth display unit 50, which includes at least one h-th type display area and at least one k-th type display area. The display panel includes a power supply voltage input terminal 60. In the fourth display unit 50, the h-th type display area is located on the side of the k-th type display area away from the power supply voltage input terminal 60, so that the display areas away from the power supply voltage input terminal 60 in the same type of display area emit light first, and the display areas closer to the power supply voltage input terminal 60 emit light later. This reduces the voltage drop on the power supply voltage line when the display areas away from the power supply voltage input terminal 60 in the same type of display area emit light, thereby improving the uniformity of the display image on the display panel.

[0108] In another embodiment of this application, such as Figure 24As shown in the figure, the display panel comprises a power voltage input end 60, and the first display part 10 is located on the side of the second display part 20 close to the power voltage input end 60; the N types of display areas comprise an hth type of display area and a kth type of display area, 0 < h ≤ N, 0 < k ≤ N, h and k are integers, and h ≠ k. In this embodiment, in the same display frame, the first display part 10 and the second display part 20 continue to be driven as shown in the figure. Figure 22 As shown in the figure, the start time of the effective period of the sweep signal SWEEP of the sub-pixel in the hth type of display area is prior to the start time of the effective period of the sweep signal SWEEP of the sub-pixel in the kth type of display area.

[0109] Optionally, in an embodiment of the present application, the first display part 10 and the second display part 20 continue to be driven as shown in the figure. Figure 24 As shown in the figure, the first display part 10 comprises at least one hth type of display area and at least one kth type of display area, and the ratio of the number of sub-pixels included in the hth type of display area to the number of sub-pixels included in the kth type of display area in the first display part 10 is n1; the second display part 20 comprises at least one hth type of display area and at least one kth type of display area, and the ratio of the number of sub-pixels included in the hth type of display area to the number of sub-pixels included in the kth type of display area in the second display part 20 is n2; wherein n1 < n2, so that the number of sub-pixels located in the area far away from the power voltage input end 60 in the display area emitting light first is more, and the number of sub-pixels located in the area close to the power voltage input end 60 is less, and the number of sub-pixels located in the area far away from the power voltage input end 60 in the display area emitting light later is less, and the number of sub-pixels located in the area close to the power voltage input end 60 is more, thereby further reducing the voltage drop on the power voltage line when the sub-pixel far away from the power voltage input end 60 emits light, and improving the uniformity of the display picture of the display panel. However, the present application is not limited thereto, and the specific implementation is determined according to the situation.

[0110] Correspondingly, the present application further provides a display device, as shown in the figure. Figure 25 The display device comprises the display panel provided by any of the above embodiments.

[0111] In summary, the display panel and the display device comprising the display panel provided by the embodiments of the present application comprise N types of display areas, the N types of display areas comprise an ith type of display area and a jth type of display area, and the light emitting periods of the ith type of display area and the jth type of display area at least partially do not overlap, so as to reduce the number of sub-pixels driven by the power voltage line in the display panel in the same time period, thereby reducing the rising amplitude of the instantaneous current on the power voltage line when each sub-pixel emitting light in the same time period emits light with the same brightness, reducing the voltage drop on the power voltage line, and improving the uniformity of the display picture.

[0112] Furthermore, this application embodiment also provides a driving method for a display panel, used to drive the display panel provided in any of the above embodiments. Specifically, in this embodiment, the driving method includes: controlling the sub-pixels included in the i-th type of display area to emit light during a first time period, and controlling the sub-pixels included in the j-th type of display area to emit light during a second time period; wherein the first time period and the second time period do not overlap at least partially, so as to reduce the number of sub-pixels driven by the power supply voltage line in the display panel during the same time period, thereby reducing the rise of instantaneous current on the power supply voltage line, reducing the voltage drop on the power supply voltage line, and improving the uniformity of the displayed image when each sub-pixel emitting light during the same time period emits light of the same brightness.

[0113] Optionally, in one embodiment of this application, the first time period and the second time period do not overlap, and the first time period and the second time period are two different light-emitting periods; in this embodiment, in the first time period, controlling the light emission of the sub-pixels included in the i-th type of display area, and in the second time period, controlling the light emission of the sub-pixels included in the j-th type of display area includes:

[0114] In the first time period, the sub-pixels included in the i-th type of display area are controlled to emit light simultaneously, and data signals are written to the sub-pixels included in the j-th type of display area; in the second time period, the sub-pixels included in the j-th type of display area are controlled to emit light simultaneously.

[0115] In one embodiment of this application, taking N as 2, and the N types of display areas including two types of display areas, namely a first type of display area A and a second type of display area B, the driving method of the display panel includes:

[0116] like Figure 26 As shown, in the first time period, the sub-pixels included in the first type of display area A are controlled to emit light simultaneously, and data signals are written to the sub-pixels included in the second type of display area B. In the second time period, the sub-pixels included in the second type of display area B are controlled to emit light simultaneously, and data signals are written to the sub-pixels included in the first type of display area A. This cycle is repeated to realize the display of each display frame.

[0117] Optionally, in one embodiment of this application, the first time period and the second time period are two adjacent light emission periods, but this application does not limit this and it depends on the specific circumstances.

[0118] The driving method provided in this application embodiment is described below using the first time period and the second time period as two adjacent light emission periods as an example.

[0119] In another embodiment of this application, taking N as 4, and the N types of display areas including four types of display areas: a first type of display area A, a second type of display area B, a third type of display area C, and a fourth type of display area, the driving method of the display panel includes:

[0120] As Figure 27 shown, in the first time period, the sub-pixels included in the first type display area A are controlled to emit light simultaneously, and the sub-pixels included in the second type display area B are written with data signals, in the second time period, the sub-pixels included in the second type display area B are controlled to emit light simultaneously, and the sub-pixels included in the third type display area C are written with data signals, in the fifth time period, the sub-pixels included in the third type display area C are controlled to emit light simultaneously, and the sub-pixels included in the fourth type display area D are written with data signals, in the sixth time period, the sub-pixels included in the fourth type display area D are controlled to emit light simultaneously, and the sub-pixels included in the first type display area A are written with data signals, and the cycle is repeated, so as to realize the display of each display frame.

[0121] Specifically, in an embodiment of the present application, the time length of writing data signals by the sub-pixels of the jth type display area is less than the time length of the first time period, so as to avoid that after the emission of the sub-pixels included in the ith type display area ends, the writing of data by the sub-pixels included in the jth type display area is not completed, which results in that the starting time of the emission of the sub-pixels included in the jth type display area is delayed for too long, and the display quality of the display picture is affected. Continue as Figure 26 and Figure 27 shown, the time length of writing data signals by the second type display area B is less than the time length of the emission of the first type display area A, the time length of writing data signals by the third type display area C is less than the time length of the emission of the second type display area B, the time length of writing data signals by the fourth type display area D is less than the time length of the emission of the third type display area C, and the time length of writing data signals by the first type display area A is less than the time length of the emission of the fourth type display area D.

[0122] In another embodiment of the present application, in the first time period, the sub-pixels included in the ith type display area are controlled to emit light, and in the second time period, the sub-pixels included in the jth type display area are controlled to emit light, which includes:

[0123] in the third time period, the sub-pixels included in the first display part are written with data signals;

[0124] in the first time period, the sub-pixels of the ith type display area on the display panel are controlled to emit light;

[0125] in the fourth time period, the sub-pixels included in the second display part are written with data signals;

[0126] in the second time period, the sub-pixels of the jth type display area on the display panel are controlled to emit light;

[0127] The order of the start time of each period is: the third period, the first period, the fourth period, and the second period, that is, the start time of the first period is later than the start time of the third period, the start time of the fourth period is later than the start time of the first period, and the start time of the second period is later than the start time of the fourth period.

[0128] In an embodiment of the present application, M is 2, N is 2, the N types of display areas include two types of display areas of a first type of display area A and a second type of display area B, the first display part includes one first type of display area A and one second type of display area B, and the second display part includes one first type of display area A and one second type of display area B, as shown in Figure 28 The driving method of the display panel includes:

[0129] In the third period, data signals are written to the sub-pixels in the first type of display area A and the second type of display area B included in the first display part;

[0130] In the first period, the sub-pixels of all the first type of display area A in the first display part and the second display part on the display panel are controlled to emit light.

[0131] In the fourth period, data signals are written to the sub-pixels in the first type of display area A and the second type of display area B included in the second display part;

[0132] In the second period, the sub-pixels of all the second type of display area B in the first display part and the second display part on the display panel are controlled to emit light, and the display of one display frame is completed.

[0133] In another embodiment of the present application, M is 4, N is 4, the M display parts include four display parts of a first display part, a second display part, a third display part, and a fourth display part, and the N types of display areas include four types of display areas of a first type of display area A and a second type of display area B, a third type of display area C, and a fourth type of display area D, each display part includes one first type of display area A, one second type of display area B, one third type of display area C, and one fourth type of display area D, as shown in Figure 29 The driving method of the display panel includes:

[0134] In the third period, data signals are written to the sub-pixels in the first type of display area A, the second type of display area B, the third type of display area C, and the fourth type of display area D included in the first display part;

[0135] In the first period, the sub-pixels of all the first type of display area A in the first display part, the second display part, the third display part, and the fourth display part on the display panel are controlled to emit light.

[0136] In the fourth time period, data signals are written to the sub-pixels in the first type display area A, the second type display area B, the third type display area C and the fourth type display area D included in the second display part;

[0137] In the second time period, the sub-pixels in the second type display area B in all of the first display part, the second display part, the third display part and the fourth display part on the display panel are controlled to emit light;

[0138] In the seventh time period, data signals are written to the sub-pixels in the first type display area A, the second type display area B, the third type display area C and the fourth type display area D included in the third display part;

[0139] In the eighth time period, the sub-pixels in the third type display area C in all of the first display part, the second display part, the third display part and the fourth display part on the display panel are controlled to emit light;

[0140] In the ninth time period, data signals are written to the sub-pixels in the first type display area A, the second type display area B, the third type display area C and the fourth type display area D included in the fourth display part;

[0141] In the tenth time period, the sub-pixels in the fourth type display area D in all of the first display part, the second display part, the third display part and the fourth display part on the display panel are controlled to emit light, and a complete display frame is displayed.

[0142] It should be noted that in the above embodiment, in the first time period, the data signals of the sub-pixels included in the first display part are data signals of a current frame display picture, and the data signals of the sub-pixels included in the second display part are data signals of a previous frame display picture; in the second time period, the data signals of the sub-pixels included in the first display part are data signals of a current frame display picture, and the data signals of the sub-pixels included in the second display part are data signals of a current frame display picture.

[0143] It should also be noted that, since the data signals written to the sub-pixels in different pixel rows are not necessarily the same, in one embodiment of the present application, in the third time period, writing data signals to the sub-pixels included in the first display part includes: at a third time, writing data signals to the sub-pixels in each of the sub-pixel rows included in the first display part in turn; similarly, in the fourth time period, writing data signals to the sub-pixels included in the second display part includes: writing data signals to the sub-pixels in each of the sub-pixel rows included in the second display part in turn.

[0144] In the embodiment, the sub-pixels included in different display areas of the same display part are sequentially written with data signals, that is, the sequence of writing data signals in each row of sub-pixels in the display panel is the same as the arrangement sequence of each row of sub-pixels in the display panel, and is independent of the display area where the sub-pixels are located, so that the data signal writing process of each row of pixels in the display panel is compatible with the data signal writing process of each row of pixels in the prior art, and the driving cost of the display panel is reduced.

[0145] In summary, the driving method of the display panel provided in the embodiment reduces the number of sub-pixels driven by the power voltage line in the same time period by controlling the sub-pixels included in the i-th display area to emit light in the first time period and controlling the sub-pixels included in the j-th display area to emit light in the second time period, and the first time period and the second time period at least partially do not overlap, so that the rising amplitude of the instantaneous current on the power voltage line is reduced when each sub-pixel emitting light in the same time period emits light with the same brightness, the voltage drop on the power voltage line is reduced, and the uniformity of the display image is improved.

[0146] The display panel provided in the application can further include the following embodiments.

[0147] In an embodiment of the application, the display panel includes N display areas, the N display areas are divided according to light emitting stages, the same display area emits light in the same light emitting stage, and the light emitting stages corresponding to different display areas at least partially overlap, for example, the light emitting stages corresponding to different display areas completely do not overlap in time sequence, so that the number of sub-pixels driven by the display panel in the same time period can be reduced, and the voltage drop on the power voltage line is reduced, and the uniformity of the display image is improved.

[0148] The display panel includes M display parts, and each display part can include N display areas. The display parts can be arranged in a specific direction (for example, column direction / row direction) in sequence. The arrangement rules of the N display areas in each display part can be the same, and for reference Figures 7-9 In the display panel, the N display areas can be periodically arranged in a specific direction.

[0149] The working process of the display panel includes a data writing stage and a light emitting stage, and the data writing stage can not overlap with the light emitting stage.

[0150] Specifically, the data writing stage can include a first data writing stage to an Nth data writing stage, and the light emitting stage can include a first light emitting stage to an Nth light emitting stage. Each stage in the data writing stage and each stage in the light emitting stage are alternately performed, that is, the sequence of each stage in the data writing stage and each stage in the light emitting stage is the first data writing stage, the first light emitting stage, the second data writing stage, the second light emitting stage, the Nth data writing stage, and the Nth light emitting stage.

[0151] In this embodiment, the light emission stage includes multiple stages. Increasing the number of times the display panel emits light can effectively reduce screen flicker and help protect the eyes.

[0152] The various display areas in the M display sections can complete the writing of data signals during the data writing stage.

[0153] Specifically, the various display areas contained in the M display units can be divided into N regions according to their physical arrangement along a specific direction (such as column / row direction), for example, regions 1 to N. In each stage of the data writing phase, data signals are written to one of these regions; specifically, data signals are written to the pixel circuits within that region. For example, in the first data writing phase, data signals are written to the pixel circuits in region 1; in the second data writing phase, data signals are written to the pixel circuits in region 2, and so on. By executing the first to Nth data writing phases, the data writing process for the various display areas in the M display units is completed.

[0154] In this embodiment, the data signals of each pixel circuit in the display area are written in stages, which reduces the data writing time between two adjacent light-emitting stages and helps to improve the display effect.

[0155] The methods for dividing the various display areas contained in M ​​display units into N regions include, but are not limited to, the following:

[0156] Method 1: At least two regions contain different numbers of display areas of various types.

[0157] For example, along the aforementioned specific direction, the number of various display areas contained in each region increases sequentially, or the number of various display areas contained in each region decreases sequentially, or the number of various display areas contained in each region first increases and then decreases.

[0158] Method 2: At least two regions contain the same number of display areas of each type.

[0159] For example, the various display areas in M ​​display units can be evenly divided into N regions along the aforementioned specific direction according to their physical arrangement.

[0160] It should be noted that if the total number of display areas of various types in M ​​display units is not divisible by N, for example, if the remainder is n, then the remainder n can be evenly distributed among the n regions. That is, in the N regions, there are n regions with one more display area of ​​various types than the other regions.

[0161] When writing data signals to each region at each stage of the data writing phase, a line-by-line writing method can be used to reduce the design complexity of the driving circuit (such as an IC). Line-by-line writing can be understood as providing data signals to the pixel circuits in each pixel row sequentially according to the arrangement order of the pixel rows.

[0162] During the light-emitting phase, each type of display area in the N types of display areas emits light simultaneously, and the light-emitting sequence of each type of display area can be, but is not limited to, the following:

[0163] Method 1: In each of the first to Nth light-emitting stages, select one type of display area to enter the light-emitting stage.

[0164] For example, the first to Nth light-emitting stages correspond to the selection of display areas of type 1 to type N. That is, in the first light-emitting stage, the pixel circuits in the first type of display area are selected to enter the light-emitting stage; in the second light-emitting stage, the pixel circuits in the second type of display area are selected to enter the light-emitting stage; and so on. In the Nth light-emitting stage, the pixel circuits in the Nth type of display area are selected to enter the light-emitting stage.

[0165] Method 2: In each of the first to Nth light-emitting stages, the first to Nth display areas sequentially enter the light-emitting stage.

[0166] For example, in each of the first to Nth light-emitting stages, the light-emitting stage of the first type of display area, the light-emitting stage of the second type of display area, and so on, the light-emitting stage of the Nth type of display area are executed sequentially.

[0167] Figure 30 This is a schematic diagram of the display area of ​​a display panel provided in an embodiment of this application. Figure 31 for Figure 30 A schematic diagram of a display unit. Figure 32 and Figure 33 They are respectively Figure 31 A circuit diagram of the pixel circuit in the image. Figure 34 for Figure 32 and Figure 33 The pixel circuit in the image can employ a driving timing diagram. Figure 35 for Figure 32 and Figure 33 Another driving timing diagram can be used for the pixel circuit in the image. Figure 36 for Figure 30 The diagram shown is a driving timing diagram for the display area. Figure 37 for Figure 30 The diagram shows another driving timing diagram for the display area. Figure 38 The display area is in Figure 36 The first luminescent stage E1 or in the middle Figure 37A schematic diagram showing the display status during the control of light emission processes E11, E21, E31, and E41, combined with... Figures 30-38 Specific examples are provided for the above technical solutions.

[0168] like Figure 30 As shown, exemplarily, the display area 100 of the display panel includes four types of display areas, i.e., N=4, namely, a first type of display area A, a second type of display area B, a third type of display area C, and a fourth type of display area D. Display areas of the same type emit light in the same light-emitting stage. Specifically, the pixel circuits of each of the first type of display areas A, the second type of display areas B, the third type of display areas C, and the fourth type of display areas D simultaneously enter the light-emitting stage. The light-emitting stages of the first type of display area A, the second type of display area B, the third type of display area C, and the fourth type of display area D may not overlap in timing.

[0169] Continue to refer to Figure 30 The display area 110 of the display panel includes M display sections, labeled as Display Section 1, Display Section 2, ..., Display Section M, arranged sequentially along the column direction Y1. Each display section includes a first-type display area A, a second-type display area B, a third-type display area C, and a fourth-type display area D. The four types of display areas in each display section are arranged along the column direction Y1, and the arrangement pattern is the same, namely ABCD. That is, the first-type display area A, the second-type display area B, the third-type display area C, and the fourth-type display area D are periodically arranged in the display area 100 according to the ABCD arrangement pattern.

[0170] Figure 30 Taking the display area 100 as an example, which includes the number of various display areas (ADs) as L, the L types of display areas are divided into 4 areas, namely the first area, the second area, the third area and the fourth area.

[0171] Each type of display area can include a single row of pixels or multiple consecutive rows of pixels.

[0172] Combination Figure 30 and Figure 31Each of the first display area A, the second display area B, the third display area C and the fourth display area D can include one pixel row 30, and each pixel row 30 includes a plurality of sub-pixels 31 arranged along a row direction X1. The display area 100 includes L types of display areas, that is, the display area 100 includes L pixel rows 30, the first area includes the first row to the L / 4th row of pixel rows 30, the second area includes the L / 4+1th row to the L / 2th row of pixel rows 30, the third area includes the L / 2+1th row to the 3L / 4th row of pixel rows 30, and the fourth area includes the 3L / 4+1th row to the Lth row of pixel rows 30.

[0173] In combination with Figures 31-33 , Figure 31 The sub-pixel 31 in Figure 32 and Figure 33 The pixel circuit in Figure 32 and Figure 33 The unit composed of the pixel circuit and the light emitting element EL.

[0174] Referring to Figure 32 The pixel circuit includes a pulse width modulation module PWM and an amplitude modulation module PAM.

[0175] The pulse width modulation module PWM is configured to output a light emitting time length control signal for controlling a light emitting time length of the light emitting element EL, and the pulse width modulation module PWM includes a pulse width driving transistor T12, a pulse width data writing transistor T5, a pulse width compensation transistor T6, a pulse width reset transistor T7, a first pulse width light emitting control transistor T5, a second pulse width light emitting control transistor T2 and a pulse width storage capacitor C1.

[0176] The first electrode of the pulse width data writing transistor T5 is connected to a pulse width data signal input end PWM_DATA, the second electrode of the pulse width data writing transistor T5 is connected to the first electrode of the pulse width driving transistor T12, and the gate electrode of the pulse width data writing transistor T5 is connected to a pulse width second scanning signal end PWM_S2[n]. The pulse width data signal input end PWM_DATA is configured to provide a pulse width data signal.

[0177] The first electrode of the pulse width compensation transistor T6 is connected to the second electrode of the pulse width driving transistor T12, the second electrode of the pulse width compensation transistor T6 is connected to the gate electrode of the pulse width driving transistor T12, and the gate electrode of the pulse width compensation transistor T6 is connected to the pulse width second scanning signal end PWM_S2[n].

[0178] The first electrode of the pulse width reset transistor T7 is connected to a reset voltage terminal VREF, the second electrode of the pulse width reset transistor T7 is connected to the gate of the pulse width driving transistor T12, and the gate of the pulse width reset transistor T7 is connected to a pulse width first scanning signal terminal PWM_S1[n]. The reset voltage terminal VREF is used to provide a reset voltage, and the reset voltage can be a constant voltage.

[0179] The first electrode of the first pulse width light emitting control transistor T11 is connected to a first power voltage terminal VDD1, the second electrode of the first pulse width light emitting control transistor T11 is connected to the first electrode of the pulse width driving transistor T12, and the gate of the first pulse width light emitting control transistor T11 is connected to a pulse width light emitting control signal terminal PWM_EM[a]. The first power voltage terminal VDD1 is used to provide a first positive power voltage.

[0180] The first electrode of the second pulse width light emitting control transistor T2 is connected to the second electrode of the pulse width driving transistor T12, the second electrode of the second pulse width light emitting control transistor T2 is an output terminal of the pulse width modulation module PWM, which can be connected to the gate of the amplitude driving transistor T0 of the amplitude modulation module PAM, and the gate of the second pulse width light emitting control transistor T2 is connected to the pulse width light emitting control signal terminal PWM_EM[a].

[0181] The first plate of the pulse width storage capacitor C1 is connected to a sweep signal terminal SWEEP[a], and the second plate of the pulse width storage capacitor C2 is connected to the gate of the pulse width driving transistor T12. The sweep signal terminal SWEEP[a] provides a sweep signal, and the sweep signal is a ramp signal.

[0182] The amplitude modulation module PAM is used to control the size of the driving current provided to the light emitting element EL, and the amplitude modulation module PAM includes an amplitude driving transistor T0, an amplitude data writing transistor T8, an amplitude compensation transistor T9, an amplitude reset transistor T10, a first amplitude light emitting control transistor T1, a second amplitude light emitting control transistor T3, and an amplitude storage capacitor C2.

[0183] The first electrode of the amplitude data writing transistor T8 is connected to an amplitude data signal input terminal PAM_DATA, the second electrode of the amplitude data writing transistor T8 is connected to the first electrode of the amplitude driving transistor T0, and the gate of the amplitude data writing transistor T8 is connected to an amplitude second scanning signal terminal PAM_S2. The amplitude data signal input terminal PAM_DATA is used to provide an amplitude data signal.

[0184] The first electrode of the amplitude compensation transistor T9 is connected to the second electrode of the amplitude driving transistor T0, the second electrode of the amplitude compensation transistor T9 is connected to the gate of the amplitude driving transistor T0, and the gate of the amplitude compensation transistor T9 is connected to the amplitude second scanning signal terminal PAM_S2.

[0185] The first terminal of the amplitude reset transistor T10 is connected to the reset voltage terminal VREF, the second terminal of the amplitude reset transistor T10 is connected to the gate of the amplitude drive transistor T0, and the gate of the amplitude reset transistor T10 is connected to the amplitude first scan signal terminal PAM_S1.

[0186] The first terminal of the first amplitude light-emitting control transistor T1 is connected to the second power supply voltage terminal VDD2, the second terminal of the first amplitude light-emitting control transistor T1 is connected to the first terminal of the amplitude driving transistor T0, and the gate of the first amplitude light-emitting control transistor T1 is connected to the amplitude light-emitting control signal terminal PAM_EM[a]. The second power supply voltage terminal VDD2 is used to provide a second positive power supply voltage, which can be the same as or different from the first positive power supply voltage.

[0187] The first terminal of the second amplitude light-emitting control transistor T3 is connected to the second terminal of the amplitude driving transistor T0. The second terminal of the second amplitude light-emitting control transistor T3 is connected to the first electrode of the light-emitting element EL (such as the positive electrode of the light-emitting element). The gate of the second amplitude light-emitting control transistor T3 is connected to the amplitude light-emitting control signal terminal PAM_EM[a].

[0188] The first plate of the amplitude storage capacitor C2 is connected to the second power supply voltage terminal VDD2, and the second plate of the amplitude storage capacitor C2 is connected to the gate of the amplitude driving transistor T0.

[0189] The pixel circuit also includes a first reset transistor T4. The first electrode of the first reset transistor T4 is connected to the first electrode of the light-emitting element EL, the second electrode of the first reset transistor T4 is connected to the third power supply voltage terminal VEE, and the gate of the first reset transistor T4 is connected to the amplitude of the first scan signal terminal PAM_S1, or the gate of the first reset transistor T4 is connected to the amplitude of the second scan signal terminal PAM_S2. The third power supply voltage terminal VEE is used to provide a negative power supply voltage.

[0190] and Figure 32 compared to, Figure 33 The pixel circuit also includes a transistor T13 for controlling the light emission duration, a second reset transistor T14, and a reset storage capacitor C3.

[0191] The first terminal of the light-emitting duration control transistor T13 is connected to the second terminal of the amplitude driving transistor T0, the second terminal of the light-emitting duration control transistor T13 is connected to the first terminal of the second amplitude light-emitting control transistor T3, and the gate of the light-emitting duration control transistor T13 is connected to the second terminal of the second pulse width light-emitting control transistor T2.

[0192] The first electrode of the second reset transistor T14 is connected with the reset voltage terminal VSET, the second electrode of the second reset transistor T14 is connected with the gate of the control light-emitting duration transistor T13, and the gate of the second reset transistor T14 is connected with the reset scanning signal terminal SET[n].

[0193] The first electrode plate of the reset storage capacitor C3 is connected with the reset voltage terminal VSET, and the second electrode plate of the reset storage capacitor C3 is connected with the gate of the control light-emitting duration transistor T13.

[0194] Figure 33 The connection relationship of the remaining transistors in the pixel circuit shown can refer to the description of Figure 32 .

[0195] In Figure 32 and Figure 33 , “n” in the pulse width first scanning signal terminal PWM_S1[n], the pulse width second scanning signal terminal PWM_S2[n] and the reset scanning signal terminal SET[n] is the serial number of the pixel row where the pixel circuit is located, wherein the signal provided by the pulse width first scanning signal terminal PWM_S1[n] of the pixel circuit in the nth row can be the same as the signal provided by the pulse width second scanning signal terminal PWM_S2[n-1] of the pixel circuit in the (n-1)th row.

[0196] In Figure 32 and Figure 33 , “a” in the sweep signal terminal SWEEP[a], the pulse width light-emitting control signal terminal PWM_EM[a] and the amplitude light-emitting control signal terminal PAM_EM[a] is the serial number of the display area type where the pixel circuit is located, for example, the pixel circuit is located in a class A display area, and the above signal terminals of the pixel circuit are respectively the sweep signal terminal SWEEP[A], the pulse width light-emitting control signal terminal PWM_EM[A] and the amplitude light-emitting control signal terminal PAM_EM[A].

[0197] Figure 32 and Figure 33 The driving mode adopted by any one of the pixel circuits 31 can include but is not limited to the driving timing provided by Figure 34 and Figure 35 .

[0198] In combination with Figures 32-34 , the working process of the pixel circuit 31 can include but is not limited to the amplitude reset process ASET, the amplitude data writing process AD, the pulse width reset process WSET, the pulse width data writing process WD and the control light-emitting process EP executed in sequence.

[0199] In the amplitude reset process ASET, the signal provided by the amplitude first scanning signal terminal PAM_S1 controls the amplitude reset transistor T10 to be turned on, and the reset voltage provided by the reset voltage terminal VREF is transmitted to the gate of the amplitude driving transistor T0.

[0200] In the amplitude data writing process AD, the signal provided by the amplitude second scan signal terminal PAM_S2 controls the amplitude data writing transistor T8 to turn on and controls the amplitude compensation transistor T9 to turn on, so as to transmit the amplitude data signal provided by the amplitude data signal input terminal PAM_DATA to the gate of the amplitude drive transistor T0, and keep the gate of the amplitude drive transistor T0 as the amplitude data signal by the amplitude storage capacitor C2.

[0201] In the pulse width reset process WSET, the signal provided by the pulse width first scan signal terminal PWM_S1[n] controls the pulse width reset transistor T7 to turn on, and transmits the reset voltage provided by the reset voltage terminal VREF to the gate of the pulse width drive transistor T12.

[0202] In the pulse width data writing process WD, the signal provided by the pulse width second scan signal terminal PWM_S2[n] controls the pulse width data writing transistor T5 to turn on and controls the pulse width compensation transistor T6 to turn on, so as to transmit the pulse width data signal provided by the pulse width data signal input terminal PWM_DATA to the gate of the pulse width drive transistor T12.

[0203] In the control emitting process EP, the pulse width emitting control signal provided by the pulse width emitting control signal terminal PWM_EM[a] controls the first pulse width emitting control transistor T11 to turn on and controls the second pulse width emitting control transistor T2 to turn on, and the amplitude emitting control signal provided by the amplitude emitting control signal terminal PAM_EM[a] controls the first amplitude emitting control transistor T1 to turn on and controls the second amplitude emitting control transistor T3 to turn on, so that the amplitude drive transistor T0 provides the driving current to the light emitting element EL according to the amplitude data signal at its gate, and the potential at the gate of the pulse width drive transistor T12 is affected by the coupling of the pulse width storage capacitor C1 by the ramp signal provided by the sweep signal terminal SWEEP[a], and the potential at the gate of the pulse width drive transistor T12 drops to the turn-on condition of the pulse width drive transistor T12, the pulse width drive transistor T12 turns on to provide the first positive power voltage provided by the first power voltage terminal VDD1 to the gate of the amplitude drive transistor T0, so that the amplitude drive transistor T0 stops providing the driving current to the light emitting element EL (as shown in Figure 32 ), or, after the pulse width drive transistor T12 turns on, the first positive power voltage provided by the first power voltage terminal VDD1 is provided to the gate of the emitting time length control transistor T13, so that the emitting time length control transistor T13 is cut off, the driving current path is cut off, and the driving current is no longer provided to the light emitting element EL (as shown in Figure 33 ), so that the sweep signal can cooperate with the pulse width data signal to control the emitting time length of the light emitting element EL.

[0204] In combination with Figure 32 , Figure 33 andFigure 35 The working process of the pixel circuit 31 can include, but is not limited to, a magnitude reset process and a pulse width reset process ASET / WSET, a magnitude data writing process and a pulse width data writing process AD / WD, and a control emitting process EP, which are sequentially performed.

[0205] Compared with the timing shown in Figure 34 , in Figure 35 , the magnitude reset process and the pulse width reset process can be completed in the same time period, and the magnitude data writing process and the pulse width data writing process can be completed in the same time period.

[0206] In the magnitude reset process and the pulse width reset process ASET / WSET, the signal of the magnitude first scan signal end PAM_S1 can multiplex the signal provided by the pulse width first scan signal end PWM_S1[n].

[0207] In the magnitude data writing process and the pulse width data writing process AD / WD, the signal of the magnitude second scan signal end PAM_S2 can multiplex the signal provided by the pulse width second scan signal end PWM_S2[n].

[0208] Figure 36 The signals in Figure 32 or Figure 33 are all P-type transistors, which are taken as examples. When the signal is at a low level, the signal controls the corresponding transistor to be turned on, and vice versa, when the signal is at a high level, the signal controls the corresponding transistor to be turned off. If part of the transistors in the pixel circuit are N-type transistors, or if all the transistors in the pixel circuit are N-type transistors, the control signal suitable for the N-type transistors can be obtained by adjusting the enable level of the signal, such as adjusting the enable level to a high level, so that the corresponding N-type transistor is turned on.

[0209] As shown in Figure 36 , the working process of the display panel includes a data writing stage and an emitting stage, and the data writing stage and the emitting stage do not overlap. The data writing stage includes a first data writing stage D1, a second data writing stage D2, a third data writing stage D3, and a fourth data writing stage D4, and the emitting stage includes a first emitting stage E1, a second emitting stage E2, a third emitting stage E3, and a fourth emitting stage E4. The stages D1-D4 of the data writing stage and the stages E1-E4 of the emitting stage are alternately performed.

[0210] In combination with Figure 30 and Figure 36 , the driving relationship of each pixel circuit of the display area 100 of the display panel is described.

[0211] In the first data writing stage Dl, the pulse width data signal PWM_DATA is written to the pixel circuits in the first area row by row, i.e. to the pixel circuits 31 in the first to L / 4th pixel rows 30 row by row.

[0212] The first light emitting stage E1 is located after the first data writing stage Dl, in which the pixel circuits 31 in each first type display area A are driven to drive the corresponding light emitting elements EL under the control of the pulse width light emitting control signal PWM_EM[A], the amplitude light emitting control signal PAM_EM[A] and the sweep signal SWEEP[A]. In the first light emitting stage E1, the area of the display area entering the light emitting stage is as shown in Figure 38 , in which the entering light emitting stage area is shown by the filled area, i.e. the pixel circuits in each first type display area A enter the light emitting stage to drive the corresponding light emitting elements EL. For the display state of the display area in the following light emitting stages or in the control of the light emitting process, it is similar to that shown in Figure 38 .

[0213] The second data writing stage D2 is located after the first light emitting stage E1, in which the pulse width data signal PWM_DATA is written to the pixel circuits in the second area row by row, i.e. to the pixel circuits 31 in the L / 4+1th to L / 2th pixel rows 30 row by row.

[0214] The second light emitting stage E2 is located after the second data writing stage D2, in which the pixel circuits 31 in each second type display area B are driven to drive the corresponding light emitting elements EL under the control of the pulse width light emitting control signal PWM_EM[B], the amplitude light emitting control signal PAM_EM[B] and the sweep signal SWEEP[B].

[0215] The third data writing stage D3 is located after the second light emitting stage E2, in which the pulse width data signal PWM_DATA is written to the pixel circuits in the third area row by row, i.e. to the pixel circuits 31 in the L / 2+1th to 3L / 4th pixel rows 30 row by row.

[0216] The third light emitting stage E3 is located after the third data writing stage D3, in which the pixel circuits 31 in each third type display area C are driven to drive the corresponding light emitting elements EL under the control of the pulse width light emitting control signal PWM_EM[C], the amplitude light emitting control signal PAM_EM[C] and the sweep signal SWEEP[C].

[0217] The fourth data writing stage D4 is located after the third light emission stage E3. In the fourth data writing stage D4, the pulse width data signal PWM_DATA is written line by line to each pixel circuit located in the fourth region, that is, the pulse width data signal PWM_DATA is written line by line to the pixel circuit 31 in the pixel row 30 from the 3L / 4+1 row to the Lth row.

[0218] The fourth light-emitting stage E4 is located after the fourth data writing stage D4. In the fourth light-emitting stage E4, each pixel circuit 31 located in each of the fourth type of display areas D drives the corresponding light-emitting element EL under the control of the pulse width light-emitting control signal PWM_EM[D], the amplitude light-emitting control signal PAM_EM[D], and the sweep frequency signal SWEEP[D].

[0219] In each of the above data writing stages D1-D4, the pulse width first scan signal PWM_S1[n] corresponding to each pixel row 30 provides a shifting enable signal according to the arrangement order of the pixel rows 30. The pulse width second scan signal PWM_S2[n] corresponding to each pixel row 30 provides a shifting enable signal according to the arrangement order of the pixel rows 30. The pulse width second scan signal PWM_S2[n] of the pixel circuit 31 in the same row is shifted backward compared to the pulse width first scan signal PWM_S1[n], so that each pixel row 30 can write data signals in a row-by-row manner.

[0220] In each of the above data writing stages D1-D4, except for the area where the pulse width data signal PWM_DATA is written, the pulse width data signal PWM_DATA in the pixel circuits of the remaining areas remains the previously written pulse width data signal PWM_DATA. For example, in the first data writing stage D1, except for the pixel circuits in the first area where the pulse width data signal PWM_DATA is rewritten, the pulse width data signal PWM_DATA of the pixel circuits in the second to fourth areas remains the previously written pulse width data signal PWM_DATA.

[0221] Combination Figure 30 and Figure 37 The driving relationship of each pixel circuit in the display area 100 of the display panel is explained.

[0222] refer to Figure 37, the driving timing of the display area includes a data writing stage and a light emitting stage, the data writing stage includes a first data writing stage D1, a second data writing stage D2, a third data writing stage and a fourth data writing stage D4, and the light emitting stage includes a first light emitting stage E1, a second light emitting stage E2, a third light emitting stage E3 and a fourth light emitting stage E4. Wherein, the driving order of each stage D1-D4 of the data writing stage is the first data writing stage D1, the second data writing stage D2, the third data writing stage and the fourth data writing stage D4, and the driving order of each stage of the light emitting stage includes: the first light emitting stage E1 is located between the first data writing stage D1 and the second data writing stage D2, the second light emitting stage E2 is located between the second data writing stage D2 and the third data writing stage D3, the third light emitting stage E3 is located between the third data writing stage D3 and the fourth data writing stage D4, and the fourth light emitting stage E4 is located after the fourth data writing stage D4.

[0223] Figure 37 The driving process of each stage D1-D4 of the data writing stage in Figure 36 is the same as the driving process of each stage D1-D4 of the data writing stage in Figure 36 , and reference can be made to the description part of Figure 36 , which will not be repeated here.

[0224] Figure 37 The stages E1-E4 of the light emitting stage in Figure 36 , compared with the stages E1-E4 of the light emitting stage in Figure 36 , the difference is that any one of the first light emitting stage E1, the second light emitting stage E2, the third light emitting stage E3 and the fourth light emitting stage E4 includes the control light emitting process (E11, E21, E31 and E41) of each pixel circuit 31 of the first type display area A, the control light emitting process (E12, E22, E32, E42) of each pixel circuit 31 of the second type display area B, the control light emitting process (E13, E23, E33, E43) of each pixel circuit 31 of the third type display area and the control light emitting process (E14, E24, E34, E44) of each pixel circuit 31 of the fourth type display area.

[0225] Specifically, in the first light emitting stage E1, E11, E12, E13 and E14 are executed in turn, and E1-E4 can not overlap in time sequence.

[0226] In the control light emitting process E11, each pixel circuit 31 located in each first type display area A is driven to drive the corresponding light emitting element EL under the control of the pulse width light emitting control signal PWM_EM[A], the amplitude light emitting control signal PAM_EM[A] and the sweep signal SWEEP[A].

[0227] In the control light emitting process E12, each pixel circuit 31 located in each second type display area B drives the corresponding light emitting element EL under the control of the pulse width light emitting control signal PWM_EM[B], the amplitude light emitting control signal PAM_EM[B] and the sweep signal SWEEP[B].

[0228] In the control light emitting process E13, each pixel circuit 31 located in each third type display area C drives the corresponding light emitting element EL under the control of the pulse width light emitting control signal PWM_EM[C], the amplitude light emitting control signal PAM_EM[C] and the sweep signal SWEEP[C].

[0229] In the control light emitting process E14, each pixel circuit 31 located in each fourth type display area D drives the corresponding light emitting element EL under the control of the pulse width light emitting control signal PWM_EM[D], the amplitude light emitting control signal PAM_EM[D] and the sweep signal SWEEP[D].

[0230] Thus, in the first light emitting stage E1, the pixel circuit 31 in each first type display area A, the pixel circuit 31 in each second type display area B, the pixel circuit 31 in each third type display area C and the pixel circuit 31 in each fourth type display area D drive the corresponding light emitting element EL to emit light in turn.

[0231] The driving timing of the second light emitting stage E2, the third light emitting stage E3 and the fourth light emitting stage E4 is similar to that of the first light emitting stage E1, which can be referred to the description of the first light emitting stage E1 and will not be repeated here.

[0232] Figure 37 Compared with the working process of the display area shown in Figure 36 Compared with the working process of the display area shown in

[0233] Figure 36 and Figure 37 In the above, the maximum value of the slope voltage of the sweep signal corresponding to each type of display area A-D (such as the voltage value corresponding to the upper left end point of the slope section in Figure 36 and Figure 37 ) can be the same or different, which can be set according to the requirements; the minimum value of the slope voltage of the sweep signal corresponding to each type of display area A-D (such as the voltage value corresponding to the lower right end point of the slope section in Figure 36 and Figure 37 ) can be the same or different, which can be set according to the requirements; the slope of the slope voltage of the sweep signal corresponding to each type of display area A-D can be the same or different, which can be set according to the requirements.

[0234] In an embodiment, the display panel can include three types of display areas, the color of the light emitting element driven by the pixel circuit in different types of display areas is different, and the maximum value, minimum value and slope of the sweep frequency signal corresponding to each type of display area can be set according to requirements when driving light emitting elements of different colors. For example, for light emitting elements with lower light emitting efficiency, the slope of the corresponding sweep frequency signal is smaller to provide a long enough light emitting time.

[0235] With reference to Figure 39 and Figure 30 Before each data writing stage D1-D4, the working process of the display panel further includes an amplitude data writing stage D_All, for example, an amplitude data writing stage D_All is inserted between the first light emitting stage E1 and the second data writing stage D2, between the second light emitting stage E2 and the third data writing stage D3, and between the third light emitting stage E3 and the fourth data writing stage D4 before the first data writing stage D1.

[0236] In the amplitude data writing stage D_All, each pixel circuit 31 in the L pixel rows 30 can complete the reset process of the gate of the amplitude driving transistor T0 under the control of the amplitude first scan signal PAM_S1 and complete the writing of the amplitude data signal PAM_DATA under the control of the amplitude second scan signal PAM_S2. The amplitude data signal PAM_DATA received by each pixel circuit 31 in the L pixel rows 30 can be the same, thereby providing the same size of driving current to each light emitting element EL, so that the light emitting element EL always works in a state with higher light emitting efficiency.

[0237] Figure 39 For Figure 36 Another driving timing diagram of the display area shown in FIG. 6.

[0238] With reference to Figure 37 The amplitude first scan signal PAM_S1 in each pixel circuit 31 can multiplex the pulse width first scan signal PWM_S1[n] of the pixel circuit 31, and the amplitude second scan signal PAM_S2 in each pixel circuit 31 can multiplex the pulse width second scan signal PWM_S2[n] of the pixel circuit 31, so that the writing of the amplitude data signal PAM_DATA of the amplitude adjustment module PAM of the pixel circuit is completed at the same time as the writing of the pulse width data signal PWM_DATA of the pulse width adjustment module PWM of the pixel circuit. For the timing of the pulse width first scan signal PWM_S1[n] and the pulse width second scan signal PWM_S2[n] in each stage D1-D4 of the data writing stage, please refer to Figure 39 and Figure 39Thus, in each of the stages D1-D4 of the data writing phase, the pixel circuits 31 in each of the display areas A-D write the amplitude data signal PAM_DATA at the same time as the pulse width data signal PWM_DATA in a row-by-row manner. The amplitude data signal PAM_DATA received by each of the pixel circuits 31 in the L pixel rows 30 can be the same, so that the same size of driving current is provided to each of the light emitting elements EL, and the light emitting elements EL always work in a state of higher light emitting efficiency.

[0239] It should be noted that, Figure 40 The amplitude first scanning signal PAM_S1 and the amplitude second scanning signal PAM_S2 are not shown, and can refer to the multiplexed signals shown in Figure 30 .

[0240] Figure 40 Another driving timing diagram of the display area shown in Figure 36 is shown.

[0241] Figure 37 The driving process of the amplitude data writing phase D_All in each of the stages D1-D4 of the data writing phase in Figure 40 and Figure 30 and the corresponding description, which will not be repeated here.

[0242] Figure 40 A driving timing of each of the stages E1-E4 of the light emitting phase is also provided. In combination with ​ and ​ , in each of the stages E1-E4 of the light emitting phase, each of the pixel circuits 31 in the entire display area 100 enters the light emitting phase under the control of the same pulse width light emitting control signal PWM_EM, the same amplitude light emitting control signal PAM_EM and the same sweeping signal SWEEP, so that the light emitting times of each of the display areas are increased, the problem of picture flicker is improved, and the eyes can be protected.

[0243] It should be noted that the name in the numerical way and the name in the textual way can be understood as referring to the same name, for example, the first light emitting phase and the 1st light emitting phase are different names of the same light emitting phase.

[0244] Each part of the specification is described in a combination of parallel and progressive manners, and each part mainly describes the difference from other parts. The same and similar parts between each part can be referred to each other.

[0245] Having described above several embodiments of the disclosure, features of the various embodiments described in this specification can be combined with each other, or substituted for each other or combined with each other, to realize or use the application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and generic principles defined herein can be applied to other embodiments without departing from the spirit or scope of the application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A display panel, characterized by, The display panel comprises N types of display areas, the N types of display areas comprise an i-th type of display area and a j-th type of display area, and the i-th type of display area and the j-th type of display area at least partially do not overlap in a light-emitting period, wherein N≥2 and N is an integer, 0 The display panel comprises M display parts, M≥2 and M is an integer, the M display parts comprise a first display part and a second display part, the first display part comprises at least one i-th type of display area, the second display part comprises at least one i-th type of display area, and the first display part comprises at least one j-th type of display area between the i-th type of display area and the i-th type of display area comprised by the second display part. The display panel comprises a pixel driving circuit and a sub-pixel, the pixel driving circuit comprises a pulse width modulation module, a light-emitting control module and a driving transistor, the pulse width modulation module receives at least a sweep signal, provides a pulse width setting signal for the light-emitting control module and / or the driving transistor, and controls a light-emitting time of the sub-pixel. The N types of display areas comprise an h-th type of display area and a k-th type of display area, 0 The display panel further comprises a power voltage input end; wherein The display panel satisfies at least one of the following conditions: The M display parts comprise a fourth display part, the fourth display part comprises at least one h-th type of display area and at least one k-th type of display area, and the h-th type of display area is located on a side of the k-th type of display area away from the power voltage input end; Or, The first display part is located on a side of the second display part close to the power voltage input end; The first display part comprises at least one h-th type of display area and at least one k-th type of display area, and in the first display part, a ratio of a number of sub-pixels comprised by the h-th type of display area to a number of sub-pixels comprised by the k-th type of display area is n1; The second display part comprises at least one h-th type of display area and at least one k-th type of display area, and in the second display part, a ratio of a number of sub-pixels comprised by the h-th type of display area to a number of sub-pixels comprised by the k-th type of display area is n2; Wherein, n1 2. The display panel of claim 1, wherein, The start time of the light-emitting period of the i-th type of display area and the j-th type of display area does not overlap.

3. The display panel of claim 1, wherein, The light-emitting period of the i-th type of display area and the j-th type of display area does not overlap.

4. The display panel of claim 3, wherein, The light-emitting period of the i-th type of display area and the j-th type of display area comprises a data writing stage.

5. The display panel of claim 4, wherein, The total number of N types of display areas is L, and the L types of display areas are arranged in a column direction; The L types of display areas are divided into N regions, and the N regions are arranged in the column direction; In one data writing stage, data signals are written to each sub-pixel comprised by one of the regions.

6. The display panel of claim 3, wherein, The light-emitting period of the i-th type of display area and the light-emitting period of the j-th type of display area are located between two adjacent data writing stages.

7. The display panel of claim 3, wherein, The time interval t between the light-emitting periods of two types of display areas with adjacent light-emitting periods satisfies: 1 microsecond ≤ t ≤ T / 2; Wherein, T represents the length of one light-emitting period.

8. The display panel of claim 1, wherein, The first display part and the second display part include the same type and number of N types of display areas, and the arrangement order of each type of display area in the column direction is the same in the first display part and the second display part.

9. The display panel of claim 8, wherein, The display panel includes a plurality of pixel rows arranged along the column direction, and the sub-pixels in the pixel rows are arranged along the row direction intersecting the column direction. Each type of display area in the N types of display areas includes one pixel row.

10. The display panel of claim 8, wherein, The display panel includes a plurality of pixel rows arranged along the column direction, and the sub-pixels in the pixel rows are arranged along the row direction intersecting the column direction. Each type of display area in the N types of display areas includes at least two pixel rows.

11. The display panel of claim 8, wherein, Each display part in the M display parts includes the N types of display areas, and the arrangement order of each type of display area in the column direction is the same in each display part.

12. The display panel of claim 1, wherein, The display panel includes a third display part, the third display part includes at least one i-th type of display area and at least one j-th type of display area, and the i-th type of display area and the j-th type of display area in the third display part are arranged along a first direction, and the first direction is the extension direction of the scan lines of the display panel.

13. The display panel of claim 1, wherein, The display panel includes a gate drive module, the gate drive module includes N gate drive circuits, the N gate drive circuits correspond to the N types of display areas one by one, and provide scan driving signals to the sub-pixels in the corresponding display area. The M display parts are arranged along a preset direction, in the preset direction, the gate drive module provides scan driving signals to the sub-pixels of each type of display area in the N types of display areas in a first order, and in one display part, the sub-pixels of each type of display area are arranged in a second order in the preset direction. Wherein, the first order and the second order are the same.

14. The display panel of claim 1, wherein, The display panel includes a gate drive module, the gate drive module includes N gate drive circuits, the N gate drive circuits correspond to the N types of display areas one by one, and provide scan driving signals to the sub-pixels in the corresponding display area. The M display parts are arranged along a preset direction, in the preset direction, the gate drive module provides scan driving signals to the sub-pixels of each type of display area in the N types of display areas in a first order, and in one display part, the sub-pixels of each type of display area are arranged in a second order in the preset direction. Wherein, the first order and the second order are not the same.

15. The display panel of claim 1, wherein: The pulse width modulation module outputs a pulse width setting signal to the first end of the light-emitting control module based on a frequency sweeping signal, The driving transistor is configured to output a driving current according to a signal of the gate of the driving transistor and a signal of the first end of the driving transistor. The light emitting control module is configured to control the sub-pixels to emit light in response to the driving current under control of a light emitting control signal, and output the pulse width setting signal to a gate electrode of the driving transistor to control a light emitting time of the sub-pixel. In the N types of display areas, the sub-pixels in the same type of display area share the sweep signal and the light emitting control signal.

16. A display device comprising: The display panel comprises any one of the display panels in claims 1-15.

17. A driving method of a display panel, applied to the display panel of any one of claims 1-15, characterized in that, The driving method comprises: controlling the sub-pixels in the i-th type of display area to emit light in a first time period, and controlling the sub-pixels in the j-th type of display area to emit light in a second time period; wherein the first time period and the second time period at least partially do not overlap.

18. The driving method according to claim 17, wherein The first time period and the second time period do not overlap, and the first time period and the second time period are two different light emitting time periods. controlling the sub-pixels in the i-th type of display area to emit light in a first time period, and controlling the sub-pixels in the j-th type of display area to emit light in a second time period comprises: controlling the sub-pixels in the i-th type of display area to emit light simultaneously in the first time period, and writing a data signal to the sub-pixels in the j-th type of display area controlling the sub-pixels in the j-th type of display area to emit light simultaneously in the second time period.

19. The driving method according to claim 18, wherein A time length of the data signal written to the sub-pixels in the j-th type of display area is less than a time length of the first time period.

20. The driving method according to claim 17, wherein controlling the sub-pixels in the i-th type of display area to emit light in a first time period, and controlling the sub-pixels in the j-th type of display area to emit light in a second time period comprises: writing a data signal to the sub-pixels in the first display part in a third time period; controlling the sub-pixels in the i-th type of display area on the display panel to emit light in the first time period; writing a data signal to the sub-pixels in the second display part in a fourth time period; controlling the sub-pixels in the j-th type of display area on the display panel to emit light in the second time period; an order of starting time points of the time periods is: the third time period, the first time period, the fourth time period, and the second time period; wherein in the first time period, the data signal of each sub-pixel in the first display part is a data signal of a current frame of display picture, and the data signal of each sub-pixel in the second display part is a data signal of a previous frame of display picture; in the second time period, the data signal of each sub-pixel in the first display part is a data signal of a current frame of display picture, and the data signal of each sub-pixel in the second display part is a data signal of a current frame of display picture.

21. The driving method of claim 17, wherein: a total number of the N types of display areas is L, and the L types of display areas are arranged in a column direction; the L types of display areas are divided into N regions, and the N regions are arranged in the column direction; the driving method of the display panel comprises a plurality of data writing stages, and in one data writing stage, data signals are written to each type of display area in one region.

22. The driving method of claim 21, wherein: the writing of the data signals to each type of display area in one region comprises writing the data signals in a line-by-line manner.

23. The driving method according to claim 21, wherein The driving method of the display panel comprises a data writing stage, the data writing stage comprises a first data writing stage to an Nth data writing stage, and the N regions are a first region to an Nth region along the column direction; In an xth data writing stage, data signals are written to each type of display area of an xth region, wherein 1≤x≤N, and x is an integer.

24. The driving method according to claim 23, wherein The driving method of the display panel comprises a light emitting stage, the light emitting stage comprises a first light emitting stage to an Nth light emitting stage; The first data writing stage to the Nth data writing stage are alternately arranged with the first light emitting stage to the Nth light emitting stage, and a yth data writing stage is located before a yth light emitting stage; Wherein, 1≤y≤N, and y is an integer.

25. The driving method according to claim 24, wherein Wherein, The N types of display areas are a first type of display area to an Nth type of display area; In a zth light emitting stage, sub-pixels included in a zth type of display area are controlled to emit light; The ith light emitting stage is the first time period, and the jth light emitting stage is the second time period; Wherein, 1≤z≤N, and z is an integer.

26. The driving method according to claim 24, wherein The N types of display areas are a first type of display area to an Nth type of display area; In a wth light emitting stage, sub-pixels included in the first type of display area to the Nth type of display area are sequentially controlled to emit light; Wherein, 1≤w≤N, and w is an integer; Any one of the first light emitting stage to the Nth light emitting stage comprises the first time period and the second time period.

Images