Display panel and electronic device

Abstract

The display panel and the electronic device are provided, and the connection between the first power auxiliary line and the cathode layer and the second power auxiliary line in the first voltage drop area and the second voltage drop area is adjusted, so that the shape formed by the connection between all the third adapters and the connection between all the fourth adapters is the same as the shape formed by the connection between all the first adapters and the connection between all the second adapters in the adapter area, the loadings of the adapter area and the voltage drop area on the transverse reset signal are the same, the display panel has uniform display brightness, and the occurrence of the split screen defect is avoided.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of display, and in particular, to a display panel and an electronic device. BACKGROUND

[0002] In recent years, with the rapid development of the display industry, consumers' requirements for the frame of display products are becoming more and more strict, and narrow frame or even zero frame has gradually become a trend, so the FIP (Fanout In Panel) scheme is proposed. The data lines in the edge area of the display area are connected to the center area through the adapter line (FIP trace) and then connected with the output trace (fanout), thereby reducing the width occupied by the output trace in the lower frame, which is the mainstream scheme of the current narrow frame design. In order to achieve the uniformity of the display effect of the FIP area (i.e. the adapter area), the area in the display panel where the FIP trace is not set will also increase the metal trace with the same design in the film layer structure as a virtual trace, and these virtual traces can be connected with the VSS signal applied on the cathode layer to form the SIP (VSS in Panel) area (i.e. the voltage drop area), which greatly reduces the voltage drop of VSS, thereby achieving the effect of reducing the power consumption of the display panel.

[0003] The existing SIP area usually adds an adapter to connect the entire surface, that is, each row of horizontal virtual traces and each column of vertical virtual traces are electrically connected through the adapter to achieve the best voltage drop effect. However, corresponding to the FIP area, there are only two adapters in each row, so the difference in the number of adapters at the junction of the FIP area and the SIP area will cause the parasitic capacitance value between the horizontal reset signal to be different, resulting in different charging effects, which leads to the difference in brightness of the corresponding area of the display panel and causes mura (mura is a phenomenon that the display screen is not uniform). SUMMARY

[0004] The purpose of the embodiments of the present disclosure is to provide a display panel and an electronic device to solve the mura problem caused by the difference in the number of adapters between the FIP area and the SIP area in the prior art.

[0005] Embodiments of the present disclosure adopt the following technical solutions: a display panel at least comprising a display area and a peripheral area, the peripheral area being adjacent to a first side of the display area, the display area being at least divided into a first transition area, a second transition area, a first voltage drop area and a second voltage drop area, the above areas not overlapping with each other, the first transition area and the second transition area being located on a side of the display area close to the peripheral area, and a first side of the first transition area and a first side of the second transition area both coinciding with the first side of the display area, a first side of the first voltage drop area completely coinciding with a second side of the first transition area, the second side of the first transition area being a side opposite to the first side of the first transition area, a first side of the second voltage drop area completely coinciding with a second side of the second transition area, the second side of the second transition area being a side opposite to the first side of the second transition area;

[0006] The display panel at least comprises:

[0007] a substrate;

[0008] a plurality of conductive layers located on a side surface of the substrate, the plurality of conductive layers being arranged in a stack, and adjacent conductive layers having an insulating layer therebetween;

[0009] a light-emitting layer located on a side surface of the plurality of conductive layers away from the substrate, the light-emitting layer at least comprising an anode layer, a light-emitting unit layer and a cathode layer arranged in sequence;

[0010] The plurality of conductive layers comprise:

[0011] a plurality of data lines, the plurality of data lines being arranged at intervals along a first direction, and the plurality of data lines all extending along a second direction intersecting the first direction; the plurality of data lines comprising a plurality of first data lines and a plurality of second data lines, the plurality of first data lines being located in a first edge region and a second edge region of the display area along the first direction, and the plurality of second data lines being located in a central region of the display area along the first direction;

[0012] a plurality of transition lines, the transition lines comprising a same number of first transition lines and second transition lines, the first transition lines having the same extension direction as the first direction, and the second transition lines having the same extension direction as the second direction; the second transition lines being located in the same conductive layer as the data lines, and the first transition lines being located in different conductive layers from the second transition lines;

[0013] The first end of the first adapter line is electrically connected to the first data line through a first adapter, the second end of the first adapter line is electrically connected to the first end of the second adapter line through a second adapter, the second end of the second adapter line extends to the edge of the display area adjacent to the peripheral area, and the second adapter line is located between two adjacent second data lines;

[0014] The shape formed by the connection between all the first adapters at the two ends of the first adapter line electrically connected to all the first data lines in the first edge area and the connection between all the second adapters on the orthographic projection of the substrate is a first shape; the first shape is located in the orthographic projection of the first adapter area on the substrate;

[0015] The shape formed by the connection between all the first adapters at the two ends of the first adapter line electrically connected to all the first data lines in the second edge area and the connection between all the second adapters on the orthographic projection of the substrate is a second shape; the second shape is located in the orthographic projection of the second adapter area on the substrate, and the first shape and the second shape are mirror images of each other;

[0016] A plurality of power auxiliary lines, the power auxiliary lines including a plurality of first power auxiliary lines and a plurality of second power auxiliary lines, the first power auxiliary lines having the same extension direction as the first direction, and the second power auxiliary lines having the same extension direction as the second direction; the second power auxiliary lines and the second adapter lines are located in the same conductive layer, and the first power auxiliary lines and the first adapter lines are located in the same conductive layer;

[0017] The first voltage drop area includes a plurality of first sub-areas arranged along the second direction, each of the first sub-areas has the same size as the first adapter area, the first end of the first power auxiliary line located in the orthographic projection range of the first sub-area on the substrate is electrically connected to the cathode layer through a third adapter, the second end of the first power auxiliary line is electrically connected to the first end of the second power auxiliary line located in the orthographic projection range of the first sub-area on the substrate through a fourth adapter, and the connection between all the third adapters and the connection between all the fourth adapters in the orthographic projection range of each first sub-area on the substrate form a first shape.

[0018] The second pressure drop region comprises a plurality of second sub-regions arranged along the second direction, each of the second sub-regions has the same size as the second transfer region, a first end of a first power auxiliary line located in the second sub-region on the substrate is electrically connected to the cathode layer through a third transfer joint, a second end of the first power auxiliary line is electrically connected to a first end of a second power auxiliary line located in the second sub-region on the substrate through a fourth transfer joint, and a line connecting all the third transfer joints in the second sub-region on the substrate and a line connecting all the fourth transfer joints form a shape of the second shape on the substrate.

[0019] The display panel provided by the embodiments of the present disclosure comprises at least a display region and a peripheral region, the peripheral region is adjacent to a first side of the display region, the display region is divided into at least a first transfer region, a second transfer region, a first transition region, a second transition region and a pressure drop region, the above regions do not overlap, the first transfer region and the second transfer region are located on a side of the display region close to the peripheral region, and a first side of the first transfer region and a first side of the second transfer region coincide with the first side of the display region, a first side of the first transition region completely coincides with a second side of the first transfer region, the second side of the first transfer region is a side opposite to the first side of the first transfer region, a first side of the second transition region completely coincides with a second side of the second transfer region, and the second side of the second transfer region is a side opposite to the first side of the second transfer region; the pressure drop region is a region other than the first transfer region, the second transfer region, the first transition region and the second transition region in the display region.

[0020] The display panel comprises at least:

[0021] a substrate;

[0022] a plurality of conductive layers arranged on one side surface of the substrate, the plurality of conductive layers are arranged in a stack, and an insulating layer is arranged between adjacent conductive layers;

[0023] a light-emitting layer arranged on a side surface of the plurality of conductive layers away from the substrate, the light-emitting layer comprises at least an anode layer, a light-emitting unit layer and a cathode layer arranged in sequence;

[0024] The plurality of conductive layers comprise:

[0025] a plurality of data lines, the plurality of data lines are arranged at intervals along a first direction, and the plurality of data lines all extend along a second direction intersecting the first direction; the plurality of data lines comprises a plurality of first data lines and a plurality of second data lines, the plurality of first data lines are located at a first edge region and a second edge region of the display area along the first direction, and the plurality of second data lines are located at a central region of the display area along the first direction;

[0026] a plurality of transfer lines, the transfer lines comprise a same number of first transfer lines and second transfer lines, the first transfer lines have the same extension direction as the first direction, and the second transfer lines have the same extension direction as the second direction; the second transfer lines are located in the same conductive layer as the data lines, and the first transfer lines and the second transfer lines are located in different conductive layers;

[0027] a first end of the first transfer line is electrically connected to the first data line through a first transfer joint, a second end of the first transfer line is electrically connected to a first end of the second transfer line through a second transfer joint, a second end of the second transfer line extends to an edge of the display area adjacent to the peripheral area, and the second transfer line is located between two adjacent second data lines;

[0028] a connection between all the first transfer joints at both ends of the first transfer line electrically connected to all the first data lines in the first edge region and a connection between all the second transfer joints form a first shape in orthographic projection on the substrate; the first shape is located in orthographic projection on the substrate of the first transfer region;

[0029] a connection between all the first transfer joints at both ends of the first transfer line electrically connected to all the first data lines in the second edge region and a connection between all the second transfer joints form a second shape in orthographic projection on the substrate; the second shape is located in orthographic projection on the substrate of the second transfer region, and the first shape and the second shape are mirror images of each other;

[0030] a plurality of power supply auxiliary lines, the power supply auxiliary lines comprise a same number of first power supply auxiliary lines and second power supply auxiliary lines, the first power supply auxiliary lines have the same extension direction as the first direction, and the second power supply auxiliary lines have the same extension direction as the second direction; the second power supply auxiliary lines are located in the same conductive layer as the second transfer lines, and the first power supply auxiliary lines are located in the same conductive layer as the first transfer lines;

[0031] All the first power auxiliary lines and all the second power auxiliary lines located within the orthographic projection range of the first transition region on the substrate form intersection points on the orthographic projection of the substrate. The number of intersection points contained in each intersection row decreases uniformly from a first value corresponding to a first intersection row to a second value corresponding to a second intersection row. The first intersection row is the intersection row closest to the first side of the first transition region, and the second intersection row is the intersection row farthest from the first side of the first transition region.

[0032] All the first power auxiliary lines and all the second power auxiliary lines located within the orthographic projection range of the second transition region on the substrate form intersection points on the orthographic projection of the substrate. The number of intersection points contained in each intersection row decreases uniformly from the first value corresponding to the first intersection row to the second value corresponding to the second intersection row. The first intersection row is the intersection row closest to the first side of the second transition region, and the second intersection row is the intersection row farthest from the first side of the second transition region.

[0033] Each of the first power auxiliary lines located within the orthographic projection range of the voltage drop region on the substrate is electrically connected to the cathode layer via a sixth adapter, and each of the first power auxiliary lines is simultaneously electrically connected to all the second power auxiliary lines located within the orthographic projection range of the third voltage drop region on the substrate via a seventh adapter.

[0034] This disclosure also provides an electronic device, which includes at least the display panel described above.

[0035] The beneficial effects of this embodiment are as follows: by adjusting the connection between the first power auxiliary line and the cathode layer and the second power auxiliary line in the first voltage drop zone and the second voltage drop zone, the shape formed by the connection between all the third adapters and the connection between all the fourth adapters is the same as the shape formed by the connection between all the first adapters and the connection between all the second adapters in the transfer zone. The transfer zone and the voltage drop zone have the same loading of the horizontal reset signal, so that the display panel has uniform display brightness and avoids the occurrence of screen splitting defects. Attached Figure Description

[0036] To more clearly illustrate the technical solutions in the embodiments of this disclosure or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0037] Figure 1 A schematic diagram of display panel wiring setup in conventional technology;

[0038] Figure 2 This is a top view of the display panel partitioning in the first embodiment of this disclosure;

[0039] Figure 3 This is a schematic diagram of a portion of the wiring arrangement in the multilayer conductive layer in the first embodiment of this disclosure;

[0040] Figure 4 This is a schematic diagram of a display panel in the first embodiment of the present disclosure;

[0041] Figure 5 This is another schematic diagram of the display panel in the first embodiment of this disclosure;

[0042] Figure 6 for Figure 5 Enlarged schematic diagram of region 1 in the middle;

[0043] Figure 7 for Figure 5 Enlarged schematic diagram of region 2 in the middle;

[0044] Figure 8 for Figure 5 Enlarged schematic diagram of region 3 in the middle;

[0045] Figure 9 for Figure 5 Enlarged schematic diagram of region 4 in the middle;

[0046] Figure 10 for Figure 5 Enlarged schematic diagram of region 5 in the middle;

[0047] Figure 11 This is a schematic diagram of a display panel according to a second embodiment of the present disclosure;

[0048] Figure 12 This is another schematic diagram of the display panel in the second embodiment of this disclosure. Detailed Implementation

[0049] Various embodiments and features of this disclosure are described herein with reference to the accompanying drawings.

[0050] It should be understood that various modifications can be made to the embodiments described herein. Therefore, the above description should not be considered as limiting, but merely as an example of embodiments. Other modifications within the scope and spirit of this disclosure will be apparent to those skilled in the art.

[0051] The accompanying drawings, which are included in and form part of this specification, illustrate embodiments of the present disclosure and, together with the general description of the disclosure given above and the detailed description of the embodiments given below, serve to explain the principles of the disclosure.

[0052] These and other characteristics of the present disclosure will become patently apparent as the description proceeds.

[0053] It should also be understood that, although the present disclosure has been described in relation to some specific examples, many other equivalent forms of which will be apparent to those skilled in the art in the light of the present disclosure, the features of which will remain within the scope of protection defined by the claims.

[0054] The above and other aspects, features, and advantages of the present disclosure will become apparent from the following detailed description, taken in conjunction with the accompanying drawings.

[0055] Specific embodiments of the present disclosure are described hereinafter with reference to the drawings; however, it will be understood that the disclosed embodiments are merely examples of the present disclosure, which can be embodied in many other forms. Well-known and / or repetitive functions and structures are not described in detail to avoid obscuring the present disclosure in unnecessary or redundant details. Therefore, specific structural and functional details disclosed herein are not intended to limit the present disclosure, but merely as a basis for the claims and representative basis for teaching one skilled in the art to variously employ the present disclosure in virtually any appropriate detailed structure.

[0056] The specification can use phrases such as "in one embodiment", "in another embodiment", "in yet another embodiment", or "in other embodiments", which can refer to one or more of the same or different embodiments under the present disclosure.

[0057] In recent years, with the rapid development of the display industry, consumers' requirements for the frame of display products are becoming more and more strict, and narrow frame or even zero frame has gradually become a trend, so the FIP scheme is proposed. The data line in the edge area of the display area is connected to the center area through the adapter line (FIP trace), and then connected with the output trace (fanout), thereby reducing the width occupied by the output trace in the lower frame, which is the mainstream scheme of the current narrow frame design. As shown in Figure 1 In order to achieve uniformity of the display effect of the FIP area, the area in the display panel where the FIP trace is not set will also increase the metal trace of the same design in the film layer structure as a virtual trace, and these virtual traces can be connected with the VSS signal applied on the cathode layer to form a SIP area, which greatly reduces the voltage drop of VSS, thereby achieving the effect of reducing the power consumption of the display panel.

[0058] The existing SIP area usually adds an adapter to connect the entire surface, that is, each row of horizontal virtual traces and each column of vertical virtual traces are electrically connected through the adapter to achieve the best voltage drop effect. However, corresponding to the FIP area, only two adapters are set for each row, and the shape of the connection line between the adapters is as shown in Figure 1The middle white solid line, so at the junction of the FIP region and the SIP region (dashed line) Figure 1 The difference in the number of adapters at the dashed line will result in different parasitic capacitance values between the lateral reset signal, resulting in different charging effects, causing the display panel to have different brightness in the upper half of the area divided by the dashed line, resulting in a poor split screen.

[0059] To solve the above problems, the first embodiment of the present disclosure provides a display panel, which adjusts the connection mode of the wiring in the remaining area on the basis of the current adapter scheme. As shown in FIG. 2, a top view of the display panel in this embodiment mainly includes a display area 10 and a peripheral area 20, the peripheral area 20 is adjacent to the first side of the display area 10, corresponding Figure 2 That is, the peripheral area 20 is connected with the lower side of the display area 10, and the peripheral area 20 is used to arrange output wiring and lap joint area pins, etc. The display area 10 is further divided into a first adapter area 31, a second adapter area 32, a first voltage drop area 41 and a second voltage drop area 42, and the above-mentioned areas do not overlap. In fact, the first adapter area 31 and the second adapter area 32 correspond to the two FIP regions provided in the FIP scheme, and the first voltage drop area 41 and the second voltage drop area 42 correspond to the SIP region. The following will be described in combination with Figures 3 to 10 The division of the first adapter area 31, the second adapter area 32, the first voltage drop area 41 and the second voltage drop area 42 will be described.

[0060] In this embodiment, from the film layer structure of the display panel, it mainly includes a substrate; a plurality of conductive layers located on one side surface of the substrate, that is, a plurality of conductive layers are stacked between the conductive layers, and the adjacent conductive layers are electrically isolated by an insulating layer. Different conductive layers are used to deploy different metal lines, including but not limited to data line data, gate line gate, source-drain metal line SD1 and SD2, etc.; a light-emitting layer located on the side surface of the plurality of conductive layers away from the substrate, which at least includes an anode layer, a light-emitting unit and a cathode layer arranged in sequence. The specific setting mode and preparation method of the above hierarchical structure can be directly realized by using conventional technology, and this embodiment will not be described in detail.

[0061] Figure 3 Part of the wiring setting in the plurality of conductive layers in the display area is shown. As shown in FIG. 3, the display area 10 is divided into a first adapter area 31, a second adapter area 32, a first voltage drop area 41 and a second voltage drop area 42, and the first adapter area 31 and the second adapter area 32 are used to deploy the FIP region, and the first voltage drop area 41 and the second voltage drop area 42 are used to deploy the SIP region. Figure 3As shown, at least a plurality of data lines 100 are included in the multi-layer conductive layer, the plurality of data lines are arranged at intervals along a first direction X, and each data line extends along a second direction Y intersecting the first direction X. In this embodiment, the first direction X refers to the horizontal direction in the plane of the display panel, and the second direction Y corresponds to the vertical direction. In combination with the positions of different data lines, the data lines are divided into a plurality of first data lines 101 and second data lines 102. The plurality of first data lines 101 are located in the first edge region 11 and the second edge region 12 of the display area 10 along the first direction X, and the plurality of second data lines 102 are located in the central region 13 of the display area along the first direction X, which are divided by dashed lines. The edge region mainly refers to the region with a rounded corner on both sides of the display area 10, and the width of the edge region in the first direction X can be greater than or equal to the width of the rounded corner in the first direction X.

[0062] The FIP scheme actually connects the first data line 101 to the central region by using the adapter line and then performs fanout wiring connection to achieve the narrow frame effect. Therefore, a plurality of adapter lines 200 are further provided in the multi-layer conductive layer, which include a same number of first adapter lines 201 and second adapter lines 202. The extension direction of the first adapter line 201 is the same as the first direction X, and the extension direction of the second adapter line 202 is the same as the second direction Y. The second adapter line 202 is located in the same conductive layer as the data line 100, and the first adapter line 201 is located in a different conductive layer from the second adapter line 202. In the adapter process, the first end of the first adapter line 201 is electrically connected to the first data line 101 through a first adapter head (indicated by a black solid circle in Figure 3 ), the second end of the first adapter line 201 is electrically connected to the first end of the second adapter line 202 through a second adapter head (indicated by a black solid triangle in Figure 3 ), and the second end of the second adapter line 202 extends to the edge (lower edge) of the display area 10 adjacent to the peripheral area 20, and the second adapter line 202 is located between two adjacent second data lines 102. That is, the first data line 101 is jumper connected to the second adapter line 202 by using the first adapter line 201 in a different layer from the first data line 101.

[0063] In actual implementation, the first adapter lines 201 and the second adapter lines 202 are usually arranged on one side of the display area 10 close to the peripheral area 20, so as to be connected with the output wires of the peripheral area 20, and since the display area has edge areas on both sides, one adapter area is arranged on each of the left and right sides, the setting principles of the adapter lines in the two adapter areas are the same, and the widths of the adapter areas in the first direction X and the second direction Y are also the same. Specifically, the first edge (lower edge) of the first adapter area 31 coincides with the first edge of the display area 20, the second edge (upper edge) opposite to the first edge of the first adapter area 31 is the position of the first adapter line 201 farthest from the first edge of the display area among all the first adapter lines 201 electrically connected with the first data line 101 in the first edge area 11, the third edge (left edge) of the first adapter area 31 coincides with the side edge of the display area 20, and the fourth edge (right edge) is the position of the second adapter line 202 farthest from the first edge area 11 among all the second adapter lines 202 electrically connected with the first data line 101 in the first edge area 11. Similarly, the first edge (lower edge) of the second adapter area 32 also coincides with the first edge of the display area 20, the second edge of the second adapter area 32 is the position of the first adapter line 201 farthest from the first edge of the display area among all the first adapter lines 201 electrically connected with the first data line 101 in the second edge area 12, the third edge of the second adapter area 32 is the position of the second adapter line 202 farthest from the second edge area among all the second adapter lines 202 electrically connected with the first data line 101 in the second edge area 12, and the fourth edge of the second adapter area coincides with the other side edge of the display area. It should be noted that the number of the second adapter lines 202 is the same as that of the first data lines 101, and the positions of the second adapter lines 202 are determined according to the arrangement of the second data lines 102 and the process requirements. In principle, the second adapter lines are preferably close to the corresponding edge area as far as possible under the condition of meeting the FIP scheme.

[0064] In the embodiment, the shape formed by the connection lines between all the first adapter heads at both ends of the first adapter lines 201 electrically connected with all the first data lines 101 in the first edge area 11 and the connection lines between all the second adapter heads on the substrate is a first shape, the first shape is usually a cross shape as shown in Figure 4 the first shape is located in the projection of the first adapter area 31 on the substrate. Similarly, the shape formed by the connection lines between all the first adapter heads at both ends of the first adapter lines 201 electrically connected with all the first data lines 101 in the second edge area 12 and the connection lines between all the second adapter heads on the substrate is a second shape; the second shape is located in the projection of the second adapter area 32 on the substrate, the first shape and the second shape are mirror images of each other, and are also cross shapes.

[0065] Further combining Figure 3Corresponding to the setting of the transfer lines, a plurality of power auxiliary lines 300 are also included in the multi-layer conductive layer, which correspond to the design of the transfer lines 200 and also include a same number of a plurality of first power auxiliary lines 301 and a plurality of second power auxiliary lines 302, the extension direction of the first power auxiliary lines 301 is the same as the first direction X, and the extension direction of the second power auxiliary lines 302 is the same as the second direction Y; the first power auxiliary lines 301 are located in the same conductive layer as the first transfer lines 201, and the second power auxiliary lines 302 are located in the same conductive layer as the second transfer lines 202. It should be noted that although the first power auxiliary lines 301 and the first transfer lines 201 are located in the same conductive layer, there is no connection relationship between them, and the second power auxiliary lines 302 and the second transfer lines 202 are the same. It should be noted that in order to distinguish the vertical second power auxiliary lines 302 and the vertical data lines 100, the second power auxiliary lines 302 are represented by dotted lines in Figure 3 , and in addition, Figure 3 , the horizontal gate lines and other traces are not shown, and all horizontal traces are only used to represent the first transfer lines or the first power auxiliary lines.

[0066] In order to avoid the difference in parasitic capacitance value between the horizontal traces in different regions and the reset signal, with reference to the positions of the first transfer area 31 and the second transfer area 32 and the transfer head setting, the corresponding transfer head setting in the first voltage drop area 41 and the second voltage drop area 42 corresponding to the first transfer area 31 and the second transfer area 32 is adjusted in this embodiment. Specifically, the first voltage drop area 41 refers to a region in the display area above the first transfer area 31 and having the same width as the first transfer area 31 in the first direction X, that is, the first edge (lower edge) of the first voltage drop area 41 completely coincides with the second edge of the first transfer area 31, the second edge of the first voltage drop area 41 coincides with the second edge (upper edge) of the display area, and the second edge of the display area is opposite to the first edge of the display area. The third edge (left edge) of the first voltage drop area 41 coincides with the side edge of the display area, and the fourth edge (right edge) of the first voltage drop area 41 is the extension line of the fourth edge of the first transfer area 31 in the second direction Y. Similarly, the first edge of the second voltage drop area 42 completely coincides with the second edge of the second transfer area 32, the second edge of the second voltage drop area 42 coincides with the second edge of the display area, the third edge of the second voltage drop area 42 is the extension line of the third edge of the second transfer area 32 in the second direction Y, and the fourth edge of the second voltage drop area coincides with the other side edge of the display area.

[0067] Taking the first voltage drop area 41 as an example, as shown in Figure 4 , the first voltage drop area 41 is divided into a plurality of first sub-areas 411 arranged in the second direction Y in sequence, and each first sub-area 411 has the same size as the first transfer area 31, that is, the widths of the two in the first direction X and the second direction Y are the same, Figure 4The first sub-regions 411 are divided by dashed lines. For a single first sub-region 411, in this embodiment, the first end of the first power supply auxiliary line 301 located within the orthogonal projection range of the first sub-region 411 onto the substrate is connected to the cathode layer via a third adapter (…). Figure 3 The first power auxiliary line 301 is electrically connected to the second power auxiliary line 302 located within the orthographic projection range of the first sub-region on the substrate via a fourth adapter. Figure 3 (The solid black pentagram in the middle indicates the electrical connection.) The shape formed by the orthogonal projection of the lines between all the third adapters and the lines between all the fourth adapters within the orthogonal projection range of each first sub-region 411 on the substrate is the first shape, which is the same as the shape of the adapter connection lines in the first adapter area 31. This makes the parasitic capacitance value and position change between the transversely arranged adapters and the reset signal in each first sub-region 411 of the first voltage drop area 41 the same as in the first adapter area 31, thereby avoiding the split-screen problem caused by uneven brightness.

[0068] Similarly, the second pressure drop region 42 includes multiple second sub-regions 421 arranged along the second direction Y (in Figure 4 (Divided by dashed lines in the middle), each second sub-region 421 is the same size as the second transition region 32. The first end of the first power auxiliary line 301 located within the orthographic projection range of the second sub-region 421 on the substrate is electrically connected to the cathode layer through a third adapter. The second end of the first power auxiliary line 301 is electrically connected to the first end of the second power auxiliary line 302 located within the orthographic projection range of the second sub-region 421 on the substrate through a fourth adapter. The shape formed by the orthographic projection of the lines between all the third adapters and the lines between all the fourth adapters within the orthographic projection range of each second sub-region 421 on the substrate is a second shape, that is, the same as the shape of the adapter connection lines in the second transition region 32.

[0069] It should be noted that the first sub-region 411 and the second sub-region 421 are only functional partitions for ease of understanding during the description process, and do not represent the physical partitions performed in the actual manufacturing process; furthermore, the multiple first sub-regions are preferably arranged sequentially from the first transition area to the second side of the display area. If the area formed on the side near the second side of the display area cannot be exactly the same as the first transition area, then when setting the third and fourth transitions, the first shape can be referred to for partial setting, and the same applies to the second sub-region.

[0070] This embodiment adjusts the connection between the first power auxiliary line and the cathode layer and the second power auxiliary line in the first voltage drop zone and the second voltage drop zone, so that the shape formed by the connection between all the third adapters and the connection between all the fourth adapters is the same as the shape formed by the connection between all the first adapters and the connection between all the second adapters in the transfer zone. The transfer zone and the voltage drop zone have the same loading of the horizontal reset signal, so that the display panel has uniform display brightness and avoids the occurrence of screen splitting defects.

[0071] Further reference Figure 4 In the actual setup of the first transition area 31 and the second transition area 32, they cannot cover the width of the display area in the first direction X. Therefore, the display area also includes a third pressure drop area 43, whose first side (bottom side) coincides with the first side of the display area. That is, the first side of the third pressure drop area 43 is the part of the first side of the display area that does not coincide with the first side of the first transition area 31 and the first side of the second transition area 32. The second side (top side) of the third pressure drop area 43 corresponds to the part of the second side of the display area that does not coincide with the second side of the first pressure drop area 41 and the second side of the second pressure drop area 42. The third side (left side) of the third pressure drop area 43 completely coincides with the fourth side of the first pressure drop area 41 and the fourth side of the first transition area 31. That is, the sum of the fourth side of the first pressure drop area 41 and the fourth side of the first transition area 31. The fourth side of the third pressure drop area 43 completely coincides with the third side of the second pressure drop area 42 and the third side of the second transition area 32.

[0072] Within the third voltage drop region 43, referencing the arrangement of the first voltage drop region 41 or the second voltage drop region 42, the third voltage drop region 43 is divided into multiple third sub-regions 431 evenly arranged along the second direction Y. The first power auxiliary line located within the orthogonal projection range of each third sub-region 431 onto the substrate and its corresponding second power auxiliary line are connected via a fifth adapter (…). Figure 3 (The solid black diamond mark indicates the electrical connection.) The shape formed by the orthographic projection of the lines between all fifth adapters within the orthographic projection range of each third sub-region 431 onto the substrate is a uniform third shape. (Reference) Figure 4 As shown, the third shape can be a straight line, a broken line, a curve, or other shapes, as long as the third shape formed in multiple third sub-regions 431 is the same. It should be noted that the first power auxiliary line 301 corresponding to the third voltage drop region 43 is connected to the first power auxiliary line 301 in the same row in the first voltage drop region 41 and the second voltage drop region 42. Therefore, no adapter is set between the first power auxiliary line 301 and the cathode layer in the third voltage drop region 43.

[0073] Corresponding to Figure 4The connection mode shown solves the problem of poor screen splitting, but the number of adapters is small, and the voltage drop effect of the power auxiliary line on the cathode is not obvious, and the power consumption is not obviously reduced. Based on this, in some embodiments, as shown in Figure 5 The third voltage drop area 43 can be simultaneously connected to all second power auxiliary lines 302 in the third voltage drop area 43 by fifth adapters within the orthographic projection range of the substrate, that is, a surface connection is formed in the third voltage drop area 43. Since the third voltage drop area 43 actually penetrates the entire display area in the second direction Y, there is no difference in the value of the transverse parasitic capacitance at different positions in the third voltage drop area 43, and thus by combining the different connection modes of the two adapters, the effect of reducing power consumption in the SIP area can be maximized while avoiding causing poor screen splitting.

[0074] In some embodiments, corresponding to the design of the multi-layer conductive layer, the first adapter and the first power auxiliary line can be set in the second source-drain metal layer SD2 of the source-drain metal layer, and the data line, the second adapter and the second power auxiliary line can be set in the first source-drain metal layer SD1 of the source-drain metal layer, wherein SD1 is closer to the substrate, and SD2 is set on the side of SD1 away from the substrate. Of course, the above hierarchical settings can also be set in other conductive layers as long as the corresponding effects can be achieved.

[0075] Figures 6 to 10 The enlarged schematic diagrams of the regions 1 to 5 marked in Figure 5 are shown respectively.

[0076] Among them, Figure 6 The enlarged schematic diagram of region 1 can be seen that the vertical second adapter line in the left first adapter area 31 accesses the data signal of the fanout, and all the second power auxiliary lines of the right third voltage drop area 43 access the VSS signal, which improves the effect of reducing power consumption. Figure 7 The enlarged schematic diagram of region 2 can be seen that all the transverse first power auxiliary lines and the vertical second power auxiliary lines in the third voltage drop area 43 are electrically connected by fifth adapters to form a surface connection in the third voltage drop area 43. It should be noted that, in combination with Figure 7 the setting positions of the red pixels (R), the blue pixels (B), the green pixels (G1 and G2) in

[0077] Figure 8 The enlarged schematic diagram of region 3 is Figure 3The position marked by the circle is the first adapter and the second adapter set in the second pressure drop zone 42, so that the orthographic projection of their connection line on the substrate forms a check mark shape. Figure 9 This is an enlarged view of area 4, showing the connection method between the first power auxiliary line and VSS at the left border of the display area. Specifically, the first power auxiliary line located on the SD2 layer is connected to the VSS signal at the border after passing through a via jumper to the SD1 layer. Figure 10 This is an enlarged schematic diagram of area 5, showing that the second power auxiliary line at the upper border of the display area can be directly connected to the VSS signal of the upper border via SD1.

[0078] The second embodiment of this disclosure also provides a display panel, similar to the display panel in the first embodiment. This display panel also has a display area 10 and a peripheral area 20. The setting principles for the first transition area 31 and the second transition area 32 in the display area 10 are the same, and the description of the first transition area 31 and the second transition area 32 in the first embodiment can be directly referred to; this embodiment will not repeat the description here. Unlike the first embodiment, the display area 10 in this embodiment also includes a first transition area 51, a second transition area 52, and a voltage drop area 40, and these areas do not overlap.

[0079] Specifically, refer to Figure 11 As shown, the first transition region 51 is the area where the first side and the second side of the first transition region 31 completely overlap. All the intersections of the first power auxiliary lines and all the second power auxiliary lines within the orthographic projection range of the first transition region 51 on the substrate form intersection points. Unlike the first embodiment where adapters are set at the intersection points in the third voltage drop region for electrical connection, no adapters are set at the intersection points in the first transition region 51 in this embodiment, keeping the first power auxiliary lines and all the second power auxiliary lines disconnected. However, the number of intersection points contained in each row is different. Specifically, it decreases uniformly from the first value corresponding to the first intersection point row to the second value corresponding to the second intersection point row. The first intersection point row is the intersection point row closest to the first side of the first transition region, and the second intersection point row is the intersection point row farthest from the first side of the first transition region. Similarly, the second transition region 52 is defined. The first side of the second transition region 52 completely coincides with the second side of the second transition region 32. All first power auxiliary lines and all second power auxiliary lines within the orthographic projection range of the second transition region 52 on the substrate form intersection points on the orthographic projection of the substrate. The number of intersection points contained in each intersection point row decreases uniformly from the first value corresponding to the first intersection point row to the second value corresponding to the second intersection point row. The first intersection point row is the intersection point row closest to the first side of the second transition region, and the second intersection point row is the intersection point row farthest from the first side of the second transition region.

[0080] The area of the display area 10 except the first transition area 31, the second transition area 32, the first transition area 51 and the second transition area 52 is the pressure drop area 40. In the embodiment, each first power auxiliary line in the pressure drop area 40 within the orthographic projection range of the substrate is electrically connected to the cathode layer through the sixth transition joint, and each first power auxiliary line is electrically connected to all the second power auxiliary lines in the third pressure drop area within the orthographic projection range of the substrate through the seventh transition joint, that is, the same surface connection as in the third pressure drop area in the first embodiment is realized in the pressure drop area 40. Further, in combination with the change of the number of intersection points in the first transition area and the second transition area, the number of transition joints gradually increases in the direction extending from the first side to the second side of the display area 10, and the screen splitting defect caused by the sudden change of the parasitic capacitance value of the adjacent position does not occur, and the good cathode pressure drop effect can be ensured.

[0081] In actual implementation, the maximum width of the first transition area 51 in the second direction Y is at most twice the maximum width of the first transition area 31 in the second direction Y. If the width of the transition area in the second direction Y (also referred to as the number of covered pixel rows) is too wide, display defects in dark state are easily caused. Therefore, the width of the first transition area 51 in the second direction Y is limited. The width limitation of the second transition area 52 in the second direction Y is the same.

[0082] Figure 11 The orthographic projection shapes of the first transition area 51 and the second transition area 52 on the substrate are triangles, which can also be semicircles or semi-ellipses. Meanwhile, the orthographic projections of the first transition area 51 and the second transition area 52 on the substrate are mirror images of each other, so as to ensure the uniformity of the overall display effect of the display panel. In the case where the orthographic projection shapes of the first transition area 51 and the second transition area 52 on the substrate are triangles, one side of the triangle coincides with the second side of the corresponding transition area, Figure 11 The triangle is a right triangle, one leg of the right triangle coincides with the second side of the transition area, and in combination with the width limitation of the transition area in the second direction Y, the angle between the hypotenuse of the right triangle and the second side of the transition area is between 45° and 65°. Figure 12 The orthographic projection shapes of the first transition area 51 and the second transition area 52 on the substrate are semicircles, and the long axis or the short axis of the semicircle coincides with the second side of the corresponding transition area. If the orthographic projection shapes of the first transition area 51 and the second transition area 52 on the substrate are semicircles, the diameter of the semicircle coincides with the second side of the corresponding transition area.

[0083] The third embodiment of the present disclosure provides an electronic device comprising the display panel provided by the first or second embodiment of the present disclosure, so that the electronic device has uniform display effect and does not have the problem of poor split screen.

[0084] The above describes the embodiments of the present disclosure in detail, but the present disclosure is not limited to these specific embodiments. Those skilled in the art can make various modifications and embodiments on the basis of the concept of the present disclosure, and these modifications and embodiments shall fall within the scope of the present disclosure.

Claims

1. A display panel, characterized by, The display panel comprises at least: a substrate; a plurality of conductive layers arranged on one side surface of the substrate, the adjacent conductive layers being separated by an insulating layer; a light-emitting layer arranged on the side surface of the plurality of conductive layers away from the substrate, the light-emitting layer comprising at least an anode layer, a light-emitting unit layer and a cathode layer arranged in sequence; wherein the plurality of conductive layers comprise: a plurality of data lines, the plurality of data lines being arranged at intervals along a first direction and extending along a second direction intersecting the first direction; the plurality of data lines comprising a plurality of first data lines and a plurality of second data lines, the plurality of first data lines being arranged in a first edge region and a second edge region of the display area along the first direction, and the plurality of second data lines being arranged in a central region of the display area along the first direction; a plurality of transfer lines, the transfer lines comprising a plurality of first transfer lines and a plurality of second transfer lines, the first transfer lines extending in the same direction as the first direction, and the second transfer lines extending in the same direction as the second direction; the second transfer lines being arranged in the same conductive layer as the data lines, and the first transfer lines being arranged in a different conductive layer from the second transfer lines; a first end of the first transfer line being electrically connected to the first data line through a first transfer joint, a second end of the first transfer line being electrically connected to a first end of the second transfer line through a second transfer joint, and a second end of the second transfer line extending to an edge of the display area adjacent to the peripheral area, and the second transfer line being arranged between two adjacent second data lines; a first shape formed by the projection of the connection between all the first transfer joints at both ends of the first transfer line electrically connected to all the first data lines in the first edge region and the connection between all the second transfer joints on the substrate, the first shape being located within the projection of the first transfer area on the substrate; and a second shape formed by the projection of the connection between all the second transfer joints on the substrate, the second shape being located within the projection of the second transfer area on the substrate. A shape formed by the orthogonal projection of the connection between all the first terminals of the first switch lines electrically connected with all the first data lines in the second edge area and the connection between all the second switch lines on the substrate is a second shape; the second shape is located in the orthogonal projection of the second switch area on the substrate, and the first shape and the second shape are mirror images of each other; A plurality of power auxiliary lines, the power auxiliary lines include a plurality of first power auxiliary lines and a plurality of second power auxiliary lines, the first power auxiliary lines have the same extension direction as the first direction, and the second power auxiliary lines have the same extension direction as the second direction; the second power auxiliary lines and the second switch lines are located in the same conductive layer, and the first power auxiliary lines and the first switch lines are located in the same conductive layer; The first voltage drop area includes a plurality of first sub-areas arranged along the second direction, each first sub-area has the same size as the first switch area, the first end of the first power auxiliary line located in the orthogonal projection range of the first sub-area on the substrate is electrically connected to the cathode layer through a third terminal, and the second end of the first power auxiliary line is electrically connected to the first end of the second power auxiliary line located in the orthogonal projection range of the first sub-area on the substrate through a fourth terminal; the shape formed by the orthogonal projection of the connection between all the third terminals and the connection between all the fourth terminals in the orthogonal projection range of each first sub-area on the substrate is the first shape; The second voltage drop area includes a plurality of second sub-areas arranged along the second direction, each second sub-area has the same size as the second switch area, the first end of the first power auxiliary line located in the orthogonal projection range of the second sub-area on the substrate is electrically connected to the cathode layer through a third terminal, and the second end of the first power auxiliary line is electrically connected to the first end of the second power auxiliary line located in the orthogonal projection range of the second sub-area on the substrate through a fourth terminal; the shape formed by the orthogonal projection of the connection between all the third terminals and the connection between all the fourth terminals in the orthogonal projection range of each second sub-area on the substrate is the second shape.

2. The display panel of claim 1, wherein, The second edge of the first switch area is the position of the first switch line farthest from the first edge of the display area among all the first switch lines electrically connected with the first data lines in the first edge area, the third edge of the first switch area coincides with the side edge of the display area, and the fourth edge of the first switch area is the position of the second switch line farthest from the first edge area among all the second switch lines electrically connected with the first data lines in the first edge area; a second edge of the second transition area is a position of a first transition line farthest from the first edge of the display area among all the first transition lines electrically connected with the first data line in the second edge area, a third edge of the second transition area is a position of a second transition line farthest from the second edge area among all the second transition lines electrically connected with the first data line in the second edge area, and a fourth edge of the second transition area coincides with another side edge of the display area; a second edge of the first voltage drop area coincides with a second edge of the display area, the second edge of the display area being opposite to the first edge of the display area, a third edge of the first voltage drop area coincides with a side edge of the display area, and a fourth edge of the first voltage drop area is an extension line of the fourth edge of the first transition area in the second direction; a second edge of the second voltage drop area coincides with the second edge of the display area, a third edge of the second voltage drop area is an extension line of the third edge of the second transition area in the second direction, and a fourth edge of the second voltage drop area coincides with another side edge of the display area.

3. The display panel of claim 2, wherein, The display area further comprises a third voltage drop area; wherein a first edge of the third voltage drop area is a part of the first edge of the display area that does not coincide with the first edge of the first transition area and the first edge of the second transition area; a second edge of the third voltage drop area is a part of the second edge of the display area that does not coincide with the second edge of the first voltage drop area and the second edge of the second voltage drop area; a third edge of the third voltage drop area completely coincides with the fourth edge of the first voltage drop area and the fourth edge of the first transition area; a fourth edge of the third voltage drop area completely coincides with the third edge of the second voltage drop area and the third edge of the second transition area.

4. The display panel of claim 3, wherein, The third voltage drop area is divided into a plurality of third sub-areas arranged uniformly along the second direction, the first power supply auxiliary line located in each third sub-area within the orthographic projection range of the substrate is electrically connected with the corresponding second power supply auxiliary line through a fifth transition joint, and the connecting line between all the fifth transition joints within the orthographic projection range of each third sub-area on the substrate forms a uniform third shape.

5. The display panel of claim 3, wherein, Each first power supply auxiliary line located in the orthographic projection range of the third voltage drop area on the substrate is electrically connected with all the second power supply auxiliary lines located in the orthographic projection range of the third voltage drop area on the substrate through a fifth transition joint.

6. A display panel, characterized by, The display panel comprises at least: a substrate; a plurality of conductive layers arranged on one side of the substrate, adjacent conductive layers being separated by an insulating layer; a light-emitting layer arranged on the side of the plurality of conductive layers away from the substrate, the light-emitting layer comprising at least an anode layer, a light-emitting unit layer and a cathode layer arranged in sequence; wherein the plurality of conductive layers comprise: a plurality of data lines arranged at intervals along a first direction, the plurality of data lines extending along a second direction intersecting the first direction; the plurality of data lines comprising a plurality of first data lines and a plurality of second data lines, the plurality of first data lines being arranged in a first edge region and a second edge region of the display area along the first direction, the plurality of second data lines being arranged in a central region of the display area along the first direction; a plurality of transfer lines, the transfer lines comprising a plurality of first transfer lines and a plurality of second transfer lines, the first transfer lines extending in the same direction as the first direction, the second transfer lines extending in the same direction as the second direction; the second transfer lines being arranged in the same conductive layer as the data lines, the first transfer lines being arranged in a different conductive layer from the second transfer lines; a first end of the first transfer line being electrically connected to the first data line via a first transfer joint, a second end of the first transfer line being electrically connected to a first end of the second transfer line via a second transfer joint, a second end of the second transfer line extending to an edge of the display area adjacent to the peripheral area, and the second transfer line being arranged between two adjacent second data lines; a first shape formed by the projection of the connection between all the first transfer joints at the two ends of the first transfer line electrically connected to all the first data lines in the first edge region and the connection between all the second transfer joints on the substrate; the first shape being located within the projection of the first transfer region on the substrate; and a second shape formed by the projection of the connection between all the first transfer joints at the two ends of the first transfer line electrically connected to all the first data lines in the second edge region and the connection between all the second transfer joints on the substrate; the second shape being located within the projection of the second transfer region on the substrate. The shape formed by the orthogonal projection of the connection between all the first terminals of the first switch lines electrically connected with all the first data lines in the second edge area and the connection between all the second switch lines on the substrate is a second shape; the second shape is located in the orthogonal projection of the second switch area on the substrate, and the first shape and the second shape are mirror images of each other; A plurality of power auxiliary lines, the power auxiliary lines including a plurality of first power auxiliary lines and a plurality of second power auxiliary lines, the first power auxiliary lines having the same extension direction as the first direction, and the second power auxiliary lines having the same extension direction as the second direction; the second power auxiliary lines and the second switch lines are located in the same conductive layer, and the first power auxiliary lines and the first switch lines are located in the same conductive layer; All the first power auxiliary lines and all the second power auxiliary lines located in the range of the orthogonal projection of the first transition area on the substrate form intersection points on the orthogonal projection of the substrate, the number of the intersection points included in each intersection point row uniformly decreases from a first value corresponding to a first intersection point row to a second value corresponding to a second intersection point row, the first intersection point row being the intersection point row closest to the first side of the first transition area, and the second intersection point row being the intersection point row farthest from the first side of the first transition area; All the first power auxiliary lines and all the second power auxiliary lines located in the range of the orthogonal projection of the second transition area on the substrate form intersection points on the orthogonal projection of the substrate, the number of the intersection points included in each intersection point row uniformly decreases from a first value corresponding to a first intersection point row to a second value corresponding to a second intersection point row, the first intersection point row being the intersection point row closest to the first side of the second transition area, and the second intersection point row being the intersection point row farthest from the first side of the second transition area; Each of the first power auxiliary lines located in the range of the orthogonal projection of the voltage drop area on the substrate is electrically connected to the cathode layer through a sixth switch terminal, and each of the first power auxiliary lines is simultaneously electrically connected to all the second power auxiliary lines located in the range of the orthogonal projection of the third voltage drop area on the substrate through a seventh switch terminal.

7. The display panel of claim 6, wherein, The maximum width of the first transition area in the second direction is at most twice the maximum width of the first switch area in the second direction; The maximum width of the second transition area in the second direction is at most twice the maximum width of the second switch area in the second direction.

8. The display panel of claim 7, wherein, The orthogonal projections of the first transition area and the second transition area on the substrate are mirror images of each other; The shape of the orthogonal projection is at least one of the following shapes: a triangle, a semicircle, and a semi-ellipse.

9. The display panel of claim 8, wherein, When the orthogonal projections of the first transition area and the second transition area on the substrate are a triangle, one side of the triangle coincides with the second side of the corresponding switch area; When the orthogonal projections of the first transition area and the second transition area on the substrate are a semicircle, the diameter of the semicircle coincides with the second side of the corresponding switch area; and When the orthogonal projections of the first transition area and the second transition area on the substrate are a semi-ellipse, the major axis of the semi-ellipse coincides with the second side of the corresponding switch area. When the orthographic projections of the first transition region and the second transition region on the substrate are semi-elliptical, a long axis or a short axis of the semi-ellipse coincides with the second side of the corresponding transition region.

10. An electronic device, comprising: At least comprising the display panel according to any one of claims 1 to 9.

Images