Display device including self-luminous device

Abstract

The present disclosure relates to a display device including a self-luminous device. The display device includes a plurality of pixels. Each of the plurality of pixels includes: a first node controller that applies a data voltage to a first node; a second node controller that shifts the voltage of a second node from a low-level driving voltage to a turn-on pulse voltage; a third node controller that applies a reference voltage having a turn-on level to a third node during a first period of a frame based on the voltage of the second node as a low-level driving voltage, and applies a low-level driving voltage to the third node during a second period of a frame based on the voltage of the second node as a turn-on pulse voltage; a driving transistor including a gate and a first electrode that is driven with an on-duty cycle during the first period and with an off-duty cycle during the second period based on the voltage of the third node; and a light-emitting device including an anode and a cathode. The light-emitting device emits light during the first period and does not emit light during the second period.

Description

Technical Field

[0001] The present disclosure relates to a display device, and more particularly to a display device including a self-luminous device. Background Art

[0002] In display devices that include self-luminous devices, representing subtle low grayscales is difficult due to the characteristics of these devices. Various methods for increasing low grayscale resolution have been proposed in the prior art. However, these methods are difficult to apply because they require a large number of transistors in a pixel circuit, resulting in low process efficiency. Alternatively, they require a micro-integrated circuit to be embedded in each pixel circuit. Summary of the Invention

[0003] In order to overcome the above-mentioned problems of the related art, the present disclosure may provide a display panel and a display device including the display panel, which may enhance low grayscale representation in a display device including a self-luminous device.

[0004] To achieve these objects and other advantages, and in accordance with the purposes of the present disclosure, as embodied and broadly described herein, a display device includes a plurality of pixels. Each of the plurality of pixels includes: a first node controller configured to apply a data voltage corresponding to input video data to a first node; a second node controller configured to shift a voltage of a second node adjacent to the first node from a low-level driving voltage to a turn-on pulse voltage corresponding to a difference between the data voltage and the low-level driving voltage; a third node controller configured to apply a reference voltage having a turn-on level to a third node during a first period in one frame based on a voltage of the second node as the low-level driving voltage, and based on a voltage of the second node as the turn-on pulse voltage, A low-level driving voltage is applied to a third node during a second period following the first period in a frame; a driving transistor including a gate connected to the third node and a first electrode to which a high-level driving voltage is applied, the driving transistor being driven with an on-duty cycle during the first period and being driven with an off-duty cycle during the second period based on the voltage of the third node; and a light-emitting device including an anode connected to the second electrode of the driving transistor and a cathode to which the low-level driving voltage is applied, wherein the light-emitting device emits light in response to a constant current applied from the driving transistor during the first period and does not emit light during the second period.

[0005] In another aspect of the present disclosure, a display device includes a plurality of pixels. Each of the plurality of pixels includes: a first node controller that applies a data voltage corresponding to input video data to a first node; a second node controller that shifts a voltage of a second node adjacent to the first node from a high-level driving voltage to an off-pulse voltage corresponding to a difference between the data voltage and the high-level driving voltage; a third node controller that applies a low-level driving voltage to a third node during a first period in a frame based on the voltage of the second node being the high-level driving voltage, and applies a reference voltage having an on-level to the third node during a second period in the frame following the first period; a driving transistor configured to include a gate connected to the third node and a first electrode to which the high-level driving voltage is applied, the driving transistor being driven with an off-duty cycle during the first period and with an on-duty cycle during the second period based on the voltage of the third node; and a light-emitting device including an anode connected to the second electrode of the driving transistor and a cathode to which the low-level driving voltage is applied, wherein the light-emitting device does not emit light during the first period and emits light in response to a constant current applied from the driving transistor during the second period. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The accompanying drawings are included to provide a further understanding of the present disclosure and are incorporated in and constitute a part of this application. The drawings illustrate embodiments of the present disclosure and together with the description serve to explain the principles of the present disclosure. In the drawings:

[0007] Figure 1 is a diagram illustrating a display device according to an embodiment of the present disclosure;

[0008] Figure 2 is a diagram illustrating configurations of a first gate driver and a second gate driver and gate signals generated by the gate drivers according to a first embodiment;

[0009] Figure 3 This is an example Figure 2 FIG. 4 is a diagram showing a configuration of a gate stage of a second gate driver;

[0010] Figure 4 is a diagram illustrating a configuration of a pixel according to the first embodiment;

[0011] Figure 5 is included in the example Figure 4 a graph showing a characteristic curve of a driving transistor in a pixel;

[0012] Figure 6 and Figure 7 This is an example Figure 4FIG. 1 is a diagram of a driving waveform of a pixel;

[0013] Figure 8 is a diagram illustrating configurations of a first gate driver and a second gate driver and gate signals generated by the gate drivers according to a second embodiment;

[0014] Figure 9 This is an example Figure 8 FIG. 1 is a diagram showing a configuration of a common gate stage of a second gate driver;

[0015] Figure 10 This is an example Figure 9 FIG. 2 is a diagram showing a driving waveform of a common gate level;

[0016] Figure 11 is a diagram illustrating a configuration of a pixel according to a second embodiment; and

[0017] Figure 12 and Figure 13 This is an example Figure 11 Figure 2 is a diagram of the pixel driving waveform. DETAILED DESCRIPTION

[0018] Hereinafter, exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. In the specification, when adding reference numerals of elements in each figure, it should be noted that the same reference numerals that have been used to represent the same elements in other figures are used for the elements whenever possible. In the following description, when it is determined that the detailed description of related known functions or configurations unnecessarily obscures the key points of the present disclosure, the detailed description will be omitted.

[0019] The display device according to an embodiment of the present disclosure may be a self-luminous display device, such as an organic light emitting diode (OLED) display device, a quantum dot display device, or a micro light emitting diode (LED) display device.

[0020] When the display device according to an embodiment of the present disclosure is an OLED display device, each pixel may include a self-luminous OLED as a self-luminous device. When the display device according to an embodiment of the present disclosure is a quantum dot display device, each pixel may include a self-luminous device including quantum dots, which are self-luminous semiconductor crystals. When the display device according to an embodiment of the present disclosure is a micro-LED display device, each pixel may include a micro-LED as a self-luminous device, which is self-luminous and includes an inorganic material.

[0021] In the following embodiments, a case where a display apparatus includes a micro LED-based self-luminous device is exemplified, but the technical spirit of the present disclosure is not limited thereto and can be applied to all types of self-luminous display apparatuses.

[0022] Figure 1is a diagram illustrating a display device according to an embodiment of the present disclosure.

[0023] Reference Figure 1 , a display device according to an embodiment of the present disclosure may include a display panel PNL, a timing controller TCON, a data driver SDIC, a gate driver GIP, and a power circuit PMIC.

[0024] Data lines DL extending in the column direction (or vertical direction) and gate lines GL extending in the row direction (or horizontal direction) may intersect each other in the display area AA of the display panel PNL, which displays an input image, and pixels PXL may be arranged in a matrix to form a pixel array in each intersection area. Each of the data lines DL may be commonly connected to the pixels PXL adjacent to it in the column direction, and each of the gate lines GL may be connected to the pixels PXL adjacent to it in the row direction. Each of the pixels PXL may include a self-luminous device implemented using a micro LED.

[0025] The timing controller TCON can receive timing signals such as a vertical synchronization signal, a horizontal synchronization signal, a data enable signal, and a dot clock from a host system, and can generate a source timing control signal SDC for controlling the operation of the data driver SDIC and a gate timing control signal GDC for controlling the operation of the gate driver GIP based on the timing signals. The timing controller TCON can provide the source timing control signal SDC to the data driver SDIC and the gate timing control signal GDC to the gate driver GIP.

[0026] The timing controller TCON may receive video data DATA (or image data) from the host system and may execute a predetermined image quality enhancement algorithm to correct the video data DATA. The timing controller TCON may provide the corrected video data DATA to the data driver SDIC through an internal interface circuit.

[0027] The data driver SDIC can be connected to the pixels PXL via data lines DL. The data driver SDIC can generate data voltages for driving the pixels PXL based on source timing control signals SDC and can supply the data voltages to the data lines DL. Each of the data voltages corresponds to video data DATA. The data driver SDIC can divide a predetermined gamma reference voltage to generate gamma compensation voltages, and can map the gamma compensation voltages to the video data DATA to generate the data voltages. The data driver SDIC may include a shift register, a latch, a digital-to-analog converter, and an output buffer.

[0028] The gate driver GIP can be connected to the pixels PXL through the gate lines GL. The gate driver GIP can generate a gate signal based on the gate timing control signal GDC and can provide the gate timing control signal GDC to the gate lines GL based on the timing of supplying the data voltage. The gate signal can select the pixel column to which the data voltage is to be supplied.

[0029] Two gate lines GL may be connected to each pixel row, and each pixel PXL may be driven by two gate signals. One of the two gate signals may have a square wave that swings between a gate-on voltage and a gate-off voltage. The other of the two gate signals may have a ramp wave that changes diagonally between the gate-on voltage and the gate-off voltage.

[0030] The gate-on voltage may be a gate high voltage VGH greater than a threshold voltage of a transistor included in the pixel PXL, and the gate-off voltage may be a gate low voltage VGL less than the threshold voltage of the transistor. The transistor may be a transistor whose gate is connected to the gate line GL, and the transistor may be turned on in response to a gate signal higher than the threshold voltage, and may be turned off in response to a gate signal lower than the threshold voltage.

[0031] The gate driver GIP can be implemented using a gate shift register including a plurality of gate stages. The input / output terminals of the gate stages can be connected to each other in a cascade scheme. The gate stages can be individually connected to the gate lines GL and can output gate signals to the gate lines GL. The gate shift register can be directly set as an intra-panel gate driver type in the frame area NAA of the display panel PNL where no image is displayed. The frame area NAA can be set outside the display area AA, but this is not required.

[0032] The power supply circuit PMIC can boost the input direct current (DC) voltage to generate the high-level driving voltage VDDEL, low-level driving voltage VSSEL, and reference voltage Vref required to drive the pixels PXL, generate the gate high voltage VGH and gate low voltage VGL required to drive the gate driver GIP, and generate the gamma source voltage required to drive the data driver SDIC. Each of the high-level driving voltage VDDEL, reference voltage Vref, and gate high voltage VGH can be a voltage for turning on the transistor of each pixel PXL. Each of the low-level driving voltage VSSEL and gate low voltage VGL can be a voltage for turning off the transistor of each pixel PXL.

[0033] The display device according to the present embodiment may not use a method of representing grayscale based on the level of the driving current applied to the light-emitting device in a state where the light-emitting period in a frame is fixed. The display device according to the present embodiment may control the length of time that the light-emitting device is turned on in a frame based on the data voltage to improve the performance of low grayscale representation, and therefore, the grayscale may be represented based on the on-duty cycle period of the light-emitting device. To this end, the display device according to the present embodiment may perform a method that controls the time when the data voltage in the pixel PXL matches the ramp waveform of the gate signal based on the level of the data voltage to adjust the on / off timing of the driving transistor, and thus pulse width modulation (PWM) drives (i.e., duty cycle drives) the light-emitting device. The following embodiments relate to driving concepts and pixel configurations for duty cycle driven light-emitting devices.

[0034] <First embodiment>

[0035] Figure 2 is a diagram illustrating configurations of a first gate driver and a second gate driver and gate signals generated by the gate drivers according to the first embodiment. Figure 3 This is an example Figure 2 FIG. 5 is a diagram showing the configuration of the gate stage of the second gate driver.

[0036] Reference Figure 2 , the gate driver GIP according to the first embodiment may include a first gate driver GIP1 driving a first gate line included in each pixel row and a second gate driver GIP2 driving a second gate line included in each pixel row.

[0037] The first gate driver GIP1 may include a plurality of first gate stages SX that output first gate signals GSIG1 having phases sequentially shifted based on a gate start signal GVST and a gate clock GCLK. The first gate stages SX may be individually connected to first gate lines of pixel rows and may output first gate signals GSIG1 having sequentially shifted phases to the first gate lines. The first gate signal GSIG1 may be a square wave that swings between a gate high voltage VGH and a gate low voltage VGL in one frame.

[0038] The second gate driver GIP2 may include a plurality of second gate stages SY that output second gate signals GSIG2 having sequentially shifted phases based on the first gate signal GSIG1. The second gate stages SY may be individually connected to the second gate lines of the pixel rows and may output second gate signals GSIG2 having sequentially shifted phases to the second gate lines. The second gate signal GSIG2 may be a ramp wave that changes diagonally between a gate high voltage VGH and a gate low voltage VGL in one frame.

[0039] Figure 3 One of the second gate stages SY included in the second gate driver GIP2 is illustrated. The second gate stage SY may include: a first switch SWx that switches on or off an electrical connection between the output node Nx and an input terminal for a gate low voltage VGL based on a first gate signal GSIG1; a second switch SWy that is diode-connected (e.g., with a drain connected to a gate) and applies a gate high voltage VGH to the output node Nx; and a storage capacitor Cx connected between the output node Nx and the input terminal for the gate low voltage VGL.

[0040] When the first gate signal GSIG1 is input as the gate high voltage VGH, the voltage of the storage capacitor Cx (eg, the voltage of the output node Nx) may drop from the gate high voltage VGH to the gate low voltage VGL in a diagonal form.

[0041] On the other hand, when the first gate signal GSIG1 is input as the gate low voltage VGL, the voltage of the storage capacitor Cx (eg, the voltage of the output node Nx) may increase diagonally from the gate low voltage VGL to the gate high voltage VGH.

[0042] As a result, in one frame, the second gate signal GSIG2 output through the output node Nx may decrease diagonally from the gate high voltage VGH to the gate low voltage VGL, and then may increase diagonally from the gate low voltage VGL to the gate high voltage VGH.

[0043] Figure 4 is a diagram illustrating the configuration of a pixel according to the first embodiment. Figure 5 is included in the example Figure 4 Graph showing characteristic curves of a driving transistor in a pixel. Figure 6 and Figure 7 This is an example Figure 4 Figure 2 is a diagram of the pixel driving waveform.

[0044] Reference Figures 4 to 7 The pixel PXL according to the first embodiment of the present disclosure may include a pixel circuit including a light emitting device EL, first to sixth transistors T1 to T6, and a capacitor C. The first to sixth transistors T1 to T6 may each be implemented as an N-type MOSFET. The sixth transistor T6 may be a driving transistor.

[0045] The pixel circuit may include a light emitting device EL, a driving transistor T6 , a first node controller NC1 , a second node controller NC2 , and a third node controller NC3 .

[0046] A first node controller NC1 may apply a data voltage Vdata for image representation to a first node N1. The first node controller NC1 may include a first transistor T1 and a capacitor C. The first transistor T1 may apply the data voltage Vdata to the first node N1 during a first period PE1 in a frame based on a first gate signal GSIG1. A gate of the first transistor T1 may be connected to a first gate line GLx to which the first gate signal GSIG1 is applied, a first electrode of the first transistor T1 may be connected to a data line DL, and a second electrode of the first transistor T1 may be connected to the first node N1. The capacitor C may be connected between the first node N1 and an input terminal for a low-level driving voltage VSSEL.

[0047] The second node controller NC2 can shift the voltage of the second node N2 adjacent to the first node N1 from the low-level driving voltage VSSEL to the conduction pulse voltage Von corresponding to the difference between the data voltage Vdata and the low-level driving voltage VSSEL. The second node controller NC2 can control the voltage of the second node N2 to the low-level driving voltage VSSEL during the first period PE1 of a frame, and can control the voltage of the second node N2 to the conduction pulse voltage Von during the second period PE2 after the first period PE1 of the frame. The second node controller NC2 may include a second transistor T2 and a third transistor T3. The second transistor T2 may apply the low-level driving voltage VSSEL to the second node N2 during the first period PE1 based on the first gate signal GSIG1. The gate of the second transistor T2 may be connected to the first gate line GLx to which the first gate signal GSIG1 is applied, the first electrode of the second transistor T2 may be connected to the second node N2, and the second electrode of the second transistor T2 may be connected to the input terminal for the low-level driving voltage VSSEL. The third transistor T3 may disconnect the first node N1 and the second node N2 during a first period PE1 based on a second gate signal GSIG2 different from the first gate signal GSIG1, and may connect the first node N1 to the second node N2 during a second period PE2. A gate of the third transistor T3 may be connected to the second gate line GLy to which the second gate signal GSIG2 is applied, a first electrode of the third transistor T3 may be connected to the first node N1, and a second electrode of the third transistor T3 may be connected to the second node N2.

[0048] The third node controller NC3 can control the voltage of the third node N3 using the voltage of the second node N2. The third node controller NC3 can apply a reference voltage Vref having a conduction level to the third node N3 during the first period PE1 based on the voltage of the second node N2 as the low-level drive voltage VSSEL, and can apply the low-level drive voltage VSSEL to the third node N3 during the second period PE2 based on the voltage of the second node N2 as the conduction pulse voltage Von. The third node controller NC3 may include a fourth transistor T4 and a fifth transistor T5. The fourth transistor T4 may be diode-connected and may apply the reference voltage Vref having a conduction level to the third node N3. The gate and first electrode of the fourth transistor T4 may be connected to the third node N3, and the second electrode of the fourth transistor T4 may be connected to the input terminal for the reference voltage Vref. The fifth transistor T5 may disconnect the third node N3 from the input terminal for the low-level driving voltage VSSEL during the first period PE1 based on the voltage of the second node N2 as the low-level driving voltage VSSEL, and may connect the third node N3 to the input terminal for the low-level driving voltage VSSEL during the second period PE2 based on the voltage of the second node N2 as the on-pulse voltage Von. A gate of the fifth transistor T5 may be connected to the second node N2, a first electrode of the fifth transistor T5 may be connected to the third node N3, and a second electrode of the fifth transistor T5 may be connected to the input terminal for the low-level driving voltage VSSEL.

[0049] The driving transistor T6 may be a constant current driving element including a gate connected to the third node N3 and a first electrode to which a high-level driving voltage VDDEL is applied. The driving transistor T6 generates a constant current by on-duty driving during a first period PE1 based on the voltage of the third node N3 and is off-duty driven during a second period PE2. A second electrode of the driving transistor T6 may be connected to the light emitting device EL.

[0050] like Figure 5As shown, the drive transistor T6 may operate not in the saturation region SR (or AR) of the characteristic curve CC of the transistor current Itr based on its drain-source voltage Vtr, but in the linear region LR. The drive transistor T6 can generate a drive current Id having a specific level corresponding to the specific drain-source voltage Vds in the linear region LR. Because the specific drain-source voltage Vds of the linear region LR is lower than the drain-source voltage in the saturation region SR, when the drive transistor T6 operates in the linear region LR, the high-level drive voltage VDDEL can be relatively low, and power consumption can be reduced by reducing the high-level drive voltage VDDEL. Because the drive transistor T6 operates in the linear region LR, the drive current Id flowing in the drive transistor T6 can be a constant current that is independent of the level of the data voltage Vdata. Because the drive transistor T6 functions as a switch rather than as an analog current generating element that controls the level of the drain current based on the level of the data voltage Vdata, it is not necessary to compensate for driving characteristic variations (threshold voltage variations and / or electron mobility variations) of the drive transistor T6 between pixels PXL. Therefore, in the present embodiment, since an additional circuit for sampling and compensating the driving characteristics of the driving transistor T6 in or outside the pixel PXL may be unnecessary, the circuit configuration can be simplified.

[0051] The light-emitting device EL can be implemented as a micro-LED, which includes an anode connected to the second electrode of the driving transistor T6, a cathode to which a low-level driving voltage VSSEL is applied, and an inorganic light-emitting layer disposed between the anode and the cathode. The light-emitting device EL can emit light during a first period PE1 in response to a constant current input from the driving transistor T6, and can not emit light during a second period PE2. In one frame, the light-emitting duty cycle of the light-emitting device EL can be based on the on-duty cycle of the driving transistor T6.

[0052] The pixel PXL according to the first embodiment having such a configuration can be Figure 6 One frame for driving the pixel PXL may include a first period PE1 and a second period PE2 subsequent to the first period PE1.

[0053] The first gate signal GSIG1 may be a square wave shifted from the gate high voltage VGH to the gate low voltage VGL in the first period PE1, and the second gate signal GSIG2 may be a ramp wave diagonally changing from the gate low voltage VGL to the gate high voltage VGH in the first and second periods PE1 and PE2.

[0054] In the first period PE1, the voltage of the first node N1 may be the data voltage Vdata, the voltage of the second node N2 may be the low-level driving voltage VSSEL, and the voltage of the third node N3 may be the reference voltage Vref. The reference voltage Vref may be a turn-on level voltage for turning on the driving transistor T6.

[0055] During the second period PE2, when the voltage level of the second gate signal GSIG2 is higher than the data voltage Vdata, the gate-source voltage Vgs of the third transistor T3 may be higher than the threshold voltage of the third transistor T3, and thus, the third transistor T3 may be turned on. Based on the turning on of the third transistor T3, the voltage at the second node N2 may be the on-pulse voltage Von. The on-pulse voltage may be between the data voltage Vdata and the low-level driving voltage VSSEL and may be the on-level voltage for turning on the fifth transistor T5. During the second period PE2, the fifth transistor T5 may be turned on by the on-pulse voltage Von of the second node N2, and thus the voltage at the third node N3 may be the low-level driving voltage VSSEL.

[0056] The on-duty ratio and off-duty ratio of the driving transistor T6 can be determined based on the voltage of the third node N3. The driving transistor T6 can be turned on by the reference voltage Vref during the first period PE1, and can be turned off by the low-level driving voltage VSSEL during the second period PE2. The on-duty ratio of the driving transistor T6 can correspond to the length of the first period PE1 in one frame, and the off-duty ratio of the driving transistor T6 can correspond to the length of the second period PE2 in one frame.

[0057] The second gate signal GSIG2 may be smaller than the data voltage Vdata in the first period PE1 and may be larger than the data voltage Vdata in the second period PE2. Since the second period PE2 starts when the voltage level of the second gate signal GSIG2 is greater than the data voltage Vdata, as the data voltage Vdata increases, the length of the second period PE2 may be shortened, and the length of the first period PE1 may be increased in one frame. In other words, the length of the first period PE1 during which the light emitting device EL emits light in one frame (i.e., the light emission duty cycle) may increase in proportion to the level of the data voltage Vdata.

[0058] For example, Figure 7 As shown, the light emission duty ratio when the data voltage Vdata is relatively high "Vdata1" can be greater than the light emission duty ratio when the data voltage Vdata is relatively low "Vdata2". Figure 7In the embodiment, the first conduction pulse voltage Von1, which is the voltage of the second node N2 when the data voltage Vdata is “Vdata1”, may be greater than the second conduction pulse voltage Von2, which is the voltage of the second node N2 when the data voltage Vdata is “Vdata2”. In addition, the length of the second period PE2 in the case where the voltage of the second node N2 is maintained at the first conduction pulse voltage Von1 may be shorter than the length of the second period PE2 in the case where the voltage of the second node N2 is maintained at the second conduction pulse voltage Von2.

[0059] <Second embodiment>

[0060] Figure 8 is a diagram illustrating configurations of a first gate driver and a second gate driver and gate signals generated by the gate drivers according to a second embodiment. Figure 9 This is an example Figure 8 FIG. 5 is a diagram showing the configuration of the common gate stage of the second gate driver. Figure 10 This is an example Figure 9 FIG. 4 is a diagram of the driving waveform of the common gate level shown in FIG.

[0061] Reference Figure 8 , the gate driver GIP according to the second embodiment may include a first gate driver GIP1 driving a first gate line included in each pixel row and a second gate driver GIP2 driving a second gate line included in each pixel row.

[0062] The first gate driver GIP1 may include a plurality of first gate stages SX that output first gate signals GSIG1 having phases sequentially shifted based on a gate start signal GVST and a gate clock GCLK. The first gate stages SX may be individually connected to first gate lines of pixel rows and may output first gate signals GSIG1 having sequentially shifted phases to the first gate lines. The first gate signal GSIG1 may be a square wave that swings between a gate high voltage VGH and a gate low voltage VGL in one frame.

[0063] The second gate driver GIP2 may include a second gate stage CSY that outputs a second gate signal GSIG2 having a phase that is sequentially shifted based on the switch control signal GCON. The second gate stage CSY may be commonly connected to the second gate line of the pixel row and may output a second gate signal GSIG2 having the same phase to the second gate line. The second gate signal GSIG2 may be a ramp wave that has a gate low voltage VGL in an address allocation period ADD of a frame and changes diagonally from the gate low voltage VGL to a gate high voltage VGH in an emission allocation period EMI following the address allocation period ADD. Here, the address allocation period ADD may be defined as a period in which the first gate line of the pixel row is sequentially scanned and the second gate line of the pixel row is scanned at the same time. In addition, the emission allocation period EMI may be defined as a maximum period in which each pixel can emit light. In all pixel rows, the emission allocation period EMI and the address allocation period ADD may be separated from each other without overlapping.

[0064] When the second gate stage CSY is configured as a common gate stage, the circuit configuration of the second gate driver GIP2 may be simplified, and thus the bezel size of the display panel may be easily reduced.

[0065] like Figure 9 and Figure 10 As shown, the second gate stage CSY may include: a first switch SWi, which connects or disconnects the electrical connection between the output node Ny and the input terminal for the gate low voltage VGL based on the switch control signal GCON; a second switch SWj, which is diode-connected and applies the gate high voltage VGH to the output node Ny; and a storage capacitor Cy, which is connected between the output node Ny and the input terminal for the gate low voltage VGL.

[0066] The switch control signal GCON may have an on-level in the address allocation period ADD and may have an off-level in the light emission allocation period EMI. In the address allocation period ADD, the voltage of the storage capacitor Cy (e.g., the voltage of the output node Ny) may decrease diagonally from the gate high voltage VGH to the gate low voltage VGL based on the switch control signal GCON having the on-level, and then may maintain the gate low voltage VGL for a certain period while the switch control signal GCON maintains the on-level.

[0067] On the other hand, in the emission distribution period EMI, the voltage of the storage capacitor Cy (eg, the voltage of the output node Ny) may increase diagonally from the gate low voltage VGL to the gate high voltage VGH based on the switching control signal GCON having the turn-off level.

[0068] As a result, the second gate signal GSIG2 output through the output node Ny can decrease diagonally from the gate high voltage VGH to the gate low voltage VGL in one frame, and then can maintain the gate low voltage VGL during a certain period, and can increase diagonally from the gate low voltage VGL to the gate high voltage VGH.

[0069] Figure 11 is a diagram illustrating the configuration of a pixel according to the second embodiment. Figure 12 and Figure 13 This is an example Figure 11 Figure 2 is a diagram of the pixel driving waveform.

[0070] Reference Figures 11 to 13 The pixel PXL according to the second embodiment of the present disclosure may include a pixel circuit including a light emitting device EL, first to sixth transistors T1 to T6, and a capacitor C. The first to sixth transistors T1 to T6 may each be implemented as an N-type MOSFET. The sixth transistor T6 may be a driving transistor.

[0071] The pixel circuit may include a light emitting device EL, a driving transistor T6 , a first node controller NC1 , a second node controller NC2 , and a third node controller NC3 .

[0072] A first node controller NC1 may apply a data voltage Vdata for image representation to a first node N1. The first node controller NC1 may include a first transistor T1 and a capacitor C. The first transistor T1 may apply the data voltage Vdata to the first node N1 during a first period PE1 in a frame based on a first gate signal GSIG1. A gate of the first transistor T1 may be connected to a first gate line GLx to which the first gate signal GSIG1 is applied, a first electrode of the first transistor T1 may be connected to a data line DL, and a second electrode of the first transistor T1 may be connected to the first node N1. The capacitor C may be connected between the first node N1 and an input terminal for a low-level driving voltage VSSEL.

[0073] The second node controller NC2 can shift the voltage of the second node N2 adjacent to the first node N1 from the high-level driving voltage VDDEL to the off-pulse voltage Voff corresponding to the difference between the data voltage Vdata and the high-level driving voltage VDDEL. The second node controller NC2 can control the voltage of the second node N2 to the high-level driving voltage VDDEL during a first period PE1 in a frame, and can control the voltage of the second node N2 to the off-pulse voltage Voff during a second period PE2 following the first period PE1 in the frame. The second node controller NC2 may include a second transistor T2 and a third transistor T3. The second transistor T2 may apply the high-level driving voltage VDDEL to the second node N2 during the first period PE1 based on the first gate signal GSIG1. The gate of the second transistor T2 may be connected to the first gate line GLx to which the first gate signal GSIG1 is applied, the first electrode of the second transistor T2 may be connected to the second node N2, and the second electrode of the second transistor T2 may be connected to the input terminal for the high-level driving voltage VDDEL. The third transistor T3 may disconnect the first node N1 and the second node N2 during a first period PE1 based on a second gate signal GSIG2 different from the first gate signal GSIG1, and may connect the first node N1 to the second node N2 during a second period PE2. A gate of the third transistor T3 may be connected to the second gate line GLy to which the second gate signal GSIG2 is applied, a first electrode of the third transistor T3 may be connected to the first node N1, and a second electrode of the third transistor T3 may be connected to the second node N2.

[0074] The third node controller NC3 can control the voltage of the third node N3 using the voltage of the second node N2. The third node controller NC3 can apply the low-level driving voltage VSSEL to the third node N3 during the first period PE1 based on the voltage of the second node N2 as the high-level driving voltage VDDEL, and can apply the reference voltage Vref having a conduction level to the third node N3 during the second period PE2 based on the voltage of the second node N2 as the off-pulse voltage Voff. The third node controller NC3 may include a fourth transistor T4 and a fifth transistor T5. The fourth transistor T4 may be diode-connected and may apply the reference voltage Vref having a conduction level to the third node N3. The gate and first electrode of the fourth transistor T4 may be connected to the third node N3, and the second electrode of the fourth transistor T4 may be connected to the input terminal for the reference voltage Vref. The fifth transistor T5 may connect the third node N3 to the input terminal for the low-level driving voltage VSSEL during the first period PE1 based on the voltage of the second node N2 as the high-level driving voltage VDDEL, and may disconnect the third node N3 from the input terminal for the low-level driving voltage VSSEL during the second period PE2 based on the voltage of the second node N2 as the off-pulse voltage Voff. A gate of the fifth transistor T5 may be connected to the second node N2, a first electrode of the fifth transistor T5 may be connected to the third node N3, and a second electrode of the fifth transistor T5 may be connected to the input terminal for the low-level driving voltage VSSEL.

[0075] The driving transistor T6 may be a constant current driving element including a gate connected to the third node N3 and a first electrode to which a high-level driving voltage VDDEL is applied. The driving transistor T6 is driven with an off-duty cycle during a first period PE1 based on the voltage of the third node N3, and is driven with an on-duty cycle during a second period PE2 to generate a constant current. A second electrode of the driving transistor T6 may be connected to the light emitting device EL.

[0076] like Figure 11As shown, the drive transistor T6 may operate not in the saturation region SR of the characteristic curve of the transistor current Itr based on its drain-source voltage Vtr, but in the linear region LR. The drive transistor T6 can generate a drive current Id having a specific level corresponding to the specific drain-source voltage Vds in the linear region LR. Because the specific drain-source voltage Vds of the linear region LR is lower than the drain-source voltage in the saturation region SR, when the drive transistor T6 operates in the linear region LR, the high-level drive voltage VDDEL can be relatively low, and power consumption can be reduced by reducing the high-level drive voltage VDDEL. Because the drive transistor T6 operates in the linear region LR, the drive current Id flowing in the drive transistor T6 can be a constant current that is independent of the level of the data voltage Vdata. Because the drive transistor T6 functions as a switch rather than as an analog current generating element that controls the level of the drain current based on the level of the data voltage Vdata, it is not necessary to compensate for the driving characteristic variations (threshold voltage variations and / or electron mobility variations) of the drive transistor T6 between pixels PXL. Therefore, in the present embodiment, since an additional circuit in or outside the pixel PXL for sampling and compensating for the driving characteristics of the driving transistor T6 may be unnecessary, the circuit configuration can be simplified.

[0077] The light-emitting device EL can be implemented as a micro-LED, which includes an anode connected to the second electrode of the driving transistor T6, a cathode to which a low-level driving voltage VSSEL is applied, and an inorganic light-emitting layer disposed between the anode and the cathode. The light-emitting device EL may not emit light during a first period PE1, and may emit light during a second period PE2 in response to a constant current input from the driving transistor T6. In a frame, the light-emitting duty cycle of the light-emitting device EL may be based on the on-duty cycle of the driving transistor T6.

[0078] The pixel PXL according to the second embodiment having such a structure can be Figure 12 The driving waveform operates according to the embodiment of the present invention. A frame for driving the pixel PXL may include a first period PE1 and a second period PE2 following the first period PE1. The first period PE1 may include the above-mentioned address allocation period. The second period PE2 may include all of the above-mentioned light emission allocation period based on the level of the data voltage Vdata, or may include a portion thereof. When the second period PE2 includes only a portion of the light emission allocation period, the length of the first period PE1 may be increased accordingly.

[0079] The first gate signal GSIG1 may be a square wave shifted from the gate high voltage VGH to the gate low voltage VGL in the first period PE1. The second gate signal GSIG2 may be a ramp wave that maintains the gate low voltage VGL during the address allocation period and then changes diagonally from the gate low voltage VGL to the gate high voltage VGH in the first and second periods PE1 and PE2.

[0080] In the first period PE1 , the voltage of the first node N1 may be the data voltage Vdata, the voltage of the second node N2 may be the high-level driving voltage VDDEL, and the voltage of the third node N3 may be the low-level driving voltage VSSEL.

[0081] During the second period PE2, when the voltage level of the second gate signal GSIG2 is higher than the data voltage Vdata, the gate-source voltage Vgs of the third transistor T3 may be higher than the threshold voltage of the third transistor T3, and thus, the third transistor T3 may be turned on. Based on the turning on of the third transistor T3, the voltage at the second node N2 may be the off-pulse voltage Voff. The off-pulse voltage Voff may be between the data voltage Vdata and the high-level driving voltage VDDEL and may be a off-level voltage for turning off the fifth transistor T5. During the second period PE2, the fifth transistor T5 may be turned off by the off-pulse voltage Voff of the second node N2, and thus the voltage at the third node N3 may be the reference voltage Vref.

[0082] The on-duty ratio and off-duty ratio of the driving transistor T6 can be determined based on the voltage of the third node N3. The driving transistor T6 can be turned off by the low-level driving voltage VSSEL during the first period PE1, and the driving transistor T6 can be turned on by the reference voltage Vref during the second period PE2. The on-duty ratio of the driving transistor T6 can correspond to the length of the second period PE2 in one frame, and the off-duty ratio of the driving transistor T6 can correspond to the length of the first period PE1 in one frame.

[0083] The second gate signal GSIG2 may be smaller than the data voltage Vdata in the first period PE1 and may be larger than the data voltage Vdata in the second period PE2. Since the second period PE2 begins when the voltage level of the second gate signal GSIG2 is greater than the data voltage Vdata, as the data voltage Vdata increases, the length of the second period PE2 may be shortened, and the length of the first period PE1 may be increased in one frame. In other words, the length of the second period PE2 during which the light emitting device EL emits light in one frame (i.e., the light emission duty cycle) may be reduced in proportion to the level of the data voltage Vdata.

[0084] For example, Figure 13As shown, the light emission duty ratio when the data voltage Vdata is relatively high "Vdata1" can be smaller than the light emission duty ratio when the data voltage Vdata is relatively low "Vdata2". Figure 13 In the embodiment, the first off-pulse voltage Voff1, which is the voltage of the second node N2 when the data voltage Vdata is “Vdata1”, may be higher than the second off-pulse voltage Voff2, which is the voltage of the second node N2 when the data voltage Vdata is “Vdata2”. In addition, the length of the second period PE2 in the case where the voltage of the second node N2 is maintained at the first off-pulse voltage Voff1 may be shorter than the length of the second period PE2 in the case where the voltage of the second node N2 is maintained at the second off-pulse voltage Voff2.

[0085] This embodiment can achieve the following effects.

[0086] In this embodiment, a gate signal that increases diagonally from a gate low voltage to a gate high voltage can be applied to a pixel, and the time for matching the data voltage in the pixel with the ramp waveform of the gate signal can be controlled based on the level of the data voltage, thereby adjusting the on / off timing of the drive transistor. In addition, the light-emitting device can be PWM-driven (i.e., duty-cycle-driven) by adjusting the on / off timing of the drive transistor. In this embodiment, the length of time the light-emitting device is turned on in a frame can be controlled based on the data voltage using a PWM scheme, and thus grayscale can be represented based on the on-duty cycle of the light-emitting device, thereby significantly enhancing low grayscale representation.

[0087] The effects according to the present disclosure are not limited to the above-described examples, and other various effects can be included in this specification.

[0088] While the present disclosure has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present disclosure as defined by the appended claims.

[0089] CROSS-REFERENCE TO RELATED APPLICATIONS

[0090] This application claims the benefit of Korean Patent Application No. 10-2021-0182746, filed on December 20, 2021, which is hereby incorporated by reference as if fully set forth herein.

Claims

1. A display device, comprising: Multiple pixels, Each of the plurality of pixels comprises: a first node controller configured to apply a data voltage corresponding to input video data to a first node; a second node controller configured to shift a voltage of a second node adjacent to the first node from a low-level driving voltage to a turn-on pulse voltage corresponding to a difference between the data voltage and the low-level driving voltage; a third node controller configured to apply a reference voltage having a turn-on level to a third node during a first period in one frame based on the voltage of the second node as the low-level drive voltage, and to apply the low-level drive voltage to the third node during a second period after the first period in the one frame based on the voltage of the second node as the turn-on pulse voltage; a driving transistor configured to include a gate connected to the third node and a first electrode to which a high-level driving voltage is applied, wherein the driving transistor is driven with an on-duty cycle during the first period and is driven with an off-duty cycle during the second period based on the voltage of the third node; and A light emitting device comprising an anode connected to the second electrode of the driving transistor and a cathode to which the low-level driving voltage is applied, wherein the light emitting device emits light during the first period in response to a constant current applied from the driving transistor and does not emit light during the second period.

2. The display device according to claim 1, wherein The level of the data voltage varies within a predetermined voltage range based on the grayscale of the input video data, and The length of the first period during which the light emitting device emits light in the one frame increases in proportion to the level of the data voltage.

3. The display device according to claim 1, wherein The first node controller includes: a first transistor configured to apply the data voltage to the first node during the first period based on a first gate signal; and A capacitor is connected between the first node and an input terminal for the low-level driving voltage.

4. The display device according to claim 3, wherein The second node controller includes: a second transistor configured to apply the low-level driving voltage to the second node during the first period based on the first gate signal; and a third transistor configured to disconnect the first node and the second node during the first period and connect the first node to the second node during the second period based on a second gate signal different from the first gate signal.

5. The display device according to claim 4, wherein The first gate signal is a square wave that shifts from a gate-on voltage to a gate-off voltage in the first period, and The second gate signal is a ramp wave that changes diagonally from the gate-off voltage to the gate-on voltage in the first period and the second period. The display device according to claim 5 , wherein: The second gate signal is smaller than the data voltage in the first period and larger than the data voltage in the second period.

7. The display device according to claim 4, wherein The third node controller includes: a fourth transistor that is diode-connected to apply the reference voltage to the third node; and a fifth transistor configured to disconnect the third node from the input terminal for the low-level drive voltage during the first period based on the voltage of the second node as the low-level drive voltage, and to connect the third node to the input terminal for the low-level drive voltage during the second period based on the voltage of the second node as the conduction pulse voltage.

8. The display device according to claim 5, further comprising: a first gate stage configured to output the first gate signal based on a gate start signal and a gate clock; as well as A second gate stage is configured to generate the second gate signal based on the first gate signal and output the second gate signal to an output node.

9. The display device according to claim 8, wherein The second gate stage comprises: a first switch configured to connect or disconnect an electrical connection between the output node and an input terminal for the gate-off voltage based on the first gate signal; a second switch diode-connected to apply the gate-on voltage to the output node; and A storage capacitor is connected between the output node and an input terminal for the gate-off voltage.

10. The display device according to claim 1, wherein The driving transistor operates in a linear region of a characteristic curve of a transistor current based on a drain-source voltage of the driving transistor, During a turn-on duty period of the driving transistor, a driving current flowing in the driving transistor is constant regardless of a level of the data voltage, and The light emission duty cycle of the light emitting device is based on the conduction duty cycle of the driving transistor.

11. A display device, comprising: Multiple pixels, Each of the plurality of pixels comprises: a first node controller that applies a data voltage corresponding to input video data to a first node; a second node controller configured to shift a voltage of a second node adjacent to the first node from a high-level driving voltage to a cut-off pulse voltage corresponding to a difference between the data voltage and the high-level driving voltage; a third node controller configured to apply a low-level driving voltage to a third node during a first period in one frame based on the voltage of the second node as the high-level driving voltage, and to apply a reference voltage having an on-level to the third node during a second period after the first period in the one frame based on the voltage of the second node as the off pulse voltage; a driving transistor configured to include a gate connected to the third node and a first electrode to which the high-level driving voltage is applied, wherein the driving transistor is driven with an off-duty cycle during the first period and is driven with an on-duty cycle during the second period based on the voltage of the third node; and A light emitting device comprising an anode connected to the second electrode of the driving transistor and a cathode to which the low-level driving voltage is applied, wherein the light emitting device does not emit light during the first period and emits light in response to a constant current applied from the driving transistor during the second period.

12. The display device according to claim 11, wherein The level of the data voltage varies within a predetermined voltage range based on the grayscale level of the input video data, and The length of the second period during which the light emitting device emits light in the one frame decreases in proportion to the level of the data voltage.

13. The display device according to claim 11, wherein The first node controller includes: a first transistor configured to apply the data voltage to the first node during the first period based on a first gate signal; and A capacitor is connected between the first node and an input terminal for the low-level driving voltage.

14. The display device according to claim 13, wherein The second node controller includes: a second transistor configured to apply the high-level driving voltage to the second node during the first period based on the first gate signal; and a third transistor configured to disconnect the first node and the second node during the first period and connect the first node to the second node during the second period based on a second gate signal different from the first gate signal.

15. The display device according to claim 14, wherein The first gate signal is a square wave that shifts from a gate-on voltage to a gate-off voltage in the first period, and The second gate signal is a ramp wave that maintains the gate-off voltage during a certain period of the first period and then changes diagonally from the gate-off voltage to the gate-on voltage from after the certain period until the end of a second period.

16. The display device according to claim 15, wherein The second gate signal is smaller than the data voltage in the first period and larger than the data voltage in the second period.

17. The display device according to claim 14, wherein: The third node controller includes: a fourth transistor that is diode-connected to apply the reference voltage to the third node; and a fifth transistor configured to connect the third node to the input terminal for the low-level driving voltage during the first period based on the voltage of the second node as the high-level driving voltage, and to disconnect the third node from the input terminal for the low-level driving voltage during the second period based on the voltage of the second node as the cut-off pulse voltage.

18. The display device according to claim 15, further comprising: a first gate stage configured to output the first gate signal based on a gate start signal and a gate clock; as well as a second gate stage configured to generate the second gate signal based on the switch control signal and output the second gate signal to an output node, The switch control signal has an on-level in an address allocation period including the certain period, and has an off-level in a light emission allocation period including the second period after the certain period.

19. The display device according to claim 18, wherein The second gate stage comprises: a first switch configured to connect or disconnect an electrical connection between the output node and an input terminal for the gate-off voltage based on the switch control signal; a second switch diode-connected to apply the gate-on voltage to the output node; and A storage capacitor is connected between the output node and an input terminal for the gate-off voltage.

20. The display device according to claim 18, wherein a plurality of first gate stages configured to output first gate signals having different phases are individually connected to different pixel rows including the plurality of pixels, The second gate stage is commonly connected to the different pixel rows, and The second gate signal is commonly applied to pixels in the different pixel rows.

21. The display device according to claim 11, wherein The driving transistor operates in a linear region of a characteristic curve of a transistor current based on a drain-source voltage of the driving transistor, During a turn-on duty period of the driving transistor, a driving current flowing in the driving transistor is constant regardless of a level of the data voltage, and The light emission duty cycle of the light emitting device is based on the conduction duty cycle of the driving transistor.

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