Pixel circuits, display panels, their fabrication methods, and display devices

Abstract

This application provides a pixel circuit, a display panel, a method for fabricating the same, and a display device. One end of the pixel circuit is connected to a power supply voltage terminal, and the other end is connected to a ground terminal. The pixel circuit includes a parallel driving circuit and a photosensitive control circuit. The driving circuit includes a driving element and a light-emitting element connected in series. The end of the driving element away from the light-emitting element is connected to the power supply voltage terminal, and the end of the light-emitting element away from the driving element is connected to the ground terminal. The photosensitive control circuit includes a series anti-reverse current element and a photoelectric conversion element. The cathode of the anti-reverse current element is connected to the power supply voltage terminal, and the anode of the anti-reverse current element is connected to the ground terminal. The anti-reverse current element prevents current flowing from the power supply voltage terminal from flowing into the photosensitive control circuit. This allows for adaptive brightness adjustment, meeting the high-brightness mode requirements of the display screen during long-lasting operation in outdoor high-brightness environments.

Description

Technical Field

[0001] This application relates to the field of display technology, specifically to a pixel circuit, a display panel, a method for manufacturing the same, and a display device. Background Technology

[0002] In recent years, the maximum intensity of solar radiation on the Earth's surface has approached 1000 W / m². 2 (0.1W / cm 2 As the intensity of sunlight varies at different times of the day, the direct radiation intensity in major cities ranges from approximately 300 to 1000 W / m². 2 Scope. Currently, research on green energy sources such as solar energy has become a major focus, leading to the rapid development of the photovoltaic industry. Organic photovoltaic (OPV) devices include organic small-molecule thin-film solar cells and polymer thin-film solar cells. Research has found that the photoelectric conversion efficiency of OPV has exceeded 19%.

[0003] Mobile electronic products such as smartphones and tablets have a growing need for long battery life, while the demand for outdoor display capabilities is also increasing. OLED display power consumption is positively correlated with brightness; high-brightness mode increases power consumption, but battery life becomes an issue due to limitations in system battery capacity. High-brightness mode presents a significant challenge to achieving long battery life. Summary of the Invention

[0004] This application addresses the shortcomings of existing technologies by proposing a pixel circuit, a display panel, a method for fabricating the same, and a display device, in order to resolve the conflict between the requirements for outdoor high-brightness mode and long battery life in existing display panels.

[0005] According to a first aspect of the embodiments of this application, a pixel circuit is provided. One end of the pixel circuit is connected to a power supply voltage terminal, and the other end is connected to a ground terminal. The pixel circuit includes a driving circuit and a photosensitive control circuit connected in parallel, wherein the driving circuit includes a driving element and a light-emitting element connected in series, the end of the driving element away from the light-emitting element is connected to the power supply voltage terminal, and the end of the light-emitting element away from the driving element is connected to the ground terminal. The photosensitive control circuit includes an anti-reverse current element and a photoelectric conversion element connected in series, the cathode of the anti-reverse current element is connected to the power supply voltage terminal, and the anode of the anti-reverse current element is connected to the ground terminal, the anti-reverse current element being used to prevent current flowing into the power supply voltage terminal from flowing into the photosensitive control circuit.

[0006] As can be seen from the above embodiments, the pixel circuit provided in this application directly adds a parallel photosensitive control circuit to the driving circuit in related technologies, avoiding the complexity of connecting the photovoltaic energy storage circuit to the system battery to increase brightness by charging the system battery. A simple and efficient circuit layout design can be achieved by adding a photoelectric conversion element. In high-brightness mode in outdoor environments, in addition to receiving the original current provided by the system, the photosensitive control circuit can provide additional photovoltaic current to the light-emitting element under sunlight conditions. The current of the light-emitting element is increased by the additional photovoltaic current value based on the original current value. Furthermore, the magnitude of the photovoltaic current is positively correlated with the intensity of solar radiation. Therefore, as the radiation intensity increases, the brightness required by the display screen increases, and the photovoltaic current also increases accordingly, which precisely meets the needs of the high-brightness mode under long battery life conditions, realizing an adaptive brightness adjustment mode.

[0007] In addition, to avoid the situation where the system power supply provides current to the light-emitting element while simultaneously providing branch current to the photoelectric conversion element, thus consuming system current, this embodiment adds an anti-reverse current component connected in series with the photoelectric conversion element to the photosensitive control circuit. The anti-reverse current component can control the current in the photosensitive control circuit to flow only from the photoelectric conversion element to the power supply voltage terminal, and prevent the current provided by the system power supply from being diverted to the photosensitive control circuit. This avoids the system battery "re-charging" the photoelectric conversion element, thus not consuming system power, which is beneficial to improving the additional power supply effect of the high-brightness mode, saving energy, and improving the utilization rate of solar energy in electronic devices.

[0008] In addition, the extra current provided by the photoelectric conversion element flows into the power supply voltage terminal and out through the ground terminal, without affecting the voltage signal in the system's own pixel driving circuit. When the pixel circuit is connected to data lines or scan lines, it can still normally control the light-emitting element to emit light, and the grayscale performance of the displayed image remains unaffected. Furthermore, since the data lines or scan lines in each pixel of the display area are interconnected, the total number of photoelectric conversion elements in each pixel can be regarded as a whole "battery" to provide power to the light-emitting element. This avoids the problem of uneven brightness enhancement caused by uneven sunlight exposure, thus improving the display effect.

[0009] In one embodiment, the end of the anti-reverse current element away from the photoelectric conversion element is connected to the power supply voltage terminal.

[0010] In one embodiment, the end of the photoelectric conversion element away from the anti-reverse current element is connected to the power supply voltage terminal.

[0011] In one embodiment, the driving element includes a driving transistor, one of its source or drain terminals being connected to the power supply voltage terminal, and the other of its source or drain terminal being connected to the ground terminal. The gate of the driving transistor is connected to a control circuit for controlling the light-emitting element to emit light.

[0012] In one embodiment, the light-emitting element includes a light-emitting diode, the anode of which is connected to the power supply voltage terminal, and the cathode of which is connected to the ground terminal.

[0013] In one embodiment, the anti-reverse current element includes an anti-reverse current diode, which controls the unidirectional flow of current in the photosensitive control circuit.

[0014] In one embodiment, the photoelectric conversion element includes a solar cell, the anode of which is connected to the power supply voltage terminal, and the cathode of which is connected to the ground terminal.

[0015] According to a second aspect of the embodiments of this application, a display panel is also provided. The display panel includes a substrate, a first conductive layer, an insulating layer, a first gate layer, an interlayer dielectric layer, a first source-drain layer, a planarization layer, an anode layer, a pixel defining layer, a second conductive layer, and a cathode layer stacked sequentially. The display panel also includes pixel circuitry as provided in the first aspect. The first conductive layer includes a first conductive region and a second conductive region spaced apart. The first source-drain layer includes a first source-drain region, a second source-drain region, a third source-drain region, and a fourth source-drain region spaced apart. The first conductive region is connected to the first source-drain region and the second source-drain region respectively through contact holes between the insulating layer and the interlayer dielectric layer. The first source-drain region, the second source-drain region, a portion of the first gate layer located between the first source-drain region and the second source-drain region, and the first conductive region constitute a driving element. The first source-drain region is connected to a power supply voltage terminal. The second conductive region includes interconnected P-type and N-type semiconductor regions. The P-type semiconductor region is connected to the third source-drain region through a contact hole between the insulating layer and the interlayer dielectric layer. The N-type semiconductor region is connected to the fourth source-drain region through a contact hole between the insulating layer and the interlayer dielectric layer. The second conductive region forms an anti-reverse current element. The fourth source-drain region is connected to the power supply voltage terminal. The anode layer includes a first anode region, the cathode layer includes a first cathode region, and the second conductive layer includes a light-emitting region. The light-emitting region is connected to the first anode region and the first cathode region, respectively. The first anode region, the light-emitting region, and the first cathode region constitute a light-emitting element. The first anode region is connected to the second source-drain region through a contact hole in the planarization layer, and the first cathode region is connected to the ground terminal.

[0016] As can be seen from the above embodiments, the anti-reverse current element in the added photosensitive control circuit is completely embedded in the conventionally designed film layer of the display film layer. This makes full use of the spare space in the first conductive layer and the source-drain layer, so that the photosensitive control circuit can be added into the pixel circuit without increasing the flat area and thickness of the display panel. Therefore, the power consumption reduction and adaptive brightness adjustment functions can be realized within the display panel. There is no need to add another film layer outside the encapsulation layer after the display panel process design is completed to integrate the solar battery circuit, and no additional function support is required at the whole machine end.

[0017] In one embodiment, the anode layer further includes a second anode region, the cathode layer further includes a second cathode region, and the second conductive layer further includes a light absorption region. The light absorption region is connected to the second anode region and the second cathode region, respectively, and the second anode region, the light absorption region, and the second cathode region constitute a photoelectric conversion element.

[0018] In one embodiment, the second anode region is connected to the third source / drain region through a contact hole in the planarization layer.

[0019] In one embodiment, the first source-drain layer further includes a fifth source-drain region, the second cathode region is connected to the fourth source-drain region through a contact hole between the pixel defining layer and the planarization layer, the fourth source-drain region is connected to the fifth source-drain region through the photoelectric conversion element, and the fifth source-drain region is connected to the power supply voltage terminal.

[0020] In one embodiment, the first conductive layer further includes a third conductive region, wherein the film layer on the side of the third conductive region away from the substrate is a light-transmitting region, and the third conductive region forms a photoelectric conversion element. The first source-drain layer further includes a fifth source-drain region, and the third conductive region includes a first semiconductor region and a second semiconductor region interconnected. The first semiconductor region is connected to the third source-drain region through a contact hole between the insulating layer and the interlayer dielectric layer; the second semiconductor region is connected to the fifth source-drain region through a contact hole between the insulating layer and the interlayer dielectric layer; the third source-drain region is connected to the fifth source-drain region through the third conductive region; and the fifth source-drain region is connected to the ground terminal.

[0021] According to a third aspect of the embodiments of this application, a display panel is provided. The display panel includes a substrate, a driving circuit layer, an anode layer, a pixel defining layer, a second conductive layer, a cathode layer, an encapsulation layer, and a third conductive layer stacked sequentially. The display panel also includes the pixel circuit provided in the first aspect. The third conductive layer includes an anti-reverse current element and a photoelectric conversion element interconnected. The photoelectric conversion element includes a first semiconductor region and a second semiconductor region interconnected. The second semiconductor region is connected to the cathode layer through a contact hole in the encapsulation layer. The anti-reverse current element includes a P-type semiconductor region and an N-type semiconductor region interconnected. The P-type semiconductor region is connected to the first semiconductor region of the photoelectric conversion element, and the N-type semiconductor region is connected to a power supply voltage terminal.

[0022] As can be seen from the above embodiments, in this application embodiment, both the anti-reverse current element and the photoelectric conversion element are disposed outside the encapsulation layer of the display panel. This can avoid changes to the original film layer structure of the display panel, avoid changes to process parameters, and avoid changes to the design of the fine metal mask (FMM), thereby reducing the impact on process design.

[0023] According to a fourth aspect of the embodiments of this application, a method for manufacturing a display panel is provided, the method comprising:

[0024] A first conductive layer is formed on the substrate.

[0025] The first conductive layer is patterned to form a first conductive region and a second conductive region.

[0026] An insulating layer is formed on the first conductive layer.

[0027] A first gate layer is formed on the insulating layer and the first gate layer is patterned to form a first gate, wherein the orthogonal projection of the first gate on the substrate is located within the first conductive region.

[0028] The gate insulating layer is formed on the first gate layer.

[0029] An interlayer dielectric layer is formed on the gate insulating layer.

[0030] The insulating layer and the interlayer dielectric layer are etched to expose the surfaces of at least a portion of the first conductive region and the second conductive region.

[0031] The first source and drain layers are formed on the interlayer dielectric layer.

[0032] The first source-drain layer is patterned to form a first source-drain region, a second source-drain region, a third source-drain region, and a fourth source-drain region. The first and second source-drain regions are both connected to the first conductive region, and the third and fourth source-drain regions are both connected to the second conductive region.

[0033] A planarization layer is formed on the first source-drain layer.

[0034] The planarization layer is etched to expose the surfaces of at least a portion of the second source / drain region and the third source / drain region.

[0035] An anode layer is formed on the planarization layer.

[0036] The anode layer is etched to form a first anode region and a second anode region. The first anode region is connected to the second source / drain region, and the second anode region is connected to the third source / drain region.

[0037] A pixel defining layer is formed on the anode layer and the pixel defining layer is patterned to form an array of pixel defining regions.

[0038] A light-emitting region of a second conductive layer is formed in the pixel-defined region, and a light-absorbing region of the second conductive layer is formed in the region outside the pixel-defined region of the pixel-defined layer. The light-emitting region and the light-absorbing region of the second conductive layer together form the second conductive layer. The light-emitting region is connected to the first anode region, and the light-absorbing region is connected to the second anode region.

[0039] A cathode layer is formed on the second conductive layer, and both the light-emitting region and the light-absorbing region of the second conductive layer are connected to the cathode layer.

[0040] In this configuration, both the first and fourth source-drain regions are connected to the power supply voltage terminal, and the cathode layer is connected to the ground terminal. The first conductive region, the first source-drain region, and the second source-drain region form a driving element; the second conductive region forms an anti-reverse current element; the first anode region, the light-emitting region of the second conductive layer, and the cathode layer form a light-emitting element; and the second anode region, the light-absorbing region of the second conductive layer, and the cathode layer form a photoelectric conversion element.

[0041] As can be seen from the above embodiments, the driving element and the anti-reverse current element in the display panel share the first conductive layer, avoiding the increase in film layer accumulation that would lead to an increase in the thickness of the display panel. In the actual manufacturing method, for the mask used to fabricate the anti-reverse current element, only a mask similar to that used to fabricate the driving element needs to be added to simultaneously form parts of the driving element and the anti-reverse current element. Simultaneously, the first anode region of the light-emitting element and the second anode region of the photoelectric conversion element share a single anode layer; the light-emitting region of the second conductive layer of the light-emitting element and the light-absorbing region of the second conductive layer of the photoelectric conversion element are located on the same layer, i.e., sharing a single second conductive layer; and the light-emitting element and the photoelectric conversion element share a single cathode layer. This simplifies the process flow while achieving adaptive brightness adjustment and avoids increasing the thickness of the display panel.

[0042] In one embodiment, the light absorption region of the second conductive layer is formed on the anode layer by a vapor deposition process.

[0043] In one embodiment, the light absorption region of the second conductive layer is formed on the anode layer by a solution method.

[0044] According to a fifth aspect of the embodiments of this application, a display device is provided. It includes pixel circuitry as provided in the first aspect, or a display panel as provided in the second or third aspects.

[0045] Additional aspects and advantages of this application will be set forth in part in the description which follows, and will become apparent from the description or may be learned by practice of this application. Attached Figure Description

[0046] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0047] Figure 1 This is a schematic diagram of a pixel circuit provided in an embodiment of this application;

[0048] Figure 2 This is a schematic diagram of another pixel circuit structure provided in an embodiment of this application;

[0049] Figure 3 This is a schematic diagram of the circuit structure of a display panel provided in an embodiment of this application;

[0050] Figure 4 This is a schematic diagram of the circuit structure of another display panel provided in an embodiment of this application;

[0051] Figure 5 This is a cross-sectional structural diagram of a display panel provided in an embodiment of this application;

[0052] Figure 6This is a cross-sectional structural diagram of another display panel provided in an embodiment of this application;

[0053] Figure 7 This is a cross-sectional structural diagram of another display panel provided in an embodiment of this application;

[0054] Figure 8 This is a cross-sectional structural diagram of another display panel provided in an embodiment of this application;

[0055] Figure 9 This is a cross-sectional structural diagram of another display panel provided in an embodiment of this application;

[0056] Figure 10 This is a schematic diagram of the planar structure of a display panel provided in an embodiment of this application;

[0057] Figure 11 This is a schematic diagram of another planar structure of a display panel provided in an embodiment of this application.

[0058] In the picture:

[0059] 100 - Display panel; 200 - Power supply voltage terminal; 300 - Ground terminal; 400 - Pixel circuit; 410 - Driving circuit; 411 - Driving element; 412 - Light-emitting element; 420 - Photosensitive control circuit; 421 - Anti-reverse current element; 422 - Photoelectric conversion element;

[0060] 1-Substrate; 2-Buffer layer; 3-First conductive layer; 31-First conductive region; 32-Second conductive region; 321-P-type semiconductor region; 322-N-type semiconductor region; 33-Third conductive region; 331-First semiconductor region; 332-Second semiconductor region; 4-Insulating layer; 5-First gate layer; 6-Gate insulating layer; 7-Second gate layer; 8-Interlayer dielectric layer; 9-First source / drain layer; 91-First source / drain region; 92- Second source / drain region; 93-Third source / drain region; 94-Fourth source / drain region; 95-Fifth source / drain region; 10-Planarization layer; 11-Anode layer; 111-First anode region; 112-Second anode region; 12-Pixel limiting layer; 13-Second conductive layer; 131-Light emitting region; 132-Light absorbing region; 14-Cathode layer; 141-First cathode region; 142-Second cathode region; 15-Encapsulation layer; 16-Third conductive layer. Detailed Implementation

[0061] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numerals in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0062] The terminology used in this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The singular forms “a,” “the,” and “the” used in this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any or all possible combinations of one or more of the associated listed items.

[0063] Currently, there is research in the field of display technology on applying solar cells to display devices to improve the battery life of electronic products. However, the existing technologies still rely on the approach of using solar cells to charge the system battery, which then powers the light-emitting elements. The main purpose is to reduce the reflectivity of the display screen or increase the light intake rate. However, integrating solar cells onto the display panel inevitably involves the circuit layout for charging the system battery. In display panels with integrated photovoltaic devices, the current generated by the photovoltaic devices is usually directly supplied to the battery in the entire system (mobile phone, tablet). This requires the entire system to have additional photovoltaic devices to charge the battery, resulting in power loss and reduced photovoltaic utilization as the battery indirectly powers the display pixels.

[0064] The pixel circuit, display panel, fabrication method, and display device provided in this application are intended to solve the above-mentioned technical problems in related technologies.

[0065] The display panel and display device in the embodiments of this application will now be described in detail with reference to the accompanying drawings. Unless otherwise specified, the features in the following embodiments may complement or combine with each other.

[0066] This application provides a pixel circuit 400. For example... Figures 1-2As shown, one end of the pixel circuit 400 is connected to the power supply voltage terminal 200, and the other end is connected to the ground terminal 300. The pixel circuit 400 includes a driving circuit 410 and a photosensitive control circuit 420 connected in parallel. The driving circuit 410 includes a driving element 411 and a light-emitting element 412 connected in series. The end of the driving element 411 away from the light-emitting element 412 is connected to the power supply voltage terminal 200, and the end of the light-emitting element 412 away from the driving element 411 is connected to the ground terminal 300. The photosensitive control circuit 420 includes an anti-reverse current element 421 and a photoelectric conversion element 422 connected in series. The cathode of the anti-reverse current element 421 is connected to the power supply voltage terminal 200, and the anode of the anti-reverse current element 421 is connected to the ground terminal 300. The anti-reverse current element 421 is used to prevent the current flowing into the power supply voltage terminal 200 from flowing into the photosensitive control circuit 420.

[0067] The pixel circuit 400 provided in this application embodiment directly adds a parallel photosensitive control circuit 420 to the driving circuit 410 in related technologies. This avoids the complexity of connecting the photovoltaic energy storage circuit to the system battery to increase brightness by charging the system battery. A simple and efficient circuit layout design can be achieved by adding optical components. In high-brightness mode in outdoor environments, in addition to receiving the original current provided by the system, the photosensitive control circuit 420 can provide additional photovoltaic current to the light-emitting element 412 under sunlight. The current of the light-emitting element 412 is increased by the additional photovoltaic current value based on the original current value. Furthermore, the magnitude of the photovoltaic current is positively correlated with the intensity of solar radiation. Therefore, as the radiation intensity increases, the brightness required by the display screen increases, and the photovoltaic current also increases accordingly. This perfectly meets the requirements of high-brightness mode under long battery life conditions, achieving an adaptive brightness adjustment mode.

[0068] In addition, to avoid the situation where the system power supply provides current to the light-emitting element 412 and simultaneously provides branch current to the photoelectric conversion element 422, thereby consuming system current, this embodiment adds an anti-reverse current element 421 connected in series with the photoelectric conversion element 422 to the photosensitive control circuit 420. The anti-reverse current element 421 can control the current in the photosensitive control circuit 420 to flow only from the photoelectric conversion element 422 to the power supply voltage terminal 200, and prevent the current provided by the system power supply from being diverted to the photosensitive control circuit 420. This avoids the system battery "re-charging" the photoelectric conversion element 422, thus not consuming system power, which is beneficial to improving the additional power supply effect of the high-brightness mode, saving energy, and improving the utilization rate of solar energy in electronic devices.

[0069] In addition, the extra current provided by the optical conversion element flows into the power supply voltage terminal 200 and out through the ground terminal 300, without affecting the voltage signal in the system's own pixel driving circuit 410. When the pixel circuit 400 is connected to data lines or scan lines, the light-emitting element 412 can still be normally controlled to emit light, and the grayscale performance of the displayed image is unaffected. Furthermore, since the data lines or scan lines in each pixel of the display area are interconnected, the total number of photoelectric conversion elements 422 in each pixel can be regarded as a whole "battery" to provide power to the light-emitting element 412, which can avoid the problem of uneven brightness enhancement caused by uneven sunlight exposure and improve the display effect.

[0070] In some embodiments, such as Figure 1 As shown, the end of the anti-reverse current element 421 that is away from the photoelectric conversion element 422 is connected to the power supply voltage terminal 200.

[0071] In some embodiments, such as Figure 2 As shown, the end of the photoelectric conversion element 422 away from the anti-reverse current element 421 is connected to the power supply voltage terminal 200.

[0072] In some embodiments, such as Figures 3-4 As shown, the driving element 411 includes a driving transistor. One of the sources or drains of the driving transistor is connected to the power supply voltage terminal 200, and the other of the sources or drains of the driving transistor is connected to the ground terminal 300. The gate of the driving transistor is connected to a control circuit, which is used to control the light-emitting element 412 to emit light.

[0073] In some embodiments, such as Figures 3-4 As shown, the driving circuit 410 also includes a switching transistor. The gate of the driving transistor is connected to the source or drain of the switching transistor, the other source or drain of the switching transistor is connected to the data line Data, and the gate of the switching transistor is connected to the scan line Scan.

[0074] It should be noted that the embodiments of this application are applicable to conventional driving circuit types in pixel circuit 400, such as 2T1C, 3T1C, 4T1C, 5T2C, 6T1C, 7T1C, 8T1C, or 9T2C. The driving transistor (TFT) can be LTPS (Low Temperature Poly-silicon), LTPO (Low Temperature Polycrystalline Oxide), or oxide type (pure oxide semiconductor). Those skilled in the art can set it according to conventional design, and are not limited to this. In this application, the power supply voltage terminal 200 is ELVDD in the figure, and the ground terminal 300 is ELVSS.

[0075] In some embodiments, such as Figures 3-4 As shown, the light-emitting element 412 includes a light-emitting diode, the anode of which is connected to the power supply voltage terminal 200, and the cathode of which is connected to the ground terminal 300.

[0076] In some embodiments, the light-emitting diode may be a light-emitting diode with a quantum well junction, a light-emitting diode with a columnar structure, or a light-emitting diode with a double-layer heterojunction.

[0077] In some embodiments, such as Figures 3-4 As shown, the anti-reverse current element 421 includes an anti-reverse current diode, which controls the unidirectional flow of current in the photosensitive control circuit 420.

[0078] It should be noted that the anti-reverse current diode provided in this embodiment is only a feasible embodiment and is not intended to limit the anti-reverse current element 421. Theoretically, any electronic component that can control the current to flow unidirectionally in the circuit can be used as an implementation method of this application embodiment.

[0079] In some embodiments, such as Figures 3-4 As shown, the photoelectric conversion element 422 includes a solar cell (organic photovoltaic device, OPV). The anode of the solar cell is connected to the power supply voltage terminal 200, and the cathode of the solar cell is connected to the ground terminal 300.

[0080] Solar cells include silicon-based solar cells and organic thin-film solar cells.

[0081] In one example, the photoelectric conversion element 422 includes a silicon-based solar cell.

[0082] Based on the same inventive concept, this application also provides a display panel 100. For example... Figures 5-8As shown, the display panel 100 includes a substrate 1, a first conductive layer 3, an insulating layer 4, a first gate layer 5, an interlayer dielectric layer 8, a first source-drain layer 9, a planarization layer 10, an anode layer 11, a pixel defining layer 12, a second conductive layer 13, and a cathode layer 14 stacked sequentially. The display panel 100 also includes a pixel circuit 400 as described above. The first conductive layer 3 includes a first conductive region 31 and a second conductive region 32 spaced apart. The first source-drain layer 9 includes a first source-drain region 91, a second source-drain region 92, a third source-drain region 93, and a fourth source-drain region 94 spaced apart. The first conductive region 31 is connected to the first source-drain region 91 and the second source-drain region 92 respectively through contact holes between the insulating layer 4 and the interlayer dielectric layer 8. The first source-drain region 91, the second source-drain region 92, the portion of the first gate layer 5 located between the first source-drain region 91 and the second source-drain region 92, and the first conductive region 31 together form a driving element 411. The first source-drain region 91 is connected to the power supply voltage terminal 200. The second conductive region 32 includes an interconnected P-type semiconductor region 321 and an N-type semiconductor region 322. The P-type semiconductor region 321 is connected to the third source-drain region 93 through contact holes between the insulating layer 4 and the interlayer dielectric layer 8. The N-type semiconductor region 322 is connected to the fourth source-drain region 94 through contact holes between the insulating layer 4 and the interlayer dielectric layer 8. The second conductive region 32 forms an anti-reverse current element 421. The fourth source-drain region 94 is connected to the power supply voltage terminal 200. The anode layer 11 includes a first anode region 111, the cathode layer 14 includes a first cathode region 141, and the second conductive layer 13 includes a light-emitting region 131. The light-emitting region 131 is connected to the first anode region 111 and the first cathode region 141, respectively. The first anode region 111, the light-emitting region 131, and the first cathode region 141 constitute a light-emitting element 412. The first anode region 111 is connected to the second source / drain region 92 through a contact hole in the planarization layer 10, and the first cathode region 141 is connected to the ground terminal 300.

[0083] In this embodiment, the anti-reverse current element 421 in the added photosensitive control circuit 420 is completely embedded in the conventionally designed film layer of the display film layer. This makes full use of the empty space in the first conductive layer 3 and the source-drain layer, so that the photosensitive control circuit 420 can be added into the pixel circuit 400 without increasing the flat area and thickness of the display panel 100. Therefore, the functions of reducing power consumption and adaptive brightness adjustment can be realized inside the display panel 100. There is no need to add another film layer outside the encapsulation layer 15 after the display panel 100 process design is completed for integrating the solar battery circuit, and no additional function support is required at the whole device end.

[0084] In some embodiments, such as Figures 5-7As shown, the anode layer 11 further includes a second anode region 112, the cathode layer 14 further includes a second cathode region 142, and the second conductive layer 13 further includes a light absorption region 132. The light absorption region 132 is connected to the second anode region 112 and the second cathode region 142 respectively. The second anode region 112, the light absorption region 132, and the second cathode region 142 constitute a photoelectric conversion element 422.

[0085] In this embodiment, the anti-reverse current element 421 and photoelectric conversion element 422 in the added photosensitive control circuit 420 are fully embedded in the conventionally designed display film layer. The anti-reverse current element 421 and photoelectric conversion element 422 are distributed in different film layers, so they can be staggered. Their orthogonal projections on the substrate 1 can partially or completely overlap. Therefore, they can be staggered to make full use of the empty space in the first conductive layer 3 and the pixel limiting layer 12, avoiding the influence on the distribution of the original circuit of the display panel 100 itself. This allows for the maximum utilization of the film layer space of the display panel 100 while achieving adaptive brightness adjustment mode.

[0086] In some embodiments, such as Figure 5 As shown, the second anode region 112 is connected to the third source-drain region 93 through a contact hole in the planarization layer 10. Assuming the current in the driving circuit 410 is I, and the current in the photosensitive control circuit 420 is I', then the current I flows as follows: power supply voltage terminal 200 - first source-drain region 91 - first conductive region 31 - second source-drain region 92 - first anode region 111 - light-emitting region 131 - cathode layer 14 - first cathode region 141 - ground terminal 300. The current I' flows as follows: power supply voltage terminal 200 - fourth source-drain region 94 - second conductive region 32 - third source-drain region 93 - second anode region 112 - light-absorbing region 132 - cathode layer 14 - first cathode region 141 - ground terminal 300.

[0087] In some embodiments, such as Figure 6 As shown, the first source-drain layer 9 also includes a fifth source-drain region 95. The second anode region 112 is connected to the fourth source-drain region 94 through a contact hole between the pixel defining layer 12 and the planarization layer 10. The fourth source-drain region 94 is connected to the fifth source-drain region 95 through a photoelectric conversion element 422. The fifth source-drain region 95 is connected to the power supply voltage terminal 200. The current flow of I is as follows: power supply voltage terminal 200 - first source-drain region 91 - first conductive region 31 - second source-drain region 92 - first anode region 111 - light-emitting region 131 - first cathode region 141 - ground terminal 300. The current flow of I' is as follows: power supply voltage terminal 200 - fifth source-drain region 95 - second anode region 112 - light-absorbing region 132 - second cathode region 142 - fourth source-drain region 94 - second conductive region 32 - third source-drain region 93 - first cathode region 141 - ground terminal 300.

[0088] In some embodiments, such as Figures 7-8 As shown, the first conductive layer 3 also includes a third conductive region 33. The film layer on the side of the third conductive region 33 away from the substrate 1 is a light-transmitting region, and the third conductive region 33 forms a photoelectric conversion element 422. The first source-drain layer 9 also includes a fifth source-drain region 95. The third conductive region 33 includes a first semiconductor region 331 and a second semiconductor region 332 that are interconnected. The first semiconductor region 331 is connected to the third source-drain region 93 through a contact hole between the insulating layer 4 and the interlayer dielectric layer 8. The second semiconductor region 332 is connected to the fifth source-drain region 95 through a contact hole between the insulating layer 4 and the interlayer dielectric layer 8. The third source-drain region 93 is connected to the fifth source-drain region 95 through the third conductive region 33. The fifth source-drain region 95 is connected to the ground terminal 300. The current of I flows from beginning to end as follows: power supply voltage terminal 200 - first source-drain region 91 - first conductive region 31 - second source-drain region 92 - first anode region 111 - light-emitting region 131 - first cathode region 141 - ground terminal 300. The current flow of I' from beginning to end is as follows: power supply voltage terminal 200 - fifth source-drain region 95 - second conductive region 32 - third source-drain region 93 - third conductive region 33 - fourth source-drain region 94 - second cathode region 142 - ground terminal 300.

[0089] In this embodiment, the photoelectric conversion element 422 and the anti-reverse current element 421 are both located on the same layer, specifically in the second conductive region 32 and the third conductive region 33, respectively. This increases the tiled area of ​​the pixel circuit 400 to some extent, while simultaneously increasing the amount of light entering the device through cathode patterning. It is worth noting that when the photoelectric conversion element 422 is located inside the display film layer, external light needs to be able to reach it. Therefore, the area of ​​the photoelectric conversion element 422 away from the substrate 1 is a light-transmitting area, ensuring that light can penetrate as much as possible onto the surface of the photoelectric conversion element 422 to achieve solar energy emission.

[0090] In some embodiments, such as Figure 7 As shown, the first semiconductor region 331 and the second semiconductor region 332 of the third conductive region 33 are arranged sequentially on the substrate 1 along the first direction, which is parallel to the surface of the substrate 1.

[0091] In some embodiments, such as Figure 8 As shown, the first semiconductor region 331 and the second semiconductor region 332 of the third conductive region 33 are sequentially stacked and staggered in the display panel 100 along the second direction, which is perpendicular to the surface of the substrate 1.

[0092] It should be noted that the film structure in the light-transmitting area can be made of polyimide (PI).

[0093] Based on the same inventive concept, this application provides a display panel 100, such as... Figure 9 As shown, the display panel 100 includes a substrate 1, a driving circuit layer, an anode layer 11, a pixel defining layer 12, a second conductive layer 13, a cathode layer 14, an encapsulation layer 15, and a third conductive layer 16, which are stacked sequentially. The display panel 100 also includes a pixel circuit 400 as described above. The third conductive layer 16 includes an anti-reverse current element 421 and a photoelectric conversion element 422 connected to each other. The driving circuit layer includes a first conductive layer 3, an insulating layer 4, a first gate layer 5, a gate insulating layer 6, a second gate layer 7, an interlayer dielectric layer 8, a first source-drain layer 9, and a planarization layer 10, which are stacked sequentially. The photoelectric conversion element 422 includes a first semiconductor region 331 and a second semiconductor region 332 connected to each other. The second semiconductor region 332 is connected to the cathode layer 14 through a contact hole in the encapsulation layer 15. The anti-reverse current element 421 includes an interconnected P-type semiconductor region 321 and an N-type semiconductor region 322. The P-type semiconductor region 321 is connected to the first semiconductor region 331 of the photoelectric conversion element 422, and the N-type semiconductor region 322 is connected to the power supply voltage terminal 200. The current flow of I is as follows: power supply voltage terminal 200 - first source-drain region 91 - first conductive region 31 - second source-drain region 92 - first anode region 111 - light-emitting region 131 - cathode layer 14 - ground terminal 300. The current flow of I' is as follows: power supply voltage terminal 200 - third conductive layer 16 - cathode layer 14 - ground terminal 300.

[0094] In this embodiment, both the anti-backflow element 421 and the photoelectric conversion element 422 are disposed outside the encapsulation layer 15 of the display panel 100. This avoids changes to the original film layer structure of the display panel 100, avoids changes to process parameters, and avoids changes to the design of the fine metal mask (FMM), thereby reducing the impact on process design.

[0095] In some embodiments, the display panel 100 further includes a gate insulating layer 6 and a second gate layer 7, which are sequentially stacked on the side of the first gate layer 5 away from the substrate 1.

[0096] Based on the same inventive concept, combined with Figure 5 As shown, this application embodiment provides a method for manufacturing a display panel 100, the method comprising:

[0097] S101: A first conductive layer 3 is formed on the substrate 1.

[0098] S102: The first conductive layer 3 is patterned to form a first conductive region 31 and a second conductive region 32.

[0099] S103: An insulating layer 4 is formed on the first conductive layer 3.

[0100] S104: A first gate layer 5 is formed on the insulating layer 4 and the first gate layer 5 is patterned to form a first gate, the orthogonal projection of the first gate on the substrate 1 is located within the first conductive region 31.

[0101] S105: A gate insulating layer 6 is formed on the first gate layer 5.

[0102] S106: An interlayer dielectric layer 8 is formed on the gate insulating layer 6.

[0103] S107: Etch the insulating layer 4 and the interlayer dielectric layer 8 to expose the surface of at least a portion of the first conductive region 31 and the second conductive region 32.

[0104] S108: A first source / drain layer 9 is formed on the interlayer dielectric layer 8.

[0105] S109: The first source-drain layer 9 is patterned to form a first source-drain region 91, a second source-drain region 92, a third source-drain region 93, and a fourth source-drain region 94. The first source-drain region 91 and the second source-drain region 92 are both connected to the first conductive region 31, and the third source-drain region 93 and the fourth source-drain region 94 are both connected to the second conductive region 32.

[0106] S110: A planarization layer 10 is formed on the first source / drain layer 9.

[0107] S111: The planarization layer 10 is etched to expose the surface of at least a portion of the second source / drain region 92 and the third source / drain region 93.

[0108] S112: An anode layer 11 is formed on the planarization layer 10.

[0109] S113: The anode layer 11 is etched to form a first anode region 111 and a second anode region 112. The first anode region 111 is connected to the second source / drain region 92, and the second anode region 112 is connected to the third source / drain region 93.

[0110] S114: A pixel defining layer 12 is formed on the anode layer 11 and the pixel defining layer 12 is patterned to form an array of pixel defining regions.

[0111] S115: A light-emitting region 131 of the second conductive layer 13 is formed in the pixel-defined region, and a light-absorbing region 132 of the second conductive layer 13 is formed in the region outside the pixel-defined region of the pixel-defined layer 12. The light-emitting region 131 and the light-absorbing region 132 of the second conductive layer 13 together form the second conductive layer 13. The light-emitting region 131 is connected to the first anode region 111, and the light-absorbing region 132 is connected to the second anode region 112.

[0112] S116: A cathode layer 14 is formed on the second conductive layer 13, and the light-emitting region 131 and the light-absorbing region 132 of the second conductive layer 13 are both connected to the cathode layer 14.

[0113] In this configuration, the first source-drain region 91 and the fourth source-drain region 94 are both connected to the power supply voltage terminal 200, and the cathode layer 14 is connected to the ground terminal 300. The first conductive region 31, the first source-drain region 91, and the second source-drain region 92 form a driving element 411, the second conductive region 32 forms an anti-reverse current element 421, the first anode region 111, the light-emitting region 131 of the second conductive layer 13, and the cathode layer 14 form a light-emitting element 412, and the second anode region 112, the light-absorbing region 132 of the second conductive layer 13, and the cathode layer 14 form a photoelectric conversion element 422.

[0114] In some embodiments, the preparation method further includes step S117: forming an encapsulation layer 15 on the cathode layer 14.

[0115] In this embodiment, the driving element 411 and the anti-reverse current element 421 in the display panel 100 share the first conductive layer 3, avoiding the increase in film layer accumulation that would increase the thickness of the display panel 100. In the actual manufacturing method, for the mask used to prepare the anti-reverse current element 421, only a mask similar to that used to prepare the driving element 411 needs to be added to simultaneously form parts of the driving element 411 and the anti-reverse current element 421. Meanwhile, the first anode region 111 of the light-emitting element 412 and the second anode region 112 of the photoelectric conversion element 422 share an anode layer 11. The light-emitting region 131 of the second conductive layer 13 of the light-emitting element 412 and the light-absorbing region 132 of the second conductive layer 13 of the photoelectric conversion element 422 are located on the same layer, i.e., sharing a second conductive layer 13. The light-emitting element 412 and the photoelectric conversion element 422 share a cathode layer 14. This simplifies the process flow while achieving adaptive brightness adjustment and avoids increasing the thickness of the display panel 100.

[0116] In some embodiments, such as Figure 10 As shown, when the photoelectric conversion element 422 is a small molecule solar cell, the light absorption region 132 of the second conductive layer 13 is formed on the anode layer 11 by a fine metal mask through a vapor deposition process.

[0117] In some embodiments, such as Figure 11 As shown, when the photoelectric conversion element 422 is a polymer solar cell, the light absorption region 132 of the second conductive layer 13 is formed on the anode layer 11 by a solution method. In this embodiment, the photoelectric conversion element 422 can be continuously distributed on the layout of the display panel 100, with a large area ratio, high space utilization, and higher brightness in the adaptive high brightness adjustment mode.

[0118] In some embodiments, there is a certain gap between the light absorption region 132 and the light emission region 131 of the second conductive layer 13 to avoid mutual interference between the organic materials of the light emission region 131 and the organic materials of the light absorption region 132.

[0119] Based on the same inventive concept, this application provides a display device. It includes the pixel circuit 400 as provided in the foregoing embodiments, or the display panel 100 as provided in the foregoing embodiments. Therefore, this display device possesses all the features and advantages of the aforementioned pixel circuit 400 or display panel 100, which will not be repeated here.

[0120] It should be noted that substrate 1 can be a rigid substrate 1 or a flexible substrate 1, and substrate 1 includes insulating materials such as glass, quartz, and polymer resin. Furthermore, substrate 1 includes CPI (Colorless Polyimide), PET (Poly-Ethylene Terephthalate), or UTG (Ultra Thin Glass). The insulating layer 4 and the interlayer dielectric layer 8 may include inorganic materials such as silicon oxide, silicon nitride, and / or silicon oxynitride. The planarization layer 10 (PLN) may include PFA (Polymer Film on Array) as a photoresist material. The anode layer 11 may include ITO or IZO. The cathode layer 14 may include Mg / Ag.

[0121] In some embodiments, a buffer layer 2 is further provided between the substrate 1 and the first conductive layer 3, which may include inorganic materials such as silicon oxide, silicon nitride and / or silicon oxynitride.

[0122] It should be noted that the display device can be any device that displays images, whether moving (e.g., video) or fixed (e.g., still images), and whether it contains text or images. More specifically, the intended embodiments can be implemented in or associated with a variety of electronic devices, such as (but not limited to) mobile phones, wireless devices, personal data assistants (PDAs), handheld or portable computers, GPS receivers / navigators, cameras, MP4 video players, camcorders, game consoles, watches, clocks, calculators, television monitors, flat panel displays, computer monitors, automotive displays (e.g., odometer displays, etc.), navigators, cockpit controllers and / or displays, displays of camera views (e.g., displays of rearview cameras in vehicles), electronic photographs, electronic billboards or signs, projectors, architectural structures, packaging and aesthetic structures (e.g., displays of images of a piece of jewelry), etc.

[0123] The above embodiments of this application can complement each other without causing conflict.

[0124] It should be noted that the dimensions of layers and regions may be exaggerated in the accompanying drawings for clarity. Furthermore, it is understood that when an element or layer is referred to as being "on" another element or layer, it can be directly on the other element, or there may be intermediate layers. Additionally, it is understood that when an element or layer is referred to as being "below" another element or layer, it can be directly below the other element, or there may be more than one intermediate layer or element. Furthermore, it is also understood that when a layer or element is referred to as being "between" two layers or two elements, it can be the only layer between the two layers or two elements, or there may be more than one intermediate layer or element. Similar reference numerals throughout indicate similar elements.

[0125] The terms “center,” “upper,” “lower,” “front,” “back,” “left,” “right,” “vertical,” “horizontal,” “top,” “bottom,” “inner,” and “outer,” etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0126] The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, unless otherwise stated, "a plurality of" means two or more.

[0127] Other embodiments of this application will readily occur to those skilled in the art upon consideration of the specification and practice of the disclosure herein. This application is intended to cover any variations, uses, or adaptations of this application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this application are indicated by the claims.

[0128] It should be understood that this application is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this application is limited only by the appended claims.

Claims

1. A display panel, comprising a substrate, a first conductive layer, an insulating layer, a first gate layer, an interlayer dielectric layer, a first source / drain layer, a planarization layer, an anode layer, a pixel defining layer, a second conductive layer, and a cathode layer stacked sequentially, the display panel further comprising a pixel circuit, one end of the pixel circuit being connected to a power supply voltage terminal and the other end being connected to a ground terminal, the pixel circuit comprising a driving circuit and a photosensitive control circuit connected in parallel, wherein: The driving circuit includes a driving element and a light-emitting element connected in series. The end of the driving element away from the light-emitting element is connected to the power supply voltage terminal, and the end of the light-emitting element away from the driving element is connected to the ground terminal. The photosensitive control circuit includes a reverse current prevention element and a photoelectric conversion element connected in series. The cathode of the reverse current prevention element is connected to the power supply voltage terminal, and the anode of the reverse current prevention element is connected to the ground terminal. The reverse current prevention element is used to prevent current flowing into the power supply voltage terminal from flowing into the photosensitive control circuit; characterized in that... The first conductive layer includes a first conductive region and a second conductive region spaced apart, and the first source-drain layer includes a first source-drain region, a second source-drain region, a third source-drain region, and a fourth source-drain region spaced apart. The first conductive region is connected to the first source-drain region and the second source-drain region respectively through the contact hole between the insulating layer and the interlayer dielectric layer. The first source-drain region, the second source-drain region, the portion of the first gate layer located between the first source-drain region and the second source-drain region, and the first conductive region constitute a driving element. The first source-drain region is connected to the power supply voltage terminal. The second conductive region includes an interconnected P-type semiconductor region and an N-type semiconductor region. The P-type semiconductor region is connected to the third source-drain region through a contact hole between the insulating layer and the interlayer dielectric layer. The N-type semiconductor region is connected to the fourth source-drain region through a contact hole between the insulating layer and the interlayer dielectric layer. The second conductive region forms an anti-reverse current element. The fourth source-drain region is connected to the power supply voltage terminal. The anode layer includes a first anode region, the cathode layer includes a first cathode region, and the second conductive layer includes a light-emitting region. The light-emitting region is connected to the first anode region and the first cathode region, respectively. The first anode region, the light-emitting region, and the first cathode region constitute a light-emitting element. The first anode region is connected to the second source-drain region through a contact hole in the planarization layer, and the first cathode region is connected to a ground terminal.

2. The display panel according to claim 1, characterized in that, The anode layer further includes a second anode region, the cathode layer further includes a second cathode region, and the second conductive layer further includes a light absorption region. The light absorption region is connected to the second anode region and the second cathode region, respectively. The second anode region, the light absorption region, and the second cathode region constitute a photoelectric conversion element.

3. The display panel according to claim 2, characterized in that, The second anode region is connected to the third source / drain region through contact holes in the planarization layer; Alternatively, the first source-drain layer may further include a fifth source-drain region, the second cathode region may be connected to the fourth source-drain region through a contact hole between the pixel defining layer and the planarization layer, the fourth source-drain region may be connected to the fifth source-drain region through the photoelectric conversion element, and the fifth source-drain region may be connected to the power supply voltage terminal.

4. The display panel according to claim 1, characterized in that, The first conductive layer further includes a third conductive region, the side of the third conductive region away from the substrate being a light-transmitting region, and the third conductive region forming a photoelectric conversion element; the first source-drain layer further includes a fifth source-drain region, the third conductive region including a first semiconductor region and a second semiconductor region interconnected; the first semiconductor region is connected to the third source-drain region through a contact hole between the insulating layer and the interlayer dielectric layer, the second semiconductor region is connected to the fifth source-drain region through a contact hole between the insulating layer and the interlayer dielectric layer, the third source-drain region is connected to the fifth source-drain region through the third conductive region, and the fifth source-drain region is connected to the ground terminal.

5. A method for manufacturing a display panel, characterized in that, The preparation method includes: A first conductive layer is formed on the substrate; The first conductive layer is patterned to form a first conductive region and a second conductive region; An insulating layer is formed on the first conductive layer; A first gate layer is formed on the insulating layer and the first gate layer is patterned to form a first gate, wherein the orthogonal projection of the first gate on the substrate is located within the first conductive region; A gate insulating layer is formed on the first gate layer; An interlayer dielectric layer is formed on the gate insulating layer; The insulating layer and the interlayer dielectric layer are etched to expose the surfaces of at least a portion of the first conductive region and the second conductive region. A first source / drain layer is formed on the interlayer dielectric layer; The first source-drain layer is patterned to form a first source-drain region, a second source-drain region, a third source-drain region, and a fourth source-drain region; the first source-drain region and the second source-drain region are both connected to the first conductive region, and the third source-drain region and the fourth source-drain region are both connected to the second conductive region; A planarization layer is formed on the first source / drain layer; The planarization layer is etched to expose the surfaces of at least a portion of the second source / drain region and the third source / drain region; An anode layer is formed on the planarization layer; The anode layer is etched to form a first anode region and a second anode region; the first anode region is connected to the second source / drain region, and the second anode region is connected to the third source / drain region; A pixel defining layer is formed on the anode layer and the pixel defining layer is patterned to form an array of pixel defining regions; A light-emitting area of ​​a second conductive layer is formed in the pixel-defined area, and a light-absorbing area of ​​the second conductive layer is formed in the area outside the pixel-defined area of ​​the pixel-defined layer. The light-emitting area and the light-absorbing area of ​​the second conductive layer together form the second conductive layer. The light-emitting area is connected to the first anode area, and the light-absorbing area is connected to the second anode area. A cathode layer is formed on the second conductive layer, and both the light-emitting region and the light-absorbing region of the second conductive layer are connected to the cathode layer. The first source-drain region and the fourth source-drain region are both connected to the power supply voltage terminal, and the cathode layer is connected to the ground terminal; the first conductive region, the first source-drain region and the second source-drain region form a driving element, the second conductive region forms an anti-reverse current element, the first anode region, the light-emitting region of the second conductive layer and the cathode layer form a light-emitting element, and the second anode region, the light-absorbing region of the second conductive layer and the cathode layer form a photoelectric conversion element.

6. The method for manufacturing a display panel according to claim 5, characterized in that, The light absorption region of the second conductive layer is formed on the anode layer by a vapor deposition process; Alternatively, the light absorption region of the second conductive layer is formed on the anode layer by a solution method.

7. A display device, characterized in that, Includes the display panel as described in any one of claims 1 to 4.

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