LEVEL CONVERTER

Abstract

A level converter for converting a voltage signal from a first voltage range to a second voltage range, comprising an input circuit configured to receive the voltage signal in the first voltage range, an output circuit configured to output the voltage signal in the second voltage range, and a protection circuit configured to prevent reverse current flow between the input circuit and the output circuit.

Description

The present disclosure relates to a level converter for converting a voltage signal from a first voltage range to a second voltage range. BACKGROUND A voltage domain refers to the voltage range in which a device operates and depends on the supply voltages provided to the device. For example, if a device receives a primary supply voltage of 5 V and a secondary supply voltage of 0 V, the device operates in a range of 0 V to 5 V and can provide an output signal within this range. A supply voltage of 0 V can be referred to as the ground voltage. The supply voltages can be provided via busbars. In certain applications, it is necessary to convert a voltage from one voltage range to another. For example, if a control signal for a circuit breaker is in a different voltage range than the control signal generator, it may be necessary to convert the control signal to the appropriate voltage range for controlling the circuit breaker. A level converter is a device for converting a signal from one voltage range to another. For a static voltage range, the first supply voltage can be variable, while the second supply voltage, which is ground, is fixed. In a floating voltage range, both the first and second supply voltages can be variable, but with a constant difference between the first and second supply voltages. Fig. 1A is a schematic representation of a known device 100, which has two sequential level shifters 102, 104 connected in series. The device 100 also has a power gate driver 108 and a power device 110. The level shifter 102 transfers the input signal 112 to the most negative (or most positive) output voltage. The level shifter transfers the input signal 112 into the flying output range, where a ground potential is never higher than the output ground of the level shifter 104. Similarly, the signal 112 could first be shifted upwards and then (downwards) into the output voltage range. In some cases, optical or magnetic signal transmission could be used as part of the level shifting process. Fig. 1B is a schematic representation of a known level converter 114 for converting a signal from an initial voltage range to a lower voltage range (WO2008 / 101548 A1). The level converter 114 receives an input signal 60 and provides output signals 65, 66. The level converter 114 comprises inverters 48, 49, 52, 53; transistors 42, 45, 43, 46, 44, 47; nodes 61, 63, 62, 64; resistors 50, 51; and diodes 54, 55. SUMMARY It is desirable to provide an improved level converter. According to a first aspect of the disclosure, a level converter is provided for converting a voltage signal from a first voltage range to a second voltage range, which includes an input circuit configured to receive the voltage signal in the first voltage range, an output circuit configured to output the voltage signal in the second voltage range, and a protection circuit configured to prevent a reverse current flow between the input circuit and the output circuit. Optionally, the first voltage range is a floating voltage range and / or the second voltage range is a floating voltage range. Optionally, the input circuit is configured to operate in the first voltage range, and the output circuit is configured to operate in the second voltage range. Optionally, the first voltage range is the voltage range from a first supply voltage to a second supply voltage, and the second voltage range is the voltage range from a third supply voltage to a fourth supply voltage. Optionally, the protection circuit includes one or more rectifier elements, each rectifier element being configured to prevent reverse current flow between the input circuit and the output circuit. Optionally, one or more of the rectifier elements contain a diode or a bipolar transistor. Optionally, the diode can be a p / n diode, a Zener diode, or a Schottky diode. Optionally, the input circuit includes a pull-up circuit coupled to the output circuit via a first section of the protection circuit, wherein the first section of the protection circuit is configured to prevent reverse current flow from the output circuit to the pull-up circuit, thereby preventing reverse current flow between the input circuit and the output circuit, and / or a pull-down circuit coupled to the output circuit via a second section of the protection circuit, wherein the second section of the protection circuit is configured to prevent reverse current flow from the pull-down circuit to the output circuit, thereby preventing reverse current flow between the input circuit and the output circuit. Optionally, the output circuit includes a latch circuit configured to provide the voltage signal in the second voltage range, wherein the pull-up circuit is coupled to the latch circuit via the first section of the protection circuit, the first section of the protection circuit being configured to prevent reverse current flow from the latch circuit to the pull-up circuit, thereby preventing reverse current flow between the input circuit and the output circuit, and / or the pull-down circuit is coupled to the latch circuit via the second section of the protection circuit, the second section of the protection circuit being configured to prevent reverse current flow from the pull-down circuit to the latch circuit, thereby preventing reverse current flow between the input circuit and the output circuit. Optionally, the first voltage range is the range from a first supply voltage to a second supply voltage; the second voltage range is the range from a third supply voltage to a fourth supply voltage; the second voltage range is positive if the fourth supply voltage is greater than the third supply voltage, and / or the second supply voltage is greater than the first supply voltage, and / or the third supply voltage is greater than the first supply voltage; the second voltage range is negative if the second supply voltage is greater than the fourth supply voltage, and / or the first supply voltage is greater than the third supply voltage; and the pull-up circuit is configured to control a state of the latch circuit based on the voltage signal received in the first range when the second voltage range is negative.and the pull-down circuit is configured to control the state of the latch circuit based on the voltage signal received in the first area when the second voltage area is positive. Optionally, the pull-up circuit is configured to control the state of the latch circuit by supplying a first pull-up signal to a first input terminal of the latch circuit and / or by supplying a second pull-up signal to a second input terminal of the latch circuit, and the pull-down circuit is configured to control the state of the latch circuit by supplying a first pull-down signal to the first input terminal of the latch circuit and / or by supplying a second pull-down signal to the second input terminal of the latch circuit. Optionally, the first pull-up signal is a first pull-up current pulse, the second pull-up signal is a second pull-up current pulse, the first pull-down signal is a first pull-down current pulse, and the second pull-down signal is a second pull-down current pulse. Optionally, the first pull-up current pulse is a set pulse for the latch circuit and the second pull-up current pulse is a reset pulse for the latch circuit, or the first pull-up current pulse is a reset pulse for the latch circuit and the second pull-up current pulse is a set pulse for the latch circuit, or the first pull-down current pulse is a set pulse for the latch circuit and the second pull-down current pulse is a reset pulse for the latch circuit, or the first pull-down current pulse is a reset pulse for the latch circuit and the second pull-down current pulse is a set pulse for the latch circuit. Optionally, the latch circuit includes a cross-coupled inverter pair. Optionally, the output circuit includes a common-mode rejection circuit coupled to the latch circuit, and the latch circuit is configured to provide the voltage signal in the second voltage range via the common-mode rejection circuit. Optionally, the level converter includes a first cascode circuit coupled between the first section of the protection circuit and the latch circuit, and a second cascode circuit coupled between the second section of the protection circuit and the latch circuit. Optionally, the protection circuit includes a first rectifier element, a second rectifier element, a third rectifier element, and a fourth rectifier element, each of the first, second, third, and fourth rectifier elements being configured to prevent reverse current flow between the input circuit and the output circuit. The first rectifier element is coupled to the first input terminal of the latch circuit and the third rectifier element. The second rectifier element is coupled to the second input terminal of the latch circuit and the fourth rectifier element. The pull-up circuit is configured to supply the first pull-up signal to the first input terminal via the first rectifier element. The pull-up circuit is configured to supply the second pull-up signal to the second input terminal via the second rectifier element.The pull-down circuit is configured to deliver the first pull-down signal to the first input terminal via the third rectifier element, and the pull-down circuit is configured to deliver the second pull-down signal to the second input terminal via the fourth rectifier element. Optionally, the pull-up circuit includes a first pull-up switch coupled to the first rectifier element and a second pull-up switch coupled to the second rectifier element, and the pull-down circuit includes a first pull-down switch coupled to the third rectifier element and a second pull-down switch coupled to the fourth rectifier element. Optionally, the pull-up circuit includes a first inverting AND gate configured to receive the voltage signal in the first region and a first indicator signal, where the first indicator signal is high when the second region is negative and low when the second region is positive; to output a first inverting AND gate signal; to provide the first inverting AND gate output signal to control the switching operation of the second pull-up switch; and a first inverter configured to receive the first inverting AND gate output signal and to provide the inverted first inverting AND gate output signal to control the switching operation of the first pull-up switch. The pull-down circuit includes a second inverting AND gate configured to...to receive the voltage signal in the first area and a second indicator signal, wherein the second indicator signal is in a high state when the second area is positive, and in a low state when the second area is negative, to output a second inverting AND gate output signal and to provide the second inverting AND gate output signal to control the switching operation of the second pull-down switch, and a second inverter configured to receive the second inverting AND gate output signal to provide the inverted second inverting AND gate output signal to control the switching operation of the first pull-down switch. Optionally, the input circuit contains a pull-up circuit and the output circuit contains a pull-down circuit, or the input circuit contains the pull-down circuit and the output circuit contains the pull-up circuit, and the pull-up circuit is coupled to the pull-down circuit via the protection circuit, the protection circuit being configured to prevent a reverse current flow from the pull-down circuit to the pull-up circuit, thereby preventing a reverse current flow between the input circuit and the output circuit. According to a second aspect of the disclosure, a power converter system is provided with a level converter for converting a voltage signal from a first voltage range to a second voltage range, which includes an input circuit configured to receive the voltage signal in the first voltage range, an output circuit configured to output the voltage signal in the second voltage range, and a protection circuit configured to prevent reverse current flow between the input circuit and the output circuit, and a power switch configured to operate in the second voltage range, wherein the level converter is configured to convert the voltage signal from the first voltage range to the second voltage range before the voltage signal is supplied to the power switch. It is understood that the power converter system of the second aspect may contain features set forth in relation to the first aspect, and may contain other features as described herein. According to a third aspect of the present disclosure, a method for converting a voltage signal from a first voltage range to a second voltage range using a level converter is provided, wherein the method includes receiving the voltage signal in the first voltage range using an input circuit, outputting the voltage signal in the second voltage range using an output circuit, and preventing a reverse current flow between the input circuit and the output circuit using a protection circuit. It is understood that the procedure of the third aspect may include the use and / or provision of features set forth in relation to the first and / or second aspect, and may include other features as described herein. BRIEF DESCRIPTION OF THE DRAWINGS The disclosure is described in more detail below by way of example and with reference to the accompanying drawings, in which: Fig. 1A is a schematic representation of a known device comprising two sequential level converters connected in series; Fig. 1B is a schematic representation of a known level converter for converting a signal from an initial voltage range to a lower voltage range; Fig. 2 is a further schematic representation of the level converter of Fig. 1B; Fig. 3 is a schematic representation of a level converter according to a first embodiment of the present disclosure; Fig. 4 is a schematic representation of a specific embodiment of the level converter according to a second embodiment of the present disclosure; Fig. 5 is a schematic representation of a specific embodiment of the level converter according to a third embodiment of the present disclosure; Fig.Figure 6 is a schematic representation of a specific embodiment of the level converter according to a fourth embodiment of the present disclosure; Figure 7 is a schematic representation of a power converter system comprising the level converter and a circuit breaker according to a fifth embodiment of the present disclosure; and Figure 8 is a graph showing the relationship between the first voltage range and examples of the second voltage range. DETAILED DESCRIPTION Fig. 2 is another schematic representation of the level converter 114 from Fig. 1B. In such conventional level converters, the output rails Vddls, Vssls (i.e., the low-side rails) are either at the same or a lower potential than the input rails Vddhs, Vsshs (i.e., the high-side rails). In the present example, during normal operation, current would flow from the upper section of the schematic diagram to the lower section. For example, current would flow from node 61 to node 62 and from node 63 to node 64. If the level converter output area (Vddls, Vssls rails) were to go to a higher potential than the input area, then parasitic diodes 200, 202, 204, 206 of transistors 42, 44, 45 and 47 could switch on. The parasitic diodes 200, 202, 204, 206 can lead to a "reverse current flow" within the level converter 114. For example, from node 62 to node 61 and from node 64 to node 63. This can have a variety of negative effects due to the differing current flow, potentially leading to abnormal behavior or even failure of the level converter 114. It is therefore desirable to provide a method for protecting level converters, such as the level converter 114, from changes in the output range that could cause a reverse current flow. Fig. 3 is a schematic representation of a level converter 300 for converting a voltage signal 302 from a first voltage range to a second voltage range according to a first embodiment of the present disclosure. The level converter 300 includes an input circuit 304 configured to receive the voltage signal 302 in the first voltage range, an output circuit 306 configured to output the voltage signal 302 in the second voltage range, and a protection circuit 308 configured to prevent reverse current flow between the input circuit 304 and the output circuit 306. The first voltage range can be, for example, a static voltage range or a flying voltage range. The second voltage range can also be, for example, a static voltage range or a flying voltage range. For example, the first voltage range can be a static voltage range and the second voltage range can be a flying voltage range, so that the level converter 300 converts the voltage signal 302 from a static voltage range to a flying voltage range during operation. In another embodiment, the input region (which is the first voltage region) could be floating, and the output region (which is the second voltage region) could be static. In yet another embodiment, neither region could be static (for example, both floating regions). If on-state information is transmitted from a circuit breaker back to a digital controller via the level converter 300, there would likely be a level conversion from a flying to a static range, since the controller is normally located in the static range. The first voltage range can be a voltage range from supply voltage VS1 to supply voltage VS2. The second voltage range can be a voltage range from supply voltage VS3 to supply voltage VS4. The input circuit 304 can be configured to operate in the first voltage range, for example by receiving the supply voltages VS1 and VS2. The output circuit 306 can be configured to operate in the second voltage range, for example by receiving the supply voltages VS3 and VS4. Fig. 4 is a schematic representation of a specific embodiment of the level converter 300 according to a second embodiment of the present disclosure. The protection circuit 308 can include one or more rectifier elements, each rectifier element being configured to prevent reverse current flow between the input circuit and the output circuit. One or more of the rectifier elements can include a diode or a bipolar transistor. The diode can be, for example, a p / n diode, a Zener diode, or a Schottky diode. One or more of the rectifier elements can be implemented using a multi-junction rectifier element, such as a thyristor. Typically, one junction is required for conduction or isolation, and the other paths are (parasitic) paths that are part of (isolated) diodes in MOS or BCD technologies. In another embodiment, one or more of the rectifier elements can be implemented using the beta of a bipolar diode and its reverse voltage. In the present example, the protection circuit 308 contains four rectifier elements 400, 402, 404, 406, and each of the rectifier elements 400, 402, 404, 406 contains a diode 408, 410, 412, 414. The input circuit 304 can include a pull-up circuit 416, which is coupled to the output circuit 306 via a first section 418 of the protection circuit 308. The first section 418 of the protection circuit 308 can be configured to prevent reverse current flow from the output circuit 306 to the pull-up circuit 416. In the present embodiment, the first section 418 of the protection circuit 308 includes the diodes 408 and 410, which serve to prevent reverse current flow. Alternatively or additionally, the input circuit 304 can include a pull-down circuit 420, which is coupled to the output circuit 306 via a second section 422 of the protection circuit 308. The second section 422 of the protection circuit 308 can be configured to prevent reverse current flow from the pull-down circuit 420 to the output circuit 306. In the present embodiment, the second section 422 of the protection circuit 308 includes diodes 412 and 414, which serve to prevent reverse current flow. The output circuit 306 can include a latch circuit 424 configured to provide the voltage signal 302 in the second voltage range. The latch circuit 424 can include a cross-coupled inverter pair 425, which includes inverters 427 and 429. The latch circuit 424 can function as a set-reset latch (SR latch), as is well known to those skilled in the art. Cross-coupled inverter pairs are known to those skilled in the art, and a similar latch structure is shown in US11695342B2. In the present example, the rectifier elements 400, 402, 404, and 406 are shown as part of the pull-up and pull-down circuits 416 and 420. However, it is understood that the rectifier elements 400, 402, 404, and 406 can alternatively be separate from the pull-up and pull-down circuits 416 and 420. For example, the rectifier elements 400, 402, 404, and 406 can be part of the latch circuit 424, or they can be separate from the pull-up and pull-down circuits 416 and 420 and the latch circuit 424. The pull-up circuit 416 can be coupled to the latch circuit 424 via the first section 418 of the protection circuit 308, thus preventing a reverse current from flowing from the latch circuit 424. The pull-down circuit 420 can be coupled to the latch circuit 414 via the second section 422 of the protection circuit 308, thus preventing a reverse current from flowing to the latch circuit 424. In the present embodiment, the first voltage range is the voltage range from a supply voltage vbat to a supply voltage vss, and the second voltage range is the voltage range from a supply voltage vddFly to a supply voltage vssFly. In this example, the second voltage range is a flying range. The second voltage range can be negative if the second supply voltage is greater than the fourth supply voltage and / or the first supply voltage is greater than the third supply voltage. The second voltage range can be positive if the fourth supply voltage is greater than the third supply voltage and / or the second supply voltage is greater than the first supply voltage and / or the third supply voltage is greater than the first supply voltage. During the operation of the level converter 300, the pull-up circuit 416 can control a state of the latch circuit 424 based on the voltage signal 302 in the first range when the second voltage range is negative. The pull-up circuit 416 can be configured to control the state of the latch circuit 424 by supplying a pull-up signal 426 to an input terminal 428 of the latch circuit 424 and / or by supplying a pull-up signal 430 to an input terminal 432 of the latch circuit 424. Each of the pull-up signals 426, 430 can be current pulses. For example, one of the pull-up signals 426, 430 can be a set pulse for the latch circuit 424, and the other of the pull-up signals 426, 430 can be a reset pulse for the latch circuit 424. During operation of the level converter 300, the pull-down circuit 420 can control the state of the latch circuit 424 based on the voltage signal 302 in the first range when the second voltage range is positive. The pull-down circuit 420 can be configured to control the state of the latch circuit 424 by supplying a pull-down signal 434 to the input terminal 428 of the latch circuit 424 and / or by supplying a pull-down signal 436 to the input terminal 432 of the latch circuit 424. Each of the pull-down signals 434, 436 can be current pulses. For example, one of the pull-down signals 434, 436 can be a set pulse for the latch circuit 424, and the other of the pull-down signals 434, 436 can be a reset pulse for the latch circuit 424. It is understood that the pull-down signal 434 is the same signal as the pull-up signal 426, and the pull-down signal 436 is the same signal as the previously described pull-up signal 430. In Fig. 4, the signals at the anodes of diodes 400 and 402 are the pull-up signals, and those at the cathodes of diodes 404 and 406 are the pull-down signals. The signals can be referred to as "high-frequency oscillation signals" because they could become negative or positive relative to the output region (unless protected by cascodes). For example, vHiSwingM could go to approximately vssFly-0.7 V when vssFly is high (e.g., 5 V) and vss is low (e.g., 0 V). Then, the off-pulse current through diode 412 is drawn from the parasitic drain-bulk diode of the n-MOS in inverter 429. When the latch switches, this n-MOS is turned on, and part of the current through diode 412 comes from the n-MOS channel. Each of the two signals can also be referred to by the reference symbols 428, 432 (referring to the latch input terminals 428, 432) when they are referred to as latch input signals. In the present embodiment, the pull-up circuit 416 serves as a pull-up pulse generator, and the pull-down circuit 420 serves as a pull-down pulse generator. Pull-up and pull-down pulse generators are known to those skilled in the art and can be used to trigger the state change at the latch 424. In the present example, the level of the output area (which is the second area) during the pulse is known. If the output area is negative, the "flyLow" signal is activated, and the pull-up circuit 416 acts; if the output area is positive, the "flyHigh" signal is activated, resulting in a pulse from the pull-down circuit 420. If it is not known whether the second voltage range is positive, negative, or whether it experiences a transient during the setting and resetting process, switch-on pulses can be generated simultaneously. Turn-on pulses can be generated by either the pull-up or pull-down pulse generator when the input has a rising edge, in order to set the latch. Turn-off pulses can be generated by either pulse generator to reset the latch. In a specific embodiment, the input should not change during the turn-on and turn-off pulses, and thus these pulses are not interrupted from the input side. Only when the output changes from positive to negative or vice versa can the diodes interrupt the turn-on and turn-off (current) pulses. In further embodiments, a constant pull-up signal or a constant pull-down signal can be used (for example, instead of pulses, current can flow continuously in the direction of the latch circuit 424). In the present embodiment, the output circuit 306 includes a common-mode rejection circuit 438 coupled to the latch circuit 424, wherein the voltage signal 302 in the second region is provided by the latch circuit 424 via the common-mode rejection circuit 438. Common-mode rejection output stages, such as the common-mode rejection circuit 438, are known to those skilled in the art and can be used to suppress current pulses that can be generated by capacitive coupling when the flying region jumps up or down. In the present example, the input circuit 304 further includes an LV level shifter 440 for separating the voltage signal 302 in the first region into differential signals q_LSO, qn_LSO, where qn_LSO is the inverse of q_LSO. The voltage signal 302 in the first region is provided to the pull-up circuit 416 and the pull-down circuit 420 as the differential signals q_LSO, qn_LSO. Furthermore, the voltage signal 302 in the second region is output by the output circuit 306 as differential signals o, o_n, where o_n is the inverse of o. In a specific embodiment, the cascodes can be separated from the rectifier elements. In a specific embodiment, a multiple pn junction element, such as a thyristor or a variable-base-voltage npn transistor, can be used as the cascode. Fig. 5 is a schematic representation of a specific embodiment of the level converter 300 according to a third embodiment of the present disclosure. In the present embodiment, the cross-coupled inverter pair contains 425 resistors R0, R1. In the present embodiment, the level converter contains 300 cascode circuits 500, 502. The cascode circuit 500 contains cascode transistors 504, 506 and the cascode circuit 502 contains cascode transistors 508, 510. Cascode transistors are well known to those skilled in the art. Cascode transistors can protect the 424 latch circuit and the output stages from overvoltages. Further embodiments using cascode transistors can employ additional circuitry to operate at low supply voltages. The function of the cascode transistors is separate from the rectifier elements. In the present embodiment, the common-mode rejection circuit contains 438 transistors T1, T2, T3, T4, T5, T6, T7, T8. In the present embodiment, the protection circuit 308 includes the diodes 408, 410, 412, 414. It is understood that in further embodiments one or more of the diodes may be implemented using a different rectifier element, as understood by those skilled in the art. As previously discussed, the rectifier elements provide reverse current protection and safeguard critical transitions in case the flying voltage output goes in the wrong direction (since without the rectifier elements, the parasitic diodes in the cascode transistors and in the pulse generator transistors would turn on). The reverse current protection function is not dependent on the bidirectional characteristic of the 300 level shifter and can therefore be used in any type of level shifter with a pull-down or pull-up path that is susceptible to reverse current. In the present embodiment, the diode 408 is coupled to the input terminal 428 of the latch circuit 424 and the diode 412; and the diode 410 is coupled to the input terminal 432 of the latch circuit 424 and the diode 414. The pull-up circuit 416 is configured to supply the pull-up signal 426 to the input terminal 428 via diode 408; the pull-up circuit 416 is configured to supply the pull-up signal 430 to the input terminal 432 via diode 410; the pull-down circuit 420 is configured to supply the pull-down signal 434 to the input terminal 428 via diode 412; and the pull-down circuit 420 is configured to supply the pull-down signal 436 to the input terminal 432 via diode 414. As discussed previously, it is understood that the pull-down signal 434 is the same signal as the pull-up signal 426, and the pull-down signal 436 is the same signal as the pull-up signal 430. In Fig. 5, the signals at the anodes of diodes 400 and 402 are the pull-up signals, and those at the cathodes of diodes 404 and 406 are the pull-down signals. The signals can be described as "high-frequency oscillation signals" because they could become negative or positive relative to the output region (unless protected by cascodes). In the present embodiment, the pull-up circuit 416 includes a pull-up switch 512 coupled to the diode 408 and a pull-up switch 514 coupled to the diode 410. In the present embodiment, the pull-down circuit 420 includes a pull-down switch 516 coupled to the diode 412 and a pull-down switch 518 coupled to the diode 414. One or more of the pull-up switches 512, 514 and the pull-down switches 516, 518 may contain transistors such as MOSFETs. The pull-up circuit 416 can further include an inverting AND gate 520 configured to receive the voltage signal 302 in the first region and an indicator signal flyLow. The indicator signal flyLow can indicate when the second region is negative. For example, the indicator signal flyLow can be high when the second region is negative and low when the second region is positive. The inverting AND gate 520 can also be configured to output an inverting AND gate output signal offPuls_n, which is used to control the switching operation of the pull-up switch 514. It is understood that the on and off pulses do not originate directly from the NAND gates 520, 524, or the inverters 522 and 526. The pulses coming from these logic gates can be as long as the pulses at the input "in". (The voltage signal 302 in the first voltage range can have frequencies in the range of a few MHz in a specific embodiment, and the interval between two edges of the voltage signal 302 in the first voltage range can be much more than 10 ns. In a specific embodiment, the pulses can have durations of less than 10 ns (to ensure that the on / off pulses are never interrupted by input changes). Pulse generator circuits 528a, 528b, 528c, 528d (which can be monostable multivibrators) generate the pulses at the edges of their inputs.As can be seen in the symbol for the pulse generator circuits 528a -528d on the schematic diagram, a pulse can only be generated on the rising edge of the input of the pulse generator 528a -528d. The pull-up circuit 416 can further include an inverter 522 configured to receive the inverting AND gate output signal offPuls_n and provide an inverted version of the signal, which is the inverting AND gate output signal onPuls_n, to control the switching operation of the pull-up switch 512. The pull-down circuit 420 can further include an inverting AND gate 524 configured to receive the voltage signal 302 in the first region and an indicator signal flyHigh. The indicator signal flyHigh can indicate when the second region is positive. For example, the indicator signal flyHigh can be high when the second region is positive and low when the second region is negative. The inverting AND gate 524 can further be configured to output an inverting AND gate output signal onPuls, which is used to control the switching operation of the pull-down switch 518. The pull-down circuit 420 can further include an inverter 526 configured to receive the inverting AND gate output signal onPuls and to provide an inverted version of the signal, which is the inverting AND gate output signal offPuls, to control the switching operation of the pull-down switch 516. The present embodiment uses set and reset pulses at the input region, which invert the cross-coupled inverter pair 425 with current pulses. In the present embodiment, the rectifier elements (provided by the diodes 408, 410, 412, 414) couple the cascode transistors 504, 506, 508, 510 of the latch circuit 424 with the pull-up and pull-down pulse generators 416, 420. Preferably, the rectifier elements ensure that the parasitic transitions do not impair the functionality of the level shifter 300. Further embodiments may include circuits to protect critical transitions from parasitic bipolars being switched on. For example, specific embodiments may limit the currents when parasitic bipolars with series resistors are switched on. Fig. 6 is a schematic representation of a specific embodiment of the level converter 300 according to a fourth embodiment of the present disclosure. The present embodiment shares features with the level converter 114 of Fig. 1B by adding the protection circuit 308, which includes rectifier elements 600, 602, wherein the rectifier element 600 includes a diode 604 and the rectifier element 602 includes a diode 606. In the present embodiment, the input circuit 304 includes the pull-up circuit 416, and the output circuit 306 includes the pull-down circuit 420. The pull-up circuit 416 is coupled to the pull-down circuit 420 via the protection circuit 308. The protection circuit 308 is configured to prevent reverse current flow from the pull-down circuit 420 to the pull-up circuit 416, thereby preventing reverse current flow between the input circuit 304 and the output circuit 306. It is understood that in a further embodiment the input circuit 304 may contain the pull-down circuit 420 and the output circuit 306 may contain the pull-up circuit 416. In the present embodiment, both the first and second stress ranges can be regular ranges (since they are both non-flying stress ranges). It is understood that in embodiments of the present disclosure, a constant current flow can occur, and the inclusion of cascodes, for example as shown in Figs. 5 and 6, prevents a permanent current flow. The following example relates to a specific embodiment of the level shifter 300 of Fig. 6: 1. P-MOS 42 switches on. 2. Zener diode 61 and cascodes conduct n-MOS. 3. Node 62 is pulled high, so that n-MOS 47 is switched on. 4. Node 64 goes low (to voltage Vssls) and n-MOS 44 switches off. 5. Node 62 goes high until the cascode 43 switches off and no current flows except for leakage currents. Due to this leakage current, Node 62 could be slightly below Vddls, approximately at the threshold of the cascode 43. Fig. 7 is a schematic representation of a power converter system 700 comprising the level converter 300 and a circuit breaker 702 according to a fifth embodiment of the present disclosure. It is understood that the level converter 300 can be implemented using one of the specific embodiments described herein, as understood by a person skilled in the art. It is understood that the schematic representation shown in Fig. 7 can be considered a power converter subsystem, wherein the full power converter system comprises additional components for power conversion. In this example, the circuit breaker 702 is configured to operate in the second voltage range. The level shifter 300 is configured to convert the voltage signal 302 from the first voltage range to the second voltage range before the voltage signal 302 is supplied to the circuit breaker 702. The voltage signal 302 can, for example, be a control signal used to drive the switching operation of the circuit breaker 702, with the level shifter 300 being used to convert the voltage signal 302 from one voltage range to the voltage range of the circuit breaker 702, thus enabling the circuit breaker 702 to be controlled using the voltage signal 302. Fig. 8 is a graph showing the relationship between the first stress range and examples of the second stress range. The supply voltages of the input range VS1-VS2 and the output range (VS3-VS4) can always be positive and can be constant but unequal. It is understood that in some of the specific embodiments of the present disclosure VS1 is referred to as vbat and VS2 is referred to as vss or GND in some of the specific embodiments of the present disclosure, so that VS1-VS2 can be written as vbat-vss or vbat-GND. It is understood that in some of the specific embodiments of the present disclosure VS3 is referred to as vddFly and VS4 is referred to as vssFly in some of the specific embodiments of the present disclosure, so that VS3-VS4 can be written as vddFly-vssFly. It is understood that in specific embodiments vddFly may be a local supply voltage (local vdd) and vssFly may be a local ground (local GND). It is also understood that VS1 -VS2 can be written as VS2 -VS1 depending on the convention; and VS3 -VS4 can be written as VS4 -VS3. In real-world applications, voltage ranges can vary (for example, during system startup) and are often peaked. This is especially true when they are buffered with small capacitors, which may exhibit real parasitic elements (such as equivalent series resistance (ESR) and equivalent series inductance (ESL)). It is understood that the relationship between VS1 and VS3 or VS4 may not be fixed. For example, VS1 may be greater than VS2, VS3, and VS4; between VS2, VS3, and VS4; or less than VS2, VS3, and VS4. The same applies to the relationship between VS2 and VS3 and VS4. Some possible combinations are shown in Fig. 8. Level-shifting implementations of the present disclosure can operate with input and output domains that can have any relationship to each other. These input / output relationships can change very rapidly over time. For example, in multi-stage DC / DC converters (MLC converters), the ground of one voltage range can jump above or below the other range within nanoseconds or even a few hundred picoseconds when (pairs of) power switches are opened and closed. Here, "above" and "below" do not simply mean several volts above and just one diode voltage below, but several volts, tens, or hundreds of volts above and below a ground voltage vss. It is understood that this is an example with diode conduction at vss. In a case of diode conduction at vdd, the opposite is true. Level-shifting embodiments of the present disclosure can operate as high-voltage level shifters for flying voltage ranges. In some topologies, such as the power stages of multi-stage DC / DC converters (MLCs), the aforementioned flying output voltage ranges can change their ground from above to below the GND of the quiet input range, and vice versa. Embodiments of the present disclosure facilitate this operation in a single level shifter. Embodiments of the present disclosure can also be applied to static level converters in which the high-voltage transistors (HV transistors) that generate the current pulses are permanently switched on and the cascode transistors stop the current pulse when the cross-coupled inverters reverse. Embodiments of the present disclosure can avoid electrical loads at auxiliary voltages. In current practice, level shifters of the signal are often converted to the output region (e.g., negative output voltage Vout) and then back to the flying region (e.g., of a flying capacitor), as described above with reference to Fig. 1A. Furthermore, embodiments of the present disclosure can eliminate wiring connections to auxiliary voltages. Various improvements and modifications can be made to the above without altering the scope of protection of the disclosure. QUOTES INCLUDED IN THE DESCRIPTION This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature WO 2008 / 101548 A1

[0007] US 11695342B2

[0051]

Claims

Level converter for converting a voltage signal from a first voltage range to a second voltage range, comprising: an input circuit configured to receive the voltage signal in the first voltage range; an output circuit configured to output the voltage signal in the second voltage range; and a protection circuit configured to prevent reverse current flow between the input circuit and the output circuit. Level converter according to claim 1, wherein the first voltage range is a floating voltage range and / or the second voltage range is a floating voltage range. Level converter according to claim 1, wherein the input circuit is configured to operate in the first voltage range and the output circuit is configured to operate in the second voltage range. Level converter according to claim 1, wherein: the first voltage range is the voltage range from a first supply voltage to a second supply voltage; and the second voltage range is the voltage range from a third supply voltage to a fourth supply voltage. Level converter according to claim 1, wherein the protection circuit comprises one or more rectifier elements, each of which is configured to prevent a reverse current flow between the input circuit and the output circuit. Level shifter according to claim 1, wherein: the input circuit comprises: a pull-up circuit coupled to the output circuit via a first section of the protection circuit, wherein the first section of the protection circuit is configured to prevent a reverse current flow from the output circuit to the pull-up circuit, thereby preventing a reverse current flow between the input circuit and the output circuit; and / or a pull-down circuit coupled to the output circuit via a second section of the protection circuit, wherein the second section of the protection circuit is configured to prevent a reverse current flow from the pull-down circuit to the output circuit, thereby preventing a reverse current flow between the input circuit and the output circuit. Level shifter according to claim 6, wherein: the output circuit comprises a latch circuit configured to provide the voltage signal in the second voltage range; wherein: the pull-up circuit is coupled to the latch circuit via the first section of the protection circuit, the first section of the protection circuit being configured to prevent reverse current flow from the latch circuit to the pull-up circuit, thereby preventing reverse current flow between the input circuit and the output circuit; and / or the pull-down circuit is coupled to the latch circuit via the second section of the protection circuit, the second section of the protection circuit being configured to prevent reverse current flow from the pull-down circuit to the latch circuit, thereby preventing reverse current flow between the input circuit and the output circuit. Level shifter according to claim 7, wherein: the first voltage range is the voltage range from a first supply voltage to a second supply voltage; the second voltage range is the voltage range from a third supply voltage to a fourth supply voltage; the second voltage range is positive if: i) the fourth supply voltage is greater than the third supply voltage; and / or ii) the second supply voltage is greater than the first supply voltage; and / or iii) the third supply voltage is greater than the first supply voltage; the second voltage range is negative if: i) the second supply voltage is greater than the fourth supply voltage; and / or ii) the first supply voltage is greater than the third supply voltage;and the pull-up circuit is configured to control a state of the latch circuit based on the voltage signal in the first range, as received, when the second voltage range is negative; and the pull-down circuit is configured to control the state of the latch circuit based on the voltage signal in the first range, as received, when the second voltage range is positive. Level converter according to claim 8, wherein: the pull-up circuit is configured to control the state of the latch circuit by supplying a first pull-up signal to a first input terminal of the latch circuit and / or by supplying a second pull-up signal to a second input terminal of the latch circuit; and the pull-down circuit is configured to control the state of the latch circuit by supplying a first pull-down signal to the first input terminal of the latch circuit and / or by supplying a second pull-down signal to the second input terminal of the latch circuit. Level converter according to claim 7 comprising: a first cascode circuit coupled between the first section of the protection circuit and the latch circuit; and a second cascode circuit coupled between the second section of the protection circuit and the latch circuit. Level shifter according to claim 9, wherein: the protection circuit comprises a first rectifier element, a second rectifier element, a third rectifier element, and a fourth rectifier element; each of the first, second, third, and fourth rectifier elements is configured to prevent reverse current flow between the input circuit and the output circuit; the first rectifier element is coupled to the first input terminal of the latch circuit and the third rectifier element; the second rectifier element is coupled to the second input terminal of the latch circuit and the fourth rectifier element; the pull-up circuit is configured to supply the first pull-up signal to the first input terminal via the first rectifier element; the pull-up circuit is configured to supply the second pull-up signal to the second input terminal via the second rectifier element;The pull-down circuit is configured to deliver the first pull-down signal to the first input terminal via the third rectifier element; and the pull-down circuit is configured to deliver the second pull-down signal to the second input terminal via the fourth rectifier element. Level shifter according to claim 1, wherein: the input circuit has a pull-up circuit and the output circuit has a pull-down circuit; or the input circuit has the pull-down circuit and the output circuit has the pull-up circuit; and the pull-up circuit is coupled to the pull-down circuit via the protection circuit, wherein the protection circuit is configured to prevent a reverse current flow from the pull-down circuit to the pull-up circuit, thereby preventing a reverse current flow between the input circuit and the output circuit. Power converter system comprising: a level converter for converting a voltage signal from a first voltage range to a second voltage range, comprising: i) an input circuit configured to receive the voltage signal in the first voltage range; ii) an output circuit configured to output the voltage signal in the second voltage range; and iii) a protection circuit configured to prevent reverse current flow between the input circuit and the output circuit; and a power switch configured to operate in the second voltage range; wherein: the level converter is configured to convert the voltage signal from the first voltage range to the second voltage range before the voltage signal is supplied to the power switch. A method for converting a voltage signal from a first voltage range to a second voltage range using a level shifter, wherein the method comprises: receiving the voltage signal in the first voltage range using an input circuit; outputting the voltage signal in the second voltage range using an output circuit; and preventing reverse current flow between the input circuit and the output circuit using a protection circuit.

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