Storage array, storage cell and data reading and writing method thereof

Abstract

The present disclosure provides a storage array, a storage cell and a method for reading and writing data thereof. By setting two storage nodes in each storage cell of the storage array of the MRAM, when one storage node in the storage cell fails, the other storage node in the storage cell can still be used to write data and read data, thereby extending the endurance and retention of the storage cell, further improving the service life of the storage cell, and increasing the stability of the MRAM.

Description

Technical Field

[0001] The present disclosure relates to the technical field of memories, and in particular, to a storage array, a storage cell, and a method for reading and writing data thereof. Background Art

[0002] Magnetic Random Access Memory (MRAM) is a non-volatile memory, which has characteristics such as relatively high read and write speeds, relatively high integration levels, and a relatively large number of repeated read and write times, and is widely used in current devices such as computers.

[0003] In the prior art, an MRAM includes a storage array composed of a plurality of storage cells, and each storage cell can perform a read operation or a write operation of data ("0" or "1") through its Magnetic Tunnel Junction (MTJ).

[0004] However, in the prior art, due to the easy damage and short effective life of the magnetic tunnel junctions in the storage cells, the stability of the MRAM is poor. Summary of the Invention

[0005] The present disclosure provides a storage array, a storage cell, and a method for reading and writing data thereof to solve the technical problem of poor stability of the MRAM.

[0006] In a first aspect of the present disclosure, a storage cell is provided, including: a first storage node, the first storage node is respectively connected to a first end of a transistor and a first bit line; a second storage node, the second storage node is respectively connected to the first end of the transistor and a second bit line; the transistor, a second end of the transistor is connected to a source line, and a third end of the transistor is connected to a word line.

[0007] In an embodiment of the first aspect of the present disclosure, the first storage node and the second storage node are arranged in parallel.

[0008] In an embodiment of the first aspect of the present disclosure, the first storage node includes a first magnetic tunnel junction, a first end of the first magnetic tunnel junction is connected to the first bit line, a second end of the first magnetic tunnel junction is connected to the first end of the transistor, and the first magnetic tunnel junction has a first magnetic characteristic; the second storage node includes a second magnetic tunnel junction, a first end of the second magnetic tunnel junction is connected to the second bit line, a second end of the second magnetic tunnel junction is connected to the first end of the transistor, and the second magnetic tunnel junction has a second magnetic characteristic; the first magnetic characteristic is different from the second magnetic characteristic.

[0009] In an embodiment of the first aspect of the present disclosure, the first magnetic tunnel junction and / or the second magnetic tunnel junction includes: a bottom electrode layer, a free layer, a tunnel barrier layer, a reference layer, and a top electrode layer.

[0010] In an embodiment of the first aspect of the present disclosure, the storage unit further includes: a switching structure; the switching structure is configured to control its first end and third end to conduct, or control its second end and third end to conduct.

[0011] The second aspect of the present disclosure provides a storage array, including: m source lines, m word lines, n first bit lines and n second bit lines, and m rows and n columns of storage units, wherein the storage unit is the storage unit according to any one of the first aspect of the present disclosure, and m and n are positive integers; each of the storage units located in the same row is connected to the same word line, each of the storage units located in the same row is connected to the same source line, the first storage node of each of the storage units located in the same column is connected to the same first bit line, and the second storage node of each of the storage units located in the same column is connected to the same second bit line.

[0012] In an embodiment of the second aspect of the present disclosure, the first bit line and the second bit line are arranged in parallel.

[0013] The third aspect of the present disclosure provides a method for reading and writing data of a storage unit, including: writing data or reading data from the storage unit according to any one of the first aspect of the present disclosure.

[0014] In an embodiment of the third aspect of the present disclosure, the writing data or reading data from the storage unit includes: controlling the first storage node to write data or read data through the first bit line, the source line, the word line, and the transistor.

[0015] In an embodiment of the third aspect of the present disclosure, the writing data or reading data from the storage unit includes: controlling the second storage node to write data or read data through the second bit line, the source line, the word line, and the transistor.

[0016] In an embodiment of the third aspect of the present disclosure, the writing data or reading data from the storage unit includes: determining whether the first storage node fails; if so, writing data or reading data from the second storage node; if not, writing data or reading data from the first storage node.

[0017] In an embodiment of the third aspect of the present disclosure, the determining whether the first storage node fails includes: determining whether the first storage node fails according to the read-write status flag of the first storage node.

[0018] In an embodiment of the third aspect of the present disclosure, the data writing or data reading of the storage unit includes: determining a first magnetic characteristic of the first storage node, a second magnetic characteristic of the second storage node, and a target magnetic characteristic required for data writing or data reading of the storage unit; when the target magnetic characteristic is the same as the first magnetic characteristic, performing data writing or data reading on the first storage node; when the target magnetic characteristic is the same as the second magnetic characteristic, performing data writing or data reading on the second storage node.

[0019] The fourth aspect of the present disclosure provides a data reading and writing device for a storage unit, including: a writing module configured to write data to the storage unit according to any one of the first aspects of the present disclosure; a reading module configured to read data from the storage unit according to any one of the first aspects of the present disclosure.

[0020] In an embodiment of the fourth aspect of the present disclosure, the writing module is specifically configured to control the first storage node to perform data writing through the first bit line, the source line, the word line, and the transistor, and control the second storage node to perform data writing through the second bit line, the source line, the word line, and the transistor; the reading module is specifically configured to control the first storage node to perform data reading through the first bit line, the source line, the word line, and the transistor, and control the second storage node to perform data reading through the second bit line, the source line, the word line, and the transistor.

[0021] In summary, the storage array, storage unit, and data reading and writing method provided by the present disclosure set two storage nodes in each storage unit of the MRAM storage array, so that when one storage node in the storage unit fails, the other storage node in the storage unit can still be used to write and read data, thereby extending the durability and retention of the storage unit, and further improving the service life of the storage unit, ensuring that the normal operation of the entire MRAM storage array will not be affected by the failure of any one storage node in a storage unit, and therefore the stability of the MRAM can also be increased. Description of the Drawings

[0022] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the following drawings are only some embodiments of the present disclosure. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0023] Figure 1 It is a schematic structural diagram of a storage array of an MRAM;

[0024] Figure 2 It is a schematic structural diagram of a storage cell of an MRAM;

[0025] Figure 3 It is a schematic structural diagram of an embodiment of a storage array of an MRAM provided by the present disclosure;

[0026] Figure 4 It is a schematic structural diagram of an embodiment of a storage cell of an MRAM provided by the present disclosure;

[0027] Figure 5 It is a schematic diagram of the control timing when the storage cell provided by the present disclosure writes and reads data to / from the first storage node;

[0028] Figure 6 It is a schematic diagram of the control timing when the storage cell provided by the present disclosure writes and reads data to / from the second storage node;

[0029] Figure 7 It is a schematic flow diagram of an embodiment of the data reading and writing method of the storage cell provided by the present disclosure;

[0030] Figure 8 It is a schematic structural diagram of an embodiment of a storage cell of an MRAM provided by the present disclosure;

[0031] Figure 9 It is a schematic diagram of the control timing when the storage cell provided by the present disclosure writes and reads data to / from the first storage node or the second storage node;

[0032] Figure 10 It is a schematic structural diagram of a data reading and writing device of a storage cell provided by the present disclosure. Detailed implementation manners

[0033] Next, the technical solutions in the embodiments of the present disclosure will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present disclosure without creative efforts shall fall within the protection scope of the present disclosure.

[0034] The terms "first", "second", "third", "fourth", etc. (if any) in the description, claims and the above accompanying drawings of the present disclosure are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged under appropriate circumstances so that the embodiments of the present disclosure described herein can be implemented in an order different from those illustrated or described herein. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device comprising a series of steps or units does not necessarily limit to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these process, method, product or device.

[0035] Figure 1 It is a schematic structural diagram of a storage array of an MRAM, showing a schematic diagram of the basic composition structure of a Magnetic Random Access Memory (MRAM for short). Among them, the storage array of the MRAM includes storage cells distributed in rows and columns, which are sequentially denoted as P11, P12, P13... etc. according to the row and column distribution rules of the storage cells. In each storage cell, the Magnetic Tunnel Junction (MTJ for short) is specifically used for reading, writing and storing information ("0" or "1"). In some embodiments, the magnetic tunnel junction includes a bottom electrode layer, a free layer, a tunnel barrier layer, a reference layer and a top electrode layer.

[0036] Figure 2 It is a schematic structural diagram of a storage cell of an MRAM, as Figure 2 shown Figure 1 in the storage array shown, the storage cell includes a magnetic tunnel junction MTJ and an N-Metal-Oxide-Semiconductor (NMOS for short). The NMOS can be used to control the current flowing through the magnetic tunnel junction. Among them, when writing to or reading from the MTJ is required, the NMOS is turned on. The word line (WL) is connected to the gate of the NMOS, the source of the NMOS is connected to the source line (SL), the drain of the NMOS is connected to one end of the magnetic tunnel junction (which can be the bottom electrode layer or the top electrode layer of the magnetic tunnel junction), and the bit line (BL) is connected to the other end of the magnetic tunnel junction. The read operation or write operation on the magnetic tunnel junction is jointly performed by the levels of the word line, bit line and select line.

[0037] However, when adopting Figure 1 and Figure 2In the MRAM with the structure shown, since the magnetic tunnel junctions in the storage cells are easily damaged and have a relatively short effective lifespan, when a magnetic tunnel junction in a storage cell fails and cannot read or write data, it will affect the normal operation of the entire MRAM storage array, greatly reducing the stability of the MRAM.

[0038] Therefore, the embodiments of the present disclosure provide a storage array of an MRAM, a storage cell, and a data reading and writing method thereof. By arranging two magnetic tunnel junctions in the storage cell of the MRAM, even if the magnetic tunnel junction in the storage cell fails and cannot read or write data, data can still be read and written through the other magnetic tunnel junction in the storage cell, thereby improving the endurance and retention of the storage cell, ensuring that the normal operation of the entire MRAM storage array will not be affected by the failure of the magnetic tunnel junction in one storage cell, and thus improving the stability of the MRAM.

[0039] The technical solutions of the present disclosure will be described in detail below with specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments.

[0040] Figure 3 It is a schematic structural diagram of an embodiment of a storage array of an MRAM provided by the present disclosure. As Figure 3 shown, the storage array includes: m source lines SL horizontally distributed in the figure, denoted as SL1, SL2, SL3..., m word lines WL horizontally distributed in the figure, denoted as WL1, WL2, WL3..., and n first bit lines BL vertically distributed in the figure, denoted as BL11, BL21, BL31..., n second bit lines BL, denoted as BL12, BL22, BL32..., and storage cells distributed in m rows and n columns, denoted as P11, P12, P13...P21, P22, P23...P31, P32, P33.... m and n are positive integers.

[0041] In Figure 3 the shown embodiment, each storage cell in the same row is respectively connected to the same word line WL. For example, the storage cells P11, P12, P13... in the first row are connected to the word line WL1, and so on; each storage cell in the same row is respectively connected to the same source line SL. For example, the storage cells P11, P12, P13... in the first row are connected to the word line SL1, and so on; each storage cell in the same column is respectively connected to the first bit line and the second bit line. For example, the storage cells P11, P21, P31... in the first column are respectively connected to the first bit line BL11, and the storage cells P11, P21, P31... in the first column are respectively connected to the second bit line BL12, and so on.

[0042] In some embodiments, such as Figure 3 In the storage array shown, the first bit line and the second bit line to which the storage cells in the same column are respectively connected are connected in parallel. For example, the first bit line BL11 and the second bit line BL12 to which the storage cells P11, P21, P31... in the first column are respectively connected are connected in parallel, and the first bit line BL21 and the second bit line BL22 to which the storage cells P12, P22, P32... in the second column are respectively connected are connected in parallel.

[0043] Figure 4 FIG. is a schematic structural diagram of an embodiment of a storage cell of an MRAM provided by the present disclosure, showing the structure of any storage cell in the storage array as shown in Figure 3 In the storage array shown in Figure 4 In [reference], taking the storage cell P11 in the first row and the first column of the storage array in Figure 3 as an example, the storage cell 10 provided in this embodiment includes: a first storage node 101, a second storage node 102, and a transistor 103.

[0044] In some embodiments, the first storage node 101 may be a magnetic tunnel junction, denoted as the first magnetic tunnel junction. The first end of the first magnetic tunnel junction is connected to the first bit line BL11, and the second end of the first magnetic tunnel junction is connected to the first end of the transistor 103. The second storage node 102 may be a magnetic tunnel junction, denoted as the second magnetic tunnel junction. The first end of the second magnetic tunnel junction is connected to the second bit line BL12, and the second end of the second magnetic tunnel junction is connected to the first end of the transistor 103. The first end of the transistor 103 is simultaneously connected to the second end of the first magnetic tunnel junction and the second end of the second magnetic tunnel junction. The second end of the transistor 103 is connected to the source line SL1, and the third end of the transistor 103 is connected to the word line WL1.

[0045] In some embodiments, the first magnetic tunnel junction and the second magnetic tunnel junction are arranged in parallel, and the first magnetic tunnel junction and the second magnetic tunnel junction can work independently of each other and are not affected by the other magnetic tunnel junction.

[0046] In some embodiments, the structure of the magnetic tunnel junction may sequentially include: a bottom electrode layer, a free layer, a tunnel barrier layer, a reference layer, and a top electrode layer. Among them, the first end of the first magnetic tunnel junction / second magnetic tunnel junction may be the bottom electrode layer, and the second end of the first magnetic tunnel junction / second magnetic tunnel junction may be the top electrode layer; or, the first end of the first magnetic tunnel junction / second magnetic tunnel junction may be the top electrode layer, and the second end of the first magnetic tunnel junction / second magnetic tunnel junction may be the bottom electrode layer.

[0047] In some embodiments, the magnetic properties of the first magnetic tunnel junction and the second magnetic tunnel junction are the same. The magnetic properties may specifically be magnetic anisotropy. When the first magnetic tunnel junction and the second magnetic tunnel junction are arranged in parallel, the storage unit can write or read data to or from any one of the first magnetic tunnel junction and the second magnetic tunnel junction.

[0048] In some embodiments, the magnetic properties of the first magnetic tunnel junction and the second magnetic tunnel junction are different. At this time, the storage unit can determine whether to write or read data to or from any one of the first magnetic tunnel junction and the second magnetic tunnel junction according to its operating parameters such as the switching current.

[0049] For example, the first magnetic tunnel junction and the second magnetic tunnel junction can be made to have different magnetic properties by setting the first magnetic tunnel junction and the second magnetic tunnel junction to different sizes and / or changing the magnetic anisotropy of the read layer.

[0050] In some embodiments, Figure 3 each storage unit in the storage array shown can adopt the structure shown in Figure 4 At this time, the first storage nodes of each storage unit in the same column of the storage array are connected to the same first bit line. For example, the first storage nodes of each storage unit in the first column of storage units P11, P21, P31... are respectively connected to the first bit line BL11, and the second storage nodes of each storage unit in the first column of storage units P11, P21, P31... are respectively connected to the second bit line BL12, and so on.

[0051] Based on the storage unit 10 shown in Figure 4 which includes two storage nodes, when writing or reading data to or from the storage unit 10, either of the storage nodes can be used.

[0052] For example, Figure 5 is a schematic diagram of the control timing when the storage unit provided in the present disclosure writes and reads data to and from the first storage node. Among them, when the storage unit writes or reads data to the first storage node, the second bit line BL12 connected to the second storage node needs to be kept at a low level, so that the second storage node is in a floating state and will not write or read data.

[0053] Further, in combination with Figure 4For the storage cell shown, when the first bit line BL11 connected to the first storage node is at a high level, the word line WL1 connected to the transistor 103 is at a high level, and the source line SL1 is at a low level, an operation of writing data 1 (WRITE1) to the first storage node of this storage cell is performed; when the first bit line BL11 connected to the first storage node is at a low level, the word line WL1 connected to the transistor 103 is at a high level, and the source line SL1 is at a high level, an operation of writing data 0 (WRITE0) to the first storage node of this storage cell is performed; when the first bit line BL11 connected to the first storage node is at a high level, the word line WL1 connected to the transistor 103 is at a high level, and the source line SL1 is at a low level, an operation of reading data (READ) from the first storage node of this storage cell is performed.

[0054] Figure 6 The figure is a schematic diagram of the control timing when the storage cell provided by the present disclosure writes data to and reads data from the second storage node. Among them, when the storage cell writes data to or reads data from the second storage node, the first bit line BL11 connected to the first storage node needs to be kept at a low level, so that the first storage node is in a floating state and no data writing or reading will occur.

[0055] Furthermore, in combination with Figure 4 For the storage cell shown, when the second bit line BL12 connected to the second storage node is at a high level, the word line WL1 connected to the transistor 103 is at a high level, and the source line SL1 is at a low level, an operation of writing data 1 (WRITE1) to the second storage node of this storage cell is performed; when the second bit line BL12 connected to the second storage node is at a low level, the word line WL1 connected to the transistor 103 is at a high level, and the source line SL1 is at a high level, an operation of writing data 0 (WRITE0) to the second storage node of this storage cell is performed; when the second bit line BL12 connected to the second storage node is at a high level, the word line WL1 connected to the transistor 103 is at a high level, and the source line SL1 is at a low level, an operation of reading data (READ) from the second storage node of this storage cell is performed.

[0056] In summary, for the storage array and storage cell of the MRAM provided in this embodiment, by setting two storage nodes in each storage cell in the storage array, when one storage node in the storage cell fails, the storage cell can still use the other storage node to write data and read data, thereby extending the durability and retention of the storage cell, and further improving the service life, ensuring that the normal operation of the entire MRAM storage array will not be affected by the failure of any storage node in one storage cell. Therefore, the stability of the MRAM can also be increased.

[0057] The present disclosure also provides a method for reading and writing data of a storage unit, which can be used to write or read data to / from the storage unit provided in any of the foregoing embodiments of the present disclosure.

[0058] In some embodiments, taking the Figure 4 shown storage unit as an example, writing or reading data to / from the storage unit includes: controlling a first storage node to write or read data through a first bit line BL11, a source line SL1, and a word line WL1 connected to the storage unit. Alternatively, writing or reading data to / from the storage unit includes: controlling a second storage node to write or read data through a second bit line BL12, a source line SL1, and a word line WL1 connected to the storage unit.

[0059] Figure 7 is a schematic flowchart of an embodiment of the method for reading and writing data of the storage unit provided by the present disclosure, which is used to perform a data writing operation or a data reading operation on a first storage node or a second storage node in the Figure 4 shown storage unit. As shown in Figure 7 the execution subject of the shown method can be any controller, control device, chip, etc. with relevant processing capabilities. Taking the controller of the MRAM storage array as an example of the execution subject, before the controller writes data to or reads data from the storage unit, it first determines a first storage node or a second storage node in the storage unit for subsequent operations through S101. When it is determined in S101 to perform subsequent operations on the first storage node in the storage unit, the operation of writing or reading data to / from the first storage node is performed through S102, and when it is determined in S101 to perform subsequent operations on the second storage node in the storage unit, the operation of writing or reading data to / from the second storage node is performed through S103.

[0060] In summary, for the reading and writing method of the storage unit provided in this embodiment, when the controller reads or writes data to the storage unit in the storage array, it first determines one of the two storage nodes of the storage unit, and then performs the operation of writing or reading data to the determined storage node. When one storage node in the storage unit fails, the controller can still control the other storage node of the storage unit to write and read data, ensuring that the controller can normally read and write data without affecting its normal working process, and increasing the stability of the controller when writing and reading data in the MRAM.

[0061] In some embodiments, in Figure 7In S101 shown above, the controller specifically determines whether to perform subsequent operations on the first storage node or the second storage node based on whether the first storage node fails. Here, in this embodiment, the magnetic properties of the first magnetic tunnel junction in the first storage node and the second magnetic tunnel junction in the second storage node can be set to be the same. At this time, the functions and operating parameters of the first storage node and the second storage node are the same, and they can be set as redundant to each other. For example, it can be default to perform operations of writing data or reading data on the first storage unit in the storage cell. When it is determined in S101 that the first storage node fails, then determine to perform operations of writing data or reading data on the second storage unit in the storage cell. Among them, the controller can specifically determine whether the first storage node fails according to the read / write status identifier of the first storage node. The read / write status identifier can be used to indicate whether the first storage node fails. When the first storage node fails, operations of writing data and reading data cannot be performed.

[0062] In some other embodiments, when the magnetic properties of the first magnetic tunnel junction and the second magnetic tunnel junction are the same, the first storage node and the second storage node can also be cyclically used for operations. For example, within a preset time period, operations of writing data or reading data can be performed on the first storage node in the storage cell, and within the next preset time period, operations of writing data or reading data can be performed on the second storage node in the storage cell, taking this as a cycle, so as to prevent frequent data reading or data writing on one storage node, and further reduce the probability of failure of this one storage node caused by frequent use. During the above cycle process, when a storage node of the storage cell fails, the cycle of the preset time period can be stopped, and subsequently, data reading or data writing will be performed on the storage node that has not failed in the storage cell.

[0063] In some embodiments, for the entire storage array of the MRAM, the controller can record the storage nodes corresponding to each storage cell in the storage array it controls in the form of identification information in Table 1 below. For example, the identification information MTJx in the first row and the first column of Table 1 is used to indicate that the storage cell P11 in the storage array uses the xth storage node to perform operations of writing data or reading data. When x is 1, MTJ1 is used to indicate the first storage node of the storage cell P11; when x is 2, MTJ2 is used to indicate the second storage node of the storage cell P11, and so on. So that before the controller writes data or reads data for each storage cell in the storage array, it first determines the first storage node or the second storage node of this storage cell through Table 1, and then writes data or reads data on the determined storage node in the storage cell.

[0064] Table 1

[0065] P11(MTJx) P12(MTJx) P13(MTJx) … P21(MTJx) P22(MTJx) P23(MTJx) … P31(MTJx) P32(MTJx) P33(MTJx) … … … … …

[0066] In some embodiments, the identification information of each memory cell as shown in Table 1 can be preset; alternatively, it can be specified by the controller of the MRAM or other devices and can be adjusted in real time.

[0067] In some embodiments, in Table 1, each memory cell can be recorded according to its address path, and the corresponding identification information of the memory cell can be recorded.

[0068] In still other embodiments, when the magnetic properties of the first magnetic tunnel junction and the second magnetic tunnel junction are different, such as Figure 7 in S101 described above, the controller can select the first magnetic tunnel junction or the second magnetic tunnel junction with the same magnetic property as the magnetic tunnel junction according to the target magnetic property required for writing or reading by the currently processed memory cell, so as to perform subsequent data writing or data reading operations on the first memory node where the first magnetic tunnel junction is located or the second memory node where the second magnetic tunnel junction is located.

[0069] Exemplarily, when the controller controls the memory cell, if the target magnetic property of the magnetic tunnel junction corresponding to the switching current value that can be provided is the same as the magnetic property of the first magnetic tunnel junction, the controller performs data writing or data reading on the first memory node; and if the target magnetic property is the same as the magnetic property of the second magnetic tunnel junction, the controller performs data writing or data reading on the second memory node.

[0070] Therefore, this embodiment can realize the flexible selection of different memory nodes in the memory cell when the controller controls the memory cell, making the use of the memory cell more intelligent, enriching the usage scenarios of the memory cell, and enabling the memory cell to use a more appropriate memory node for data writing or data reading, improving the working stability and working efficiency of the MRAM.

[0071] In some embodiments, Figure 8 is a schematic structural diagram of an embodiment of a memory cell of the MRAM provided by the present disclosure. In the Figure 8 shown embodiment, on the basis of setting two memory cells in the memory cell 10, the selection of the two memory cells in the memory cell 10 is realized through the switching structure 104. At this time, for the memory array where the memory cell is located, a bit line BL can be set for each column of memory cells to realize the Figure 1 shown memory array structure. For example, as shown in Figure 8 the first end of the first memory cell 101 is connected to the first end a of the switching structure 104, the first end of the second memory cell 102 is connected to the second end b of the switching structure 104, and the third end c of the switching structure 104 is connected to the bit line BL1.

[0072] The switch structure 104 can be used to control the conduction between its first terminal a and third terminal c, enabling the first storage node 101 in the storage cell 10 to perform operations of writing data or reading data; alternatively, the switch structure can be used to control the conduction between its second terminal b and third terminal c, enabling the second storage node 102 in the storage cell 10 to perform operations of writing data or reading data.

[0073] Figure 9 FIG. is a timing diagram for controlling data writing and data reading of the first storage node or the second storage node in the storage cell provided by the present disclosure. Among them, it shows the timing diagram for Figure 8 data writing and data reading of the first storage node or the second storage node therein. When the first terminal a and the third terminal c of the switch structure 104 are conducting, when the bit line BL1 is at a high level, the word line WL1 connected to the transistor 103 is at a high level, and the source line SL1 is at a low level, an operation of writing data 1 (WRITE1) to the first storage node of the storage cell is performed; when the second terminal b and the third terminal c of the switch structure are conducting, the bit line BL1 is at a low level, the word line WL1 connected to the transistor 103 is at a high level, and the source line SL1 is at a high level, an operation of writing data 0 (WRITE0) to the first storage node of the storage cell is performed; when the first bit line BL11 connected to the first storage node is at a high level, the word line WL1 connected to the transistor 103 is at a high level, and the source line SL1 is at a low level, an operation of reading data (READ) from the first storage node of the storage cell is performed.

[0074] In summary, in the storage cell provided in this embodiment, in addition to setting two storage nodes in the storage cell, a switch structure is also provided, such that when one storage node in the storage cell fails, the storage cell can still use the other storage node to write data and read data. The connection between the bit line and one of the storage nodes can be achieved through the switch structure. On the basis of extending the endurance and retention of the storage cell and thus improving the service life and increasing the stability of the MRAM, the structural complexity of the entire MRAM storage array is further reduced, and the layout is more simple and compact.

[0075] In the foregoing embodiments, the data reading and writing methods of the storage cell provided by the present disclosure have been introduced. In order to implement the various functions of the data reading and writing methods of the storage cell provided by the present disclosure, as the execution subject, the controller may include a hardware structure and / or a software module, and implement the above various functions in the form of a hardware structure, a software module, or a combination of a hardware structure and a software module. Whether a certain function among the above various functions is executed in the form of a hardware structure, a software module, or a combination of a hardware structure and a software module depends on the specific application and design constraint conditions of the technical solution.

[0076] For example, Figure 10The structural schematic diagram of a data reading and writing device for a storage unit provided by the present disclosure is as follows Figure 10 As shown, the device 100 includes a writing module 1001 and a reading module 1002. Among them, the writing module 1001 is configured to write data to the storage unit in any embodiment of the present disclosure, and the reading module 1002 is configured to read data from the storage unit in any embodiment of the present disclosure.

[0077] Specifically, for the specific principles and implementation manners of the above steps respectively executed by each module in the data reading and writing device of the storage unit, reference may be made to the description in the data reading and writing method of the storage unit in the foregoing embodiments of the present disclosure, and details will not be repeated here.

[0078] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present disclosure, rather than to limit them; although the present disclosure has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements for some or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present disclosure.

Claims

1. A storage unit, characterized in that, Comprising: A first storage node, the first storage node being connected to a first end of a transistor and a first bit line respectively; A second storage node, the second storage node being connected to the first end of the transistor and a second bit line respectively; The transistor, a second end of the transistor being connected to a source line, and a third end of the transistor being connected to a word line; A controller, the controller being configured to control the storage unit, select a storage node in the storage unit for data writing or reading operations, specifically: when performing data writing or reading operations, first determine one of the two storage nodes of the storage unit, and then perform data writing or reading operations on the determined storage node, such that when one storage node in the storage unit fails, the controller can also control the other storage node of the storage unit for data writing or reading.

2. The memory cell according to claim 1, wherein: The first storage node and the second storage node are arranged in parallel.

3. The storage unit according to claim 1, wherein: The first storage node includes a first magnetic tunnel junction, a first end of the first magnetic tunnel junction being connected to the first bit line, a second end of the first magnetic tunnel junction being connected to the first end of the transistor, and the first magnetic tunnel junction having a first magnetic characteristic; The second storage node includes a second magnetic tunnel junction, a first end of the second magnetic tunnel junction being connected to the second bit line, a second end of the second magnetic tunnel junction being connected to the first end of the transistor, and the second magnetic tunnel junction having a second magnetic characteristic; The first magnetic characteristic is different from the second magnetic characteristic.

4. The storage unit according to claim 3, wherein: The first magnetic tunnel junction and / or the second magnetic tunnel junction includes: a bottom electrode layer, a free layer, a tunnel barrier layer, a reference layer, and a top electrode layer.

5. The storage unit according to claim 1, wherein The first storage node includes a first magnetic tunnel junction, a first end of the first magnetic tunnel junction being connected to the first bit line, a second end of the first magnetic tunnel junction being connected to the first end of the transistor; The second storage node includes a second magnetic tunnel junction, a first end of the second magnetic tunnel junction being connected to the second bit line, a second end of the second magnetic tunnel junction being connected to the first end of the transistor; The first magnetic tunnel junction and the second magnetic tunnel junction have the same magnetic characteristic.

6. A storage array, characterized in that, Comprising: m source lines, m word lines, n first bit lines and n second bit lines, m rows and n columns of storage units, wherein the storage unit is the storage unit according to any one of claims 1 to 5, and m and n are positive integers; Each of the storage units in the same row is connected to the same word line, each of the storage units in the same row is connected to the same source line, the first storage nodes of each of the storage units in the same column are connected to the same first bit line, and the second storage nodes of each of the storage units in the same column are connected to the same second bit line.

7. The storage array according to claim 6, wherein: The first bit line and the second bit line are arranged in parallel.

8. A method for reading and writing data of a storage unit, characterized in that Comprising: Performing data writing or data reading on the storage unit according to any one of claims 1 to 5.

9. The method according to claim 8, wherein Performing data writing or data reading on the storage unit includes: controlling the first storage node to perform data writing or data reading through the first bit line, the source line, and the word line.

10. The method according to claim 8, wherein Performing data writing or data reading on the storage unit includes: controlling the second storage node to perform data writing or data reading through the second bit line, the source line, and the word line.

11. The method according to claim 9 or 10, characterized in that Performing data writing or data reading on the storage unit includes: Determining whether the first storage node fails; If so, performing data writing or data reading on the second storage node; If not, performing data writing or data reading on the first storage node.

12. The method according to claim 11, wherein Determining whether the first storage node fails includes: determining whether the first storage node fails according to the read-write status identifier of the first storage node.

13. The method according to claim 9 or 10, characterized in that, Performing data writing or data reading on the storage unit includes: Determining the first magnetic characteristic of the first storage node, the second magnetic characteristic of the second storage node, and the target magnetic characteristic required for data writing or data reading of the storage unit; When the target magnetic characteristic is the same as the first magnetic characteristic, performing data writing or data reading on the first storage node; When the target magnetic characteristic is the same as the second magnetic characteristic, performing data writing or data reading on the second storage node.

14. A data reading and writing device for a storage unit, characterized in that, Including: A writing module configured to perform data writing on the storage unit according to any one of claims 1 to 5; A reading module configured to perform data reading on the storage unit according to any one of claims 1 to 5.

15. The apparatus according to claim 14, wherein The writing module is specifically configured to control the first storage node to perform data writing through the first bit line, the source line, and the word line, and control the second storage node to perform data writing through the second bit line, the source line, and the word line; The reading module is specifically configured to control the first storage node to perform data reading through the first bit line, the source line, and the word line, and control the second storage node to perform data reading through the second bit line, the source line, and the word line.

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