Negative voltage control circuits, methods, memory and electronic devices

Abstract

This application relates to a negative voltage control circuit, method, memory, and electronic device, belonging to the field of electronic circuits. The negative voltage control circuit includes: a voltage detection module and a control module; the voltage detection module is connected to the data line of the memory cell and is used to detect the voltage of the data line; the control module is connected to the voltage detection module and a negative voltage generating circuit, and the control module is used to control the negative voltage generating circuit to turn on when the voltage of the data line is lower than a preset voltage, so that the negative voltage generating circuit pulls down the voltage of the data line to a negative voltage, wherein the preset voltage is the voltage at which the memory cell can write data 0. This negative voltage control circuit can effectively detect the optimal turn-on time of the negative voltage generating circuit, effectively improving the write operation yield of the memory cell. Furthermore, the circuit structure is simple, the area is small, and costs are effectively saved.

Description

Technical Field

[0001] This application belongs to the field of electronic circuits, and specifically relates to a negative voltage control circuit, method, memory, and electronic device. Background Technology

[0002] In recent years, with the widespread adoption of handheld devices, the demand for low power consumption has increased, leading to a decrease in chip voltage. At low voltages, the write failure rate of Static Random Access Memory (SRAM) increases, causing memory cells to fail to store correct data and resulting in chip malfunction. Therefore, a negative voltage data line write auxiliary circuit is needed to perform write operations on SRAM to improve write yield.

[0003] The negative voltage data line write auxiliary circuit consists of two parts: a negative voltage generation circuit and a negative voltage control circuit. The negative voltage control circuit provides a control line to turn the negative voltage generation circuit on and off. During a write operation, the control line turns on the negative voltage generation circuit, pulling the data line below the negative voltage, thereby improving the write operation yield.

[0004] However, existing negative voltage control circuits are not ideal for improving the write operation capability of memory. Furthermore, existing negative voltage control circuits are generally complex in structure and large in area, leading to increased costs. Summary of the Invention

[0005] Therefore, the purpose of this application is to provide a negative voltage control circuit, a method memory, and an electronic device to improve the problems of the existing negative voltage control circuits having less than ideal write operation capability and complex structure.

[0006] The embodiments of this application are implemented as follows:

[0007] In a first aspect, embodiments of this application provide a negative voltage control circuit, including: a voltage detection module and a control module; the voltage detection module is used to connect to a data line of a storage unit, and the voltage detection module is used to detect the voltage of the data line; the control module is connected to the voltage detection module and a negative voltage generating circuit, and the control module is used to control the negative voltage generating circuit to turn on when the voltage of the data line is lower than a preset voltage, so that the negative voltage generating circuit pulls down the voltage of the data line to a negative voltage, wherein the preset voltage is the voltage at which the storage unit can write data 0.

[0008] In this embodiment, the negative voltage control circuit can automatically fit the write voltage of the memory cell and effectively detect the optimal turn-on time of the negative voltage generation circuit. That is, the negative voltage generation circuit is only turned on when the voltage of the data line drops below the voltage at which the memory cell can write data 0. Since the voltage of the data line in this embodiment needs to drop to a lower voltage before the negative voltage generation circuit is turned on, the pull-down amplitude of the data line is larger (i.e., the pull-down capability is stronger), thereby effectively improving the write operation yield of the memory cell. Moreover, the circuit structure is simple and the area is small, effectively saving costs.

[0009] In one possible implementation of the first aspect embodiment, the voltage detection module includes: an inverter; the input terminal of the inverter is connected to the data line of the storage unit, and the output terminal and internal nodes of the inverter are connected to the control module; the inverter is used to detect the voltage of the data line, and when the voltage of the data line is lower than the switching voltage of the inverter, the inverter outputs a high level; the control module is further used to adjust the switching voltage of the inverter to be less than the preset voltage, wherein the control module is used to control the opening of the negative voltage generating circuit when it detects that the voltage of the inverter has switched from a low level to a high level.

[0010] In this embodiment, an inverter is used to detect the voltage of the data line. When the voltage at the inverter input (i.e., the voltage of the data line) is high, the inverter outputs a low voltage. When the voltage at the inverter input is lower than the inverter's flip-flop voltage, the inverter outputs a high voltage. Simultaneously, a control module adjusts the inverter's flip-flop voltage to lower it by a preset voltage. This requires the data line voltage to drop to a lower level before the inverter flips, thus enabling the function of controlling the negative voltage generation circuit to turn on when the data line voltage is lower than the preset voltage. Because of the inverter's simple structure, it effectively reduces circuit area and implementation cost while achieving the invention's objective.

[0011] In one possible implementation of the first aspect embodiment, the inverter includes: a first PMOS (Positive channel Metal Oxide Semiconductor), a second PMOS, and a first NMOS (Negative channel Metal Oxide Semiconductor); the source of the first PMOS is connected to a power supply, the drain of the first PMOS is connected to the source of the second PMOS, the drain of the second PMOS is connected to the drain of the first NMOS, and the source of the first NMOS is grounded; the gates of the first PMOS, the second PMOS, and the first NMOS are all connected to the data line of the memory cell, and the drain and source of the second PMOS are also connected to the control module; wherein, the control module pulls down the voltage of the source of the second PMOS to reduce the threshold voltage of the second PMOS, so that the data line voltage when the second PMOS is turned on is less than the data line voltage when the first PMOS is turned on.

[0012] In this embodiment, the three transistors described above are used to construct an inverter. When the first PMOS transistor is turned on, the control module pulls down the threshold voltage of the second PMOS transistor, so that the data line voltage when the second PMOS transistor is turned on is lower than the data line voltage when the first PMOS transistor is turned on. That is, the data line voltage needs to drop to a lower voltage (below the voltage at which the memory cell can write data 0) before the second PMOS transistor can turn on. This allows the drain of the second PMOS transistor to flip to a high voltage, thereby enabling the negative voltage generation circuit to be turned on at the optimal time and pulling the data line of the memory cell to a negative voltage. Since transistors have advantages such as small size and low cost, the area and cost of this negative voltage control circuit are further reduced.

[0013] In one possible implementation of the first aspect embodiment, the control module includes an adjustment switch for adjusting the threshold voltage of the second PMOS; the first terminal of the adjustment switch is connected to an internal node of the voltage detection module, the control terminal of the adjustment switch is connected to the output terminal of the voltage detection module and the negative voltage generating circuit, and the second terminal of the adjustment switch is grounded.

[0014] In this embodiment, an adjustment switch is used to regulate the voltage of the internal nodes of the voltage detection module. This allows the negative voltage generation circuit to be activated at the optimal time when the data line voltage is lower than a preset voltage (the voltage at which the memory cell can write data 0), thereby enhancing the write operation capability of the memory. While achieving its inventive objective, this approach simplifies the circuit structure, reduces cost, and increases practicality.

[0015] In one possible implementation of the first aspect embodiment, the negative voltage control circuit includes: a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, and a third PMOS transistor; the source of the first PMOS transistor is connected to a power supply, the drain of the first PMOS transistor is connected to the source of the second PMOS transistor, the drain of the second PMOS transistor is connected to the drain of the first NMOS transistor, and the source of the first NMOS transistor is grounded; the gates of the first PMOS transistor, the second PMOS transistor, and the first NMOS transistor are all connected to the data line of the memory cell, the drain of the second PMOS transistor is also connected to the gate of the third PMOS transistor, the source of the third PMOS transistor is connected to the source of the second PMOS transistor, the source of the third PMOS transistor is grounded, and the gate of the third PMOS transistor is also connected to the negative voltage generating circuit.

[0016] In this embodiment, the negative voltage control circuit with the above-described structure can enhance the write operation yield of the memory cell while minimizing circuit area and design cost.

[0017] In one possible implementation of the first aspect embodiment, the dimensions of the first PMOS transistor and the second PMOS transistor are the same as the dimensions of the pull-up transistor of the memory cell; and / or the dimensions of the first NMOS transistor are the same as the dimensions of the pull-down transistor of the memory cell.

[0018] In this embodiment, since the first PMOS transistor, the second PMOS transistor, and / or the first NMOS transistor and the memory cell have the same device type and size, their electrical characteristics are the same as or close to the circuit characteristics of the memory cell, making the voltage detection more accurate.

[0019] Secondly, embodiments of this application also provide a memory, including: a memory circuit and a write auxiliary circuit, wherein the write auxiliary circuit includes a negative voltage generating circuit and a negative voltage control circuit as provided in any possible implementation of the first aspect embodiment and / or in combination with the first aspect embodiment, wherein the negative voltage control circuit is connected to the negative voltage generating circuit.

[0020] Thirdly, embodiments of this application also provide an electronic device, including a processor and a memory as described above.

[0021] Fourthly, this application also provides a negative voltage control method, comprising: detecting the voltage of the data line of the storage unit; when the voltage of the data line is lower than a preset voltage, controlling the activation of the negative voltage generating circuit so that the negative voltage generating circuit pulls down the voltage of the data line to a negative voltage; wherein the preset voltage is the voltage at which the storage unit can write data 0.

[0022] Other features and advantages of this application will be set forth in the following description. The objectives and other advantages of this application can be realized and obtained through the structures specifically pointed out in the written description and the accompanying drawings. Attached Figure Description

[0023] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the embodiments will be briefly described below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. The above and other objects, features, and advantages of this application will become clearer through the drawings. The same reference numerals indicate the same parts in all the drawings. The drawings are not intentionally drawn to scale to actual size; the focus is on illustrating the main points of this application.

[0024] Figure 1 This illustration shows a connection diagram of a negative voltage control circuit, a data line, and a negative voltage generation circuit provided in an embodiment of this application.

[0025] Figure 2 A schematic diagram of the structure of a storage unit provided in an embodiment of this application is shown.

[0026] Figure 3 A schematic diagram of a negative voltage control circuit provided in an embodiment of this application is shown.

[0027] Figure 4 A schematic diagram of another negative voltage control circuit provided in an embodiment of this application is shown.

[0028] Figure 5 A flowchart illustrating a negative voltage control method provided in an embodiment of this application is shown.

[0029] Figure 6 A schematic diagram of the structure of an electronic device provided in an embodiment of this application is shown. Detailed Implementation

[0030] The technical solutions in the embodiments of this application will now be described with reference to the accompanying drawings.

[0031] It should be noted that similar reference numerals and letters in the following figures denote similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. Furthermore, relational terms such as "first," "second," etc., in the description of this application are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one…" does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0032] Furthermore, the term "and / or" in this application is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Based on this, this application provides a simple negative voltage control circuit 100 that can automatically fit the write voltage of the memory cell to generate a control signal, thereby enabling the negative voltage generation circuit 110 to be turned on at an optimal time, such as when the voltage of the data line is detected to drop below the voltage at which the memory cell can write data 0. The negative voltage control circuit 100 detects the voltage of the data line of the memory cell, and when it detects that the voltage of the data line has dropped below the voltage at which the memory cell can write data 0, it generates a control signal (high level) to control the activation of the negative voltage generation circuit 110, so that the negative voltage generation circuit 110 pulls the voltage of the data line down to a negative voltage.

[0033] The following will combine Figure 1 The negative voltage control circuit 100 provided in this application embodiment will be described. The negative voltage control circuit 100 includes a voltage detection module 10 and a control module 20. The voltage detection module 10 is connected to the data line of the storage unit, and the control module 20 is connected to the voltage detection module 10 and the negative voltage generation circuit 110, which is also connected to the data line of the storage unit.

[0034] The voltage detection module 10 is used to detect the voltage of the data line, and the control module 20 is used to control the negative voltage generation circuit 110 to turn on when the voltage of the data line is lower than the preset voltage, so that the negative voltage generation circuit 110 pulls down the voltage of the data line to a negative voltage. The preset voltage is the voltage at which the storage unit can write data 0.

[0035] In one implementation, the structure of the memory cell is as follows: Figure 2 As shown. Among them, Figure 2 In this circuit, WL represents the word line, BL and BLB are a pair of data lines (or bit lines), and PU and PD transistors, along with PU_X and PD_X transistors, form two inverters connected end-to-end. That is, the output of one inverter (composed of PU and PD transistors) is connected to the input of the other inverter (composed of PU_X and PD_X transistors), and vice versa. The two inverters connected end-to-end form a latch. Under normal conditions, the data stored at memory points Q and QB is very stable and complementary; for example, when Q=0, QB=1, or when Q=1, QB=0.

[0036] Assume Q = 0, QB = 1, and BL = BLB = 1 (indicating a high level). When WL = 1, both PG and PG_X transistors are on. Since Q = 0, the PG transistor pulls down the voltage of data line BL, while the voltage of data line BLB remains constant, creating a voltage difference between BL and BLB. Conversely, if Q = 1 and QB = 0, then when WL = 1, it pulls down the voltage of BLB, while the voltage of BL remains constant, again creating a voltage difference between BL and BLB.

[0037] Since the storage unit has two data lines, namely BL and BLB, two negative voltage control circuits 100 are needed to detect the voltage of these two data lines. For example, one negative voltage control circuit 100 is used to detect the voltage of the BL data line, and the other negative voltage control circuit 100 is used to detect the voltage of the BLB data line.

[0038] By detecting the data line voltage of the storage cell, when the voltage drops below the voltage at which the storage cell can write data 0, the negative voltage generation circuit 110 is activated to further pull the data line voltage down to a negative voltage, thereby enhancing the write operation capability. In this embodiment, the voltage at which the storage cell can write data 0 is preferably 10% of the power supply voltage.

[0039] In one optional embodiment, the voltage detection module 10 includes a comparator. One input terminal of the comparator (such as the inverting input terminal) is connected to the data line of the storage unit, and another input terminal of the comparator (such as the negative input terminal) is used to receive a preset voltage, wherein the preset voltage is the voltage at which the storage unit can write data 0. The output terminal of the comparator is connected to the control module 20. When the voltage of the data line is greater than the preset voltage, the comparator outputs a high level; when the voltage of the data line is less than the preset voltage, the comparator outputs a low level. The control module 20 can control the negative voltage generation circuit 110 to be turned on or off based on the output result of the comparator. In this embodiment, the control module 20 may include a controller for controlling the negative voltage generation circuit 110 to be turned on when the voltage of the data line is lower than the preset voltage.

[0040] In another optional implementation, the voltage detection module 10 includes an inverter. The input terminal of the inverter is connected to the data line of the storage unit, and the output terminal and internal nodes of the inverter are connected to the control module 20. When the voltage at the input terminal of the inverter (i.e., the voltage of the data line) is high, the inverter outputs a low voltage; when the voltage at the input terminal of the inverter is lower than the inverter's flip voltage, the inverter outputs a high level. The control module 20 adjusts the flip voltage of the inverter to make it lower than a preset voltage, so that the voltage of the data line needs to drop to a lower voltage before the inverter can flip, thereby realizing the function of controlling the negative voltage generation circuit 110 to turn on when the voltage of the data line is lower than the preset voltage.

[0041] Among them, such as Figure 3 As shown, the inverter includes a first PMOS transistor ( Figure 3 P1 in the middle), the second PMOS transistor ( Figure 3 P2 in the middle), the first NMOS transistor ( Figure 3 In the N1 configuration, the source of the first PMOS transistor is connected to the power supply, the drain of the first PMOS transistor is connected to the source of the second PMOS transistor, the drain of the second PMOS transistor is connected to the drain of the first NMOS transistor, and the source of the first NMOS transistor is grounded. The gates of the first PMOS transistor, the second PMOS transistor, and the first NMOS transistor are all connected to the data lines of the memory cell. The drain and source of the second PMOS transistor are also connected to the control module 20. The control module pulls down the voltage of the source of the second PMOS transistor to reduce the threshold voltage of the second PMOS transistor, so that the data line voltage when the second PMOS transistor is turned on is lower than the data line voltage when the first PMOS transistor is turned on. That is, the data line voltage needs to drop to a lower voltage for the inverter to flip. Figure 3 The IN terminal is used to connect to the data line of the memory cell and represents the voltage of the data line of the memory cell. The OUT terminal is used to connect to... Figure 1 The negative voltage generating circuit 110 is connected, and the control signal is sent to the negative voltage generating circuit 110.

[0042] In this circuit, the gates of the first PMOS transistor, the second PMOS transistor, and the first NMOS transistor are all input terminals of the inverter. The drain of the first PMOS transistor or the source of the second PMOS transistor is an internal node of the inverter, and the drain of the second PMOS transistor or the drain of the first NMOS transistor is the output terminal of the inverter.

[0043] Optionally, the device types and sizes of the first PMOS transistor and the second PMOS transistor, as well as the pull-up transistors of the memory cells (i.e., Figure 2 The device type and size of the PU transistor and PU_X transistor in the memory cell are consistent, and / or the device type and size of the first NMOS transistor are consistent with those of the pull-down transistor of the memory cell (i.e., Figure 2 The device types and sizes of the PD transistors and PD_X transistors in the memory cell are consistent. That is, in one embodiment, the device types and sizes of the first PMOS transistor and the second PMOS transistor are consistent with the device types and sizes of the pull-up transistors of the memory cell. In this case, it is not necessary to consider whether the size of the first NMOS transistor is consistent with the device type and size of the pull-down transistor of the memory cell. In another embodiment, the device types and sizes of the first NMOS transistor are consistent with the device types and sizes of the pull-down transistors of the memory cell. In this case, it is not necessary to consider whether the sizes of the first PMOS transistor and the second PMOS transistor are consistent with the size of the pull-up transistors of the memory cell. In yet another embodiment, the device types and sizes of the first PMOS transistor and the second PMOS transistor are consistent with the device types and sizes of the pull-up transistors of the memory cell, and the device types and sizes of the first NMOS transistor are consistent with the device types and sizes of the pull-down transistors of the memory cell.

[0044] Since P1, P2, N1 and the memory cell have the same device type and size, their electrical characteristics are the same as or close to the circuit characteristics of the memory cell, making voltage detection more accurate.

[0045] In one optional implementation, the control module 20 includes a controller for controlling the activation of the negative voltage generation circuit 110 when the voltage of the data line is lower than a preset voltage.

[0046] In another optional embodiment, when the voltage detection module 10 includes an inverter, the control module 20 includes an adjustment switch for adjusting the threshold voltage of the second PMOS; the first end of the adjustment switch is connected to the internal node of the voltage detection module 10, the control end of the adjustment switch is connected to the output end of the voltage detection module 10 and the negative voltage generation circuit 110, and the second end of the adjustment switch is grounded.

[0047] Optionally, the regulating switch can be a PMOS transistor, such as... Figure 4 In this case, the P3 transistor is used. At this point, the gate of the PMOS transistor is the control terminal of the adjustment switch, the source of the PMOS transistor is the first terminal of the adjustment switch, and the drain of the PMOS transistor is the second terminal of the adjustment switch. It can be understood that since the source and drain of a transistor are equivalent, it can also be reversed, i.e., the drain of the PMOS transistor is the first terminal of the adjustment switch, and the source of the PMOS transistor is the second terminal of the adjustment switch.

[0048] In one implementation, such as Figure 4 As shown, the negative voltage control circuit 100 includes: a first PMOS transistor ( Figure 4 P1 in the middle), the second PMOS transistor ( Figure 4 P2 in the middle), the first NMOS transistor ( Figure 4 N1 in the middle), the third PMOS transistor ( Figure 4(P3 in the diagram). The source of the first PMOS transistor is connected to the power supply, the drain of the first PMOS transistor is connected to the source of the second PMOS transistor, the drain of the second PMOS transistor is connected to the drain of the first NMOS transistor, and the source of the first NMOS transistor is grounded. The gates of the first PMOS transistor, the second PMOS transistor, and the first NMOS transistor are all connected to the data lines of the memory cell. The drain of the second PMOS transistor is also connected to the gate of the third PMOS transistor, the source of the third PMOS transistor is connected to the source of the second PMOS transistor, the drain of the third PMOS transistor is grounded, and the gate of the third PMOS transistor is also connected to the negative voltage generation circuit 110. Figure 4 The IN terminal is used to connect to the data line of the storage unit, and the OUT terminal is used to connect to... Figure 1 The negative voltage generating circuit 110 is connected.

[0049] When the data line voltage is greater than the threshold voltage of N1, N1 conducts, and P1 and P2 are cut off. At this time, the voltage at the OUT terminal is 0, and P3 conducts. When the data line voltage is less than the threshold voltage of P1, P1 conducts. At this time, both P1 and P3 conduct. P3 pulls the voltage at point A below the power supply voltage, thereby reducing the threshold voltage of P2. Therefore, the data line voltage needs to drop to a lower voltage for P2 to conduct, causing the OUT output to flip to a high voltage. This activates the negative voltage generation circuit 110, pulling the data line of the memory cell to a negative voltage. This further ensures the write operation of the memory cell, thereby improving the yield and efficiency of the write operation.

[0050] The negative voltage control circuit 100 provided in this embodiment can effectively detect the turn-on time of the optimal negative voltage generation circuit 110, thereby effectively improving the write operation yield of the memory cell. Furthermore, the circuit structure is simple (e.g., it may only include...). Figure 4 The four transistors shown have a small area, which effectively saves costs.

[0051] Based on the same inventive concept, this application also provides a negative voltage control method, which will be described below in conjunction with... Figure 5 The flowchart shown illustrates this.

[0052] S1: Detects the voltage of the data line of the storage unit.

[0053] In one alternative implementation, the voltage detection module 10 described above can be used to detect the voltage of the data line of the storage unit.

[0054] S2: When the voltage of the data line is lower than the preset voltage, control the opening of the negative voltage generating circuit 110 so that the negative voltage generating circuit 110 pulls down the voltage of the data line to a negative voltage.

[0055] In one alternative implementation, the voltage detection module 10 described above can be used to implement process S2. The preset voltage is the voltage at which the storage unit can write data 0.

[0056] The implementation principle and technical effects of the method embodiment are the same as those of the aforementioned negative voltage control circuit 100 embodiment. For the sake of brevity, any parts not mentioned in the method embodiment can be referred to the corresponding content in the aforementioned negative voltage control circuit 100 embodiment.

[0057] Based on the same inventive concept, embodiments of this application also provide a memory, which includes a memory circuit and a write auxiliary circuit for pulling down the data line voltage of the memory cells. Using the write auxiliary circuit to perform write operations on the memory circuit can improve the write operation yield of the memory.

[0058] The auxiliary circuit includes a negative voltage generating circuit 110 and the aforementioned negative voltage control circuit 100. The negative voltage control circuit 100 is connected to the negative voltage generating circuit 110 and is used to control the opening and closing of the negative voltage generating circuit 110.

[0059] The negative voltage control circuit 100 provided in the memory embodiment has the same implementation principle and technical effect as the aforementioned negative voltage control circuit 100 embodiment. For the sake of brevity, any parts not mentioned in the memory embodiment can be referred to the corresponding content in the aforementioned negative voltage control circuit 100 embodiment.

[0060] Based on the same inventive concept, embodiments of this application also provide an electronic device, which includes the aforementioned memory. For example, in one embodiment, the structure of the electronic device is as follows: Figure 6 As shown, the electronic device 200 includes: a transceiver 210, a memory 220, a communication bus 230, and a processor 240.

[0061] The transceiver 210, memory 220, and processor 240 are electrically connected directly or indirectly to achieve data transmission or interaction. For example, these components can be electrically connected to each other through one or more communication buses 230 or signal lines. The transceiver 210 is used to send and receive data. The memory 220 is used to store computer programs, which include at least one software functional module that can be stored in the memory 220 in the form of software or firmware or embedded in the operating system (OS) of the electronic device 200. The processor 240 is used to execute the software functional modules or computer programs stored in the memory 220.

[0062] The memory 220 may be, but is not limited to, random access memory (RAM), read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), etc.

[0063] Processor 240 may be an integrated circuit chip with signal processing capabilities. The aforementioned processor can be a general-purpose processor, including a Central Processing Unit (CPU), a Network Processor (NP), etc.; it can also be a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. The general-purpose processor can be a microprocessor, or processor 240 can be any conventional processor.

[0064] Among them, the aforementioned electronic devices 200 include, but are not limited to, mobile phones, tablets, computers, industrial control equipment, vehicle-mounted equipment, servers, etc.

[0065] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0066] In addition, the functional modules in the various embodiments of this application can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.

[0067] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A negative voltage control circuit, characterized in that, include: A voltage detection module is used to connect to the data line of the storage unit, and the voltage detection module is used to detect the voltage of the data line; A control module is connected to the voltage detection module and the negative voltage generation circuit. The control module is used to control the negative voltage generation circuit to turn on when the voltage of the data line is lower than the preset voltage, so that the negative voltage generation circuit pulls down the voltage of the data line to a negative voltage. The preset voltage is the voltage at which the storage unit can write data 0. The voltage detection module includes an inverter; The input terminal of the inverter is connected to the data line of the storage unit, and the output terminal and internal nodes of the inverter are connected to the control module. The inverter is used to detect the voltage of the data line. When the voltage of the data line is lower than the switching voltage of the inverter, the inverter outputs a high level. The control module is also used to adjust the switching voltage of the inverter to be less than the preset voltage. The control module is used to control the negative voltage generation circuit to turn on when it detects that the voltage of the inverter has switched from low level to high level.

2. The negative voltage control circuit according to claim 1, characterized in that, The inverter includes: a first PMOS transistor, a second PMOS transistor, and a first NMOS transistor; The source of the first PMOS transistor is connected to the power supply, the drain of the first PMOS transistor is connected to the source of the second PMOS transistor, the drain of the second PMOS transistor is connected to the drain of the first NMOS transistor, and the source of the first NMOS transistor is grounded. The gates of the first PMOS transistor, the second PMOS transistor, and the first NMOS transistor are all connected to the data line of the memory cell, and the drain and source of the second PMOS transistor are also connected to the control module. Specifically, the control module pulls down the source voltage of the second PMOS transistor to reduce the threshold voltage of the second PMOS transistor, so that the data line voltage when the second PMOS transistor is turned on is less than the data line voltage when the first PMOS transistor is turned on.

3. The negative voltage control circuit according to claim 2, characterized in that, The control module includes an adjustment switch for adjusting the threshold voltage of the second PMOS; the first terminal of the adjustment switch is connected to the internal node of the voltage detection module, the control terminal of the adjustment switch is connected to the output terminal of the voltage detection module and the negative voltage generation circuit, and the second terminal of the adjustment switch is grounded.

4. The negative voltage control circuit according to claim 1, characterized in that, The negative voltage control circuit includes: a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, and a third PMOS transistor; wherein, the inverter includes the first PMOS transistor, the second PMOS transistor, and the first NMOS transistor; and the control module includes the third PMOS transistor. The source of the first PMOS transistor is connected to the power supply, the drain of the first PMOS transistor is connected to the source of the second PMOS transistor, the drain of the second PMOS transistor is connected to the drain of the first NMOS transistor, and the source of the first NMOS transistor is grounded. The gates of the first PMOS transistor, the second PMOS transistor, and the first NMOS transistor are all connected to the data line of the memory cell. The drain of the second PMOS transistor is also connected to the gate of the third PMOS transistor. The source of the third PMOS transistor is connected to the source of the second PMOS transistor. The source of the third PMOS transistor is grounded. The gate of the third PMOS transistor is also connected to the negative voltage generating circuit.

5. The negative voltage control circuit according to claim 4, characterized in that, The dimensions of the first PMOS transistor and the second PMOS transistor are the same as the dimensions of the pull-up transistor of the memory cell; and / or The size of the first NMOS transistor is the same as the size of the pull-down transistor of the memory cell.

6. A memory, characterized in that, include: The memory circuit and the write auxiliary circuit, wherein the write auxiliary circuit includes: a negative voltage generating circuit and a negative voltage control circuit as described in any one of claims 1-5, wherein the negative voltage control circuit is connected to the negative voltage generating circuit.

7. The memory according to claim 6, characterized in that, The memory is an SRAM memory.

8. An electronic device, characterized in that, Includes a processor and the memory as described in claim 6 or 7.

9. A negative voltage control method, characterized in that, The method, applied to the negative voltage control circuit as described in any one of claims 1-5, comprises: Detect the voltage of the data lines in the storage unit; When the voltage of the data line is lower than the preset voltage, the negative voltage generating circuit is turned on so that the negative voltage generating circuit pulls the voltage of the data line down to a negative voltage. The preset voltage is the voltage at which the storage unit can write data 0.

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