Recess etching method and manufacturing method of fin field effect transistor
By employing a three-step etching method during the silicon trench etching process of fin field-effect transistors, byproducts are removed and smooth surface trenches are formed, solving the problems of high surface roughness and defect state density of the trenches, thus enabling the smooth progress of selective epitaxy and improving device performance.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- BEIJING NAURA MICROELECTRONICS EQUIP CO LTD
- Filing Date
- 2023-02-27
- Publication Date
- 2026-06-26
AI Technical Summary
In the existing technology, the large surface roughness of the grooves during the silicon trench etching process of fin field-effect transistors leads to a high interface defect state density, which cannot meet the requirements of selective epitaxy of SiP and SiGe.
A three-step etching method is adopted, including main etching, byproduct removal and over-etching steps. Byproducts on the inner wall of the initial groove are removed by plasma physical collision to form a smooth surface groove.
It effectively reduces the surface roughness and defect state density of the groove, ensuring the normal progress of subsequent selective epitaxial processes and improving device performance.
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Figure CN116313770B_ABST