Method of manufacturing a semiconductor structure

Abstract

The present disclosure provides a method for manufacturing a semiconductor structure. The method comprises: providing a substrate, the substrate comprising an array region, a core region and a peripheral region; forming a sequentially stacked metal layer and a first mask layer on the substrate, and forming a first pattern in the first mask layer located in the array region and the core region; forming a second mask layer on the first mask layer with the first pattern, and forming a second pattern in the second mask layer located in the array region and the core region; etching the first mask layer with the first pattern based on the second pattern, and forming a third pattern in the first mask layer located in the array region and the core region; forming a third mask layer on the first mask layer, and forming a fourth pattern in the third mask layer located in the peripheral region; transferring the fourth pattern to the first mask layer located in the peripheral region; and etching the metal layer based on the third pattern and the fourth pattern to form a metal line. The method can improve the yield of the semiconductor structure.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor fabrication technology, and in particular to a method for fabricating a semiconductor structure. Background Technology

[0002] As semiconductor technology continues to mature, the requirements for high density and large capacity of semiconductor memory chips are becoming increasingly stringent. In the process of semiconductor structure fabrication, the patterns are numerous and dense, and the requirements for precision are also increasing.

[0003] Different functional areas on the substrate of a semiconductor structure have different pattern densities. In the process of semiconductor fabrication, there are multiple process steps, such as deposition, etching, and cleaning. The pattern density will affect the processing effect of the same process step, such as etching rate and deposition rate. When the pattern density differs greatly, it will lead to dimensional deviations after processing in the same process step, resulting in defects in the semiconductor structure and reducing yield.

[0004] The information disclosed in the background section is only intended to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute related technology known to those skilled in the art. Summary of the Invention

[0005] This disclosure provides a method for fabricating a semiconductor structure, which can improve the yield of semiconductor structures.

[0006] This disclosure provides a method for fabricating a semiconductor structure, comprising: providing a substrate, the substrate including an array region, a core region, and a peripheral region; forming a metal layer and a first mask layer sequentially stacked on the substrate, and forming a first pattern in the first mask layer located in the array region and the core region; forming a second mask layer on the first mask layer having the first pattern, and forming a second pattern in the second mask layer located in the array region and the core region; etching the first mask layer having the first pattern based on the second pattern, and forming a third pattern in the first mask layer located in the array region and the core region; forming the third mask layer on the first mask layer, and forming a fourth pattern in the third mask layer located in the peripheral region; transferring the fourth pattern to the first mask layer located in the peripheral region; and etching the metal layer based on the third pattern and the fourth pattern to form a metal line.

[0007] In some embodiments of this disclosure, forming a second mask layer on a first mask layer having the first pattern, and forming a second pattern in the second mask layer located in the array region and the core region, includes: forming a second mask layer on a first mask layer having the first pattern; forming a second preset pattern in the second mask layer; conformally forming a second sacrificial layer on the second mask layer having the second preset pattern; filling the spaces between the second sacrificial layers with a second filler layer; removing the second sacrificial layer; and forming the second pattern between the second filler layer and the second mask layer.

[0008] In some embodiments of this disclosure, forming a second preset pattern in the second mask layer includes: forming a first photoresist layer on the second mask layer; forming the second preset pattern in the first photoresist layer; transferring the second preset pattern to the second mask layer; and removing the first photoresist layer.

[0009] In some embodiments of this disclosure, in the vertical direction, the second pattern is located directly above the first mask layer having the first pattern, and the density of the third pattern is twice the density of the first pattern.

[0010] In some embodiments of this disclosure, forming a third mask layer on the first mask layer and forming a fourth pattern in the third mask layer located in the peripheral region includes: forming a third mask layer on the first mask layer; forming a second photoresist layer on the third mask layer; forming a fourth pattern in the second photoresist layer located in the peripheral region; transferring the fourth pattern to the third mask layer and removing the second photoresist layer.

[0011] In some embodiments of this disclosure, forming a first pattern in a first mask layer located in the array region and the core region includes: forming an initial spin coating layer on the first mask layer; forming a first preset pattern in the initial spin coating layer located in the array region and the core region; conformally forming a first sacrificial layer on the initial spin coating layer having the first preset pattern; filling a first filler layer between the first sacrificial layers; removing the first sacrificial layer and forming the first pattern between the first filler layer and the initial spin coating layer; and transferring the first pattern to the first mask layer.

[0012] In some embodiments of this disclosure, forming a first preset pattern in the initial spin coating layer located in the array region and the core region includes: forming an initial photoresist layer on the initial spin coating layer; forming the first preset pattern in the initial photoresist layer located in the array region and the core region; and transferring the first preset pattern to the initial spin coating layer.

[0013] In some embodiments of this disclosure, the density of the fourth pattern is less than the density of the third pattern in the first mask layer located in the core region.

[0014] In some embodiments of this disclosure, after forming a metal layer on the substrate, the method further includes: forming a hard mask layer on the metal layer; forming a dielectric layer on the hard mask layer; and forming the first mask layer on the dielectric layer.

[0015] In some embodiments of this disclosure, etching the metal layer to form a metal line based on the third pattern and the fourth pattern includes: transferring the third pattern and the fourth pattern in the first mask layer to the hard mask layer and the dielectric layer, and removing the dielectric layer; etching the metal layer based on the third pattern and the fourth pattern in the hard mask layer to form the metal line.

[0016] As can be seen from the above technical solutions, the semiconductor structure preparation method and semiconductor structure of this disclosure have at least one of the following advantages and positive effects:

[0017] In this embodiment of the present disclosure, after the second mask layer is formed, the core region and the array region are etched simultaneously to give the first mask layer a third pattern. Although the density of the pattern in the first mask layer located in the core region is greater than the density of the pattern in the first mask layer located in the peripheral region before the third mask layer is formed, making the height of the third mask layer located in the peripheral region greater than the height of the third mask layer located in the core region, the fourth pattern is formed only in the third mask layer located in the peripheral region. Therefore, when etching the third mask layer, only the third mask layer located in the peripheral region is etched, and the third mask layer located in the core region is not etched at the same time. This avoids etching defects caused by the height difference between the third mask layers located in the peripheral region and the core region, thereby improving the yield of the semiconductor structure. Attached Figure Description

[0018] The above and other features and advantages of this disclosure will become more apparent from a detailed description of exemplary embodiments thereof with reference to the accompanying drawings.

[0019] Figure 1 This is a schematic diagram showing the dimensional inhomogeneity of a semiconductor structure in the vertical direction in related technologies;

[0020] Figure 2 This is a flowchart illustrating a method for fabricating a semiconductor structure according to some embodiments of this disclosure;

[0021] Figures 3 to 8 This is a schematic diagram illustrating a semiconductor structure with a first pattern formed on a first mask layer, as shown in some embodiments of the present disclosure.

[0022] Figures 9 to 15This is a schematic diagram illustrating the formation of a second mask layer on a first mask layer and the formation of a second pattern on the second mask layer, as shown in some embodiments of this disclosure;

[0023] Figure 16 This is a schematic diagram illustrating the transfer of a second pattern onto a first mask layer to form a third pattern, as shown in some embodiments of this disclosure;

[0024] Figures 17 to 18 This is a schematic diagram illustrating the formation of a third mask layer having a fourth pattern, as shown in some embodiments of this disclosure;

[0025] Figure 19 This is a schematic diagram illustrating the transfer of a fourth pattern to a first mask layer, as shown in some embodiments of this disclosure;

[0026] Figure 20 This is a schematic diagram illustrating the transfer of the third and fourth patterns of the first mask layer to the hard mask layer, as shown in some embodiments of this disclosure.

[0027] Figure 21 This is a schematic diagram illustrating the etching of metal layers based on third and fourth patterns to form metal lines, as shown in some embodiments of this disclosure.

[0028] Explanation of reference numerals in the attached figures:

[0029] 10', Substrate; 20', Metal layer; 30', Oxide layer; 40', Mask layer; 50', Photoresist layer; A', Array region; B', Core region; C', Peripheral region;

[0030] 10. Substrate; 20. Metal layer; 30. Hard mask layer; 31. Dielectric layer; 40. First mask layer; 50. Initial swirl coating layer; 51. Initial anti-reflection layer; 52. Initial photoresist layer; 53. First sacrificial layer; 54. First filler layer; 60. Second mask layer; 61. First swirl coating layer; 62. First oxide layer; 63. Second swirl coating layer; 64. First anti-reflection layer; 65. Second sacrificial layer; 66. Second filler layer; 70. First photoresist layer; 80. Third mask layer; 81. Third swirl coating layer; 82. Second anti-reflection layer; 90. Second photoresist layer; A. Array area; B. Core area; C. Peripheral area; S1. First pattern; S11. First preset pattern; S2. Second pattern; S21. Second preset pattern; S3. Third pattern; S4. Fourth pattern; Y. Vertical direction. Detailed Implementation

[0031] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, they are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore their detailed description will be omitted.

[0032] In the following description of different exemplary embodiments of the present disclosure, reference is made to the accompanying drawings, which form part of the present disclosure and illustrate, by way of example, different exemplary structures that can implement various aspects of the present disclosure. It should be understood that other specific embodiments of components, structures, exemplary devices, systems, and steps may be used, and structural and functional modifications may be made without departing from the scope of the present disclosure. Furthermore, while the terms “above,” “between,” “within,” etc., may be used in this specification to describe different exemplary features and elements of the present disclosure, these terms are used herein only for convenience, such as according to the orientation of the examples in the drawings. Nothing in this specification should be construed as requiring a specific three-dimensional orientation of the structure to fall within the scope of the present disclosure. Moreover, the terms “first,” “second,” etc., in the claims are used only as illustrative marks and not as numerical limitations on the object.

[0033] The flowcharts shown in the accompanying drawings are merely illustrative and do not necessarily include all content and operations / steps, nor do they necessarily have to be performed in the described order. For example, some operations / steps can be broken down, while others can be combined or partially combined; therefore, the actual execution order may change depending on the specific circumstances.

[0034] In addition, in the description of this disclosure, "multiple" means at least two, such as two, three, etc., unless otherwise expressly and specifically limited.

[0035] like Figure 1 As shown, in related technologies, for example, when manufacturing metal lines for semiconductor structures, in order to ensure that the size and pattern of the metal lines are more accurate, a metal layer 20' is usually formed on a substrate 10' of the semiconductor structure, an oxide layer 30' is formed on the metal layer 20', a patterned mask layer 40' is formed on the oxide layer 30', and an etching process is used to transfer all the patterns in the mask layer 40' to the oxide layer 30'. Then, the metal layer 20' is etched using the pattern in the oxide layer 30' to form the metal lines.

[0036] Because the density of the metal wire pattern varies in different regions of the substrate 10', the density of the pattern in the mask layer 40' also varies in different regions. The pattern density can be understood as the degree of density of the pattern. The substrate 10' has an array region A', a core region B' surrounding the array region A', and a peripheral region C' surrounding the core region B'. The density of the metal wire pattern gradually decreases from the array region A' to the peripheral region C'. Figure 1 As shown, after the oxide layer 30' is etched for the first time, the density of the pattern in the array region A' and the core region B' of the oxide layer 30' is greater than the density of the pattern in the peripheral region C'. In related technologies, in order to cut off the lines formed in the core region B' and the peripheral region C' of the oxide layer 30' in the above etching process, a mask layer 40' needs to be deposited on the oxide layer 30' after the first etching, and a photoresist layer 50' is formed on the mask layer 40'. A pattern is formed in the core region B' and the peripheral region C' of the photoresist layer 50', and the pattern is transferred to the mask layer 40'. The pattern of the mask layer 40' is then used to continue etching the core region B' and the peripheral region C' of the oxide layer 30', finally forming an oxide layer 30' with a pattern of metal lines.

[0037] However, due to the different densities of the oxide layer 30' pattern in different regions, the resulting mask layer 40' has different thicknesses in the vertical Y direction, such as... Figure 1 As shown, the thickness of the mask layer 40' located in the peripheral region C' is greater than the thickness of the core region B' and the array region A'. When this mask layer 40' is etched, the oxide layer 30' located in the peripheral region C' is etched, while the oxide layer 30' located in the core region B' is over-etched, potentially etched into the layer structure below the oxide layer 30', forming an over-etching defect. If the etching conditions are adjusted, such as reducing the concentration of the etchant or shortening the etching time, the oxide layer 30' located in the core region B' can be etched just enough to expose the underlying layer structure, but the oxide layer 30' located in the peripheral region C' will not be completely etched, leaving some oxide residue. This residual oxide will further affect subsequent processes, thus affecting the yield of the semiconductor structure.

[0038] Based on this, embodiments of this disclosure provide a method for fabricating a semiconductor structure. (See reference...) Figures 2 to 21 ,in, Figure 2 A flowchart illustrating a method for fabricating a semiconductor structure according to an embodiment of this disclosure is shown. Figures 3 to 21 Cross-sectional schematic diagrams of the semiconductor structure are shown at different steps of the fabrication method. For example... Figure 2 As shown, the method for preparing the semiconductor structure according to the present disclosure includes steps S210 to S270.

[0039] S210: Provides a substrate 10, which includes an array region A, a core region B, and a peripheral region C.

[0040] like Figure 3 As shown, the substrate 10 includes a semiconductor substrate on which shallow trench isolation is formed, with active regions disposed between the shallow trench isolations. The shallow trench isolation is used for insulating isolation and its material can be silicon nitride or silicon dioxide. The substrate 10 includes an array region A, a core region B surrounding the array region A, and a peripheral region C surrounding the core region B. Major semiconductor devices, such as transistors, bit lines, and word lines, can be formed in the array region A and the core region B. The gate of the transistor is connected to the word line, the drain is connected to the bit line, and the source is connected to a capacitor. The voltage signal on the word line can control the transistor to turn on or off, thereby reading data information stored in the capacitor through the bit line, or writing data information into the capacitor for storage through the bit line. Alternatively, a core circuit can be formed in the core region B, and a peripheral circuit can be formed in the peripheral region C. To highlight the fabrication process of this invention, the various device structures located in the substrate 10 are omitted in the accompanying drawings.

[0041] In some embodiments, the semiconductor substrate can be made of silicon, silicon carbide, silicon-on-insulator, silicon-on-insulator, silicon-germanide-on-insulator, or germanium-on-insulator, etc. The semiconductor substrate can also be implanted with certain dopant particles to alter its electrical parameters according to design requirements.

[0042] S220: A metal layer 20 and a first mask layer 40 are formed sequentially on the substrate 10, and a first pattern S1 is formed in the first mask layer 40 located in the array region A and the core region B.

[0043] In this process, a metal layer 20 and a first mask layer 40 can be formed sequentially on the substrate 10 using a deposition process.

[0044] The deposition process in the embodiments of this disclosure can be chemical vapor deposition, physical vapor deposition, atomic layer deposition, spin coating, molecular beam epitaxy, etc. Those skilled in the art can choose according to the actual situation, and no special limitation is made here.

[0045] In some embodiments, the material of the metal layer 20 may include at least one of copper, tungsten and aluminum, and the material of the first mask layer 40 may be silicon oxide, without any special limitation.

[0046] In some embodiments, such as Figure 3 As shown, the formation of the first pattern S1 in the first mask layer 40 located in the array region A and the core region B in S220 may include the following contents A1 to A6.

[0047] A1: An initial spin coating layer 50 is formed on the first mask layer 40.

[0048] Specifically, such as Figure 3 As shown, a film-forming liquid is applied to the first mask layer 40, and then the substrate 10 is rotated at high speed. Under the action of centrifugal force, the film-forming liquid diffuses to the edge of the first mask layer 40, leaving a spin-coated layer at the edge of the first mask layer 40. The initial spin-coated layer 50 can be a spin-on hard mask (SOH). The spin-coating process can be performed at low temperatures to avoid damage to other film layers caused by high temperatures and to form a uniform spin-coated layer.

[0049] A2: A first preset pattern S11 is formed in the initial spin coating 50 located in the array region A and the core region B.

[0050] like Figures 3 to 4 As shown, forming a first preset pattern S11 in the initial spin coating layer 50 located in the array region A and the core region B in A2 may include: forming an initial photoresist layer 52 on the initial spin coating layer 50; forming a first preset pattern S11 in the initial photoresist layer 52 located in the array region A and the core region B; and transferring the first preset pattern S11 to the initial spin coating layer.

[0051] Continue to refer to Figure 3 In some embodiments, an initial antireflective layer 51 may be formed on the initial spin coating layer 50 before the initial photoresist layer 52 is formed, and then the initial photoresist layer 52 is formed on the initial antireflective layer 51.

[0052] In some embodiments, the initial photoresist layer 52 may be made of photoresist, and a first preset pattern S11 may be formed in the initial photoresist layer 52 located in the array region A and the core region B through exposure and development processes.

[0053] In the developing process, a developing solution is used to remove the exposed photoresist. In some embodiments, the initial anti-reflective layer 51 may be made of silicon oxynitride.

[0054] A3: A first sacrificial layer 53 is conformally formed on an initial spin coating 50 having a first preset pattern S11.

[0055] like Figure 5 As shown, a first sacrificial layer 53 can be conformally formed on an initial spin coating 50 having a first preset pattern S11 using a deposition process. The first sacrificial layer 53 can be formed as a barrier on the spaced sides and top surface of the initial spin coating 50.

[0056] In some embodiments, the first sacrificial layer 53 may be made of at least one of silicon oxide and silicon oxynitride. The material of the first sacrificial layer 53 may be the same as that of the first mask layer 40.

[0057] A4: Fill the spaces between the first sacrificial layers 53 with the first filler layer 54.

[0058] like Figure 5 As shown, after the first sacrificial layer 53 is formed, there are still gaps between the first sacrificial layers 53. Figure 6 As shown, the first filling layer 54 can be filled in the gaps between the first sacrificial layers 53 using a deposition process.

[0059] like Figure 6 As shown, the first filler layer 54 is located in the gap and is higher than the first sacrificial layer 53 on the initial spin coating layer 50. Figure 7 As shown, chemical mechanical polishing (CMP) can be used to remove the first filler layer 54 above the first sacrificial layer 53 and the first sacrificial layer 53 located on the top surface of the initial spin coating 50, thereby planarizing the top surfaces of the first filler layer 54, the initial spin coating 50, and the first sacrificial layer 53 located on the side of the initial spin coating 50, which facilitates subsequent processes. Alternatively, CMP can be used to remove only the first filler layer 54 above the first sacrificial layer 53, retaining the first sacrificial layer 53 located on the top surface of the initial spin coating 50, allowing this first sacrificial layer 53 to be etched away in subsequent processes.

[0060] Continue to refer to Figure 6 Since the density of the first preset pattern S11 in array region A is greater than that in core region B, after the formation of the first filling layer 54, the height of the first filling layer 54 in array region A (its dimension in the vertical Y direction, which can also be understood as the thickness of the first filling layer 54 on the first sacrificial layer 53) is slightly smaller than that in core region B. However, the height difference is within the allowable range of process error, so it will not affect subsequent processes. Furthermore, since the initial spin coating layer 50 in peripheral region C has not yet formed a pattern, the height of the first filling layer 54 in peripheral region C is greater than that in core region B, and the height difference is relatively large. Figure 6 As shown in the image.

[0061] A5: Remove the first sacrificial layer 53 and form a first pattern S1 between the first filler layer 54 and the initial spin coating layer 50.

[0062] like Figure 7 As shown, the first sacrificial layer 53 located on the initial spin coating 50 can be removed by an etching process, and the first pattern S1 can be formed in the first fill layer 54 and the initial spin coating 50.

[0063] A6: Transfer the first pattern S1 to the first mask layer 40.

[0064] like Figure 8 As shown, according to the first pattern S1, the first mask layer 40 is etched further to transfer the first pattern S1 into the first mask layer 40, so that the first mask layer 40 located in the array region A and the core region B has the first pattern S1. Since the initial spin coating layer 50 located in the peripheral region C does not have the first preset pattern S11, the first mask layer 40 located in the peripheral region C is not etched and does not have a pattern.

[0065] In some embodiments, since there are more devices formed in the array region A than in the core region B and the peripheral region C, the density of the final pattern formed in the array region A is also the highest. Therefore, during the fabrication process, the density of the first pattern S1 in the portion of the first mask layer 40 located in the array region A can be slightly greater than the density of the first pattern S1 in the first mask layer 40 located in the core region B.

[0066] The etching process in this embodiment can be a wet etching process or a dry etching process. The dry etching process can be a plasma etching process, where the etching gas used is chlorine. By controlling the amount of etching gas, the degree of etching can be controlled. The wet etching process can use concentrated sulfuric acid and hydrogen peroxide as etchants. By adjusting the concentration of the etchant, the degree of etching can also be controlled; further details are omitted here.

[0067] S230: A second mask layer 60 is formed on the first mask layer 40 on which the first pattern is formed, and a second pattern S2 is formed in the second mask layer 60 located in the array region A and the core region B. Specifically, S230 may include the following contents B1 to B5.

[0068] B1: A second mask layer 60 is formed on a first mask layer 40 on which a first pattern is formed.

[0069] like Figure 9 As shown, the second mask layer 60 can be formed on the first mask layer 40 by a deposition process. The material of the second mask layer 60 is different from that of the first mask layer 40. For example, the first mask layer 40 can be made of silicon oxide, and the second mask layer 60 can be made of silicon nitride; no special limitation is made here. The second mask layer 60 can be a single layer or a multilayer stack.

[0070] Continue to refer to Figure 9The first mask layer 40 located in array region A and core region B has a first pattern S1. The density of the first pattern S1 in array region A is greater than that in core region B. Therefore, after the second mask layer 60 is formed, the height of the second mask layer 60 in array region A (its dimension in the vertical Y direction, which can also be understood as the thickness of the second mask layer 60 on top of the first mask layer 40) is slightly smaller than that of the second mask layer 60 in core region B. However, the height difference between the two is within the allowable error range of the process, so the height difference will not affect subsequent processes. In addition, since the first mask layer 40 located in peripheral region C has not formed a pattern, the height of the second mask layer 60 in peripheral region C is greater than that of the second mask layer 60 in core region B, and the height difference between the two is large, exceeding the allowable error range of the process.

[0071] In some embodiments, such as Figure 9 As shown, the second mask layer 40 is a multi-layered stack. The formation of the second mask layer 60 on the first mask layer 40 includes: forming a first swirl coating layer 61, a first oxide layer 62, a second swirl coating layer 63 and a first anti-reflection layer 64 stacked sequentially on the first mask layer 40.

[0072] Specifically, a first spin coating layer 61 is formed on the first mask layer 40 using a spin coating process. After the first spin coating layer 61 is formed and stabilized, a first oxide layer 62 can be formed on the first spin coating layer 61 using other deposition processes. Then, a second spin coating layer 63 is formed on the first oxide layer 62 using a spin coating process. After the second spin coating layer 63 is formed and stabilized, a first anti-reflection layer 64 can be formed on the second spin coating layer 63 using other deposition processes to form the second mask layer 60 in this embodiment of the present disclosure.

[0073] The first spin coating 61 and the second spin coating 63 can be spin-coated hard masks, and both are made of the same material, which simplifies the process. The first oxide layer 62 can be made of silicon oxide, and the first anti-reflective layer 64 can be a silicon oxynitride layer formed on the second spin coating 63 using a deposition process.

[0074] In other embodiments, the second mask layer 60 may include a first swirl coating layer 61 and a first antireflective layer 64 sequentially stacked on the first mask layer 40, i.e., the swirl coating layer in the second mask layer 60 has only one layer.

[0075] B2: Form a second preset pattern S21 in the second mask layer.

[0076] like Figure 10 and Figure 11As shown, B2 may include: forming a first photoresist layer 70 on the second mask layer 60, forming a second preset pattern S21 in the first photoresist layer 70, transferring the second preset pattern S21 to the second mask layer 60, and removing the first photoresist layer 70.

[0077] Specifically, such as Figure 10 As shown, a first photoresist layer 70 is formed on the second mask layer 60, and the first photoresist layer 70 can be photoresist. A second preset pattern S21 is formed in the first photoresist layer 70 located in the array region A and the core region B. Specifically, the second preset pattern S21 can be formed in the first photoresist layer 70 located in the array region A and the core region B through exposure and development processes.

[0078] like Figure 11 As shown, based on the second preset pattern S21 of the first photoresist layer 70, the second mask layer 60 is etched using a wet etching process or a dry etching process. For example, the first anti-reflective layer 64 and the second spin coating layer 63 in the second mask layer 60 are etched. The etching stops at the first oxide layer 62, and the second preset pattern S21 is transferred to the second spin coating layer 63, that is, transferred to the second mask layer 60. Therefore, the first oxide layer 62 can serve as an etching stop layer to prevent over-etching and damage to the first spin coating layer 61.

[0079] In some embodiments, such as Figure 11 As shown, after the second preset pattern S21 is transferred to the first anti-reflective layer 64 and the second spin coating layer 63, the first photoresist layer 70 can be removed by chemical mechanical polishing or etching.

[0080] In other embodiments, the second mask layer 60 only has a first swirl coating layer 61 and a first anti-reflective layer 64. In this case, the second pattern S2 can be transferred to the first swirl coating layer 61 by etching the first anti-reflective layer 64 and the first swirl coating layer 61 based on the second preset pattern S21 in the first photoresist layer 70, thus saving process steps. Those skilled in the art can choose the above embodiments according to actual conditions, as long as the second preset pattern S21 can ultimately be formed in the second mask layer 60; no special limitations are made here.

[0081] B3: A second sacrificial layer 65 is conformally formed on a second mask layer 60 having a second preset pattern S21.

[0082] like Figure 12 As shown, a second sacrificial layer 65 can be conformally formed on a second mask layer 60 having a second preset pattern S21 (e.g., the first anti-reflection layer 64 and the second spin coating layer 63 in the above embodiment) using a deposition process. The second sacrificial layer 65 can be formed as a barrier on the spaced sides and top surface of the second mask layer 60.

[0083] In some embodiments, the material of the second sacrificial layer 65 may be at least one of silicon oxide or silicon oxynitride, and the material of the second sacrificial layer 65 may be the same as that of the first mask layer 40.

[0084] B4: Fill the space between the second sacrificial layers 65 with a second filler layer 66.

[0085] like Figure 12 As shown, after the formation of the second sacrificial layer 65, there are still gaps between the second sacrificial layers 65. Figure 13 As shown, a second filling layer 66 can be filled in the gaps between the second sacrificial layers 65 using a deposition process.

[0086] like Figure 13 As shown, the second filler layer 66 is located in the gap and is higher than the second sacrificial layer 65 on the first antireflective layer 64. Figure 14 As shown, the second filler layer 66, which is higher than the second sacrificial layer 65, can be removed using a chemical mechanical polishing process, thereby planarizing the top surfaces of the second filler layer 66, the second mask layer 60, and the second sacrificial layer 65 to facilitate subsequent processes. Of course, when removing the second filler layer 66, which is higher than the second sacrificial layer 65, using a chemical mechanical polishing process, the second sacrificial layer 65 located on the top surface of the first antireflective layer 64 can also be removed simultaneously.

[0087] Continue to refer to Figure 13 Since the density of the second preset pattern S21 located in array region A is greater than that located in core region B, after the formation of the second fill layer 66, the height of the second fill layer 66 located in array region A (its dimension in the vertical Y direction, which can also be understood as the thickness of the second fill layer 66 on the second sacrificial layer 65) is slightly smaller than that of the second fill layer 66 located in core region B. However, the height difference between the two is within the allowable range of process error, so the height difference will not affect subsequent processes. In addition, since the second mask layer 60 located in peripheral region C does not form the second preset pattern S21, the height of the second fill layer 66 in peripheral region C is greater than that in core region B, and the height difference between the two is relatively large.

[0088] B5: Remove the second sacrificial layer 65 and form a second pattern S2 between the second filler layer 66 and the second mask layer 60.

[0089] like Figure 14 and Figure 15 As shown, the second sacrificial layer 65 can be removed using an etching process, and the first anti-reflective layer 64 can also be removed using an etching process, as shown. Figure 15 As shown, a second pattern S2 is formed between the second filler layer 66 and the second spin coating layer 63.

[0090] S240: Based on the second pattern S2, the first mask layer 40 with the first pattern S1 is etched so that the first mask layer 40 located in the array region A and the core region B forms the third pattern S3.

[0091] like Figure 16 As shown, after the second pattern S2 is formed, the second pattern S2 is transferred to the first mask layer 40 having the first pattern S1 using an etching process, so that a third pattern S3, which is a combination of the first pattern S1 and the second pattern S2, is formed in the first mask layer 40 located in the array region A and the core region B.

[0092] Specifically, the second pattern S2 between the second filler layer 66 and the second swirl coating layer 63 can be transferred to the first oxide layer 62 and the first swirl coating layer 61 first, and then the second pattern S2 in the first oxide layer 62 and the first swirl coating layer 61 can be transferred to the first mask layer 40, so that the second pattern S2 combines with the first pattern S1 in the first mask layer 40 to form the third pattern S3. The first oxide layer 62 and the first swirl coating layer 61 can be removed by etching, that is, the second mask layer 60 can be removed, such as... Figure 16 As shown, the first mask layer 40 with the third pattern S3 is exposed.

[0093] In some embodiments, the second pattern S2 is located directly above the first mask layer 40 having the first pattern S1, such that the density of the third pattern S3 is twice the density of the first pattern S1.

[0094] like Figure 15 As shown, in some embodiments, the second pattern S2 is located at the middle position directly above the first mask layer 40, that is, the projection of the second pattern S2 along the vertical direction Y on the first mask layer 40 is located at the middle position of the first mask layer 40. This means that the first mask layer 40 between the first patterns S1 can be divided into two equal parts. Therefore, when the second pattern S2 is transferred to the first mask layer 40, the number of first mask layers 40 is doubled, and the density of the third pattern S3 formed is doubled compared to the density of the first pattern S1.

[0095] from Figure 16As can be seen, the third pattern S3 of the first mask layer 40 located in array region A and core region B meets the processing requirements and there is no over-etching or incomplete etching. Although the heights of the initial spin coating layer 50 and the second mask layer 60 above the first mask layer 40 located in the peripheral region C are higher than those of the initial spin coating layer 50 and the second mask layer 60 located in array region A and core region B, since the first pattern S1, the second pattern S2, and the third pattern S3 are all formed in array region A and core region B, and not in peripheral region C, no matter how high the initial spin coating layer 50 and the second mask layer 60 are located in the peripheral region, there will be no incomplete etching or over-etching in the first mask layer 40, ensuring the accuracy of etching and the integrity of the pattern, and improving the electrical performance of the semiconductor structure.

[0096] S250: A third mask layer 80 is formed on the first mask layer 40, and a fourth pattern S4 is formed in the first mask layer 40 located in the peripheral region C.

[0097] Specifically, such as Figure 17 As shown, S250 may include the following contents C1 to C4.

[0098] C1: A third mask layer 80 is formed on the first mask layer 40.

[0099] like Figure 17 As shown, a third mask layer 80 can be formed on the first mask layer 40 using a deposition process. The material of the third mask layer 80 is different from that of the first mask layer 40. In some embodiments, the first mask layer 40 can be made of silicon oxide, and the third mask layer 80 can be made of silicon nitride; no special limitation is made here. The third mask layer 80 can be a single layer or a multilayer stack.

[0100] Continue to refer to Figure 17 In some embodiments, a third mask layer 80 is formed on the first mask layer 40, including: forming a third spin coating layer 81 and a second anti-reflection layer 82 stacked sequentially on the first mask layer 40.

[0101] Specifically, a third spin coating layer 81 can be formed on the first mask layer 40 using a spin coating process. After the third spin coating layer 81 is formed and stabilized, a second anti-reflection layer 82 can be formed on the third spin coating layer 81 using other deposition processes. The material of the second anti-reflection layer 82 can be silicon oxynitride.

[0102] C2: A second photoresist layer 90 is formed on the third mask layer 80.

[0103] Continue to refer to Figure 17 A second photoresist layer 90 is formed on the third mask layer 80 using a deposition process. The second photoresist layer 90 can be a photoresist.

[0104] C3: A fourth pattern S4 is formed in the second photoresist layer 90 located in the outer region C.

[0105] refer to Figure 18 In some embodiments, a fourth pattern S4 can be formed in the second photoresist layer 90 located in the peripheral region C using exposure and development processes.

[0106] C4: Transfer the fourth pattern S4 to the third mask layer 80 and remove the second photoresist layer 90.

[0107] In some embodiments, the fourth pattern S4 based on the second photoresist layer 90 can be transferred to the third mask layer 80 by etching the second antireflective layer 82 and the third spin coating layer 81 using a wet etching process or a dry etching process.

[0108] In some embodiments, the second photoresist layer 90 may be removed using an etching process or a chemical mechanical polishing process.

[0109] In some embodiments, the density of the fourth pattern S4 is less than the density of the third pattern S3 located in the first mask layer 40 in the core region B. That is, in subsequent processes, after the fourth pattern S4 is transferred to the first mask layer 40, the density of the third pattern S3 in the core region B of the first mask layer 40 is greater than the density of the fourth pattern S4 located in the peripheral region C. Therefore, the density of the final metal line pattern will decrease from the core region B to the peripheral region C to meet the electrical performance requirements of the semiconductor structure.

[0110] Before the formation of the third mask layer 80, since no pattern is formed in the first mask layer 40 located in the peripheral region C, that is, the density of the third pattern S3 in the first mask layer 40 located in the array region A and the core region B is much greater than the pattern density (no pattern) of the first mask layer 40 located in the peripheral region C. Therefore, in some embodiments, due to the influence of the pattern density, after the third mask layer 80 is formed on the first mask layer 40, as... Figure 17 As shown, in the vertical direction Y, the height of the third mask layer 80 located in the peripheral region C is greater than the height of the third mask layer 80 located in the core region B. Here, in this embodiment of the disclosure, the vertical direction Y refers to the direction perpendicular to the surface of the substrate 10.

[0111] In some embodiments, the height of the third mask layer 80 located in the peripheral region C is 35–45 nm greater than the height of the third mask layer 80 located in the core region B. Specifically, in addition to the two extreme values ​​mentioned above, the height of the third mask layer 80 located in the peripheral region C is 36 nm, 37 nm, 38 nm, 39 nm, 40 nm, 41 nm, 42 nm, 43 nm, or 44 nm greater than the height of the third mask layer 80 located in the core region B, without any particular limitation. For example, the height of the third mask layer 80 located in the core region B is 51 nm, and the height of the third mask layer 80 located in the peripheral region C is 91 nm.

[0112] Although the aforementioned height difference is generated in the third mask layer 80 located in the core region B and the peripheral region C, in the embodiments of this disclosure, in S230 and S240, a second pattern S2 is formed in the second mask layer 60 located in the array region A and the core region B, and the first mask layer 40 is etched based on the second pattern S2. Since the first mask layer 40 located in the core region B has been etched synchronously with the array region A, in S250, the fourth pattern S4 is formed only in the portion of the third mask layer 80 in the peripheral region C. That is, only the third mask layer 80 located in the peripheral region C needs to be etched. However, in related technologies, in order to cut the lines formed in the core region B and the peripheral region C, the pattern of the core region B is not formed synchronously with the pattern of the array region A in the second mask layer 60 as in S230 and S240 of this disclosure, and the first mask layer 40 located in the core region B and the array region A is etched synchronously. Instead, the pattern of the core region B and the pattern of the peripheral region C are formed simultaneously in the third mask layer 80. However, due to the different heights of the third mask layer 80 located in the core region B and the peripheral region C, when etching the third mask layer 80, the portion located in the peripheral region C may be incompletely etched or the portion located in the core region B may be over-etched, thus causing defects.

[0113] In this embodiment, the core region B and the array region A are etched simultaneously, and only the peripheral region C is etched in the third mask layer 80. This is different from the third mask layer 80 in related technologies where the core region B and the peripheral region C are etched simultaneously. This avoids the defects caused by the height difference mentioned above, such as incomplete etching of the peripheral region C or over-etching of the core region B, thereby improving the yield of the semiconductor structure without increasing the complexity of the process steps.

[0114] In some embodiments, steps S230 and S240 can be executed first, i.e., a second mask layer 60 can be formed on the first mask layer 40, and a second pattern S2 can be formed in the second mask layer 60 located in the array region A and the core region B. Based on the second pattern S2, the first mask layer 40 having a first pattern S1 is etched, and a third pattern S3 is formed in the first mask layer 40 located in the array region A and the core region B. Then, step S250 is executed, i.e., a third mask layer 80 is formed on the first mask layer 40, and a fourth pattern S4 is formed in the third mask layer 80 located in the peripheral region C. Of course, in other embodiments, step S250 can be executed first, i.e., a third mask layer 80 is formed on the first mask layer 40, and a fourth pattern S4 is formed in the third mask layer 80 located in the peripheral region C. Then, steps S230 and S240 are executed. Since S230 and S240 operate in array area A and core area B, and S250 operates in peripheral area C, they do not affect each other, so the execution order is not important.

[0115] S260: Transfer the fourth pattern S4 to the first mask layer 40 located in the peripheral region C.

[0116] like Figure 19 As shown, the fourth pattern S4 based on the third mask layer 80 can be transferred to the first mask layer 40 with the third pattern S3 using an etching process, so that the first mask layer 40 located in the array region A, the core region B and the peripheral region C all have patterns corresponding to the metal lines.

[0117] S270: Based on the third pattern S3 and the fourth pattern S4, the metal layer 20 is etched to form a metal line.

[0118] Based on the third pattern S3 and the fourth pattern S4 of the first mask layer 40, the metal layer 20 can be etched using an etching process to form the metal lines of the desired pattern.

[0119] In some embodiments, such as Figure 3 As shown, after forming the metal layer 20 on the substrate 10 in step S220, the process further includes: forming a hard mask layer 30 on the metal layer 20; forming a dielectric layer 31 on the hard mask layer; and forming a first mask layer 40 on the dielectric layer 31. The dielectric layer 31 can be made of silicon oxynitride. When etching the first mask layer 40, the dielectric layer 31 can act as an etching stop layer to protect the hard mask layer 30 from damage.

[0120] In some embodiments, the material of the hard mask layer 30 may include at least one of polysilicon and carbon, and the hard mask layer 30 may be formed on the metal layer 20 using a deposition process.

[0121] In some embodiments, S270 may include: transferring the third pattern S3 and the fourth pattern S4 of the first mask layer 40 to the hard mask layer 30 and the dielectric layer 31, and removing the dielectric layer 31; based on the third pattern S3 and the fourth pattern S4 in the hard mask layer 30, etching the metal layer 20 to form a metal line.

[0122] like Figure 19 As shown, after the third pattern S3 and the fourth pattern S4 are formed in the first mask layer 40, as Figure 20 As shown, the fourth pattern S4 can be transferred to the hard mask layer 30 using an etching process, and then the hard mask layer 30 can be used as follows: Figure 21 As shown, the third pattern S3 and the fourth pattern S4 are transferred to the metal layer 20 to form a metal line with the desired pattern.

[0123] After the metal lines are formed, the hard mask layer 30 can be removed using etching or chemical mechanical polishing.

[0124] In some embodiments, according to the electrical performance requirements of the semiconductor structure, the density of the metal wire pattern gradually decreases from the array region A to the core region B. Therefore, during the fabrication process of the semiconductor structure, such as Figure 8 As shown, the density of the first pattern S1 in the first mask layer 40 located in the array region A is greater than the density of the first pattern S1 located in the core region B. Therefore, when forming the second mask layer 60 (as shown in the image), the density of the first pattern S1 is greater than the density of the first pattern S1 located in the core region B. Figure 9 As shown, the height of the second mask layer 60 located in the core region B is slightly greater than the thickness of the second mask layer 60 located in the array region A. For example, the height of the portion of the second mask layer 60 located in the core region B is 5-10 nm greater than the height located in the array region A. Specifically, in addition to the two extreme values, this thickness can also be 6 nm, 8 nm, or 9 nm. Since this height difference is less than 10 nm, when etching the second mask layer 60 located in the array region A and the core region B in S230 to form the second pattern S2, there will be no defects caused by etching size deviation, and the yield of the semiconductor structure will not be affected.

[0125] In summary, the semiconductor structure fabrication method of this disclosure involves simultaneously etching the core region B and the array region A after forming the second mask layer 60, so that the first mask layer 40 has a third pattern S3. Although the pattern density in the first mask layer 40 located in the core region B is greater than the pattern density in the first mask layer 40 located in the peripheral region C before the formation of the third mask layer 80, resulting in the height of the third mask layer 80 located in the peripheral region C being greater than the height located in the core region B, the fourth pattern S4 is formed only in the third mask layer 80 located in the peripheral region C. Therefore, when etching the third mask layer 80, only the third mask layer 80 located in the peripheral region C is etched, and the third mask layer 80 located in the core region B is not etched simultaneously. This avoids etching defects caused by the height difference between the third mask layers 80 located in the peripheral region C and the core region B, thereby improving the yield of the semiconductor structure and enabling the fabrication of a semiconductor structure with high-density patterns, thus improving the electrical performance of the semiconductor structure.

[0126] This disclosure also provides a semiconductor structure prepared by the method described in any of the above embodiments. The specific method steps will not be repeated here.

[0127] The semiconductor structure prepared using the preparation method of the present disclosure reduces defects generated during the preparation process, improves the yield and electrical performance of the semiconductor structure.

[0128] It should be understood that this disclosure is not limited to the detailed structure and arrangement of the components presented in this specification. This disclosure is capable of other embodiments and can be implemented and performed in various ways. The foregoing variations and modifications fall within the scope of this disclosure. It should be understood that this disclosure, as disclosed and defined in this specification, extends to all alternative combinations of two or more individual features mentioned or apparent in the text and / or drawings. All these different combinations constitute multiple alternative aspects of this disclosure. The embodiments described in this specification illustrate the best known mode for implementing this disclosure and will enable those skilled in the art to adopt this disclosure.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, include: A substrate is provided, the substrate comprising an array region, a core region, and a peripheral region; A metal layer and a first mask layer are formed in sequence on the substrate, and a first pattern is formed in the first mask layer located in the array region and the core region; A second mask layer is formed on a first mask layer on which the first pattern is formed, and a second pattern is formed in the second mask layer located in the array region and the core region; Based on the second pattern, a first mask layer having the first pattern is etched to form a third pattern in the first mask layer located in the array region and the core region; A third mask layer is formed on the first mask layer, and only the third mask layer located in the peripheral region is etched, and a fourth pattern is formed in the third mask layer located in the peripheral region; The fourth pattern is transferred to the first mask layer located in the peripheral region; Based on the third and fourth patterns, the metal layer is etched to form metal lines.

2. The method according to claim 1, characterized in that, Forming a second mask layer on a first mask layer having the first pattern, and forming a second pattern in the second mask layer located in the array region and the core region, including: A second mask layer is formed on the first mask layer on which the first pattern is formed; A second preset pattern is formed in the second mask layer; A second sacrificial layer is conformally formed on a second mask layer having the second preset pattern; A second filler layer is filled between the second sacrificial layers; Remove the second sacrificial layer and form the second pattern between the second filler layer and the second mask layer.

3. The method according to claim 2, characterized in that, Forming a second preset pattern in the second mask layer includes: A first photoresist layer is formed on the second mask layer; The second preset pattern is formed in the first photoresist layer; The second preset pattern is transferred to the second mask layer, and the first photoresist layer is removed.

4. The method according to any one of claims 1 to 3, characterized in that, In the vertical direction, the second pattern is located directly above the first mask layer having the first pattern, and the density of the third pattern is twice the density of the first pattern.

5. The method according to any one of claims 1 to 3, characterized in that, A third mask layer is formed on the first mask layer, and only the third mask layer located in the peripheral region is etched, forming a fourth pattern in the third mask layer located in the peripheral region, including: A third mask layer is formed on the first mask layer; A second photoresist layer is formed on the third mask layer; A fourth pattern is formed in the second photoresist layer located in the peripheral region; Only the third mask layer located in the peripheral area is etched, the fourth pattern is transferred to the third mask layer, and the second photoresist layer is removed.

6. The method according to any one of claims 1 to 3, characterized in that, Forming a first pattern in a first mask layer located in the array region and the core region includes: An initial spin coating layer is formed on the first mask layer; A first preset pattern is formed in the initial swirl coating located in the array region and the core region; A first sacrificial layer is conformally formed on the initial spin coating having the first preset pattern; Fill the spaces between the first sacrificial layers with a first filler layer; Remove the first sacrificial layer and form the first pattern between the first filler layer and the initial spin coating layer; The first pattern is transferred into the first mask layer.

7. The method according to claim 6, characterized in that, Forming a first preset pattern in the initial swirl coating located in the array region and the core region includes: An initial photoresist layer is formed on the initial spin coating layer; The first preset pattern is formed in the initial photoresist layer located in the array region and the core region; The first preset pattern is transferred to the initial spin coating.

8. The method according to any one of claims 1 to 3, characterized in that, The density of the fourth pattern is less than the density of the third pattern in the first mask layer located in the core region.

9. The method according to any one of claims 1 to 3, characterized in that, After forming the metal layer on the substrate, the method further includes: A hard mask layer is formed on the metal layer; A dielectric layer is formed on the hard mask layer; The first mask layer is formed on the dielectric layer.

10. The method according to claim 9, characterized in that, Based on the third and fourth patterns, the metal layer is etched to form metal lines, including: The third and fourth patterns in the first mask layer are transferred to the hard mask layer and the dielectric layer, and the dielectric layer is removed; Based on the third and fourth patterns in the hard mask layer, the metal layer is etched to form the metal line.

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