Wafer level nanometer air channel transistor preparation method based on tilt angle deposition

Abstract

The application provides a wafer-level nanometer air channel transistor preparation method based on an inclination angle deposition, and belongs to the technical field of semiconductor transistors. The method forms a patterned step on a substrate, forms a horizontal nanometer air channel between the upper and lower parts of the patterned step by using the self-shadow shielding effect of the patterned step, controls the size of the formed nanometer air channel by controlling the height of the patterned step and the angle of the inclination angle deposition, and the precision can reach the nanometer level. The edge of the film generated by the inclination angle deposition is a sharp triangular structure, which is beneficial to increasing a field enhancement factor and improving the performance of a device. The method is compatible with a semiconductor process, can realize batch preparation of a large-area wafer-level horizontal nanometer air channel transistor array, has the advantages of high yield, process consistency and good repeatability, is suitable for wafer-level preparation of nanometer air channel diode devices, and is suitable for wafer-level preparation of nanometer air channel triode devices with different structures such as a back gate, a top gate and a side gate.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor transistor technology, specifically relating to a wafer-level nano-air channel transistor fabrication method based on tilt deposition. Background Technology

[0002] Semiconductor transistors are limited by lattice scattering and carrier transport speed in solids, making it difficult to further improve response speed and operating frequency. Furthermore, heat generation and power consumption are becoming increasingly prominent issues. Vacuum is an ideal medium for high-speed ballistic electron transport, where electrons can travel at near-light speeds, three orders of magnitude faster than carrier transport speeds in semiconductors. Recently, nanoscale air-channel transistors have emerged, combining the advantages of vacuum and solid-state electronic devices. By reducing the cathode-anode or source-drain-gate spacing to the nanoscale, the channel size for electron transport is reduced to below its mean free path in air, allowing electrons to perform ballistic transport in air without a vacuum. Thanks to the significantly reduced channel size, nanoscale air-channel transistors can operate at low voltages comparable to semiconductor transistors and can be fabricated using semiconductor micro / nano processes, offering significant advantages such as miniaturization, high integration, and large-scale mass production. Compared to traditional solid-state semiconductor devices, the electron transport process of this type of device is not affected by scattering in the solid lattice. With the same channel size and device area, its response speed and operating frequency can be far higher than those of semiconductor transistors. It can operate in ultra-high frequency bands above millimeter waves, terahertz, and even petahertz. Furthermore, it possesses a series of advantages such as low heat generation, low power consumption, radiation resistance, and tolerance to high and low temperatures. Therefore, nano-air channel transistors are expected to become another revolutionary and disruptive type of transistor after traditional vacuum transistors and solid-state semiconductor transistors.

[0003] Most reported nano-air-channel transistors are fabricated using sophisticated nanoscale processes such as electron beam lithography and focused ion beam etching. These methods are highly dependent on expensive nanofabrication equipment, and suffer from low yields, poor process consistency and repeatability, making large-area mass production impossible. In response, several new fabrication methods for nano-air-channel transistors have been reported in recent years. For example, patent CN 112103158 A proposes a method for fabricating vertical nano-air-channel diodes using selective etching of nanofilms. However, this method is only suitable for vertical nano-air-channel structures and is not applicable to horizontal nano-air-channel transistors with smaller capacitance and greater bandwidth. Patent CN 112951916 A proposes a nano-air-channel transistor based on sidewall technology and its fabrication method, which can be used for horizontal nano-air-channel transistors. However, the chemical mechanical polishing (CMP) process used in this method is greatly affected by wafer warpage and has limited control precision, making it difficult to fabricate uniform device arrays on large-area wafers. Some literature also reports the use of semiconductor-incompatible processes such as self-assembled micro / nanosphere masks or metal fractures to create gaps to fabricate horizontal nano-air channel transistors. Overall, truly suitable large-area wafer-level fabrication processes for horizontal nano-air channel transistors remain extremely scarce, representing a bottleneck hindering their practical application. Therefore, there is an urgent need to develop a method with nanometer-level processing precision suitable for mass production on large-area wafers to reduce the fabrication cost of nano-air channel transistors and promote their practical application. Summary of the Invention

[0004] To address the shortcomings of existing technologies, this invention proposes a wafer-level nano-air channel transistor fabrication method based on tilt deposition. The aim is to provide a method that achieves nanometer-level channel processing precision, is fully compatible with semiconductor processes, exhibits good repeatability, stability, and consistency, does not rely on expensive nanofabrication equipment, is low-cost, has high yield, and can be used to mass-produce nano-air channel transistors on large-area wafers.

[0005] The above-mentioned technical objective of the present invention is achieved through the following technical solution:

[0006] A method for fabricating wafer-level nano-air channel transistors based on tilt deposition, characterized in that the method includes the following steps:

[0007] S1. Forming patterned steps on the substrate;

[0008] S2. Angle deposition is used to form horizontal nano-air channels between the upper and lower parts of the steps by utilizing the self-shadowing effect of the edges of the patterned steps;

[0009] The size of the formed nano-air channels is controlled by controlling the height of the patterned step in S1 and the angle of the tilt deposition in S2.

[0010] S3. The horizontal nano-air channel can be used directly as the channel of a nano-air channel transistor, or as a pattern mask, to transfer the gap between the nano-air channels to the underlying material through further etching or etching.

[0011] S4. For horizontal structure nano-air channel diodes: Patterning is performed by photolithography to form the nano-air channel diode with the desired structure.

[0012] For a vertical source-drain side-gate structure nano-air channel transistor: the patterned steps formed in S1 include a source thin film, a middle nano-insulating layer, and a drain thin film; in S2, a gate thin film is deposited at an angle to achieve self-alignment of the source, drain, and gate; further, part of the source or drain and the middle nano-insulating layer on the patterned steps are removed to expose the drain or source, forming the desired vertical source-drain side-gate structure nano-air channel transistor.

[0013] For a back-gate structure nano-air channel transistor: the horizontal nano-air channel in S3 is patterned to form the source and drain; the gate is further fabricated on the back side of the substrate directly below the horizontal nano-air channel to form the desired back-gate structure nano-air channel transistor.

[0014] For a top-gate nano-air channel transistor: the patterned step formed in S1 includes a first lower source film or a first lower drain film and an upper photoresist; the tilted deposited film in S2 includes a second lower drain film or a second lower source film, a middle nano-insulating layer and an upper gate film; the upper photoresist and the tilted deposited film on the patterned step are stripped away to achieve self-alignment of the source / drain and the gate; further, the tilted deposited film under the patterned step is patterned and part of the middle nano-insulating layer and the upper gate film are removed to expose the drain or source, forming the desired top-gate nano-air channel transistor.

[0015] For a horizontal source-drain dual-gate nano-air channel transistor: the pattern step formed in S1 includes a lower source film or a lower drain film and a first upper photoresist layer; the film deposited at the tilt angle in S2 is a lower drain film or a lower source film; after forming the first nano-air channel in S3, a second photoresist pattern is formed on one side perpendicular to the first nano-air channel, and excess source and drain films are removed to form a second pattern step; the first gate film is deposited at the tilt angle of the second pattern step, forming a second nano-air channel between the source film, the drain film, and the first gate film. Simultaneously, source-drain and gate self-alignment is achieved; after stripping the second photoresist and first gate film on the second pattern step, a third photoresist pattern is formed on the other side perpendicular to the first nano-air channel, and excess source and drain films are removed to form the third pattern step; the second gate film is deposited using the tilt angle of the third pattern step, and the third nano-air channel is formed between the source film, drain film and the second gate film, while simultaneously achieving source-drain and gate self-alignment; excess source film, drain film and second gate film are stripped and patterned to remove, forming a horizontal source-drain dual-gate structure nano-air channel transistor.

[0016] The advantages of this invention are as follows:

[0017] 1. The tilt deposition method proposed in this invention utilizes the self-shading effect of the stepped structure edges during the deposition process to prepare nano-air channel structures, such as... Figure 1 As shown, the nanochannel size can be easily adjusted by controlling the thickness of the step and the angle of the deposition tilt, with control precision reaching the nanometer level. Figure 7 , 8 As shown. It does not rely on expensive nanofabrication equipment, is low-cost, simple and easy to implement, fully compatible with semiconductor processes, and has good repeatability, stability and consistency. It is suitable for mass production of large-area wafer-level nano-air channel transistor arrays and has real practicality.

[0018] 2. The tilt deposition method proposed in this invention is not limited by the depth ratio of traditional patterning and etching processes. By adjusting the thickness of the thin film deposited at the tilt angle, it is suitable for the fabrication of nano-air channel transistors with a large depth ratio.

[0019] 3. Due to the self-shading effect of the steps, the tilt deposition method will not deposit thin films on the sidewalls of the steps, making it very suitable for obtaining high-yield nano-air channel transistor arrays through the lift-off process.

[0020] 4. The nano-air channel generated by tilt deposition has a relatively sharp triangular structure on one side of the film edge, which is beneficial to increase the field enhancement factor and obtain a low turn-on voltage and a large emission current.

[0021] 5. The tilt deposition method proposed in this invention provides a self-alignment function for the source, drain and gate of the nano-air channel transistor with top gate and side gate structure while forming the channel, thus avoiding the overlay error problem when the nano-air channel and gate are generated by traditional photolithography. Attached Figure Description

[0022] Figure 1 This is a schematic diagram illustrating the basic principle of the wafer-level nano-air channel transistor fabrication method based on tilt deposition proposed in this invention.

[0023] Figure 2 This is a schematic diagram of the process flow for a horizontal nano-air channel diode fabrication method based on tilt deposition proposed in this invention. Wherein: 11, insulating substrate; 12, cathode film; 13, first photoresist; 141, anode film on the step; 142, anode film below the step; 15, nano-air channel; 16, second photoresist.

[0024] Figure 3 This is a schematic diagram of the fabrication process of a vertical source / drain and horizontal gate structure nano-air channel transistor based on tilt deposition proposed in this invention. Wherein: 21, insulating substrate; 22, source thin film; 23, nano-insulating layer; 24, drain thin film; 25, photoresist; 261, gate thin film on the step; 262, gate thin film below the step; 27, in-plane nano-air channel between the source and drain.

[0025] Figure 4 This is a schematic diagram of the fabrication process of a nano-air channel transistor with a horizontal channel and vertical back gate structure based on tilt deposition, as proposed in this invention. Wherein: 31, Si substrate; 32, oxide thin film; 33, Si thin film; 34, first photoresist; 351, metal thin film on the step; 352, metal thin film below the step; 36, second photoresist; 371, upper metal thin film; 372, metal cathode; 373, metal anode; 38, back gate; 39, horizontal nano-air channel between source and drain.

[0026] Figure 5 This is a schematic diagram of the fabrication process of a nano-air channel transistor with a horizontal channel and vertical top gate structure based on tilt deposition, as proposed in this invention. Wherein: 41, insulating substrate; 42, drain film; 43, photoresist; 441, source film on the step; 442, source film below the step; 451, nano-insulating layer on the step; 452, nano-insulating layer below the step; 461, gate film on the step; 462, gate film below the step; 47, metal electrode; 48, nano-air channel between the source and drain.

[0027] Figure 6This is a schematic diagram of the fabrication process of a horizontal channel, dual-gate nano-air channel transistor based on tilt deposition proposed in this invention. Wherein: 51, insulating substrate; 52, source film; 53, first photoresist; 541, drain film on the step; 542, drain film below the step; 55, first nano-air channel; 56, second photoresist; 571, first gate film on the step; 572, first gate film below the step; 58, second nano-air channel; 59, third photoresist; 5101, second gate film on the step; 5102, second gate film below the step; 511, third nano-air channel.

[0028] Figure 7 This is a scanning electron microscope (SEM) image of a 450nm air channel formed by tilt deposition.

[0029] Figure 8 This is a scanning electron microscope image of the 25nm air channel formed by tilt deposition. Detailed Implementation

[0030] The technical solutions of the present invention will be further described below with reference to the accompanying drawings and embodiments.

[0031] Example 1

[0032] A method for fabricating horizontal nano-air channel diodes based on tilt deposition, the process flow of which is as follows: Figure 2 As shown, it includes the following steps:

[0033] S1. Growing a cathode film on an insulating substrate.

[0034] S2. Photolithography and etching to form a cathode thin film - first photoresist double-layer pattern step.

[0035] S3. An inclined deposition of anode thin films is adopted, and the self-shading effect of the edge of the patterned steps is used to form horizontal nano-air channels between the upper and lower parts of the steps.

[0036] The size of the formed nano-air channels is controlled by adjusting the height of the patterned steps and the angle of the tilt deposition in S2.

[0037] S4. Strip and remove the first photoresist and anode film on the step.

[0038] S5. Photolithography forms a second photoresist pattern on both sides of the horizontal nano-air channel.

[0039] S6. Etch excess cathode and anode films and remove the second photoresist to form a horizontal nano-air channel diode.

[0040] Example 2

[0041] A method for fabricating a vertical source / drain, horizontal gate structure nano-air channel transistor based on tilt deposition, the process flow of which is as follows: Figure 3 As shown, it includes the following steps:

[0042] S1. Source film, nano sacrificial layer and drain film are sequentially deposited on insulating substrate.

[0043] S2. Photolithography forms a photoresist pattern.

[0044] S3. Etching forms a patterned step from bottom to top: source thin film - nano sacrificial layer - drain thin film - photoresist.

[0045] S4. An inclined deposition of the gate film is adopted, and the self-shadowing effect of the edge of the pattern step is used to form a horizontal nano-air channel between the source and the gate between the upper and lower steps.

[0046] The size of the formed nano-air channels is controlled by adjusting the height of the patterned steps and the angle of the tilt deposition in S3.

[0047] S5. Strip away the photoresist and gate film on the step.

[0048] S6. Photolithography and etching remove part of the drain film and part of the nano sacrificial layer on the step to expose the source, and etch the nano sacrificial layer to form an in-plane nano air channel between the source and drain, thus completing the fabrication of a vertical source-drain and horizontal gate structure nano air channel transistor.

[0049] Example 3

[0050] A method for fabricating a nano-air channel transistor with a horizontal channel and vertical back-gate structure based on tilt deposition is described below. Figure 4 As shown, it includes the following steps:

[0051] S1. An oxide thin film and a Si thin film are sequentially prepared on a Si substrate to form an SOI substrate.

[0052] S2. Photolithography forms the first photoresist pattern step.

[0053] S3. A first metal thin film is deposited at an angle, and the self-shading effect of the edge of the pattern step is used to form a horizontal nano-air channel between the source and drain between the upper and lower steps.

[0054] The size of the formed nano-air channels is controlled by adjusting the height of the patterned steps and the angle of the tilt deposition in S2.

[0055] S4. Dry etching or wet etching is used to transfer horizontal nano-air channels into the Si thin film and remove the resist.

[0056] S5. Photolithography and deposition of a second metal thin film.

[0057] S6. Strip and pattern the second metal thin film to form the source and drain electrodes, deposit the back electrode on the back side of the Si substrate to form a horizontal channel, vertical back gate structure nano-air channel transistor.

[0058] Example 4

[0059] A method for fabricating a nano-air channel transistor with a horizontal channel and vertical top gate structure based on tilt deposition is described below. Figure 5 As shown, it includes the following steps:

[0060] S1. Deposit a drain film on an insulating substrate and generate a photoresist pattern using photolithography.

[0061] S2. Etching the drain film to form a drain film-photoresist double-layer pattern step.

[0062] S3. A source thin film, a nano-insulating layer, and a gate thin film are sequentially deposited using tilt deposition. The self-shading effect of the patterned step edges is utilized to form a horizontal nano-air channel between the source and drain between the upper and lower edges of the step. The size of the formed nano-air channel is controlled by adjusting the height of the patterned step in S2 and the tilt deposition angle.

[0063] S4. Strip away the photoresist, source film, nano-insulating layer and gate film on the patterned steps.

[0064] S5. Photolithography patterning and etching are used to remove part of the nano-insulating layer and part of the gate film under the step, exposing the source electrode.

[0065] S6. Photolithography is performed to fabricate electrodes on the source and drain electrodes, thus completing the fabrication of a horizontal channel and vertical top gate structure nano-air channel transistor.

[0066] Example 5

[0067] A method for fabricating a horizontal channel, double-gate nano-air channel transistor based on tilt deposition, the process flow of which is as follows: Figure 6 As shown, it includes the following steps:

[0068] S1. Deposit a source film on an insulating substrate, and use photolithography to form a source film-first photoresist first pattern step in the X-axis direction;

[0069] S2. Deposit a drain film along the X-axis using the tilt angle of the first pattern step to form a first nano-air channel.

[0070] S3. Strip and remove the first photoresist and drain film on the first pattern step.

[0071] S4. Photolithography and etching are used to remove excess source and drain films, forming a second pattern step in the positive Y-axis direction.

[0072] S5. Deposit the first gate film along the positive Y-axis using the second pattern step tilt angle to form the second nano-air channel.

[0073] S6. Remove the second photoresist and the first gate film from the second pattern step.

[0074] S7. Photolithography and etching are used to remove excess source film, drain film, and first gate film, forming a third pattern step in the negative Y-axis direction.

[0075] S8. A second gate film is deposited along the negative Y-axis using the tilt angle of the third pattern step to form a third nanometer air channel.

[0076] S9. Strip and pattern the removal of excess source film, drain film, and second film to prepare a horizontal channel, double-gate planar nano-air channel transistor.

[0077] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.

Claims

1. A method for fabricating wafer-level nano-air channel transistors based on tilt deposition, characterized in that, The method includes the following steps: S1. A patterned step is formed on a substrate, the patterned step comprising a first electrode thin film, a middle nano insulating layer, a second electrode thin film and photoresist arranged sequentially from bottom to top; S2. An inclined deposition of the gate film is adopted, and the self-shadowing effect of the edge of the patterned step is used to form a horizontal nano-air channel between the upper and lower steps; The size of the formed nano-air channels is controlled by controlling the height of the patterned step in S1 and the angle of the tilt deposition in S2. S3. Strip away the photoresist and gate film on the patterned steps; S4. Remove part of the second electrode film and part of the middle nano-insulating layer on the patterned step to expose the first electrode film; the first electrode film serves as the drain or source, and the second electrode film serves as the source or drain, forming the desired vertical source-drain side-gate structure nano-air channel transistor.

2. A method for fabricating wafer-level nano-air channel transistors based on tilt-angle deposition, characterized in that, The method includes the following steps: S1. A patterned step is formed on a substrate, the patterned step comprising a first lower electrode film and an upper photoresist layer; S2. The second lower electrode film, the middle nano insulating layer and the upper gate film are deposited sequentially by tilt deposition; the self-shadowing effect of the pattern step edge is used to form a horizontal nano air channel between the upper and lower steps; The horizontal nano-air channel serves as the channel for the nano-air channel transistor. The size of the formed nano-air channel is controlled by controlling the height of the pattern step in S1 and the angle of the tilt deposition in S2. S3. Remove the thin film and upper photoresist deposited at the tilt angle on the patterned steps; S4. Pattern the thin film deposited at the angle below the patterned step and remove part of the middle nano-insulating layer and part of the upper gate film to expose the second lower electrode film; S5. Using the first lower electrode film as the source or drain and the second lower electrode film as the drain or source, electrodes are fabricated above the first and second lower electrode films respectively to form the desired top-gate structure nano-air channel transistor.

Images