Chip carrier, method of forming the same, method of forming a wafer bond structure

Abstract

A chip carrier, a chip carrier forming method and a wafer bonding structure forming method, wherein the chip carrier forming method comprises: providing an initial substrate; forming a plurality of initial grooves in the initial substrate to form a substrate; forming a side wall structure on the sidewall surface of the initial groove to form a first opening in the initial groove, the side wall structure exposes the substrate surface, the thickness of the bottom of the side wall structure is greater than the thickness of the top of the side wall structure, the inner surface of each first opening is charged with a first polarity, the first surface of the chip structure is charged with a second polarity, and each first opening is used to fix a chip structure. The chip carrier, the chip carrier forming method and the wafer bonding structure forming method improve the alignment accuracy during the bonding process of the chip and the wafer, reduce the alignment difficulty, and improve the efficiency of the bonding integration process.

Description

[0001] The present application relates to the technical field of semiconductor, and particularly relates to a chip carrier, a forming method of the chip carrier, a wafer bonding structure and a forming method of the wafer bonding structure. BACKGROUND

[0002] Electronic integrated packaging is an important link of semiconductor integrated process. Among them, the traditional electronic packaging technology mainly takes 2D stacking as the main part, that is, electronic components are installed on the surface of the PCB substrate in a flat manner. Such 2D stacked chips have great limitations in performance, quantity, running speed and the like.

[0003] In recent years, the die on wafer integrated mode can make the density of the chips stacked in the three-dimensional direction larger and greatly improve the chip speed and power consumption by integrating different size chips (dies) on the target wafer through hybrid bonding.

[0004] However, in the existing die on wafer integrated mode, the alignment accuracy of the chip and the wafer still has great room for improvement, and the efficiency of the bonding integrated process is low, and the actual mass production is difficult. SUMMARY

[0005] The technical problem solved by the present application is to provide a chip carrier, a forming method of the chip carrier, a wafer bonding structure and a forming method thereof, which improves the alignment accuracy in the bonding process of the chip and the wafer, reduces the alignment difficulty and improves the efficiency of the bonding integrated process.

[0006] To solve the above technical problems, the technical scheme of the present application provides a forming method of a chip carrier, comprising: providing an initial substrate; forming a plurality of initial grooves in the initial substrate to form a substrate; forming a side wall structure on the side wall surface of the initial groove and forming a first opening in the initial groove, the side wall structure exposes the surface of the substrate, the thickness of the bottom of the side wall structure is greater than the thickness of the top of the side wall structure, and each first opening is used to fix a chip structure; and applying a first polarity charge to the inner surface of each first opening to make it have a first polarity charge.

[0007] Optionally, the forming method of the side wall structure comprises: forming a side wall material layer on the bottom surface, the side wall surface and the top surface of the substrate; and etching back the side wall material layer until the top surface of the substrate and the bottom surface of the initial groove are exposed, and the side wall structure is formed on the side wall surface of the initial groove.

[0008] Optionally, the side wall structure is a single-layer structure.

[0009] Optionally, the material of the side wall structure comprises silicon nitride or a flexible material.

[0010] Optionally, the side wall structure is a double-layer structure, and the side wall structure comprises a first side wall on the side wall surface of the initial groove and a second side wall on the surface of the first side wall, wherein the material hardness of the second side wall is less than the material hardness of the first side wall.

[0011] Optionally, the material of the first side wall comprises silicon nitride, and the material of the second side wall comprises polyvinyl alcohol, polyester, polyimide or polyethylene naphthalate.

[0012] Optionally, the side wall structure comprises a plurality of side walls, and the number of the side walls is greater than 2; the material hardness of each side wall is the same or different.

[0013] Optionally, the bottom size of each first opening is equal to the size of each chip structure.

[0014] Optionally, the material of the initial substrate comprises silicon oxide.

[0015] Correspondingly, the technical scheme of the present application further provides a chip carrier, comprising: a substrate, wherein the substrate is internally provided with a plurality of initial grooves; a side wall structure on the side wall surface of the initial groove, wherein the side wall structure exposes the surface of the substrate, the thickness of the bottom of the side wall structure is greater than the thickness of the top of the side wall structure; a first opening in the initial groove, wherein each first opening is used for fixing a chip structure; and the inner surface of each first opening is provided with an electric charge of a first polarity.

[0016] Optionally, the side wall structure is a single-layer structure.

[0017] Optionally, the material of the side wall structure comprises silicon nitride or a flexible material.

[0018] Optionally, the side wall structure is a double-layer structure, and the side wall structure comprises a first side wall on the side wall surface of the initial groove and a second side wall on the surface of the first side wall, wherein the material hardness of the second side wall is less than the material hardness of the first side wall.

[0019] Optionally, the material of the first side wall comprises silicon nitride, and the material of the second side wall comprises polyvinyl alcohol, polyester, polyimide or polyethylene naphthalate.

[0020] The technical scheme of the present application provides a wafer bonding structure forming method, characterized in that: forming a plurality of mutually separated chip structures, each of the chip structures comprising opposite first and second surfaces; applying a second polarity charge to the first surface of each of the chip structures to make it carry a second polarity charge; providing a chip carrier, the chip carrier comprising: a substrate having a plurality of initial grooves therein; a sidewall structure on the sidewall surface of the initial grooves, the sidewall structure exposing the surface of the substrate, the thickness of the bottom of the sidewall structure being greater than the thickness of the top of the sidewall structure; a plurality of first openings in the initial grooves; applying a first polarity charge to the inner surface of each of the first openings to make it carry a first polarity charge; fixing a chip structure in each first opening, the first surface of each chip structure being in direct contact with the surface of the substrate; providing a target wafer, the target wafer having opposite third and fourth surfaces; after fixing the chip structures to the chip carrier, bonding the second surface of the chip carrier and the chip structures to the third surface of the target wafer to electrically connect the chip structures to the target wafer.

[0021] Optionally, the method for forming each chip structure comprises: providing an initial wafer structure, the initial wafer structure having a plurality of chip regions and a cutting channel region between adjacent chip regions; cutting the initial wafer structure along the cutting channel region to form a plurality of chip structures.

[0022] Optionally, the process for cutting the initial wafer structure comprises: a plasma dry etching cutting process.

[0023] Optionally, the initial wafer structure comprises: an initial wafer device layer; an initial dielectric layer on the initial wafer device layer; a first electrical interconnection layer in the initial dielectric layer; an initial first protective layer on the surface of the first electrical interconnection layer and the initial dielectric layer; after cutting the initial wafer structure, the initial wafer device layer becomes a first device layer, the initial dielectric layer becomes a first dielectric layer, the initial first protective layer becomes a first protective layer, the exposed surface of the first device layer becomes the first surface of each chip structure, and the exposed surface of the first protective layer becomes the second surface of each chip structure.

[0024] Optionally, before cutting the initial wafer structure, the method further comprises: bonding the initial first protective layer to an initial carrier; bonding the initial wafer device layer to the surface of an adhesive structure; removing the initial carrier to expose the surface of the initial first protective layer; and after forming each chip structure, the method further comprises: removing the adhesive structure.

[0025] Optionally, after fixing each chip structure to the chip carrier, the method further comprises: filling a second protective layer on the surface of each chip structure and the surface of the substrate; planarizing the second protective layer; and forming a first hybrid bonding plug in the second protective layer.

[0026] Optionally, the target wafer comprises: a second device layer, the second device layer has an electrical connection plug therein; a third dielectric layer on a surface of the second device layer; a second electrical interconnection layer in the third dielectric layer; a fourth dielectric layer on a surface of the third dielectric layer and the second electrical interconnection layer; a second hybrid bonding plug in the fourth dielectric layer, the third surface exposes the second hybrid bonding plug, and the fourth surface exposes the second device layer.

[0027] Optionally, after the chip structure is bonded to the target wafer, the method further comprises: thinning the second device layer until the electrical connection plug is exposed; and forming a solder ball on a surface of the electrical connection plug.

[0028] Correspondingly, the technical scheme of the present application also provides a wafer bonding structure, comprising: a chip carrier, the chip carrier comprises: a substrate, the substrate has a plurality of initial grooves therein; a side wall structure on a surface of a side wall of the initial groove, the side wall structure exposes a surface of the substrate, a thickness of a bottom of the side wall structure is greater than a thickness of a top of the side wall structure; a plurality of first openings in the initial grooves; a chip structure fixed in each first opening, each chip structure has opposite first and second surfaces, and the first surface of each chip structure directly contacts the surface of the substrate; and a target wafer, the target wafer has opposite third and fourth surfaces, the second surface of the chip structure is bonded to the third surface of the target wafer, so that the chip structure is electrically connected to the target wafer.

[0029] Optionally, the material of the substrate comprises silicon or glass.

[0030] Compared with the prior art, the technical scheme of the embodiment of the present application has the following beneficial effects:

[0031] The technical scheme of the present application provides a chip carrier forming method, in which an initial groove is formed in the substrate, and a side wall structure is formed on the sidewall surface of the initial groove, the thickness of the bottom of the side wall structure is greater than the thickness of the top of the side wall structure, thereby forming a first opening in the exposed part of the side wall structure, applying a charge of a first polarity to the inner surface of the first opening to make it have a charge of a first polarity, applying a charge of a second polarity to the first surface of the chip structure to make it have a charge of a second polarity, and using the attractive force of the opposite charges to achieve self-alignment positioning of the chip structure in the substrate during the process of placing the chip structure in the corresponding first opening; further, the opening morphology of the initial groove is adjusted by the side wall structure, so that the size of the top of the first opening is greater than the size of the bottom, and therefore, the larger top opening provides more redundant space for the placement of the chip structure, reducing the difficulty of precise positioning; after the chip structure is placed in the corresponding first opening, the self-alignment positioning of the chip structure in the substrate can be achieved by the gradually shrinking sidewall morphology of the first opening from top to bottom; and finally, the dual self-alignment function of polarity attraction and self-alignment sidewall is formed, which makes the chip structure more accurately fit the predetermined position of the substrate, thereby improving the positioning accuracy of the chip structure, reducing the difficulty of precise positioning, reducing the time required for positioning, and improving the positioning efficiency.

[0032] Further, the material of the side wall structure includes a flexible material, which has a protective effect on the sidewall of the chip structure during the self-alignment process of the chip structure in the first opening, and the flexible material is more easily deformed, thereby making the chip structure fit the sidewall of the first opening better and reducing the gap and air bubbles between the chip structure and the surrounding structure.

[0033] The chip carrier provided by the technical scheme has the side wall structure on the side wall surface of the initial groove, the thickness of the bottom of the side wall structure is greater than the thickness of the top of the side wall structure, and thus the part exposed by the side wall structure becomes a first opening; the inner surface of the first opening is charged with a first polarity by applying an electric charge of the first polarity to the inner surface; the first surface of the chip structure is charged with a second polarity by applying an electric charge of the second polarity to the first surface; in the process of placing the chip structure into the corresponding first opening, the self-alignment positioning of the chip structure in the substrate is realized by using the attraction of the opposite charges; the opening morphology of the initial groove is adjusted by the side wall structure, so that the size of the top of the first opening is greater than the size of the bottom, and thus the larger top opening provides more redundant space for the placement of the chip structure, and the difficulty of accurate positioning is reduced; after the chip structure is placed into the corresponding first opening, the self-alignment positioning of the chip structure in the substrate is realized by the side wall morphology of the first opening which gradually shrinks from top to bottom, and finally the dual self-alignment function of polarity attraction and self-alignment side wall is formed, so that the chip structure is more accurately attached to the predetermined position of the substrate, thereby improving the positioning accuracy of the chip structure, reducing the difficulty of accurate positioning, reducing the time required for positioning, and improving the positioning efficiency.

[0034] The chip carrier includes the side wall structure which adjusts the opening morphology of the initial groove of the substrate, so that the size of the top of the first opening is greater than the size of the bottom, and different polarities of electric charges are applied to the inner surface of the first opening and the first surface of the chip structure; in the process of placing the chip structure into the corresponding first opening, the self-alignment positioning of the chip structure in the substrate is realized by using the attraction of the opposite charges; finally, the dual self-alignment function of polarity attraction and self-alignment side wall is formed, thereby improving the positioning accuracy of the chip structure on the substrate, reducing the difficulty of accurate positioning, reducing the time required for positioning, improving the positioning efficiency, and further improving the accuracy and efficiency of the bonding of the chip structure and the target wafer.

[0035] The chip carrier includes the side wall structure which adjusts the opening morphology of the initial groove of the substrate, so that the size of the top of the first opening is greater than the size of the bottom, and different polarities of electric charges are applied to the inner surface of the first opening and the first surface of the chip structure; in the process of placing the chip structure into the corresponding first opening, the self-alignment positioning of the chip structure in the substrate is realized by using the attraction of the opposite charges; finally, the dual self-alignment function of polarity attraction and self-alignment side wall is formed, thereby improving the positioning accuracy of the chip structure on the substrate, reducing the difficulty of accurate positioning, and further improving the accuracy of the bonding of the chip structure and the target wafer. BRIEF DESCRIPTION OF DRAWINGS

[0036] Figures 1 to 5is a cross-sectional structure schematic diagram of a forming process of a chip carrier of an embodiment of the present application;

[0037] Figures 6 to 17 is a cross-sectional structure schematic diagram of a forming process of a wafer bonding structure of an embodiment of the present application. Embodiments

[0038] As described in the background, in the existing integration mode of "chip on wafer", the alignment accuracy of the chip and the wafer still has a large space for improvement, and the bonding integration process is low in efficiency and difficult in actual mass production.

[0039] In a bonding process of "chip on wafer", after the initial wafer is prepared, the initial wafer is cut into a plurality of chips (die); a target wafer is provided, and the surface of the target wafer is marked with a chip predetermined bonding position; and each chip is bonded to the corresponding predetermined bonding position on the surface of the target wafer according to the chip predetermined bonding position. In the process of bonding the chip and the target wafer, it is difficult to align each chip with the predetermined bonding position on the target wafer, the alignment error is large, and the alignment time is long, which is not conducive to mass production.

[0040] In another bonding process of "chip on wafer", after the initial wafer is cut into a plurality of chips (die), the chip is grabbed by a mechanical device, and an adhesive is coated on the contact surface of the mechanical device and the chip; the chip is pre-attached to the surface of a carrier according to the predetermined bonding position of the chip to form a pre-integrated chip group; and the pre-integrated chip group is bonded to a target wafer to realize the bonding of each chip and the target wafer. In the process of pre-attaching the chip to the surface of the carrier, the error of aligning each chip with the predetermined bonding position on the surface of the carrier is large, and the alignment time is long. In addition, in the process of grabbing the chip by the mechanical device, an adhesive is coated on the contact surface of the mechanical device and the chip, the adhesive is difficult to remove, and the residual adhesive can easily affect the bonding quality of the chip and the target wafer, resulting in poor bonding performance.

[0041] To solve the above technical problems, the technical scheme of the present application provides a chip carrier forming method, in which an initial groove is formed in a substrate, and a side wall structure is formed on the side wall surface of the initial groove, the thickness of the bottom of the side wall structure is greater than the thickness of the top of the side wall structure, so that a first opening is formed in the exposed part of the side wall structure, the opening morphology of the initial groove is adjusted by the side wall structure, the size of the top of the first opening is greater than the size of the bottom, therefore, the larger top opening provides more redundant space for the placement of the chip structure, and the difficulty of accurate positioning is reduced; after the chip structure is placed in the corresponding first opening, the self-alignment positioning of the chip structure in the substrate can be realized through the gradually shrinking side wall morphology of the first opening from top to bottom, and finally the chip structure is more accurately attached to the predetermined position of the substrate, so that the positioning accuracy of the chip structure is improved, the difficulty of accurate positioning is reduced, the time required for positioning is reduced, and the positioning efficiency is improved.

[0042] To make the above-mentioned purposes, features and benefits of the present application more obvious and easy to understand, the specific embodiments of the present application will be described in detail below with reference to the accompanying drawings.

[0043] Figures 1 to 5 is a cross-sectional structure schematic diagram of the chip carrier forming process of the embodiment of the present application.

[0044] Please refer to Figure 1 , an initial substrate 140 is provided; a mask layer 152 is formed on the surface of the initial substrate 140.

[0045] In the embodiment, the initial substrate 140 provides space and platform for the integration of subsequent chip structures.

[0046] In the embodiment, the material of the initial substrate 140 includes silicon or glass.

[0047] In the embodiment, the mask layer 152 exposes part of the surface of the initial substrate 140, and the mask layer 152 defines the position and size of the initial groove to be formed subsequently.

[0048] Please refer to Figure 2 , the initial substrate 140 is etched with the mask layer 152 as a mask, and a plurality of initial grooves 151 are formed in the initial substrate 140; the mask layer 152 is removed; an initial oxide layer (not shown) is formed on the side wall surface and the bottom surface of the initial groove 151 and the top surface of the initial substrate 140, thereby forming a substrate 150.

[0049] In the embodiment, the initial recesses 151 provide space for the chip structures to be integrated on the substrate 150, and the positions of the initial recesses 151 determine the positions of the chip structures to be integrated on the substrate 150, and the opening sizes of the initial recesses 151 correspond to the sizes of the chip structures.

[0050] For the convenience of understanding, the initial oxide layer is used to adjust the contact stress between the initial substrate 140 and other structures, and thus, in the subsequent embodiment description, the initial oxide layer is taken as a part of the substrate 150, and other structures in contact with the surface of the initial oxide layer are taken as being in direct contact with the surface of the substrate 150.

[0051] In the embodiment, the etching process of the initial substrate 140 includes a dry etching process.

[0052] Referring to Figure 3 A side wall material layer 155 is formed on the bottom, sidewall and top of the initial recess 151.

[0053] Specifically, the side wall material layer 155 is located on the surface of the initial oxide layer (not shown).

[0054] In the embodiment, the side wall material layer 155 provides raw material for the side wall structure to be formed subsequently.

[0055] Referring to Figure 4 The side wall material layer 155 is etched back until the surface of the top of the substrate 150 and the surface of the bottom of the initial recess 151 are exposed, a side wall structure 153 is formed on the sidewall surface of the initial recess 151, a first opening 161 is formed in the initial recess 151, the side wall structure 153 exposes the surface of the substrate 150, the thickness of the bottom of the side wall structure 153 is greater than the thickness of the top of the side wall structure 153, and each of the first openings 161 is used to fix a chip structure.

[0056] In the embodiment, the sidewall surface of the side wall structure 153 is a circular arc surface, the thickness of the side wall structure 153 gradually increases from the top to the bottom of the side wall structure 153, and the thickness refers to the size of the side wall structure 153 in the direction perpendicular to the sidewall surface of the initial recess 151. Due to the presence of the side wall structure 153, the size H2 of the top of each of the first openings 161 is greater than the size H1 of the bottom, and the size refers to the width of the first opening 161 in the direction parallel to the bottom surface of the substrate 150.

[0057] By forming the initial groove 151 in the initial substrate 140, the bonding position of the chip structure on the substrate 150 can be more accurately positioned. Compared with the traditional process of reading the bonding mark on the substrate to bond the chip structure, the predetermined bonding position of the chip structure is positioned by the initial groove 151 in the embodiment, so that the position error of the chip structure bonding is smaller. In addition, the thickness of the bottom of the side wall structure 153 formed on the sidewall of the initial groove 151 is greater than the thickness of the top of the side wall structure 153, so that the opening morphology of the initial groove 151 can be adjusted by the side wall structure 153, and the size H2 of the top of the first opening 161 between the adjacent side wall structures 153 is greater than the size H1 of the bottom. In the process of subsequently placing the chip structure into each first opening 161, the larger top opening provides more redundant space for the placement of the chip structure, reducing the difficulty of accurate positioning; after the chip structure is placed into the corresponding first opening 161, the self-alignment positioning of the chip structure in the substrate 150 can be realized by the gradually shrinking sidewall morphology of the first opening 161 from top to bottom, so that the chip structure is more accurately bonded with the predetermined position of the substrate 150, thereby improving the positioning accuracy of the chip structure, reducing the difficulty of accurate positioning, reducing the time required for positioning, and improving the positioning efficiency.

[0058] In the embodiment, the side wall structure 153 is a single-layer structure, and the material of the side wall structure 153 is silicon nitride. In the process of etching the side wall material layer 155, the process of etching back the silicon nitride is more mature, and the thickness of the top and the bottom of the formed side wall structure 153 can be more flexibly controlled, so as to form a side wall structure 153 with a small top thickness and a large bottom thickness.

[0059] In the embodiment, the thickness of the bottom of the side wall structure 153 ranges from 1 micrometer to 3 micrometers, so that the difference between the top size H2 and the bottom size H1 of the first opening 161 ranges from 2 micrometers to 10 micrometers.

[0060] In another embodiment, the material of the side wall structure is a flexible material. Therefore, in the self-alignment process of the chip structure in the first opening, the flexible material has a protective effect on the sidewall of the chip structure, and the flexible material is more easily deformed, so that the chip structure is better bonded with the sidewall of the first opening, and the gap and bubbles between the chip structure and the surrounding structure are reduced.

[0061] Specifically, the flexible material includes polyvinyl alcohol, polyester or polyimide, polyethylene naphthalate, or photoresist.

[0062] In another embodiment, the side wall structure is a double-layer structure, and the side wall structure comprises a first side wall located on the surface of the initial groove side wall and a second side wall located on the surface of the first side wall, and the material hardness of the second side wall is less than that of the first side wall. Specifically, the material of the first side wall comprises silicon nitride, and the material of the second side wall comprises polyvinyl alcohol, polyester or polyimide or polyethylene naphthalate.

[0063] In this embodiment, the side wall structure is a double-layer structure, and the material hardness of the first side wall and the second side wall is different. Therefore, by combining different materials, not only the top thickness of the side wall structure can be controlled by the more mature etching process of the hard material to form a side wall structure with large bottom thickness and small top thickness, but also the flexible material is formed on the surface of the hard material, and the flexible material is more easily deformed, so that the adhesion of the chip structure to the first opening side wall is better.

[0064] In other embodiments, the side wall structure comprises a plurality of side walls, and the number of the side walls is greater than 2; the material hardness of each side wall is the same or different, so that more choices are provided for the shape and hardness design of the side wall structure.

[0065] In this embodiment, after the side wall structure 153 is formed, the region of the initial groove 151 between the adjacent side wall structures 153 is the first opening 161. The bottom size of each first opening 161 is equal to the size of the chip structure placed in the first opening 161 subsequently.

[0066] In this embodiment, after the first opening 161 is formed, the inner surface of the first opening 161 is applied with the charge of the first polarity to make the inner surface of the first opening 161 have the charge of the first polarity; please refer to Figure 5 , the charge of the first polarity is a positive charge; in another embodiment, the charge of the first polarity is a negative charge.

[0067] In this embodiment, the chip carrier is arranged in a closed chamber, and the inner surface of the first opening 161 is sprayed by using a charge gun to apply the charge of the first polarity to make the inner surface of the first opening 161 have the charge of the first polarity; in addition, in another embodiment, a charged body with the charge of the first polarity can also be used to contact the inner surface of the first opening 161 to make the inner surface of the first opening 161 have the charge of the first polarity.

[0068] Correspondingly, the embodiment of the present application also provides a chip carrier formed by using the above method.

[0069] Please continue to refer to Figure 5The chip carrier comprises a substrate 150, the substrate 150 has a plurality of initial grooves 151, a sidewall structure 153 is arranged on the sidewall surface of the initial grooves 151, the sidewall structure 153 exposes the surface of the substrate 150, the thickness of the bottom of the sidewall structure 153 is greater than the thickness of the top of the sidewall structure 153, a first opening 161 is arranged in the initial groove 151, the first opening 161 is used for fixing a chip structure, and the inner surface of the first opening 161 is provided with an electric charge of a first polarity.

[0070] In the embodiment, the sidewall structure 153 is a single-layer structure.

[0071] In the embodiment, the material of the sidewall structure 153 comprises silicon nitride.

[0072] In another embodiment, the material of the sidewall structure comprises a flexible material.

[0073] In another embodiment, the sidewall structure is a double-layer structure, the sidewall structure comprises a first sidewall arranged on the sidewall surface of the initial groove and a second sidewall arranged on the surface of the first sidewall, the material hardness of the second sidewall is less than the material hardness of the first sidewall, the material of the first sidewall comprises silicon nitride, and the material of the second sidewall comprises polyvinyl alcohol, polyester, polyimide or polyethylene naphthalate.

[0074] Correspondingly, the embodiment of the present application further provides a forming method of a wafer bonding structure based on the above chip carrier.

[0075] Figures 6 to 17 is a cross-sectional structure schematic diagram of the forming process of the wafer bonding structure of the embodiment of the present application.

[0076] Firstly, a plurality of mutually independent chip structures are formed, and each chip structure comprises a first surface and a second surface. Specifically, the process of forming the chip structure is as shown in Figures 6 to 10 .

[0077] Please refer to Figure 6 , an initial wafer structure (not shown) is provided.

[0078] Specifically, the initial wafer structure comprises an initial wafer device layer 131, an initial dielectric layer 132 arranged on the initial wafer device layer 131, a first electric interconnection layer 104 arranged in the initial dielectric layer 132, a first etching stop layer 103 arranged on the surface of the first electric interconnection layer 104 and the initial dielectric layer 132, and an initial first protective layer 134 arranged on the surface of the first etching stop layer 103.

[0079] In the embodiment, the material of the initial dielectric layer 132 comprises silicon oxide, and the material of the initial first protective layer 134 comprises silicon oxide.

[0080] In the embodiment, the initial wafer structure has a plurality of chip regions (not shown) and a plurality of streets (not shown) between the adjacent chip regions, and the initial wafer structure is cut along the streets.

[0081] Referring to Figure 7 The initial first protective layer 134 is attached to the initial carrier 110.

[0082] In the embodiment, the material of the initial carrier 110 includes silicon oxide.

[0083] In the embodiment, the initial carrier 110 is used to assist the flipping process of the initial wafer structure.

[0084] Referring to Figure 8 The initial wafer device layer is attached to the surface of the adhesive structure 111.

[0085] In the embodiment, the adhesive structure 111 is used to fix the initial wafer structure, thereby facilitating the subsequent cutting process.

[0086] Referring to Figure 9 The initial carrier 110 is removed to expose the surface of the initial first protective layer 134, and the initial wafer structure is cut into a plurality of chip structures 120 along the streets.

[0087] In the embodiment, the process of cutting the initial wafer structure includes a plasma dry etching cutting process.

[0088] Compared with the traditional wafer cutting process, the plasma dry etching cutting process can further optimize the boundary morphology of the chip structure 120 after cutting and reduce the size error.

[0089] In the embodiment, after the initial wafer structure is cut, the initial wafer device layer 131 becomes the first device layer 100, the initial dielectric layer 132 becomes the first dielectric layer 101, and the initial first protective layer 134 becomes the first protective layer 102. The chip structure 120 includes the first device layer 100, the first dielectric layer 101, the first electrically interconnected layer 104, the first etching stop layer 103, and the first protective layer 102. The exposed surface of the first device layer 100 is the first surface of each chip structure 120, and the exposed surface of the first protective layer 102 is the second surface of each chip structure 120.

[0090] In the embodiment, the first protective layer 102 provides protection for the first electrically interconnected layer 104, and the first etching stop layer 103 is used as a stop layer in the subsequent planarization process.

[0091] Please refer to Figure 10 , remove the adhesive structure 111, and separate the chip structures 120 from each other.

[0092] In another embodiment, the process of cutting the initial wafer structure includes laser cutting, blade cutting, or a combination of the two.

[0093] In other embodiments, the process of attaching the initial carrier, the adhesive structure, and the initial wafer structure can be omitted, and the initial wafer structure can be directly cut.

[0094] In this embodiment, after forming the mutually separated chip structures 120, a second polarity charge is applied to the first surface of each chip structure to make it carry a second polarity charge; please refer to Figure 11 , the second polarity charge is a negative charge; in another embodiment, the second polarity charge is a positive charge.

[0095] In this embodiment, the chip structures 120 are placed in a closed chamber, and the first surface of the chip structure 120 is sprayed with a charge gun to apply a second polarity charge to make it carry a second polarity charge; in addition, in another embodiment, a charged body with a second polarity charge can also be used to contact the first surface of the chip structure 120 to make it carry a second polarity charge.

[0096] In this embodiment, the chip carrier and the chip structure 120 are both placed in a closed chamber. Optionally, the closed chamber has a gas injection port, and the closed chamber is injected with inert gas through the gas injection port. Under the action of the inert gas, the chip structure 120 is suspended directly above the chip carrier. Because the inner surface of the first opening 161 of the chip carrier and the first surface of the chip structure 120 carry charges of different polarities, there is an attractive force between the chip carrier and the chip structure 120. Under the action of this attractive force and the suspension force of the inert gas, the chip structure 120 is placed in the corresponding first opening 161, and self-alignment positioning of the chip structure in the substrate is achieved. Then, the opening morphology of the initial recess is adjusted by the side wall structure, so that the size of the top of the first opening is larger than the size of the bottom. Therefore, the larger top opening provides more redundant space for the placement of the chip structure, reducing the difficulty of precise positioning. After the chip structure is placed in the corresponding first opening, self-alignment positioning of the chip structure in the substrate can also be achieved by the gradually shrinking side wall morphology of the first opening from top to bottom, and finally the dual self-alignment function of polarity attraction and self-alignment side wall is formed, which makes the chip structure more accurately attached to the predetermined position of the substrate, thereby improving the positioning accuracy of the chip structure, reducing the difficulty of precise positioning, reducing the time required for positioning, and improving the efficiency of positioning.

[0097] Please refer toFigure 12 A chip carrier is provided, which comprises: a substrate 150 having a plurality of initial grooves (not shown) therein; a side wall structure 153 on the sidewall surface of the initial grooves, the side wall structure 153 exposing the surface of the substrate 150, the thickness of the bottom of the side wall structure 153 being greater than the thickness of the top of the side wall structure 153; a plurality of first openings 161 (as shown in Figure 4 ) in the initial grooves; and a chip structure 120 fixed in each first opening 161, the first surface of each chip structure 120 directly contacting the surface of the substrate 150.

[0098] In this embodiment, the forming method and structure of the chip carrier are as described above and will not be repeated here. Figures 1 to 5

[0099] In this embodiment, the side wall structure 153 adjusts the opening morphology of the initial grooves, so that the size of the top of the first opening 161 is greater than the size of the bottom. Therefore, the larger top opening provides more redundant space for the placement of the chip structure 120, reducing the difficulty of accurate positioning. After the chip structure 120 is placed in the corresponding first opening 161, the self-alignment positioning of the chip structure 120 in the substrate 150 can be achieved through the gradually shrinking sidewall morphology of the first opening 161 from top to bottom, so that the chip structure 120 is more accurately attached to the predetermined position of the substrate 150, thereby improving the positioning accuracy of the chip structure 120, reducing the difficulty of accurate positioning, and enabling more accurate attachment of smaller chip structures 120, while reducing the time required for positioning and improving the efficiency of positioning.

[0100] In this embodiment, the first surface of each chip structure 120 faces the surface of the substrate 150, and each chip structure 120 is fixed in the first opening 161 by applying pressure to the chip structure 120.

[0101] In this embodiment, the size of the bottom of each first opening 161 is equal to the size of each chip structure 120, and the size of the chip structure 120 is the width of the chip structure 120 in the direction parallel to the bottom surface of the substrate 150.

[0102] Please refer to Figure 13 , the first protective layer 102 is planarized until the surface of the first etching stop layer 103 is exposed; and a second protective layer 170 is filled on the surface of each chip structure 120 and the surface of the substrate 150.

[0103] In this embodiment, the material of the second protective layer 170 includes silicon oxide.

[0104] ​The second protective layer 170 fills the gap between the chip structure 120 and the sidewall structure 153, and the top surface of the second protective layer 170 is higher than the surface of the chip structure 120.

[0105] Referring to Figure 14 The second protective layer 170 is planarized, and a first hybrid bonding plug 171 is formed in the second protective layer 170.

[0106] In this embodiment, before the second protective layer 170 is planarized, a second etching stop layer 172 is formed on the second protective layer 170, which is used as a stop layer for planarizing the second protective layer 170.

[0107] In this embodiment, the first hybrid bonding plug 171 is used as a bonding plug in the subsequent bonding process of the chip structure 120 and a target wafer. Specifically, the first hybrid bonding plug 171 is located on the surface of the first electrically conductive interconnection layer 104 and is electrically connected to the first electrically conductive interconnection layer 104.

[0108] Referring to Figure 15 The surface of the chip structure 120 is subjected to a plasma activation treatment.

[0109] In this embodiment, the plasma activation treatment is used to assist the subsequent bonding process of the chip structure 120 and a target wafer.

[0110] Referring to Figure 16 A target wafer (not shown) is provided, which has opposite third and fourth surfaces.

[0111] Specifically, the target wafer includes a second device layer 180 having an electrically conductive plug 190 therein, a third dielectric layer 181 on the surface of the second device layer 180, the electrically conductive plug 190 also being partially located in the third dielectric layer 181, a second electrically conductive interconnection layer 184 in the third dielectric layer 181, a third etching stop layer 183 on the surface of the third dielectric layer 181 and the second electrically conductive interconnection layer 184, a fourth dielectric layer 182 on the surface of the third etching stop layer 183, and a second hybrid bonding plug 185 in the fourth dielectric layer 182, the third surface exposing the second hybrid bonding plug 185, and the fourth surface exposing the second device layer 180.

[0112] In this embodiment, the second hybrid bonding plug 185 is used as a bonding plug in the subsequent bonding process of the chip structure 120 and a target wafer. Specifically, the second hybrid bonding plug 185 is located on the surface of the second electrically conductive interconnection layer 184 and is electrically connected to the second electrically conductive interconnection layer 184.

[0113] Then, a third surface of the target wafer is subjected to a plasma activation treatment for assisting a subsequent bonding process of the target wafer and the chip structure 120.

[0114] Please refer to Figure 17 The chip carrier and a second surface of the chip structure 120 are bonded towards a third surface of the target wafer, so that the chip structure 120 is electrically connected with the target wafer; the second device layer 180 is subjected to a thinning treatment until the electrical connection plug 190 is exposed; and a solder ball 191 is formed on the surface of the electrical connection plug 190.

[0115] In the embodiment, the first hybrid bonding plug 171 is electrically connected with the second hybrid bonding plug 185, so that the chip structure 120 is electrically connected with the target wafer, and the alignment and bonding process of the chip structure 120 and the target wafer is completed.

[0116] In the embodiment, the electrical connection plug 190 penetrates the second device layer 180. The solder ball 191 can be used as an electrical connection point between the chip structure 120 and a PCB substrate.

[0117] In the embodiment, the material of the substrate 150 includes silicon or glass.

[0118] In the embodiment, the sidewall structure 153 included in the chip carrier adjusts the opening morphology of the initial groove of the substrate 150, so that the size of the top of the first opening 161 is larger than the size of the bottom, thereby improving the positioning accuracy of the chip structure 120 on the chip carrier, reducing the difficulty of accurate positioning, reducing the time required for positioning, and improving the positioning efficiency; and further, in the bonding process of the chip structure 120 and the target wafer, since the actual positioning of the chip structure 120 on the chip carrier has a small error with the designed predetermined bonding position, the bonding accuracy and efficiency of the chip structure 120 and the target wafer are finally improved.

[0119] In addition, since each chip structure 120 is integrated on each chip carrier before being bonded with the target wafer, after the activation treatment of the chip structure 120 and the first hybrid bonding plug 171, the operation time required during the bonding of the chip structure 120 and the target wafer is short, and the activation treatment on the surface of the chip structure 120 is not easy to fail, thereby further improving the bonding effect.

[0120] Correspondingly, the embodiment of the present application also provides a wafer bonding structure formed by using the above method.

[0121] Please continue to refer to Figure 17, the wafer bonding structure is characterized in that comprising: a chip carrier, the chip carrier comprises: a substrate 150, the substrate 150 has several initial grooves; side wall structure 153 on the side wall surface of the initial groove, the side wall structure 153 exposes the surface of the substrate 150, the thickness of the bottom of the side wall structure 153 is greater than the thickness of the top of the side wall structure 153; several first openings 161 (as shown in Figure 4 Figure) in the initial groove; chip structure 120 fixed in each first opening 161, each chip structure 120 has opposite first and second surfaces, and the first surface of each chip structure 120 is in direct contact with the surface of the substrate 150; target wafer, the target wafer has opposite third and fourth surfaces, and the second surface of the chip structure 120 is bonded to the third surface of the target wafer, so that the chip structure 120 is electrically connected to the target wafer.

[0122] In the embodiment, the material of the substrate 150 includes silicon or glass.

[0123] Wherein, the side wall structure 153 included in the chip carrier adjusts the opening morphology of the initial groove of the substrate 150, so that the size of the top of the first opening 161 is greater than the size of the bottom, thereby improving the positioning accuracy of the chip structure 120 on the substrate 150, reducing the difficulty of accurate positioning, and further improving the bonding accuracy of the chip structure 120 and the target wafer.

[0124] Although the present application is disclosed as above, the present application is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present application, and therefore the protection scope of the present application should be subject to the scope defined by the claims.

Claims

1. A method of forming a chip carrier, characterized by, The method comprises the following steps: providing an initial substrate; forming a plurality of initial recesses in the initial substrate to form a substrate; forming a sidewall structure on the sidewall surface of the initial recess, exposing the substrate surface, the thickness of the bottom of the sidewall structure being greater than the thickness of the top of the sidewall structure, each of the first openings being used for fixing a chip structure; applying a first polarity charge to the inner surface of each of the first openings to make it have a first polarity charge; the method for forming the sidewall structure comprises the following steps: forming a sidewall material layer on the bottom surface, sidewall surface and top surface of the substrate; etching back the sidewall material layer until the top surface of the substrate and the bottom surface of the initial recess are exposed, and forming a sidewall structure on the sidewall surface of the initial recess; the bottom size of each of the first openings is equal to the size of each chip structure.

2. The method of claim 1, wherein The sidewall structure is a single-layer structure.

3. The method of claim 2, wherein the chip carrier is formed by a process comprising: The material of the sidewall structure comprises silicon nitride or flexible material.

4. The method of claim 1, wherein The sidewall structure is a double-layer structure, and the sidewall structure comprises a first sidewall on the sidewall surface of the initial recess and a second sidewall on the surface of the first sidewall, the material hardness of the second sidewall being less than that of the first sidewall.

5. The method of claim 4, wherein the chip carrier is formed by a process comprising: The material of the first sidewall comprises silicon nitride, and the material of the second sidewall comprises polyvinyl alcohol, polyester or polyimide.

6. The method of claim 1, wherein The sidewall structure comprises a plurality of sidewalls, the number of layers of the sidewalls being greater than 2, and the material hardness of each of the sidewalls being the same or different.

7. The method of claim 1, wherein The material of the initial substrate comprises silicon oxide.

8. A chip carrier, characterized by The method comprises the following steps: a substrate having a plurality of initial recesses therein; a sidewall structure on the sidewall surface of the initial recess, the sidewall structure exposing the substrate surface, the thickness of the bottom of the sidewall structure being greater than the thickness of the top of the sidewall structure, the sidewall structure being formed by a back etching process; a first opening in the initial recess, each of the first openings being used for fixing a chip structure; the inner surface of each of the first openings having a first polarity charge; the bottom size of each of the first openings being equal to the size of each chip structure.

9. The chip carrier of claim 8, wherein, The sidewall structure is a single-layer structure.

10. The chip carrier of claim 9, wherein, The material of the sidewall structure comprises silicon nitride or flexible material.

11. The chip carrier of claim 8, wherein, The sidewall structure is a double-layer structure, and the sidewall structure comprises a first sidewall on the sidewall surface of the initial recess and a second sidewall on the surface of the first sidewall, the material hardness of the second sidewall being less than that of the first sidewall.

12. The chip carrier of claim 11, wherein, The material of the first sidewall comprises silicon nitride, and the material of the second sidewall comprises polyvinyl alcohol, polyester or polyimide.

13. A method of forming a wafer bonding structure, comprising: The method comprises the following steps: forming a plurality of mutually independent chip structures, each of the chip structures comprising opposite first and second surfaces; applying a second polarity charge to the first surface of each of the chip structures to make it have a second polarity charge; providing a chip carrier, the chip carrier comprising: a substrate having a plurality of initial recesses therein; a sidewall structure on the sidewall surface of the initial recess, the sidewall structure exposing the substrate surface, the thickness of the bottom of the sidewall structure being greater than the thickness of the top of the sidewall structure; a plurality of first openings in the initial recess; The method for forming the side wall structure comprises: forming a side wall material layer on the initial recess bottom surface, the side wall surface and the substrate top surface; etching back the side wall material layer until the substrate top surface and the initial recess bottom surface are exposed, and forming a side wall structure on the initial recess side wall surface; The bottom size of each first opening is equal to the size of each chip structure; Applying a charge of a first polarity to the inner surface of each first opening to make it carry a charge of the first polarity; Fixing a chip structure in each first opening, and making the first surface of each chip structure directly contact the substrate surface; Providing a target wafer having opposite third and fourth surfaces; After fixing the chip structures to the chip carrier, bonding the second surface of the chip carrier and the chip structures to the third surface of the target wafer to electrically connect the chip structures to the target wafer.

14. The method of claim 13, wherein The method for forming each chip structure comprises: providing an initial wafer structure having a plurality of chip regions and a plurality of cutting lane regions between adjacent chip regions; and cutting the initial wafer structure along the cutting lane regions to form a plurality of chip structures.

15. The method of claim 14, wherein The process for cutting the initial wafer structure comprises: a plasma dry etching cutting process.

16. The method of claim 14, wherein The initial wafer structure comprises: an initial wafer device layer; an initial dielectric layer on the initial wafer device layer; a first electrical interconnection layer in the initial dielectric layer; an initial first protective layer on the surface of the first electrical interconnection layer and the initial dielectric layer; after cutting the initial wafer structure, the initial wafer device layer becomes a first device layer, the initial dielectric layer becomes a first dielectric layer, the initial first protective layer becomes a first protective layer, the exposed surface of the first device layer becomes the first surface of each chip structure, and the exposed surface of the first protective layer becomes the second surface of each chip structure.

17. The method of claim 16, wherein Before cutting the initial wafer structure, the method further comprises: bonding the initial first protective layer to an initial carrier; bonding the initial wafer device layer to the surface of an adhesive structure; removing the initial carrier to expose the surface of the initial first protective layer; and after forming each chip structure, the method further comprises: removing the adhesive structure.

18. The method of claim 13, wherein After fixing each chip structure to the chip carrier, the method further comprises: filling a second protective layer on the surface of each chip structure and the substrate surface; planarizing the second protective layer; and forming a first hybrid bonding plug in the second protective layer.

19. The method of claim 13, wherein The target wafer comprises: a second device layer having an electrical connection plug therein; a third dielectric layer on the surface of the second device layer; a second electrical interconnection layer in the third dielectric layer; a fourth dielectric layer on the surface of the third dielectric layer and the second electrical interconnection layer; and a second hybrid bonding plug in the fourth dielectric layer, wherein the third surface exposes the second hybrid bonding plug, and the fourth surface exposes the second device layer.

20. The method of claim 19, wherein After bonding the chip structures to the target wafer, the method further comprises: thinning the second device layer until the electrical connection plug is exposed; and forming a solder ball on the surface of the electrical connection plug.

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