Semiconductor devices and layout structures

Abstract

The present disclosure provides a semiconductor device and a layout structure. In the semiconductor device, a first type of guard ring is arranged on at least one side of a second type of transistor, and a second type of guard ring is arranged on at least one side of the first type of transistor, so that multiple signal lines in a first metal layer in the semiconductor layout structure can be arranged between a first power line and a first ground line, and in the second metal layer, multiple second power lines are connected to a first power line, and multiple second ground lines are connected to a first ground line, thereby reducing the width of the first power line and the first ground line in the first metal layer, thereby achieving the technical effect of reducing the size of the semiconductor layout structure.

Description

Technical Field

[0001] The present disclosure relates to the field of memory technology, and in particular to a semiconductor device and a layout structure. Background Art

[0002] As the market's performance requirements for semiconductor devices continue to increase, the size of semiconductor devices is becoming smaller and smaller. In order to adapt to the trend of smaller semiconductor device sizes, it is necessary to further optimize semiconductor devices and semiconductor layout structures. Summary of the Invention

[0003] The present disclosure aims to provide a semiconductor device and layout structure with a smaller size.

[0004] A first aspect of the present disclosure provides a semiconductor device, comprising: a first type substrate; a second type well, arranged on the first type substrate; at least one first type transistor, arranged on the second type well; at least one second type transistor, arranged on the first type substrate; at least one first type guard ring, arranged on the first type substrate and located on at least one side of the second type transistor; and at least one second type guard ring, arranged on the second type well and located on at least one side of the first type transistor.

[0005] In an embodiment of the first aspect of the present disclosure, the at least one first-type guard ring is arranged on the first side and the second side of the second-type transistor, and the at least one second-type guard ring is arranged on the first side and the second side of the first-type transistor; or, the at least one first-type guard ring is arranged on the first side of the second-type transistor, and the at least one second-type guard ring is arranged on the first side of the first-type transistor; or, the at least one first-type guard ring is arranged on the first side of the second-type transistor, and the at least one second-type guard ring is arranged on the second side of the first-type transistor; the first side and the second side are two opposite directions.

[0006] In an embodiment of the first aspect of the present disclosure, the first type is P-type and the second type is N-type; or, the first type is N-type and the second type is P-type.

[0007] A second aspect of the present disclosure provides a semiconductor layout structure, comprising: a device layer, comprising a semiconductor device as described in any one of the first aspects of the present disclosure; and a first metal layer, located above the device layer, for controlling the semiconductor device.

[0008] In an embodiment of the second aspect of the present disclosure, the first metal layer includes: a first power line, a first ground line, and a plurality of signal lines extending in a first direction; the plurality of signal lines are located between the first power line and the first ground line.

[0009] In an embodiment of the second aspect of the present disclosure, the device layer and the first metal layer form a standard layout structure unit; and a plurality of the standard layout structure units share the first power line or the first ground line.

[0010] In an embodiment of the second aspect of the present disclosure, the second type well is shared among device layers in a plurality of the standard layout structure units.

[0011] In an embodiment of the second aspect of the present disclosure, it further includes: a second metal layer located above the first metal layer and connected to the first metal layer.

[0012] In an embodiment of the second aspect of the present disclosure, the second metal layer includes: a plurality of second power lines and a plurality of second ground lines extending in a second direction; the second direction is orthogonal to the first direction.

[0013] In an embodiment of the second aspect of the present disclosure, at least two of the second power lines are connected to the first power line through a connection hole; and at least two of the second ground lines are connected to the first ground line through a connection hole.

[0014] In an embodiment of the second aspect of the present disclosure, each of the second power lines is connected to the first power line through only one connection hole; and each of the second ground lines is connected to the first ground line through only one connection hole.

[0015] A third aspect of the present disclosure provides a semiconductor layout structure, comprising: a device layer, the device layer comprising: a first type substrate, a second type well, a plurality of first type transistors, a plurality of second type transistors, at least one first type guard ring and at least one second type guard ring; the second type well is arranged on the first type substrate, the plurality of first type transistors are arranged in turn on the second type well, and the plurality of second type transistors are arranged in turn on the first type substrate; the at least one first type guard ring is arranged on the first type substrate and is located on at least one side of the plurality of second type transistors; the at least one second type guard ring is arranged on the second type well and is located on at least one side of the plurality of first type transistors; a first metal layer, the first metal layer is located above the device layer and is used to control the device layer.

[0016] In an embodiment of the third aspect of the present disclosure, the first metal layer includes: a first power line, a first ground line, and a plurality of signal lines extending in a first direction, and the plurality of signal lines are located between the first power line and the first ground line.

[0017] In an embodiment of the third aspect of the present disclosure, the device layer and the first metal layer form a standard layout structure unit; and a plurality of the standard layout structure units share the first power line or the first ground line.

[0018] In an embodiment of the third aspect of the present disclosure, when a plurality of the standard layout structure units share the first power line or the first ground line, the guard rings of adjacent standard layout structure units are staggered in the vertical direction.

[0019] In an embodiment of the third aspect of the present disclosure, the second type well is shared among device layers in a plurality of the standard layout structure units.

[0020] In an embodiment of the third aspect of the present disclosure, it further includes: a second metal layer, which is located above the first metal layer and connected to the first metal layer.

[0021] In an embodiment of the third aspect of the present disclosure, the second metal layer includes multiple second power lines and multiple second ground lines; the extension direction of the second power lines and the second ground lines is orthogonal to the extension direction of the first power lines and the first ground lines.

[0022] In an embodiment of the third aspect of the present disclosure, at least two of the second power lines are connected to the first power lines through a connection hole; and at least two of the second ground lines are connected to the first ground line through a connection hole.

[0023] In an embodiment of the third aspect of the present disclosure, each of the second power lines is connected to the first power line through only one connection hole; and each of the second ground lines is connected to the first ground line through only one connection hole.

[0024] In summary, the semiconductor device and layout structure provided by the present disclosure set a first type of guard ring on at least one side of a second type of transistor and a second type of guard ring on at least one side of a first type of transistor in the semiconductor device, so that multiple signal lines in the first metal layer in the semiconductor layout structure can be set between the first power line and the first ground line, and the second metal layer is connected to a first power line by multiple second power lines and a first ground line by multiple second ground lines, thereby reducing the width of the first power line and the first ground line in the first metal layer, thereby achieving the technical effect of reducing the size of the semiconductor layout structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or related technologies, the following briefly introduces the drawings required for use in the embodiments or related technical descriptions. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0026] Figure 1 It is a structural schematic diagram of a semiconductor device;

[0027] Figure 2 A schematic diagram of a semiconductor layout structure;

[0028] Figure 3 is a schematic structural diagram of a first metal layer;

[0029] Figure 4 is a schematic structural diagram of a second metal layer;

[0030] Figure 5 A schematic structural diagram of an embodiment of a semiconductor device provided by the present disclosure;

[0031] Figure 6 A schematic structural diagram of another embodiment of a semiconductor device provided by the present disclosure;

[0032] Figure 7 A schematic diagram of an embodiment of a semiconductor layout structure provided by the present disclosure;

[0033] Figure 8 A schematic diagram of an embodiment of a semiconductor layout structure provided by the present disclosure;

[0034] Figure 9 A schematic structural diagram of an embodiment of a device layer in a semiconductor layout structure provided by the present disclosure;

[0035] Figure 10 A schematic structural diagram of an embodiment of a semiconductor layout structure provided by the present disclosure;

[0036] Figure 11 A schematic structural diagram of another embodiment of the semiconductor layout structure provided by the present disclosure;

[0037] Figure 12 A schematic diagram of an embodiment of a semiconductor layout structure provided by the present disclosure;

[0038] Figure 13 A schematic structural diagram of another embodiment of a semiconductor device provided by the present disclosure;

[0039] Figure 14 A schematic diagram of another embodiment of the semiconductor layout structure provided by the present disclosure;

[0040] Figure 15 A schematic structural diagram of an embodiment of a device layer in a semiconductor layout structure provided by the present disclosure;

[0041] Figure 16 A schematic structural diagram of an embodiment of a semiconductor layout structure provided by the present disclosure;

[0042] Figure 17 A schematic diagram of another embodiment of the semiconductor layout structure provided by the present disclosure

[0043] Figure 18 A schematic structural diagram of an embodiment of a device layer in a semiconductor layout structure provided by the present disclosure;

[0044] Figure 19 A schematic structural diagram of an embodiment of a semiconductor layout structure provided by the present disclosure;

[0045] Figure 20 This is a structural schematic diagram of another embodiment of the semiconductor layout structure provided by the present disclosure. DETAILED DESCRIPTION

[0046] The following will be combined with the accompanying drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. Obviously, the embodiments described are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of the present disclosure.

[0047] The terms "first," "second," "third," "fourth," and the like (if any) in the specification and claims of the present disclosure and in the accompanying drawings are used to distinguish similar objects and are not necessarily used to describe a particular order or sequential sequence. It should be understood that the terms used in this manner are interchangeable where appropriate, so that the embodiments of the present disclosure described herein, for example, can be implemented in orders other than those illustrated or described herein. In addition, the terms "including" and "having," and any variations thereof, are intended to cover non-exclusive inclusions, e.g., a process, method, system, product, or apparatus comprising a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0048] Figure 11 is a schematic structural diagram of a semiconductor device, comprising: a first-type substrate 10, a second-type well 11, at least one first-type transistor 12, at least one second-type transistor 13, at least one first-type guard ring 14, and at least one second-type guard ring 15. The second-type well 11, at least one second-type transistor 13, and at least one first-type guard ring 14 are disposed on the first-type substrate 10, while the at least one first-type transistor 12 and at least one second-type guard ring 15 are disposed on the second-type well 11.

[0049] Figure 1 In the embodiment, a semiconductor device includes a first type transistor 12, a second type transistor 13, a first type guard ring 14 and a second type guard ring 15. Figure 1 A two-dimensional coordinate system xy is established on the plane where the semiconductor device is located. In the y direction, the second type transistor 13 is arranged below the first type transistor 12, the first type guard ring 14 is arranged below the second type transistor 13, and the second type guard ring 15 is arranged above the first type transistor 12.

[0050] The first type and the second type are different types, for example, the first type is P-type and the second type is N-type; or the first type is N-type and the second type is P-type.

[0051] Figure 2 A schematic diagram of a semiconductor layout structure, with vertical Figure 1 In the z direction of the two-dimensional coordinate system xy, a three-dimensional coordinate system xyz is established, which includes from top to bottom in the z direction: device layer L1, first metal layer L2 and third metal layer L3. The device layer L1 includes at least one Figure 1 In the semiconductor device shown, the first metal layer L2 is located above the device layer L1 and is used to control the semiconductor devices in the device layer L1.

[0052] Figure 3 Schematic diagram of the structure of a first metal layer, including: a first power line 21, a first ground line 22, and multiple signal lines 23 extending in the x-direction. In the y-direction, at least one signal line 23 is provided on both sides of the first power line 21 and the second ground line 22. Figure 3 The positions of the first power line 21 and the first ground line 22 can be interchanged.

[0053] Figure 4FIG2 is a schematic diagram of the structure of a second metal layer, including a second power line 31 and a second ground line 32 extending in the y direction. The second power line 31 in the second metal layer L3 is connected to the first power line 21 in the first metal layer L2 via two connection holes 41, and the second ground line 32 in the second metal layer L3 is connected to the first ground line 22 in the second metal layer L2 via two connection holes 42.

[0054] In the above Figures 1-4 In the provided semiconductor device and layout structure, the width D1 of the first power line 21 and the first ground line 22 in the first metal layer L1 is relatively large, resulting in a larger size of the semiconductor device and its layout structure. Therefore, how to optimize the semiconductor device and the semiconductor layout structure so that the size of the semiconductor device and the layout structure is smaller is the technical problem solved by the technical solution provided in the embodiment of the present disclosure. The technical solution of the present disclosure is described in detail below with specific embodiments. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments.

[0055] Figure 5 A schematic structural diagram of an embodiment of a semiconductor device provided by the present disclosure includes: a first-type substrate 10, a second-type well 11, at least one first-type transistor 12, at least one second-type transistor 13, at least one first-type guard ring 14, and at least one second-type guard ring 15. The second-type well 11, at least one second-type transistor 13, and at least one first-type guard ring 14 are disposed on the first-type substrate 10, while the at least one first-type transistor 12 and at least one second-type guard ring 15 are disposed on the second-type well 11.

[0056] by Figure 5 A two-dimensional coordinate system xy is established on the plane where the semiconductor device is located. In the y direction, the second type transistor 13 is arranged below the first type transistor 12, the first type guard ring 14 is arranged on at least one side of the second type transistor 13 in the x direction, and the second type guard ring 15 is arranged on at least one side of the first type transistor 12 in the x direction. The at least one side includes Figure 5 Left and / or right in the x-direction.

[0057] Figure 5 In the example, a semiconductor device includes a first-type transistor 12, a second-type transistor 13, a first-type guard ring 14, and a second-type guard ring 15. The first-type guard ring 14 is arranged on the first side (left side) of the second-type transistor 13 in the x-direction, and the second-type guard ring 15 is arranged on the first side of the first-type transistor 12 in the x-direction.

[0058] or, Figure 6 A schematic structural diagram of another embodiment of a semiconductor device provided by the present disclosure, Figure 6 In the semiconductor device A shown, the first type guard ring 14 is arranged on the second side (right side) of the second type transistor 13 in the x direction, and the second type guard ring 15 is arranged on the second side of the first type transistor 12 in the x direction; Figure 6 In the semiconductor device B shown, the first type guard ring 14 is arranged on the first side of the second type transistor 13 in the x direction, and the second type guard ring 15 is arranged on the second side of the first type transistor 12 in the x direction; Figure 6 In the semiconductor device C shown, the first type guard ring 14 is arranged on the second side of the second type transistor 13 in the x direction, and the second type guard ring 15 is arranged on the first side of the first type transistor 12 in the x direction; Figure 6 In the semiconductor device D shown, the first type guard rings 14 are provided on the first and second sides of the second type transistor 13 in the x direction, and the second type guard rings 15 are provided on the first and second sides of the first type transistor 12 in the x direction.

[0059] The first type and the second type are different types, for example, the first type is P-type and the second type is N-type; or the first type is N-type and the second type is P-type.

[0060] In summary, if Figure 6 The provided semiconductor device sets a first type of guard ring on at least one side of a second type of transistor and sets a second type of guard ring on at least one side of a first type of transistor, so that when the semiconductor device is connected to the first metal layer, the width of the first power line and the first ground line in the first metal layer can be reduced, thereby achieving the technical effect of reducing the size of the semiconductor layout structure in which the semiconductor device is located.

[0061] Specifically, Figure 7 This is a schematic diagram of an embodiment of a semiconductor layout structure provided by the present disclosure. The present disclosure also provides a semiconductor layout structure, including a device layer and a first metal layer. Figure 2 In the structure, the device layer includes at least one Figure 6 In the semiconductor device shown, the first metal layer is arranged above the device layer in the z direction. The first metal layer can be used to control the semiconductor devices in the device layer.

[0062] like Figure 7 As shown, the first metal layer includes: a first power line 21, a first ground line 22 and a plurality of signal lines 23 extending in a first direction. Figure 7 In the x direction, the plurality of signal lines 23 are located between the first power line 21 and the first ground line 22, that is, Figure 7In the y direction, the first power line 21 is located above the plurality of signal lines 23 and the first ground line 22 is located below the plurality of signal lines 23, or the first ground line 22 is located above the plurality of signal lines 23 and the first power line 21 is located below the plurality of signal lines 23.

[0063] Figure 8 This is a schematic diagram of an embodiment of a semiconductor layout structure provided by the present disclosure, as shown in FIG. Figure 8 The semiconductor layout structure shown in Figure 7 The base shown also includes: a second metal layer. Figure 2 In the structure, the second metal layer is located above the first metal layer in the z direction, and the second metal layer includes a plurality of second power lines 31 and second ground lines 32 extending in the second direction. The second direction is orthogonal to the first direction. When the first direction is Figure 8 When the x direction is in the Figure 8 y direction in .

[0064] exist Figure 8 In the example shown, in order to reduce the width of the first power line 21 and the first ground line 22 in the first metal layer, at least two second power lines 31 in the second metal layer are connected to the same first power line 21 in the first metal layer through connecting holes, and at least two second ground lines 32 in the second metal layer are connected to the same first ground line 22 in the first metal layer through connecting holes.

[0065] Specifically, each second power line is connected to the first power line through only one connection hole. For example, second power line 31a is connected to first power line 21 through connection hole 41a, and second power line 31b is connected to first power line 21 through connection hole 41b. Second power line 31a and second power line 31b are simultaneously connected to first power line 21 in parallel. Each second ground line is connected to the first ground line through only one connection hole. For example, second ground line 32a is connected to first ground line 22 through connection hole 42a, and second ground line 32b is connected to first electrical ground line 22 through connection hole 42b. Second ground line 32a and second ground line 32b are simultaneously connected to first ground line 22 in parallel. Thus, by increasing the number of second power lines 32 and second ground lines 33 in the second metal layer, the density of the connections in the second metal layer is increased, compensating for the problem of increased resistance caused by the reduction in the width of the first power line 21 and the first ground line 22 in the first metal layer, so that the overall resistance of the first power line 21 and the second power line 31, as well as the resistance through the first ground line 22 and the second ground line 32 can still meet the requirements of design standards such as resistance drop (IR drop) and electromigration (EM).

[0066] In summary, the semiconductor layout structure provided by this embodiment has a first-type guard ring in the device layer disposed on at least one side of the second-type transistor, and a second-type guard ring disposed on at least one side of the first-type transistor, so that a plurality of signal lines in the first metal layer can be disposed between the first power line and the first ground line, and a plurality of second power lines are connected to a first power line and a plurality of second ground lines are connected to a first ground line in the second metal layer. Under the condition that the wiring requirements and the resistance voltage drop (IR drop) requirements are met, only one connection hole needs to be provided on the first power line to be connected to a second power line, and only one connection hole needs to be provided on the first ground line to be connected to a second ground line. Figure 7 In the semiconductor layout structure shown, the width D2 of the first power line and the first ground line is less than Figure 2 The width D1 shown in FIG. Figure 7 The overall width of the semiconductor layout structure shown in the y direction is less than Figure 2 The overall width of the semiconductor layout structure in the y direction is shown, thereby achieving the technical effect of reducing the size of the semiconductor layout structure.

[0067] In some embodiments, as Figure 2 He Ru Figure 5 In the semiconductor device shown, the distance D5 between the first type transistor 12 and the second type guard ring, as well as the distance D5 between the second type transistor 13 and the first type guard ring 14, both comply with the distances specified by the process design rules related to the active region (Active). The distance D4 between the first type transistor 12 and the boundary of the second type well 11, as well as the distance D4 between the second type transistor 13 and the boundary of the second type well 11, both comply with the distances specified by the process design rules related to the Well. Figure 3 The distance D0 between the signal lines 23 in the first metal layer of the semiconductor layout structure shown is Figure 7 In the semiconductor layout structure shown, the distance D0 between the signal lines 23 in the first metal layer is the same; Figure 3 The number of signal lines 23 in the first metal layer in the semiconductor layout structure shown is Figure 7 In the semiconductor layout structure shown, the number of signal lines 23 in the first metal layer is the same, thereby achieving the technical effect of reducing the size of the semiconductor layout structure without changing the design rules of the semiconductor device and the layout structure.

[0068] In some embodiments, as Figure 7The device layer and the first metal layer shown can form a standard layout structure unit. Since the first power line and the first ground line are arranged on the upper and lower sides of multiple signal lines in the first metal layer, when two standard layout structure units are arranged in an upper and lower manner, the semiconductor devices in the device layers of the two standard layout structure units can share the same adjacent first power line or first ground line in the first metal layer.

[0069] For example, Figure 9 This is a schematic structural diagram of an embodiment of a device layer in a semiconductor layout structure provided by the present disclosure. Figure 9 In case E on the left, the device layer includes two Figure 5 The semiconductor devices shown are denoted as semiconductor device a and semiconductor device b, semiconductor device a is located above semiconductor device b in the y direction, and the two semiconductor devices are arranged on the same first type substrate 10. The second type transistor 13a of semiconductor device a is arranged above the first type transistor 12a in the y direction, and the second type transistor 13b of semiconductor device b is arranged below the first type transistor 12b in the y direction. The first type guard ring 14a of semiconductor device a is arranged on the left side of the second type transistor 13a in the x direction, and the second type guard ring 15a is arranged on the left side of the first type transistor 12a in the x direction. The first type guard ring 14b of semiconductor device b is arranged on the left side of the second type transistor 13b in the x direction, and the second type guard ring 15b is arranged on the left side of the first type transistor 12b in the x direction. In some embodiments, as Figure 9 In case F on the right, the two semiconductor devices in the device layer share the second type well 11. At this time, the first type transistor 12a and the second type guard ring 15a of semiconductor device a and the first type transistor 12b and the second type guard ring 15b of semiconductor device b are set on the same second type well 11.

[0070] Figure 10 This is a schematic diagram of a semiconductor layout structure according to an embodiment of the present disclosure, as shown in FIG. Figure 10 In the semiconductor layout structure shown in Figure 9 Taking the device layer in case F on the right as an example, in the first metal layer set on the device layer, when semiconductor device a and semiconductor device b share the first ground line 22 in the first metal layer, the y direction includes: the first power line 21a and multiple signal lines 23a corresponding to semiconductor device a, the first ground line 22, and the multiple signal lines 23b and the first ground line 21b corresponding to semiconductor device b.

[0071] or, Figure 11This is a structural schematic diagram of another embodiment of the semiconductor layout structure provided by the present invention. When semiconductor device a and semiconductor device b share the first power line 21 in the first metal layer, the y direction includes: a first ground line 22a and multiple signal lines 23a corresponding to semiconductor device a, a first power line 21, and multiple signal lines 23b and a first ground line 22b corresponding to semiconductor device b.

[0072] It should be noted that if Figure 10 and Figure 11 In the embodiment, the device layer includes two semiconductor devices. According to the same method as above, when the first power supply line or the first connection line in the first metal layer extends in the x direction, both sides thereof may be provided with the following Figure 10 or Figure 11 In the standard layout structure unit in the form of a mosaic, the two semiconductor devices in the standard layout structure unit can share the adjacent first power line or first ground line. This change is an increase in quantity, and the specific implementation method and principle are the same, so they will not be repeated.

[0073] In summary, in the semiconductor layout structure provided by this embodiment, since the first power line and the first ground line are arranged on the upper and lower sides of multiple signal lines in the first metal layer, the semiconductor devices assembled in the standard layout structure unit can share the adjacent first ground line or first power line, thereby reducing the height of the standard layout structure unit in the y direction and further reducing the size of the semiconductor layout structure.

[0074] Figure 12 This is a schematic diagram of an embodiment of a semiconductor layout structure provided by the present disclosure. The present disclosure also provides a semiconductor layout structure, including a device layer and a first metal layer. Figure 2 In the structure, the first metal layer is arranged above the device layer in the z direction, and the first metal layer can be used to control the semiconductor devices in the device layer.

[0075] like Figure 12 In the semiconductor layout structure shown, the device layer specifically includes: a first type substrate 10, a second type well 11, a plurality of first type transistors 12, a plurality of second type transistors 13, at least one first type guard ring 14 and at least one second type guard ring 15. The second type well 11, the plurality of second type transistors 13 and the at least one first type guard ring 14 are arranged on the first type substrate 10, and the plurality of second type transistors 13 are arranged on the first type substrate 10. Figure 12 The plurality of first type transistors 12 and at least one second type guard ring 15 are arranged in sequence in the x direction. Figure 12The first type guard ring 14 is arranged on at least one side of the plurality of second type transistors 13 in the x direction, and the second type guard ring 15 is arranged on at least one side of the plurality of first type transistors 12 in the x direction. Figure 12 Left and / or right in the x-direction.

[0076] exist Figure 12 In the example, a semiconductor device includes four first-type transistors 12, four second-type transistors 13, a first-type guard ring 14, and a second-type guard ring. The first-type guard ring 14 is arranged on the first side (left side) of the plurality of sequentially arranged second-type transistors 13 in the x-direction, and the second-type guard ring 15 is arranged on the first side of the plurality of sequentially arranged first-type transistors 12 in the x-direction. For another example, Figure 13 A schematic structural diagram of another embodiment of the semiconductor device provided by the present disclosure is shown in FIG. Figure 13 As shown, the first type guard ring 14 can be set on the first side of the multiple second type transistors 13 in the x-direction, and the second type guard ring 15 can be set on the second side (right side) of the multiple first type transistors 12 in the x-direction; or, the first type guard ring 14 can be set on the second side of the multiple second type transistors 13 in the x-direction, and the second type guard ring 15 can be set on the first side of the multiple first type transistors 12 in the x-direction; or, the first type guard ring 14 can be set on the second side of the multiple second type transistors 13 in the x-direction, and the second type guard ring 15 can be set on the second side of the multiple first type transistors 12 in the x-direction.

[0077] The first type and the second type are different types, for example, the first type is P-type and the second type is N-type; or the first type is N-type and the second type is P-type.

[0078] Figure 14 A schematic diagram of another embodiment of the semiconductor layout structure provided by the present disclosure, such as Figure 14 The device layers of the semiconductor layout structure include Figure 12Taking the semiconductor device shown in FIG. as an example, the structure of the first and second metal layers above the device layer is illustrated. The first metal layer includes: a first power line 21 extending in the x-direction; a first ground line 22; and multiple signal lines 23, with the multiple signal lines 23 located between the first power line 21 and the first ground line 22. The second metal layer includes multiple second power lines 31 and second ground lines 32 extending in the y-direction. At least two second power lines 31 in the second metal layer are connected to the same first power line 21 in the first metal layer via connection holes, and at least two second ground lines 32 in the second metal layer are connected to the same first ground line 22 in the first metal layer via connection holes. Specifically, second power line 31a is connected to first power line 21 via connection hole 41a, and second power line 31b is connected to first power line 21 via connection hole 41b. The second power line 31a and the second power line 31b are simultaneously connected to the first power line 21 in parallel. Each second grounding wire is connected to the first grounding wire only through one connection hole. For example, the second grounding wire 32a is connected to the first grounding wire 22 through the connection hole 42a, and the second grounding wire 32b is connected to the first electrical grounding wire 22 through the connection hole 42b. The second grounding wire 32a and the second grounding wire 32b are connected to the first grounding wire 22 in parallel.

[0079] In summary, the semiconductor layout structure provided by this embodiment has a first-type guard ring arranged on at least one side of a plurality of second-type transistors in the device layer, and a second-type guard ring arranged on at least one side of a plurality of first-type transistors, so that a plurality of signal lines in the first metal layer can be arranged between the first power line and the first ground line, and in the second metal layer, a plurality of second power lines are connected to a first power line, and a plurality of second ground lines are connected to a first ground line. Under the condition of meeting the wiring requirements and the resistance voltage drop (IR drop) requirements, only one connection hole needs to be set on the first power line to connect to a second power line, and only one connection hole needs to be set on the first ground line to connect to a second ground line, so that Figure 14 In the semiconductor layout structure shown, the width of the first power line and the first ground line is less than Figure 2 The width D1 shown in FIG. Figure 13 The overall width of the semiconductor layout structure shown in the y direction is less than Figure 2 The overall width of the semiconductor layout structure in the y direction is shown, thereby achieving the technical effect of reducing the size of the semiconductor layout structure.

[0080] In some embodiments, as Figure 14The device layer and the first metal layer shown can form a standard layout structure unit. Since the first power line and the first ground line are arranged on the upper and lower sides of multiple signal lines in the first metal layer, when the standard layout structure unit adopts an upper and lower arrangement, the semiconductor devices in the device layers of these two standard layout structure units can share the same adjacent first power line or first ground line in the first metal layer.

[0081] Figure 15 This is a schematic diagram of the structure of an embodiment of a device layer in a semiconductor layout structure provided by the present disclosure. The device layer includes a semiconductor device S1 and a semiconductor device S2, with semiconductor device S1 disposed above semiconductor device S2 in the y direction. Semiconductor devices S1 and S2 can share a second-type well 11. This allows the first-type transistor S1-12 and second-type guard ring S1-15 of semiconductor device S1, and the first-type transistor S2-12 and second-type guard ring S2-15 of semiconductor device S2, to be disposed in the same second-type well 11.

[0082] Figure 16 This is a schematic diagram of a semiconductor layout structure according to an embodiment of the present disclosure, as shown in FIG. Figure 16 In the semiconductor layout structure shown, when the semiconductor device S1 and the semiconductor device S2 share the first ground line 22 in the first metal layer, the first metal layer includes, in sequence in the y direction: a first power line 21a and multiple signal lines 23a corresponding to the semiconductor device S1, a first ground line 22, and multiple signal lines 23b and a first ground line 21b corresponding to the semiconductor device S2.

[0083] or, Figure 17 This is a structural schematic diagram of another embodiment of the semiconductor layout structure provided by the present invention. When the semiconductor device S1 and the semiconductor device S2 share the first power line 21 in the first metal layer, the first metal layer includes in sequence in the y direction: a first ground line 22a and multiple signal lines 23a corresponding to the semiconductor device S1, a first power line 21, and multiple signal lines 23b and a second power line 22b corresponding to the semiconductor device S2.

[0084] In other embodiments, when the standard layout structural units are arranged in an up-and-down manner, when adjacent standard layout units share a first signal line or a first power line, the guard rings of the two adjacent standard layout units are arranged in an up-and-down staggered manner.

[0085] For example, Figure 18This is a schematic diagram of the structure of an embodiment of a device layer in a semiconductor layout structure provided by the present disclosure. The device layer includes three semiconductor devices, denoted as semiconductor device S1, semiconductor device S2, and semiconductor device S3. Semiconductor device S2 and semiconductor device S3 are arranged in sequence in the x-direction, and semiconductor device S1 is arranged above semiconductor device S2 and semiconductor device S3 in the y-direction. Figure 14 As shown, semiconductor device S1, semiconductor device S2 and semiconductor device S3 can share the second type well 11, so that the first type transistor and the second type guard ring of semiconductor device S1, the first type transistor and the second type guard ring of semiconductor device S2 and the first type transistor and the second type guard ring of semiconductor device S3 are all arranged on the same second type well 11.

[0086] like Figure 18 As shown, in the x-direction, the second type guard ring S1-15 of the standard layout unit S1 is arranged between the second type guard ring S2-15 of the standard layout unit S2 and the second type guard ring S3-15 of the standard layout unit S3. In the x-direction, the guard rings of the standard layout units S2, S1 and S3 are arranged in an up-down staggered manner. It can be understood that in the x-direction, other standard layout units can also be arranged in sequence according to the up-down staggered guard ring manner.

[0087] by Figure 18 In the example, the first-type transistor S2-12 at point P in the standard layout unit S2 is used. When the guard rings of the standard layout units S2, S1, and S3 are sequentially staggered, the distances between the first-type transistor S2-12 and the second-type guard ring S1-15 of the standard layout unit S1, the second-type guard ring S2-15 of the standard layout unit S2, and the second-type guard ring S3-15 of the standard layout unit S3 are all less than the minimum diameter interval of the second-type guard rings, where the minimum diameter interval is Figure 14 Among the second-type guard rings S1-1, S2-15, and S3-15, the minimum diameter interval between any two second-type guard rings is half of the minimum diameter interval, which is the effective range of one second-type guard ring. The first-type transistor S2-12 at point P is also within the effective range of these three second-type guard rings. This allows the second-type guard rings of these three standard layout cells to act on the first-type transistor S2-12 at point P, achieving more effective and comprehensive protection for the first-type transistor S2-12.

[0088] Figure 19 This is a schematic diagram of a semiconductor layout structure according to an embodiment of the present disclosure, as shown in FIG. Figure 18In the semiconductor layout structure shown, when the semiconductor device S1, the semiconductor device S2, and the semiconductor device S3 share the first ground line 22 in the first metal layer, the first metal layer includes, in sequence in the y direction: a first power line 21a and multiple signal lines 23a corresponding to the semiconductor device S1, a first ground line 22, and multiple signal lines 23b and a first ground line 21b corresponding to the semiconductor device S2 and the semiconductor device S3.

[0089] or, Figure 20 This is a schematic diagram of another embodiment of the semiconductor layout structure provided by the present disclosure. When semiconductor devices S1, S2, and S3 share a first power line in a first metal layer, the first metal layer includes, in order along the y-direction: a first ground line 22a and multiple signal lines 23a corresponding to semiconductor device S1, a first power line 21, and multiple signal lines 23b and second power lines 22b corresponding to semiconductor devices S2 and S3. This reduces the overall width of the semiconductor layout structure in the y-direction, thereby achieving the technical effect of reducing the size of the semiconductor layout structure.

[0090] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present disclosure, rather than to limit them. Although the present disclosure has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present disclosure.

Claims

1. A semiconductor device, characterized in that: include: a first type of substrate; a second type well, disposed on the first type substrate; a plurality of first-type transistors arranged on the second-type well along a first direction; a plurality of second-type transistors, arranged on the first-type substrate along the first direction; at least one first-type guard ring, disposed on the first-type substrate and located only on a first side of the plurality of second-type transistors; at least one second-type guard ring, disposed on the second-type well and located only on the first side of the plurality of first-type transistors; The first side is orthogonal to the first direction.

2. The semiconductor device according to claim 1, wherein The first type is P type, and the second type is N type; Alternatively, the first type is N-type and the second type is P-type.

3. A semiconductor layout structure, characterized in that: include: A device layer comprising the semiconductor device according to any one of claims 1 to 2; The first metal layer is located above the device layer and is used to control the semiconductor device.

4. The semiconductor layout structure according to claim 3, wherein: The first metal layer includes: a first power line, a first ground line, and a plurality of signal lines extending in the first direction; The plurality of signal lines are located between the first power line and the first ground line.

5. The semiconductor layout structure according to claim 4, wherein: The device layer and the first metal layer form a standard layout structure unit; The first power line or the first ground line is shared by a plurality of the standard layout structure units.

6. The semiconductor layout structure according to claim 5, characterized in that: The second type of well is shared among device layers in a plurality of the standard layout structure units.

7. The semiconductor layout structure according to any one of claims 4 to 6, characterized in that: Also includes: The second metal layer is located above the first metal layer and connected to the first metal layer.

8. The semiconductor layout structure according to claim 7, wherein: The second metal layer includes: a plurality of second power lines and a plurality of second ground lines extending in a second direction; The second direction is orthogonal to the first direction.

9. The semiconductor layout structure according to claim 8, wherein: At least two of the second power lines are connected to the first power line through the connection hole; At least two of the second grounding lines are connected to the first grounding line through the connection holes.

10. The semiconductor layout structure according to claim 8 or 9, characterized in that: Each of the second power lines is connected to the first power line via only one connection hole; Each of the second grounding lines is connected to the first grounding line through only one connection hole.

11. A semiconductor layout structure, characterized in that: include: a device layer comprising: a first type substrate, a second type well, a plurality of first type transistors, a plurality of second type transistors, at least one first type guard ring, and at least one second type guard ring; The second type well is provided on the first type substrate, the plurality of first type transistors are sequentially provided on the second type well along a first direction, and the plurality of second type transistors are sequentially provided on the first type substrate along the first direction; The at least one first type guard ring is disposed on the first type substrate and is located only on a first side of the plurality of second type transistors; The at least one second-type guard ring is disposed on the second-type well and is located only on the first side of the plurality of first-type transistors; wherein the first side is orthogonal to the first direction; A first metal layer is located above the device layer and is used to control the device layer. The device layer and the first metal layer form a standard layout structure unit.

12. The semiconductor layout structure according to claim 11, wherein: The first metal layer includes: A first power line, a first ground line, and a plurality of signal lines extending in the first direction, wherein the plurality of signal lines are located between the first power line and the first ground line.

13. The semiconductor layout structure according to claim 12, wherein: The first power line or the first ground line is shared by a plurality of the standard layout structure units.

14. The semiconductor layout structure according to claim 12, wherein: When a plurality of the standard layout structure units share the first power line or the first ground line, the guard rings of adjacent standard layout structure units are arranged in a vertically staggered manner.

15. The semiconductor layout structure according to claim 13, wherein: The second type of well is shared among device layers in a plurality of the standard layout structure units.

16. The semiconductor layout structure according to claim 12, wherein: Also includes: A second metal layer is located above the first metal layer and connected to the first metal layer.

17. The semiconductor layout structure according to claim 16, wherein: The second metal layer includes a plurality of second power lines and a plurality of second ground lines; The extending directions of the second power line and the second ground line are perpendicular to the extending directions of the first power line and the first ground line.

18. The semiconductor layout structure according to claim 17, wherein: At least two of the second power lines are connected to the first power lines through the connection holes; At least two of the second grounding lines are connected to the first grounding line through a connection hole.

19. The semiconductor layout structure according to claim 18, wherein: Each of the second power lines is connected to the first power line via only one connection hole; Each of the second grounding lines is connected to the first grounding line through only one connection hole.

Images