Image sensor and method of forming the same

Abstract

Various embodiments of the present invention are directed to an image sensor. The image sensor includes a deep trench isolation (DTI) structure disposed in a substrate. A pixel region of the substrate is disposed within an inner perimeter of the DTI structure. A photodetector is disposed in the pixel region of the substrate. A gate electrode structure is at least partially over the pixel region of the substrate. A first gate dielectric structure is partially over the pixel region of the substrate. A second gate dielectric structure is partially over the pixel region of the substrate. The gate electrode structure is over the portion of the first gate dielectric structure and the portion of the second gate dielectric structure. The first gate dielectric structure has a first thickness. The second gate dielectric structure has a second thickness that is greater than the first thickness. Embodiments of the present application also provide methods for forming an image sensor.

Description

Technical Field

[0001] Embodiments of this application relate to image sensors and methods of forming the same. Background Technology

[0002] Many modern electronic devices (e.g., smartphones, digital cameras, biomedical imaging devices, automotive imaging devices, etc.) include image sensors. Image sensors include one or more photodetectors (e.g., photodiodes, phototransistors, photoresistors, etc.) configured to absorb incident radiation and output an electrical signal corresponding to the incident radiation. Some types of image sensors include charge-coupled device (CCD) image sensors and complementary metal-oxide-semiconductor (CMOS) image sensors. Compared to CCD image sensors, CMOS image sensors are favored due to their low power consumption, small size, fast data processing, direct data output, and low manufacturing cost. Some types of CMOS image sensors include front-illuminated (FSI) image sensors and back-illuminated (BSI) image sensors. Summary of the Invention

[0003] Some embodiments of this application provide an image sensor, including: a deep trench isolation (DTI) structure disposed in a semiconductor substrate, wherein the DTI structure extends laterally through the semiconductor substrate in a closed-loop path, and wherein a pixel region of the semiconductor substrate is disposed within the inner periphery of the DTI structure; a photodetector disposed in the pixel region of the semiconductor substrate; a gate electrode structure partially located above the pixel region of the semiconductor substrate; a first gate dielectric structure partially located above the pixel region of the semiconductor substrate; and a second gate dielectric structure partially located above the pixel region of the semiconductor substrate, wherein the gate electrode structure is located above portions of the first gate dielectric structure and portions of the second gate dielectric structure, and wherein the thickness of the portion of the second gate dielectric structure is greater than the thickness of the portion of the first gate dielectric structure.

[0004] Some other embodiments of this application provide an image sensor, including: an isolation structure disposed in a semiconductor substrate, wherein the isolation structure extends vertically from a first surface of the semiconductor substrate through the semiconductor substrate to a second surface of the semiconductor substrate opposite to the first surface of the semiconductor substrate; a floating diffusion node disposed in the semiconductor substrate and on the side of the isolation structure; a photodetector disposed in the semiconductor substrate and laterally disposed between the floating diffusion node and the isolation structure; a gate electrode structure disposed above the semiconductor substrate and laterally disposed between the floating diffusion node and the photodetector, wherein the first surface of the semiconductor substrate is perpendicularly disposed between the gate electrode structure and the second surface of the semiconductor substrate; a first gate dielectric structure disposed above the first surface of the semiconductor substrate; and a second gate dielectric structure disposed above the first surface of the semiconductor substrate and on the side of the first gate dielectric structure, wherein the thickness of the second gate dielectric structure is greater than the thickness of the first gate dielectric structure, wherein the second gate dielectric structure is located above the isolation structure, and wherein the gate electrode structure is partially located above the first gate dielectric structure and the second gate dielectric structure.

[0005] Further embodiments of this application provide a method for forming an image sensor, the method comprising: forming a photodetector in a semiconductor substrate; forming a first gate dielectric structure over a first side of the semiconductor substrate; forming a second gate dielectric structure over the first side of the semiconductor substrate, wherein the second gate dielectric structure is formed to have a thickness greater than that of the first gate dielectric structure; forming a gate electrode structure partially located over the first gate dielectric structure and partially located over the second gate dielectric structure; forming a trench in the semiconductor substrate exposing a portion of the second gate dielectric structure, wherein the trench is formed from a second side of the semiconductor substrate opposite to the first side of the semiconductor substrate; and forming a back-side deep trench isolation (BDTI) structure in the trench. Attached Figure Description

[0006] The various aspects of the invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industrial practice, the components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the components may be arbitrarily increased or decreased.

[0007] Figures 1A to 1B Various views of some embodiments of an image sensor are shown, including a first gate dielectric structure having a first thickness and a second gate dielectric structure having a second thickness greater than the first thickness.

[0008] Figures 2A to 2B It shows Figures 1A to 1B Various views of some other embodiments of the image sensor.

[0009] Figure 3 It shows Figures 2A to 2B Layout diagrams of some other embodiments of the image sensor.

[0010] Figure 4 It shows Figures 2A to 2B Layout diagrams of some other embodiments of the image sensor.

[0011] Figure 5 It shows Figure 3 Layout diagrams of some other embodiments of the image sensor.

[0012] Figure 6 It shows Figure 5 Layout diagrams of some other embodiments of the image sensor.

[0013] Figure 7 It shows Figures 1A to 1B Cross-sectional views of some other embodiments of the image sensor.

[0014] Figure 8 It shows Figure 7 Cross-sectional views of some other embodiments of the image sensor.

[0015] Figure 9 It shows Figure 8 Layout diagrams of some embodiments of the second chip of the image sensor.

[0016] Figure 10 It shows Figure 8 Circuit diagrams of some embodiments of the image sensor.

[0017] Figure 11 It shows Figure 10 Circuit diagrams of some other embodiments of the circuit diagram.

[0018] Figures 12 to 24 A series of cross-sectional views are shown of some embodiments of a method for forming an image sensor including a first gate dielectric structure having a first thickness and a second gate dielectric structure having a second thickness greater than the first thickness.

[0019] Figure 25 Flowcharts of some embodiments of a method for forming an image sensor including a first gate dielectric structure having a first thickness and a second gate dielectric structure having a second thickness greater than the first thickness are shown. Detailed Implementation

[0020] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the invention. Of course, these are merely examples and are not intended to limit the invention. For example, in the following description, forming a first component on or over a second component can include embodiments where the first and second components are in direct contact, and can also include embodiments where an additional component can be formed between the first and second components, such that the first and second components are not in direct contact. Furthermore, reference numerals and / or characters may be repeated in various instances of the invention. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0021] Furthermore, for ease of description, this document uses spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” to describe the relationship between one element or component and another (or other elements or components) as shown in the figures. In addition to the orientations depicted in the figures, spatial relative terms are intended to include different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted accordingly.

[0022] Many portable electronic devices (e.g., cameras, cell phones, etc.) include image sensors for capturing images. One example of such an image sensor is a complementary metal-oxide-semiconductor (CMOS) image sensor (CIS) with an array of pixel sensors. Each pixel sensor includes a photodetector disposed in a substrate. Each pixel sensor includes a transfer gate configured to transfer accumulated charge from the photodetector to a floating diffusion node. A back-side deep trench isolation (BDTI) structure is disposed in the substrate and laterally surrounds the photodetector. The BDTI structure provides good electrical isolation between the photodetectors.

[0023] Typically, a shallow trench isolation (STI) structure and / or a contact etch stop layer (CESL) are required to form the BDTI structure. The STI structure is disposed within the substrate. The CESL is disposed above the front side of the substrate and above the transport gate. Since the BDTI structure is formed from the back side of the substrate, the STI structure and / or CESL are needed to ensure that the BDTI structure formation process has a safe landing area (e.g., an area near / on the front side of the substrate where the etch process used to form the BDTI structure can land / stop without damaging other structures such as the transport gate, conductive contacts, etc.). Relying on the STI structure and / or CESL to provide a safe landing area can adversely affect the performance of the CIS (e.g., poor dark current performance, poor white pixel performance, poor full-well capacity, etc.).

[0024] For example, to provide a safe landing area for the STI structure, the STI must be relatively large (e.g., due to the difficulty in controlling the stacking during BDTI structure formation). Therefore, the STI consumes a significant portion of the CIS area. Consequently, the size of the photodetector (e.g., the coverage area) may have to be reduced, which can adversely affect CIS performance (e.g., reduced full-well capacity performance). Furthermore, the processes used to form the STI structure (e.g., etching the substrate) can damage the substrate, which can further degrade CIS performance (e.g., damage can adversely affect dark current and / or white pixel performance). Additionally, guard well regions (e.g., p-wells) are often used in conjunction with the STI structure to protect the STI structure and / or ensure proper passivation of the STI / substrate interface, which can further degrade CIS performance (e.g., guard well regions consume even more area, which can further reduce full-well capacity performance).

[0025] In another example, the CESL can serve as a safe landing area (e.g., without an STI structure). In such a case, a large area (e.g., large lateral spacing) must be reserved between the BDTI structure and the conductive contacts (e.g., metal contacts) extending (vertically) from the transfer gate. This large area is required to ensure that the BDTI structure formation process does not damage the conductive contacts (and / or the transfer gate), which could adversely affect the performance of the CIS and / or reduce yield (e.g., due to disruption of CIS functionality during manufacturing). For example, because the CESL is positioned above the transfer gate and the conductive contacts penetrate the CESL, if the etching process of the BDTI formation process unintentionally occurs below the conductive contacts (e.g., due to difficulty in controlling the stacking), the etching process of the BDTI formation process may undesirably etch through the transfer gate and into the conductive contacts, thereby damaging the conductive contacts (and / or the transfer gate). The large area restricts the location of the conductive contacts and back-end process (BEOL) wiring (e.g., metal layer 1 wiring). Therefore, using CESL for safe landing areas may limit the ability to scale down CIS size (e.g., limit the development of CIS with extremely small pixel pitch).

[0026] Various embodiments of the present invention relate to image sensors (e.g., CIS). The image sensor includes a deep trench isolation (DTI) structure disposed in a semiconductor substrate. Pixel regions of the semiconductor substrate are disposed within the inner perimeter of the DTI structure. A photodetector is disposed in the pixel regions of the semiconductor substrate. A gate electrode structure is at least partially located above the pixel regions of the semiconductor substrate. A first gate dielectric structure is partially located above the pixel regions of the semiconductor substrate. A second gate dielectric structure is partially located above the pixel regions of the semiconductor substrate. The gate electrode structure is located above portions of the first and second gate dielectric structures. The first gate dielectric structure has a first thickness. The second gate dielectric structure has a second thickness greater than the first thickness. The dielectric structure is disposed above the semiconductor substrate. Conductive contacts are disposed in the dielectric structure and extend perpendicularly from the gate electrode structure. The conductive contacts are located above portions of the second gate dielectric structure.

[0027] Because the second gate dielectric structure has a second thickness, it can be used to provide a safe landing region for the process used to form the DTI structure. Therefore, compared to a typical CIS, the size of the gate electrode (e.g., the gate electrode of the transfer gate) can be increased and / or the gate electrode can be positioned closer (in the lateral direction) to the DTI. Consequently, the conductive contacts can also be positioned closer to the DTI (and in some cases overlap with the DTI) compared to a typical CIS. Furthermore, because the gate electrode structure is located above portions of the first and second gate dielectric structures, the charge accumulated in the photodetector can be effectively transferred from the photodetector to the floating diffusion node (e.g., if the transfer gate has a gate dielectric that is too thick near the floating diffusion node, the ability of the transfer gate to control charge transfer from the photodetector to the floating diffusion node may be adversely affected). Therefore, image sensors can improve their ability to scale down CIS dimensions.

[0028] Figures 1A to 1B Various views 100a-100b of some embodiments of an image sensor are shown, including a first gate dielectric structure 112 having a first thickness 114 and a second gate dielectric structure 116 having a second thickness 118 greater than the first thickness 114. More specifically, Figure 1A Cross-sectional view 100a shows some embodiments of an image sensor including a first gate dielectric structure having a first thickness and a second gate dielectric structure having a second thickness greater than the first thickness. Figure 1B It shows Figure 1A The layout diagram of the image sensor shown is 100b. Figure 1A Cross-sectional view 100a along Figure 1B Line AA is cut off.

[0029] like Figures 1A to 1BAs shown in views 100a-100b, the image sensor includes a substrate 102 (e.g., a semiconductor substrate). The substrate 102 has a front side 102f and a back side 102b opposite to the front side 102f. In some embodiments, the front side 102f of the substrate 102 is defined by a first surface (e.g., a front surface), and the back side 102b of the substrate 102 is defined by a second surface (e.g., a back surface) opposite to the first surface. The substrate 102 may include any type of semiconductor body (e.g., a single-crystal silicon / CMOS block, silicon-germanium (SiGe), silicon-on-insulator (SOI), etc.). In some embodiments, the image sensor (e.g., a back-illuminated image sensor) is configured to record incident radiation (e.g., photons) passing through the back side 102b of the substrate 102.

[0030] A photodetector 104 (e.g., a photodiode) is disposed in a substrate 102. The photodetector 104 includes a portion of the substrate 102 having a first doping type (e.g., n-type / p-type). In some embodiments, a portion of the substrate 102 adjacent to the photodetector 104 has a second doping type opposite to the first doping type (e.g., p-type / n-type), or may be inherent thereto. The photodetector 104 is configured to absorb incident radiation (e.g., light) and generate an electrical signal corresponding to the incident radiation.

[0031] A floating diffusion node 106 is disposed in the substrate 102 and laterally spaced from the photodetector 104. The floating diffusion node 106 is a region of the substrate 102 having a first doping type. In some embodiments, a doped well 108 is disposed in the substrate 102. In a further embodiment, the floating diffusion node 106 may be disposed in the doped well 108. The doped well 108 is a region of the substrate 102 having a second doping type.

[0032] A gate electrode structure 110 is disposed above the front side 102f of the substrate 102. The front side 102f of the substrate 102 is vertically disposed between the gate electrode structure 110 and the back side 102b of the substrate 102. In some embodiments, the gate electrode structure 110 is or includes, for example, polysilicon, metals (e.g., aluminum (Al), copper (Cu), titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (Mo), cobalt (Co), etc.), some other conductive materials, or combinations thereof.

[0033] A first gate dielectric structure 112 is disposed above the front side 102f of the substrate 102. The first gate dielectric structure 112 has a first thickness 114. In some embodiments, the first gate dielectric structure 112 is or includes, for example, an oxide (e.g., silicon dioxide (SiO2)), a high-k dielectric material (e.g., hafnium oxide (HfO), tantalum oxide (TaO), hafnium silicon oxide (HfSiO), hafnium tantalum oxide (HfTaO), aluminum oxide (AlO), zirconium oxide (ZrO), some other dielectric materials having a dielectric constant greater than about 3.9), some other dielectric materials, or combinations thereof.

[0034] The second gate dielectric structure 116 is disposed above the front side 102f of the substrate 102. In some embodiments, the second gate dielectric structure 116 is disposed on the side of the first gate dielectric structure 112, such as... Figure 1A As shown in cross-sectional view 100a, the second gate dielectric structure 116 has a second thickness 118 greater than the first thickness 114. In some embodiments, the second gate dielectric structure 116 is or includes, for example, an oxide (e.g., silicon dioxide (SiO2)), a high-k dielectric material (e.g., hafnium oxide (HfO), tantalum oxide (TaO), hafnium silicon oxide (HfSiO), hafnium tantalum oxide (HfTaO), aluminum oxide (AlO), zirconium oxide (ZrO), some other dielectric materials having a dielectric constant greater than about 3.9), some other dielectric materials, or combinations thereof. In some embodiments, the second gate dielectric structure 116 and the first gate dielectric structure 112 have the same chemical composition (e.g., SiO2). In other embodiments, the first gate dielectric structure 112 and the second gate dielectric structure 116 may have different chemical compositions. In some embodiments, the second gate dielectric structure 116 laterally surrounds the first gate dielectric structure 112.

[0035] In some embodiments, the gate electrode structure 110 is or includes polysilicon. In such embodiments, the first gate dielectric structure 112 and / or the second gate dielectric structure 116 may be or include, for example, oxides (e.g., SiO2). In other embodiments, the gate electrode structure 110 may be or includes metals such as aluminum (Al), copper (Cu), titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (Mo), cobalt (Co), etc. In such embodiments, the first gate dielectric structure 112 and / or the second gate dielectric structure 116 may be or include high-k dielectric materials such as hafnium oxide (HfO), tantalum oxide (TaO), hafnium silicon oxide (HfSiO), hafnium tantalum oxide (HfTaO), aluminum oxide (AlO), zirconium oxide (ZrO), etc.

[0036] The gate electrode structure 110 is at least partially located on the first gate dielectric structure 112. The gate electrode structure 110 is at least partially located on the second gate dielectric structure 116. The gate electrode structure 110 is located on a portion 120 of the first gate dielectric structure 112 and a portion 122 of the second gate dielectric structure 116. In some embodiments, the portion of the gate electrode structure 110 located on the portion 120 of the first gate dielectric structure 112 has a first height (e.g., the vertical distance between the upper and lower surfaces). In a further embodiment, the portion of the gate electrode structure 110 located on the portion 122 of the second gate dielectric structure 112 has a second height less than the first height. In a still further embodiment, the portion of the gate electrode structure 110 located on the portion 120 of the first gate dielectric structure 112 is referred to as a first portion of the gate electrode structure 110; and the portion of the gate electrode structure 110 located on the portion 122 of the second gate dielectric structure 116 is referred to as a second portion of the gate electrode structure 110.

[0037] A transfer gate 124 is defined by the gate electrode structure 110, the portion of the first gate dielectric structure 112 located thereon, and the portion of the second gate dielectric structure 116 located thereon. For example, the transfer gate 124 is defined by the gate electrode structure 110, the portion 120 of the first gate dielectric structure 112, and the portion 122 of the second gate dielectric structure 116. The transfer gate 124 is disposed on the front side 102f of the substrate 102. The transfer gate 124 is configured to selectively form a conductive channel between the photodetector 104 and the floating diffusion node 106, thereby allowing charge accumulated in the photodetector 104 (e.g., by absorbing incident radiation) to be transferred to the floating diffusion node 106.

[0038] An interlayer dielectric (ILD) structure 126 is disposed over the front side 102f of the substrate 102. The ILD structure 126 is disposed over the first gate dielectric structure 112, the second gate dielectric structure 116, and the gate electrode structure 110 (and thus the transport gate 124). In some embodiments, the ILD structure 126 comprises one or more stacked ILD layers, which may respectively comprise a low-k dielectric (e.g., a dielectric material having a dielectric constant less than about 3.9), an oxide (e.g., SiO2), etc. In some embodiments, the ILD structure 126 is referred to as a dielectric structure.

[0039] Interconnect structure 128 (e.g., copper interconnect) is disposed in ILD structure 126 and above the front side 102f of substrate 102. Interconnect structure 128 includes a plurality of conductive contacts 128a (e.g., metal contacts), a plurality of conductive vias 128b (e.g., metal vias), and a plurality of wires 128c (e.g., metal wires). In some embodiments, interconnect structure 128 may be or include, for example, copper (Cu), aluminum (Al), tungsten (W), gold (Au), some other conductive materials, or combinations thereof. In a further embodiment, the plurality of conductive contacts 128a may include a first conductive material (e.g., W), and the plurality of conductive vias 128b and the plurality of wires 128c may include a second conductive material (e.g., Cu) different from the first conductive material.

[0040] The plurality of conductive contacts 128a include a first conductive contact 128a1 and a second conductive contact 128a2. The first conductive contact 128a1 extends vertically from the gate electrode structure 110 to a first of the plurality of wires 128c. The first conductive contact 128a1 electrically couples the gate electrode structure 110 to the first of the plurality of wires 128c. The first conductive contact 128a1 is located on the second gate dielectric structure 116. In some embodiments, the first conductive contact 128a1 is located on a portion 122 of the second gate dielectric structure 116.

[0041] The second conductive contact 128a2 extends vertically from the floating diffusion node 106 to the second of the plurality of wires 128c. The second conductive contact 128a2 electrically couples the floating diffusion node 106 to the second of the plurality of wires 128c.

[0042] A deep trench isolation (DTI) structure 130 is disposed in a substrate 102. The DTI structure 130 extends from the back side 102b of the substrate 102 into the substrate 102. In some embodiments, the DTI structure 130 extends vertically through the substrate 102 from the back side 102b (e.g., a back surface) to at least the front side 102f (e.g., a front surface) of the substrate 102 (e.g., the DTI structure 130 extends completely through the substrate 102). In some embodiments, the DTI structure 130 contacts (e.g., directly contacts) a second gate dielectric structure 116. In a further embodiment, the DTI structure 130 may extend vertically through the substrate 102 (e.g., from the back side 102b and through the front side 102f) to contact the second gate dielectric structure 116. In some embodiments, the DTI structure 130 is referred to as an isolation structure. In other embodiments, the DTI structure 130 may be referred to as a back-side deep trench isolation (BDTI) structure.

[0043] Because the second gate dielectric structure 116 has a second thickness 118, it can serve as a safe landing region for the process of forming the DTI structure 130, as will be described in more detail below. Therefore, the size of the gate electrode structure 110 can be increased and / or the gate electrode structure 110 can be configured to be closer (in the lateral direction) to the DTI structure 130 compared to a typical image sensor (e.g., an image sensor with a transfer gate having a gate dielectric of consistently uniform thickness). Consequently, the first conductive contact 128a1 can also be configured to be closer to the DTI structure 130 compared to a typical image sensor. Furthermore, because the gate electrode structure 110 is located on portion 120 of the first gate dielectric structure 112 and portion 122 of the second gate dielectric structure 116, the charge accumulated in the photodetector 104 can be effectively transferred from the photodetector 104 to the floating diffusion node 106 (e.g., if the transfer gate 124 has too thick a gate dielectric near the floating diffusion node 106, the ability of the transfer gate 124 to control the transfer of charge from the photodetector 104 to the floating diffusion node 106 may be adversely affected). Therefore, the size of the image sensor can be smaller than (e.g., scaled down more than) a typical image sensor (e.g., the ability to scale down the image sensor size can be improved because the gate electrode structure 110 is located on portion 120 of the first gate dielectric structure 112 and portion 122 of the second gate dielectric structure 116).

[0044] Also there Figures 1A to 1B As shown in views 100a-100b, the DTI structure 130 extends laterally through the substrate 102. In some embodiments, the DTI structure 130 extends laterally through the substrate 102 in a closed-loop path. In some embodiments, the DTI structure 130 may laterally surround the photodetector 104. In a further embodiment, the DTI structure 130 laterally surrounds the floating diffusion node 106 (and the doped well 108). The pixel region 132 of the substrate 102 is disposed within a first perimeter 134 (e.g., an inner perimeter) of the DTI structure 130. The first perimeter 134 of the DTI structure 130 is defined by sidewalls (e.g., inner sidewalls) of the DTI structure 130.

[0045] In some embodiments, pixel region 132, components disposed within pixel region 132 (e.g., structural components) (e.g., photodetector 104, floating diffusion node 106, and doped well 108), and transfer gate 124 are part of pixel 133 of an image sensor. For example, pixel 133 includes pixel region 132, photodetector 104, floating diffusion node 106 (and doped well 108), and transfer gate 124 (which includes gate electrode structure 110, a portion 120 of first gate dielectric structure 112, and a portion 122 of second gate dielectric structure 116).

[0046] A gate electrode structure 110 is partially located on the pixel region 132 of the substrate 102. In some embodiments, the gate electrode structure 110 is laterally disposed within a first perimeter 134 of the DTI structure 130 (e.g., entirely laterally disposed therein). A first gate dielectric structure 112 is partially located on the pixel region 132 of the substrate 102. In some embodiments, the first gate dielectric structure 112 is laterally disposed within the first perimeter 134 of the DTI structure 130 (e.g., entirely laterally disposed therein). A second gate dielectric structure 116 is partially located on the pixel region 132 of the substrate 102. The second gate dielectric structure 116 is at least partially located on the DTI structure 130. In some embodiments, the second gate dielectric structure 116 is located on the DTI structure 130 (e.g., entirely therein). In some embodiments, a first conductive contact 128a1 is laterally disposed within the first perimeter 134 of the DTI structure 130.

[0047] The first gate dielectric structure 112 has a perimeter 136 (e.g., an outer perimeter). The perimeter 136 of the first gate dielectric structure 112 is defined by a sidewall (e.g., an outer sidewall) of the first gate dielectric structure 112. In some embodiments, the perimeter 136 of the first gate dielectric structure 112 is laterally disposed within a first perimeter 134 of the DTI structure 130.

[0048] In some embodiments, the second gate dielectric structure 116 has a sidewall 138 laterally disposed between the first sidewall 140 and the second sidewall 142 of the gate electrode structure 110. In some embodiments, the sidewall 138 of the second gate dielectric structure 116 is laterally adjacent (e.g., in direct contact) to the sidewall of the first gate dielectric structure 112 between the first sidewall 140 and the second sidewall 142 of the gate electrode structure 110. In some embodiments, the sidewall 138 of the second gate dielectric structure 116 faces the first gate dielectric structure 112. The first sidewall 140 of the gate electrode structure 110 is opposite to the second sidewall 142 of the gate electrode structure 110. The first sidewall 140 of the gate electrode structure 110 faces the first sidewall 144 of the DTI structure 130. In some embodiments, a first conductive contact 128a1 is laterally disposed between the second sidewall 142 of the gate electrode structure 110 and the first sidewall 144 of the DTI structure 130. In some embodiments, the first sidewall 140 of the gate electrode structure 110 has a first length; and the second sidewall 142 of the gate electrode structure 110 has a second length greater than the first length.

[0049] In some embodiments, a floating diffusion node 106 (and a doped well 108) is disposed in a pixel region 132 of the substrate 102. The floating diffusion node 106 (and the doped well 108) is disposed on a side of the DTI structure 130 (e.g., on the side of the first sidewall 144 of the DTI structure 130). A photodetector 104 is laterally disposed between the floating diffusion node 106 and the DTI structure 130 (e.g., the first sidewall 144 of the DTI structure 130).

[0050] In some embodiments, the floating diffusion node 106 (and the doped well 108) is laterally disposed within the perimeter 136 of the first gate dielectric structure 112. In some embodiments, the second conductive contact 128a2 is laterally disposed within the first perimeter 134 of the DTI structure 130. In a further embodiment, the second conductive contact 128a2 is laterally disposed within the perimeter 136 of the first gate dielectric structure 112.

[0051] In some embodiments, the first thickness 114 is less than or equal to about 70 angstroms. (For example, due to the manufacturing process, approximately (Including minor variations). In a further embodiment, the first thickness 114 is approximately Peace Treaty Between. In some embodiments, if the first thickness 114 is greater than approximately Then the transmission gate 124 may not be able to control the charge flow between the photodetector 104 and the floating diffusion node 106.

[0052] In some embodiments, the second thickness 118 is approximately Peace Treaty Between. In some embodiments, the second thickness 118 is approximately... In some embodiments, if the second thickness 118 is greater than approximately The transfer gate 124 may then be unable to control the charge flow between the photodetector 104 and the floating diffusion node 106 (e.g., due to a reduction in the effective height of the gate electrode structure 110). In a further embodiment, if the second thickness 118 is less than approximately The second dielectric structure 122 may not be usable as a safe landing area (e.g., because the etching process used to form the DTI structure 130 can easily etch completely through the second gate dielectric structure 116).

[0053] Figures 2A to 2B It shows Figures 1A to 1B Various views 200a-200b of some other embodiments of the image sensor. More specifically, Figure 2A It shows Figures 1A to 1B Cross-sectional view 200a of some other embodiments of the image sensor. Figure 2B It shows Figure 2A The layout diagram of the image sensor shown is 200b. Figure 2A Cross-sectional view 200a along Figure 2B Line AA is cut off.

[0054] like Figures 2A to 2B As shown in views 200a-200b, in some embodiments, the gate electrode structure 110 is located on top of the DTI structure 130. In a further embodiment, a first perimeter 134 of the DTI structure 130 is partially disposed within the perimeter 202 (e.g., outer perimeter) of the gate electrode structure 110. The perimeter 202 of the gate electrode structure 110 is defined by a sidewall (e.g., outer sidewall) of the gate electrode structure 110. In a further embodiment, a second perimeter 204 of the DTI structure 130 is partially disposed within the perimeter 202 of the gate electrode structure 110. The second perimeter 204 of the DTI structure 130 is defined by a sidewall (e.g., outer sidewall) of the DTI structure 130.

[0055] In some embodiments, a first sidewall 144 of the DTI structure 130 is laterally disposed between the first sidewall 140 and the second sidewall 142 of the gate electrode structure 110. In a further embodiment, a second sidewall 206 of the DTI structure 130 is laterally disposed between the first sidewall 140 and the second sidewall 142 of the gate electrode structure 110. In some embodiments, a third sidewall 208 of the DTI structure 130 is laterally disposed between the third sidewall 210 and the fourth sidewall 212 of the gate electrode structure 110. The third sidewall 210 of the gate electrode structure 110 is opposite to the fourth sidewall 212 of the gate electrode structure 110. In a further embodiment, a fourth sidewall 214 of the DTI structure 130 is laterally disposed between the third sidewall 210 and the fourth sidewall 212 of the gate electrode structure 110. In some embodiments, the DTI structure 130 is laterally disposed between the sidewall 138 of the second gate dielectric structure 116 and the first sidewall 140 of the gate electrode structure 110.

[0056] Also there Figures 2A to 2B As shown in views 200a-200b, in some embodiments, the first conductive contact 128a1 is located on the DTI structure 130. In such embodiments, the first conductive contact 128a1 is at least partially laterally disposed between the first perimeter 134 and the second perimeter 204 of the DTI structure 130. In further embodiments, the first perimeter 134 and / or the second perimeter 204 of the DTI structure 130 may be partially disposed within the perimeter of the first conductive contact 128a1. Because the first conductive contact 128a1 is located on the DTI structure 130, the size of the image sensor can be even smaller compared to a typical image sensor.

[0057] Also there Figures 2A to 2B As shown in views 200a-200b, in some embodiments, the front side 102f (e.g., the front surface) of the substrate 102 is perpendicularly disposed between the surface 216 (e.g., the upper surface) of the DTI structure 130 and the back side 102b (e.g., the back surface) of the substrate 102. In such an embodiment, the surface 218 of the second gate dielectric structure 116 is perpendicularly disposed between the surface 216 of the DTI structure 130 and the front side 102f (e.g., the front surface) of the substrate 102. In a further such embodiment, the surface 218 of the second gate dielectric structure 116 may be adjacent to (e.g., in direct contact with) the front side 102f of the substrate 102.

[0058] Figure 3 It shows Figures 2A to 2B Layout diagram 300 of some other embodiments of the image sensor.

[0059] like Figure 3 As shown in layout diagram 300, in some embodiments, a first conductive contact 128a1 is disposed within (e.g., completely disposed therein) the second perimeter 204 of the DTI structure 130. In some embodiments, the first conductive contact 128a1 is laterally disposed between the second perimeter 204 and the first perimeter 134 of the DTI structure 130. In some embodiments, the first conductive contact 128a1 is disposed outside (e.g., completely disposed therein) the first perimeter 134 of the DTI structure 130.

[0060] Figure 4 It shows Figures 2A to 2B Layout diagram 400 shows some other embodiments of the image sensor.

[0061] like Figure 4 As shown in layout figure 400, in some embodiments, one or more sidewalls of the gate electrode structure 110 may be substantially aligned with one or more sidewalls of the DTI structure 130 (e.g., substantially aligned includes minor variations due to manufacturing processes). For example, in some embodiments, the first sidewall 140 of the gate electrode structure 110 is substantially aligned with the first sidewall 144 of the DTI structure 130. In some embodiments, the third sidewall 210 of the gate electrode structure 110 is substantially aligned with the third sidewall 208 of the DTI structure 130. In such embodiments, the first conductive contact 128a1 may be laterally disposed within the first perimeter 134 of the DTI structure 130.

[0062] Figure 5 It shows Figure 3 Layout diagram 500 of some other embodiments of the image sensor.

[0063] like Figure 5 As shown in layout diagram 500, the image sensor includes a plurality of pixels 502. For example, the image sensor includes a first pixel 502a, a second pixel 502b, a third pixel 502c, and a fourth pixel 502d. The plurality of pixels 502 are arranged in an array including rows and columns. In some embodiments, each of the pixels of the plurality of pixels 502 includes a component (e.g., a structural component / assembly) substantially similar to the pixel 133 described herein. In a further embodiment, each of the pixels of the plurality of pixels 502 has a substantially similar layout.

[0064] For example, such as Figure 5 As shown in the layout diagram 500, the first pixel 502a includes a transmission gate 124 (which includes a gate electrode structure 110, a portion 120 of a first gate dielectric structure 112, and a portion 122 of a second gate dielectric structure 116), a first gate dielectric structure 112, a floating diffusion node 106, and a pixel region 132. Although not shown in Figure 5 As shown, but it should be understood that the first pixel 502a includes a photodetector 104 (and a doped well 108) and any other components that can be disposed in the pixel region 132 (see example). Figures 1A to 1B The first conductive contact 128a1 extends vertically from the gate electrode structure 110 to the first of the plurality of wires 128c (see example). Figures 1A to 1B The second conductive contact 128a2 extends vertically from the floating diffusion node 106 to the second of the plurality of conductors 128c (see example). Figures 1A to 1B )).

[0065] The second pixel 502b, the third pixel 502c, and the fourth pixel 502d include components substantially similar to those of the first pixel 502a. Furthermore, the first pixel 502a, the second pixel 502b, the third pixel 502c, and the fourth pixel 502d have substantially similar layouts. For example, the second pixel 502b includes a pixel region 504 disposed in the substrate 102 (not shown), which is substantially similar to pixel region 132. A photodetector (not shown) and a floating diffusion node 506 (and a doped well (not shown)) are disposed in pixel region 504. The photodetector disposed in pixel region 504 is substantially the same as photodetector 104. The floating diffusion node 506 (and the doped well) disposed in pixel region 504 is substantially the same as floating diffusion node 106 (and doped well 108).

[0066] The second gate dielectric structure 116 is partially located on the pixel region 504. The third gate dielectric structure 508 is partially located on the pixel region 504. The third gate dielectric structure 508 is substantially the same as the first gate dielectric structure 112. The gate electrode structure 510 is at least partially located on the third gate dielectric structure 508. The gate electrode structure 510 is at least partially located on the second gate dielectric structure 116. The gate electrode structure 510 is located on a portion 512 of the third gate dielectric structure 508 and a portion 514 of the second gate dielectric structure 116. The gate electrode structure 510 is substantially the same as the gate electrode structure 110.

[0067] The gate electrode structure 510, a portion 512 of the third gate dielectric structure 508, and a portion 514 of the second gate dielectric structure 116 define a transfer gate 516. The transfer gate 516 is substantially identical to the transfer gate 124. The third conductive contact 128a3 of the plurality of conductive contacts 128a (see...) Figures 1A to 1B ) Extending vertically from the gate electrode structure 510 to the third of the plurality of wires 128c (see Figures 1A to 1BThe third conductive contact 128a3 electrically couples the gate electrode structure 510 to the third of the plurality of conductors 128c. The third conductive contact 128a3 is substantially the same as the first conductive contact 128a1. The plurality of conductive contacts 128a (see...) Figures 1A to 1B The fourth conductive contact 128a4 extends vertically from the floating diffusion node 506 to the fourth of the plurality of conductors 128c (see Figures 1A to 1B The fourth conductive contact 128a4 electrically couples the floating diffusion node 506 to the fourth of the plurality of conductors 128c. The fourth conductive contact 128a4 is substantially the same as the second conductive contact 128a2.

[0068] The DTI structure 130 extends laterally through the substrate 102 and laterally surrounds each of the pixel regions of the plurality of pixels 502. For example, the DTI structure 130 extends laterally through the substrate 102 and laterally surrounds pixel region 132, pixel region 504, etc. Figure 5 As shown in layout diagram 500, the second gate dielectric structure 116 extends laterally above the substrate 102 and laterally surrounds other gate dielectric structures of the plurality of pixels 502. For example, the second gate dielectric structure 116 extends laterally above the substrate 102 and laterally surrounds the first gate dielectric structure 112, the third gate dielectric structure 508, etc., as shown in the layout diagram 500. Figure 5 The layout is shown in diagram 500. Although Figure 5 Four (4) pixels are shown, but it should be understood that... Figure 5 Image sensors can include any number of pixels (e.g., 1, 2, 4, 8, 16, 32, 64, etc.).

[0069] Figure 6 It shows Figure 5 Layout diagram 600 shows some other embodiments of the image sensor.

[0070] like Figure 6 As shown in layout diagram 600, in some embodiments, the transmission gate of pixel 502 is located on DTI structure 130. For example, transmission gate 124 is located on DTI structure 130, transmission gate 516 is located on DTI structure 130, etc. Figure 6 The layout is shown in Figure 600. In a further embodiment, conductive contacts 128a, which extend vertically from the gate electrodes of the plurality of pixels 502, are located on the DTI structure 130. For example, a first conductive contact 128a1 is located on the DTI structure 130, a third conductive contact 128a3 is located on the DTI structure 130, and so on. Figure 6 The layout is shown in diagram 600. Although Figure 6 Four (4) pixels are shown, but it should be understood that... Figure 6Image sensors can include any number of pixels (e.g., 1, 2, 4, 8, 16, 32, 64, etc.).

[0071] Figure 7 It shows Figures 1A to 1B Cross-sectional view 700 of some other embodiments of the image sensor.

[0072] like Figure 7 As shown in cross-sectional view 700, the image sensor may include a sidewall spacer 702 disposed above the substrate 102 and along the sidewall of the gate electrode structure 110. In some embodiments, the sidewall spacer 702 is disposed above the first gate dielectric structure 112 and the second gate dielectric structure 116. The sidewall spacer 702 may extend laterally around the gate electrode structure 110 in a closed-loop path.

[0073] The sidewall spacer 702 has a first height above the first gate dielectric structure 112 and a second height less than the first height above the second gate dielectric structure 116. For example, the sidewall spacer 702 has a first portion located above the first gate dielectric structure 112 and a second portion located above the second gate dielectric structure 116. The first portion of the sidewall spacer 702 has the first height, and the second portion of the sidewall spacer has a second height less than the first height, such as... Figure 7 As shown in cross-sectional view 700. In some embodiments, the sidewall spacer 702 may be or include, for example, oxides (e.g., SiO2), nitrides (e.g., SiN), or oxynitrides (e.g., SiO2). X N Y ), some other dielectrics or combinations thereof (e.g., ONO sidewall spacers).

[0074] A contact etch stop layer (CESL) 704 may be disposed over the substrate 102, the first gate dielectric structure 112, the second gate dielectric structure 116, the gate electrode structure 110, and the sidewall spacers 702. In some embodiments, the CESL 704 is lined with the first gate dielectric structure 112, the second gate dielectric structure 116, the gate electrode structure 110, and the sidewall spacers 702. A plurality of conductive contacts 128a penetrate the CESL 704. For example, a first conductive contact 128a1 penetrates the CESL 704 to contact the gate electrode structure 110, and a second conductive contact 128a2 penetrates the CESL 704 to contact the floating diffusion node 106. The CESL 704 may be or include, for example, oxides (e.g., SiO2), nitrides (e.g., SiN), oxynitrides (e.g., SiON), some other dielectric materials, or combinations thereof.

[0075] In some embodiments, dielectric layer 706 liner the back side 102b (e.g., the back surface) of the substrate and the DTI structure 130. Dielectric layer 706 extends from the back side 102b and along the sidewalls of the DTI structure 130 into the substrate 102. In some embodiments, dielectric layer 706 is referred to as a dielectric pad layer.

[0076] In some embodiments, the dielectric layer 706 penetrates the front side 102f (e.g., the front surface) of the substrate 102 and partially penetrates the second gate dielectric structure 116, such as Figure 7 The cross-sectional view 700 shows this. In some embodiments, the dielectric layer 706 also liners the upper surface of the DTI structure 130, such that the dielectric layer 706 is vertically disposed between the DTI structure 130 and the second gate dielectric structure 116 (e.g., directly vertically disposed between them). In some embodiments, the dielectric layer 706 may be or include, for example, oxides (e.g., SiO2), nitrides (e.g., SiN), oxynitrides (e.g., SiON), carbides (e.g., silicon carbide (SiC)), high-k dielectrics (e.g., HfO, TaO, etc.), some other dielectric materials, or combinations thereof. In some embodiments, the DTI structure 130 may be or include, for example, oxides (e.g., SiO2), nitrides (e.g., SiN), oxynitrides (e.g., SiON), tetraethyl orthosilicate (TEOS), some other dielectric materials, or combinations thereof. In some embodiments, the DTI structure 130 has a first chemical composition (e.g., TEOS), and the dielectric layer 706 has a second chemical composition (e.g., a high-k dielectric) different from the first chemical composition. In embodiments where the image sensor includes a dielectric layer 706 and a DTI structure 130, portions of the surface (e.g., sidewalls, top surface, etc.) of the DTI structure 130 and the inner lining DTI structure of the dielectric layer 706 can be collectively referred to as the DTI structure (e.g., BDTI structure).

[0077] In some embodiments, the light transmission structure 708 is disposed along the dielectric layer 706 and the DTI structure 130. In some embodiments, the dielectric layer 706 perpendicularly separates the light transmission structure 708 from the back side 102b of the substrate 102. In some embodiments, the light transmission structure 708 is an anti-reflection layer (e.g., an anti-reflection coating (ARC)). In some embodiments, the light transmission structure 708 is or includes, for example, oxides (e.g., SiO2), nitrides (e.g., SiN), carbides (e.g., SiC), high-k dielectrics (e.g., HfO, TaO, etc.).

[0078] In some embodiments, the dielectric grid 710 is disposed along the light transmission structure 708. The light transmission structure 708 can vertically separate the dielectric grid 710 from the back side 102b of the substrate 102. The dielectric grid 710 can be or includes, for example, oxides (e.g., SiO2), nitrides (e.g., SiN), carbides (e.g., SiC), high-k dielectrics (e.g., HfO, TaO, etc.), low-k dielectrics, some other dielectrics, or combinations thereof.

[0079] In some embodiments, a metal grid 712 is embedded in a dielectric grid 710. The metal grid 712 is configured to reflect incident radiation away from the back side 102b of the substrate 102. An optical transmission structure 708 can vertically separate the metal grid 712 from the back side 102b of the substrate 102. In some embodiments, the metal grid 712 is or includes, for example, aluminum (Al), cobalt (Co), copper (Cu), silver (Ag), gold (Au), tungsten (W), some other metals, or combinations thereof.

[0080] In some embodiments, an electromagnetic radiation (EMR) filter 714 (e.g., an infrared filter, a color filter, etc.) is disposed along the light transmission structure 708 and within the dielectric grid 710. The light transmission structure 708 can vertically separate the EMR filter 714 from the back side 102b of the substrate 102. The EMR filter 714 is configured to transmit a specific wavelength (or a specific wavelength range) of incident radiation. It should be understood that the EMR filter 714 may be one of a plurality of EMR filters disposed within the dielectric grid 710.

[0081] In some embodiments, the microlens 716 is disposed along the EMR filter 714. In some embodiments, the EMR filter 714 vertically separates the microlens 716 from the back side 102b of the substrate 102. In some embodiments, the microlens 716 is substantially centered above the pixel region 132. The microlens 716 is configured to focus incident radiation toward the photodetector 104. It should be understood that the microlens 716 may be one of a plurality of microlenses disposed along a plurality of EMR filters.

[0082] Figure 8 It shows Figure 7 Cross-sectional view 800 of some other embodiments of the image sensor.

[0083] like Figure 8As shown in cross-sectional view 800, in some embodiments, the IC includes a first chip 802, a second chip 804, and a third chip 806. The first chip 802, the second chip 804, and the third chip 806 are bonded together. The first chip 802, the second chip 804, and the third chip 806 are stacked vertically and electrically coupled together. In such embodiments, the image sensor may be referred to as a three (3) chip image sensor (e.g., a 3-chip CIS).

[0084] The first chip 802 includes a substrate 102, a photodetector 104, a floating diffusion node 106, a doped well 108, a first gate dielectric structure 112, a second gate dielectric structure 116, a gate electrode structure 110, a transfer gate 124, a sidewall spacer 702, an ILD structure 126, a first conductive contact 128a1, and a second conductive contact 128a2. Although not in Figure 8 As shown, but it should be understood that the first chip 802 may include Figures 1A to 7 Any of the components (e.g., structural components) of the image sensor shown.

[0085] The second chip 804 includes a substrate 808 (e.g., a semiconductor substrate). One or more readout transistors 810 (e.g., a reset transistor, a source follower transistor, a row select transistor, a halo transistor, etc.) are disposed on / in the substrate 808. In some embodiments, an isolation structure 812 (e.g., a shallow trench isolation (STI) structure) is disposed in the substrate 808 and laterally surrounds the one or more readout transistors 810.

[0086] An ILD structure 814 is disposed above a substrate 808 and one or more readout transistors 810. An interconnect structure 816 (e.g., a copper interconnect structure) is embedded in the ILD structure 814. The interconnect structure 816 electrically couples one or more readout transistors 810 together in a predetermined manner. The interconnect structure 816 includes a plurality of conductive elements 818 (e.g., metal lines, vias, and / or contacts) and a plurality of conductive bonding pads 820. In some embodiments, a first conductive contact 128a1 and a second conductive contact 128a2 extend vertically from a first chip 802 to corresponding conductive elements of the plurality of conductive elements 818, thereby electrically coupling the first chip 802 to a second chip 804.

[0087] The third chip 806 includes a substrate 822 (e.g., a semiconductor substrate). One or more logic transistors 824 are disposed on / in the substrate 822. In some embodiments, an isolation structure 825 (e.g., an STI structure) is disposed in the substrate 822 and laterally surrounds the one or more logic transistors 824.

[0088] ILD structure 826 is vertically disposed between substrate 822 and ILD structure 814. Interconnect structure 828 (e.g., copper interconnect structure) is embedded in ILD structure 826. Interconnect structure 828 electrically couples one or more logic transistors 824 together in a predetermined manner. Interconnect structure 828 includes a plurality of conductive parts 830 (e.g., metal lines, vias, and / or contacts) and a plurality of conductive bonding pads 832. Conductive bonding pads 832 are electrically coupled to conductive bonding pads 820, thereby electrically coupling second chip 804 to third chip 806.

[0089] In some embodiments, the first chip 802 may include only a pass gate (e.g., pass gate 124) and not any one of the one or more read transistors 810 or any one of the one or more logic transistors 824. In such embodiments, the second chip 804 may include only one or more read transistors 810 and not any one of the one or more logic transistors 824 or any one of the pass gates. In a further such embodiment, the third chip 806 may include only one or more logic transistors 824 and not any one of the one or more read transistors 810 or any one of the pass gates.

[0090] In other embodiments, the first chip 802 includes only a transfer gate (e.g., transfer gate 124) and excludes any one of the one or more readout transistors 810 or any one of the one or more logic transistors 824. In such embodiments, the second chip 804 may include only one or more readout transistors 810 and one or more logic transistors 824, excluding any one of the transfer gates. In a further such embodiment, the image sensor may include only the first chip 802 and the second chip 804 (e.g., a 2-chip CIS).

[0091] In other embodiments, the first chip 802 includes only a transfer gate (e.g., transfer gate 124) and one or more readout transistors 810, excluding any one of the one or more logic transistors 824. In such embodiments, the second chip 804 may include only one or more logic transistors 824, excluding either the transfer gate or any one of the one or more readout transistors 810. In a further such embodiment, the image sensor may include only the first chip 802 and the second chip 804 (e.g., a 2-chip CIS).

[0092] In other embodiments, the first chip 802 includes only a transfer gate (e.g., transfer gate 124) and one or more logic transistors 824, excluding any one of the one or more readout transistors 810. In such embodiments, the second chip 804 may include only one or more readout transistors 810, excluding either the transfer gate or any one of the one or more logic transistors 824. In a further such embodiment, the image sensor may include only the first chip 802 and the second chip 804 (e.g., a 2-chip CIS).

[0093] In other embodiments, the first chip 802 may include a transfer gate, one or more readout transistors 810, and one or more logic transistors 824. In such embodiments, the image sensor may consist only of the first chip 802 (e.g., a 1-chip CIS).

[0094] Figure 9 It shows Figure 8 Layout diagram 900 of some embodiments of the second chip of the image sensor.

[0095] like Figure 9 As shown in layout diagram 900, the second chip 804 includes one or more read transistors 810. The one or more read transistors 810 include a first read transistor 810a, a second read transistor 810b, and a third read transistor 810c. Each read transistor includes a gate stack having a gate electrode structure located on top of a gate dielectric structure. For example, the first read transistor 810a includes a first gate stack 902a, the second read transistor 810b includes a second gate stack 902b, and the third read transistor 810c includes a third gate stack 902c. The first gate stack 902a includes a first gate electrode structure located on top of a first gate dielectric structure, the second gate stack 902b includes a second gate electrode structure located on top of a second gate dielectric structure, and the third gate stack 902c includes a third gate electrode structure located on top of a third gate dielectric structure.

[0096] Each of the readout transistors includes a pair of source / drain regions disposed on opposite sides of the corresponding gate stack. For example, the first readout transistor 810a includes a first source / drain region pair 904 disposed on opposite sides of the first gate stack 902a. The second readout transistor 810b includes a second source / drain region pair 906 disposed on opposite sides of the second gate stack 902b. The third readout transistor 810c includes a third source / drain region pair 908 disposed on opposite sides of the third gate stack 902c.

[0097] In some embodiments, the first readout transistor 810a is a reset transistor, the second readout transistor 810b is a row select transistor, and the third readout transistor 810c is a source follower transistor. In a further embodiment, Figure 9 The layout diagram 900 is directly located in Figure 1B Layout diagram 100b Figure 2B Layout diagram 200b Figure 3 Layout diagram 300 Figure 4 Layout diagram 400 Figure 5 Layout diagram 500 or Figure 6 The layout diagram is on 600. Although Figure 9 Only three (3) readout transistors are shown, but it should be understood that the second chip 804 may include any number of readout transistors (e.g., 1, 2, 4, 5, 6, 10, 20, etc.) configured to operate the pixels (e.g., pixel 133) of the first chip 802 (e.g., anti-halo transistors, or other types of transistors that provide special functions to pixel 133).

[0098] Figure 10 It shows Figure 8 Circuit diagram 1000 of some embodiments of the image sensor.

[0099] like Figure 10 As shown in circuit diagram 1000, transfer gate 124 controls the charge flowing to (and out of) photodetector 104. For example, transfer gate 124 controls the flow of charge accumulated in photodetector 104 to floating diffusion node 106. The gate electrode of third readout transistor 810c and the source / drain of first readout transistor 810a may be electrically coupled to floating diffusion node 106. The first source / drain region of second readout transistor 810b may be electrically coupled to the source / drain region of third readout transistor 810c. The second source / drain region of second readout transistor 810b may be electrically coupled to in-pixel circuitry 1002 (e.g., circuitry including one or more in-pixel transistors). In-pixel circuitry 1002 may be electrically coupled to application-specific integrated circuit (ASIC) 1004 (e.g., circuitry including logic transistor 824).

[0100] In some embodiments, the first chip includes a photodetector 104, a transmission gate 124, and a floating diffusion node 106. In some embodiments, the second chip 804 includes a first readout transistor 810a, a second readout transistor 810b, a third readout transistor 810c, and in-pixel circuitry 1002 (e.g., in-pixel transistor). In some embodiments, the third chip 806 includes an ASIC 1004.

[0101] Figure 11 It shows Figure 10Circuit diagram 1100 of some other embodiments of the circuit diagram.

[0102] like Figure 11 As shown in circuit diagram 1100, the first chip 802 may include a plurality of photodetectors. For example, the first chip 802 may include a first photodetector 1102, a second photodetector 1104, a third photodetector 1106, and a fourth photodetector 1108. Each of the plurality of photodetectors may be substantially the same as photodetector 104 (see example...). Figures 1A to 1B Although circuit diagram 1100 shows a first chip 802 comprising four (4) photodetectors, it should be understood that the first chip 802 may comprise any number of photodetectors (e.g., 1, 2, 4, 8, 16, 32, 64, etc.).

[0103] The first chip 802 also includes a plurality of transfer gates. For example, the first chip 802 may include a first transfer gate 1110, a second transfer gate 1112, a third transfer gate 1114, and a fourth transfer gate 1116. Each of the plurality of transfer gates may be substantially the same as transfer gate 124 (see example). Figures 1A to 1B Although circuit diagram 1100 shows a first chip 802 including four (4) transfer gates, it should be understood that the first chip 802 may include transfer gates (e.g., 1, 2, 4, 8, 16, 32, 64, etc.) for each of the photodetectors of the first chip 802. The multiple transfer gates respectively control the flow of charge to (and out of) the multiple photodetectors. For example, a first transfer gate 1110 controls the flow of charge accumulated in the first photodetector 1102 to a floating diffusion node 106, a second transfer gate 1112 controls the flow of charge accumulated in the second photodetector 1104 to a floating diffusion node 106, a third transfer gate 1114 controls the flow of charge accumulated in the third photodetector 1106 to a floating diffusion node 106, and a fourth transfer gate 1116 controls the flow of charge accumulated in the fourth photodetector 1108 to a floating diffusion node 106.

[0104] Figures 12 to 24 A series of cross-sectional figures 1200-2400 illustrate some embodiments of a method for forming an image sensor including a first gate dielectric structure having a first thickness and a second gate dielectric structure having a second thickness greater than the first thickness.

[0105] like Figure 12As shown in cross-sectional view 1200, a photodetector 104 is formed in a substrate 102. The photodetector 104 includes a region of the substrate 102 having a first doping type (e.g., n-type / p-type) opposite to the second doping type (e.g., p-type / n-type). In some embodiments, the photodetector 104 can be formed by a doping process (e.g., by ion implantation, diffusion, etc.) that selectively implants a dopant of the first doping type (e.g., n-type dopant) into the substrate 102 using a masking layer (not shown) (e.g., positive / negative photoresist, hard mask, etc.) on the front side 102f of the substrate 102. Subsequently, in some embodiments, the masking layer is stripped (e.g., by plasma ashing).

[0106] Also there Figure 12 As shown in cross-sectional view 1200, in some embodiments, a doped well 108 is formed in substrate 102. The doped well 108 is a region of substrate 102 having a second doping type. In some embodiments, the doped well 108 is formed laterally spaced from photodetector 104. In some embodiments, the doped well 108 can be formed by a doping process (e.g., by ion implantation, diffusion, etc.) that selectively implants a second doping type dopant (e.g., p-type dopant) into substrate 102 using a masking layer (not shown) (e.g., positive / negative photoresist, hard mask, etc.) on the front side 102f of substrate 102. Subsequently, in some embodiments, the masking layer is stripped.

[0107] like Figure 13 As shown in cross-sectional view 1300, a first gate dielectric layer 1302 is formed over the front side 102f of the substrate 102. In some embodiments, the first gate dielectric layer 1302 is formed on the front side 102f of the substrate 102. The first gate dielectric layer 1302 is formed to have a third thickness 1304. The first gate dielectric layer 1302 may be or include, for example, oxides (e.g., SiO2), high-k dielectric materials (e.g., hafnium oxide (HfO), tantalum oxide (TaO), hafnium silicon oxide (HfSiO), hafnium tantalum oxide (HfTaO), aluminum oxide (AlO), zirconium oxide (ZrO), some other dielectric materials having a dielectric constant greater than about 3.9), some other dielectric materials, or combinations thereof.

[0108] In some embodiments, the process for forming the first gate dielectric layer 1302 includes depositing or growing (e.g., blanket deposition / growth) a dielectric material on the front side 102f of the substrate 102. The dielectric material may be, or include, for example, oxides (e.g., SiO2), high-k dielectric materials (e.g., hafnium oxide (HfO), tantalum oxide (TaO), hafnium silicon oxide (HfSiO), hafnium tantalum oxide (HfTaO), aluminum oxide (AlO), zirconium oxide (ZrO), some other dielectric materials having a dielectric constant greater than about 3.9), some other dielectric materials, or combinations thereof. The dielectric material may be deposited or grown by, for example, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), thermal oxidation, sputtering, some other deposition or growth processes, or combinations thereof.

[0109] Subsequently, a patterned masking layer 1306 (e.g., positive / negative photoresist, hard mask, etc.) is formed over the dielectric material. In some embodiments, the process for forming the patterned masking layer 1306 includes depositing a masking layer (not shown) on the dielectric material. The masking layer can be deposited by, for example, CVD, PVD, ALD, spin coating, some other deposition processes, or a combination thereof. Subsequently, the masking layer is exposed to the pattern (e.g., by a photolithography process, such as photolithography, extreme ultraviolet lithography, etc.) and developed, thereby forming the patterned masking layer 1306 over the dielectric material.

[0110] With the patterned masking layer 1306 positioned appropriately above the dielectric material, an etching process is then performed on the dielectric material. The etching process removes the unmasked portions of the dielectric material, thereby forming a first gate dielectric layer 1302 over the front side 102f of the substrate 102. The etching process can be, or includes, for example, a wet etching process, a dry etching process, a reactive ion etching (RIE) process, some other etching processes, or a combination thereof. Subsequently, in some embodiments, the patterned masking layer 1306 is stripped.

[0111] like Figure 14 As shown in cross-sectional view 1400, a second gate dielectric layer 1402 is formed over the front side 102f of the substrate 102 and the first gate dielectric layer 1302. The second gate dielectric layer 1402 is formed to have a fourth thickness 1404. In some embodiments, the fourth thickness 1404 is substantially the same as the third thickness 1304. In other embodiments, the fourth thickness 1404 is different from (e.g., greater than or less than) the third thickness 1304. The fourth thickness 1404 is different from the first thickness 114 (see...). Figures 1A to 1B Same as above. The third thickness is 1304 (see...). Figure 13 The sum of the thicknesses 1404 and 1404 is the same as that of the thickness 118.

[0112] The second gate dielectric layer 1402 may be or include, for example, oxides (e.g., SiO2), high-k dielectric materials (e.g., hafnium oxide (HfO), tantalum oxide (TaO), hafnium silicon oxide (HfSiO), hafnium tantalum oxide (HfTaO), aluminum oxide (AlO), zirconium oxide (ZrO), some other dielectric materials having a dielectric constant greater than about 3.9), some other dielectric materials, or combinations thereof. In some embodiments, the second gate dielectric layer 1402 has the same chemical composition as the first gate dielectric layer 1302. In other embodiments, the second gate dielectric layer 1402 has a different chemical composition than the first gate dielectric layer 1302.

[0113] In some embodiments, the process for forming the second gate dielectric layer 1402 includes depositing (e.g., blanket deposition) the second gate dielectric layer 1402 on the front side 102f of the substrate 102 and on the first gate dielectric layer 1302. The second gate dielectric layer 1402 can be deposited by, for example, CVD, PVD, ALD, sputtering, some other deposition processes, or combinations thereof.

[0114] In some embodiments, a first gate dielectric structure 112 and a second gate dielectric structure 116 are formed over the front side 102f of the substrate 102 by forming a first gate dielectric layer 1302 and a second gate dielectric layer 1402. In other words, in some embodiments, the first gate dielectric structure 112 and the second gate dielectric structure 116 are formed by forming a first gate dielectric layer 1302 and a second gate dielectric layer 1402. In some embodiments, the second gate dielectric structure 116 includes a first portion of the first gate dielectric layer 1302 and the second gate dielectric layer 1402, such as... Figure 14 As shown in the cross-sectional view 1400. In a further embodiment, the first gate dielectric structure 112 includes a second portion of the second gate dielectric layer 1402, as shown in the cross-sectional view 1400. Figure 14 As shown in cross-sectional view 1400, the first gate dielectric structure 112 is formed with a first thickness 114. The second gate dielectric structure 116 is formed with a second thickness 118.

[0115] Although Figures 13 to 14Possible processes for forming the first gate dielectric structure 112 and the second gate dielectric structure 116 are illustrated, but it should be understood that the first gate dielectric structure 112 and the second gate dielectric structure 116 can be formed by other processes. For example, in some embodiments, the first gate dielectric structure 112 (or the second gate dielectric structure 116) can be formed by a first forming process (e.g., a growth / deposition process) and a patterning process; and then, after forming the first gate dielectric structure 112 (or the second gate dielectric structure 116), the second gate dielectric structure 116 (or the first gate dielectric structure 112) can be formed by a second forming process (e.g., masking the first gate dielectric structure 112, and then performing another growth / deposition process).

[0116] like Figure 15 As shown in cross-sectional view 1500, a gate electrode structure 110 is formed above the front side 102f of the substrate 102, above the first gate dielectric structure 112, and above the second gate dielectric structure 116. The gate electrode structure 110 is formed to be partially located above the first gate dielectric structure 112. The gate electrode structure 110 is formed to be partially located above the second gate dielectric structure 116.

[0117] In some embodiments, the process for forming the gate electrode structure 110 includes forming a gate electrode layer (not shown) over a first gate dielectric structure 112 and a second gate dielectric structure 116. Subsequently, a patterned masking layer is formed over the gate electrode layer. The patterned masking layer can be formed by depositing a masking layer (not shown) on the first gate dielectric structure 112 and the second gate dielectric structure 116 (e.g., by spin coating), exposing the masking layer to a pattern (e.g., by photolithography, such as photolithography, extreme ultraviolet lithography, etc.), and developing the masking layer to form the patterned masking layer. Subsequently, with the patterned masking layer in place, an etching process is performed on the gate electrode layer to selectively etch the gate electrode layer according to the patterned masking layer. The etching process removes the unmasked portions of the gate electrode layer, thereby forming the gate electrode structure 110. In some embodiments, the etching process can be or includes, for example, a wet etching process, a dry etching process, a RIE process, some other etching processes, or a combination thereof. The patterned masking layer is then stripped. In some embodiments, forming the gate electrode structure 110 completes the formation of the transfer gate 124.

[0118] Also there Figure 15As shown in cross-sectional view 1500, a floating diffusion node 106 is formed in substrate 102. The floating diffusion node 106 is a region of substrate 102 having a first doping type. In some embodiments, the floating diffusion node 106 can be formed by a doping process (e.g., by (angled) ion implantation, diffusion, etc.) that utilizes a masking layer (not shown) (e.g., positive / negative photoresist, hard mask, etc.) on the front side 102f of substrate 102 to selectively implant a dopant of the first doping type (e.g., n-type dopant) into substrate 102. In some embodiments, the gate electrode structure 110 serves at least partially as a masking layer. Subsequently, in some embodiments, the masking layer is stripped.

[0119] like Figure 16 As shown in cross-sectional view 1600, sidewall spacers 702 are formed along the sidewalls of the gate electrode structure 110. The sidewall spacers 702 are formed over the first gate dielectric structure 112 and the second gate dielectric structure 116. In some embodiments, the process for forming the sidewall spacers 702 includes depositing a spacer layer (not shown) over the first gate dielectric structure 112, the second gate dielectric structure 116, and the gate electrode structure 110. The spacer layer can be deposited by, for example, CVD, PVD, ALD, some other deposition processes, or a combination thereof. Subsequently, the horizontal portion of the spacer layer is etched away (e.g., by an anisotropic etching process), thereby leaving the vertical portion of the spacer layer in place as the sidewall spacers 702.

[0120] like Figure 17 As shown in cross-sectional view 1700, a contact etch stop layer (CESL) 704 is formed over the first gate dielectric structure 112, the second gate dielectric structure 116, the gate electrode structure 110, and the sidewall spacer 702. In some embodiments, the process for forming the CESL 704 includes depositing the CESL 704 on the first gate dielectric structure 112, the second gate dielectric structure 116, the gate electrode structure 110, and the sidewall spacer 702. The CESL 704 can be deposited by, for example, CVD, PVD, ALD, some other deposition processes, or combinations thereof.

[0121] like Figure 18 As shown in cross-sectional view 1800, an ILD structure 126 is formed above the front side 102f of the substrate 102. The ILD structure 126 is also formed above the first gate dielectric structure 112, the second gate dielectric structure 116, the gate electrode structure 110, the sidewall spacer 702, and the CESL 704. Figure 18As shown in cross-sectional view 1800, an interconnect structure 128 is formed in the ILD structure 126 and above the front side 102f of the substrate 102. In some embodiments, the interconnect structure 128 includes a plurality of conductive contacts 128a, a plurality of conductive vias 128b, and a plurality of wires 128c. The plurality of conductive contacts 128a may include a first conductive contact 128a1 and a second conductive contact 128a2.

[0122] In some embodiments, the process for forming the ILD structure 126 and the interconnect structure 128 includes forming a first ILD layer over the front side 102f of the substrate 102. Contact openings are then formed in the first ILD layer. A conductive material (e.g., tungsten (W)) is then formed on the first ILD layer and in the contact openings. A planarization process (e.g., chemical mechanical planarization (CMP)) is then performed on the conductive material to form a plurality of conductive contacts 128a in the first ILD layer. A second ILD layer is then formed over the first ILD layer and the plurality of conductive contacts 128a. A plurality of trenches are then formed in the second ILD layer. A conductive material (e.g., copper (Cu)) is formed on the second ILD layer and in the trenches. A planarization process (e.g., CMP) is then performed on the conductive material to form a first group of conductors (e.g., conductors of a first conductor layer (e.g., metal layer 1)) of a plurality of conductors 128c.

[0123] Subsequently, the remaining conductors of the plurality of conductive vias 128b and the plurality of conductors 128c of the interconnect structure 128 can be formed by repeated damascene processes (e.g., single damascene or double damascene processes) until a predetermined number of conductive vias and conductors are formed in the ILD structure 126. The damascene process can be implemented by depositing a subsequent ILD layer over the second ILD layer and the first conductor group of the plurality of conductors 128c, etching the subsequent ILD layer to form one or more vias and / or one or more trenches in the subsequent ILD layer, and filling the one or more vias and / or one or more trenches with a conductive material (e.g., copper (Cu)). Subsequently, a planarization process (e.g., CMP) is performed on the conductive material to form the second conductor group of the plurality of conductors 128c (e.g., conductors of the second conductor layer (e.g., metal layer 2)) and / or the conductive vias of the plurality of conductive vias 128b extending vertically between the first conductor group and the second conductor group. This damascene process is repeated until each of the plurality of conductive vias 128b and each of the plurality of wires 128c of the interconnect structure 128 is formed in the ILD structure 126. The ILD layer can be formed by, for example, CVD, PVD, ALD, some other deposition process, or a combination thereof. Conductive materials (e.g., tungsten (W), copper (Cu), etc.) can be formed using deposition processes (e.g., CVD, PVD, sputtering, etc.) and / or plating processes (e.g., electrochemical plating, electroless plating, etc.).

[0124] like Figure 19 As shown in cross-sectional view 1900, a trench 1902 is formed in substrate 102. Trench 1902 extends from the back side 102b of substrate 102 into substrate 102. Trench 1902 is formed over (e.g., directly over) the second gate dielectric structure 116.

[0125] In some embodiments, trench 1902 extends vertically from the back side 102b (e.g., a back surface) of substrate 102 through substrate 102 to at least the front side 102f (e.g., a front surface) of substrate 102 (e.g., trench 1902 extends completely through substrate 102). In a further embodiment, trench 1902 is formed to penetrate the second gate dielectric structure 116 (e.g., formed to extend at least partially vertically through the second gate dielectric structure 116), such as Figure 19 As shown in cross-sectional view 1900. In such an embodiment, trench 1902 exposes a portion of the second gate dielectric structure 116. In some embodiments, the portion of the second gate electrode exposed by trench 1902 is laterally disposed between opposite sides of the gate electrode structure 110 (see, for example...). Figures 2A to 2B ).

[0126] Trench 1902 is formed to extend laterally through substrate 102. In some embodiments, trench 1902 is formed to extend laterally through substrate 102 in a closed-loop path. In some embodiments, trench 1902 is formed to laterally surround photodetector 104. In a further embodiment, trench 1902 is formed to laterally surround floating diffusion node 106 (and doped well 108).

[0127] In some embodiments, the process for forming the trench 1902 includes forming a patterned masking layer 1904 over the back side 102b of the substrate 102. In some embodiments, the process for forming the patterned masking layer 1904 includes flipping (e.g., rotating 180 degrees). Figure 18 The structure shown is such that the back side 102b of the substrate 102 faces upward. A masking layer (not shown) is then deposited on the back side 102b of the substrate 102. The masking layer can be deposited by, for example, CVD, PVD, ALD, spin coating, some other deposition processes, or a combination thereof. The masking layer is then exposed to a pattern (e.g., by a photolithography process, such as photolithography, extreme ultraviolet lithography, etc.) and developed, thereby forming a patterned masking layer 1904 over the back side 102b of the substrate 102.

[0128] With the patterned masking layer 1904 properly positioned above the back side 102b of the substrate 102, an etching process 1906 is then performed on the substrate 102. The etching process 1906 removes the unmasked portions of the substrate 102, thereby forming trenches 1902 in the substrate 102. The etching process can be, or includes, for example, a wet etching process, a dry etching process, a RIE process, some other etching processes, or a combination thereof. Subsequently, in some embodiments, the patterned masking layer 1904 is stripped.

[0129] Because the second gate dielectric structure 116 has a second thickness 118 and because the trench 1902 is formed over (e.g., directly over) the second gate dielectric structure 116, the etching process 1906 will not undesirably etch through (e.g., completely through) the second gate dielectric structure 116 and damage components disposed on the front side 102f of the substrate 102 (e.g., gate electrode structure 110, interconnect structure 128, etc.). In other words, the second gate dielectric structure 116 can be used to provide a safe landing area for forming the trench 1902. Therefore, the size of the image sensor can be smaller than (e.g., scaled down more than) a typical image sensor (e.g., the image sensor's ability to scale down is improved because the second gate dielectric structure 116 is a safe landing area for forming the trench 1902).

[0130] like Figure 20 As shown in the cross-sectional view 2000, a dielectric layer 706 is formed in the trench 1902 and above the back side 102b of the substrate 102. The dielectric layer 706 is formed to line the surface of the trench 1902 (e.g., sidewalls and lower surface). In some embodiments, the dielectric layer 706 is formed to contact (e.g., directly contact) the second gate dielectric structure 116, such as... Figure 20 As shown in the cross-sectional view 2000. More specifically, the dielectric layer 706 is formed as the portion of the second gate dielectric structure 116 exposed by the trench 1902 (see...). Figure 19 In other embodiments, dielectric layer 706 is omitted. In some embodiments, the process for forming dielectric layer 706 includes depositing dielectric layer 706 on the back side 102b of substrate 102 and along the surface of trench 1902. Dielectric layer 706 can be deposited by, for example, CVD, PVD, ALD, some other deposition process or a combination thereof.

[0131] Also there Figure 20 As shown in cross-sectional view 2000, a DTI structure 130 is formed in trench 1902. The DTI structure 130 is formed to extend from the back side 102b of substrate 102 into substrate 102. The DTI structure 130 is formed over (e.g., directly over) the second gate dielectric structure 116.

[0132] In some embodiments, the DTI structure 130 extends vertically through the substrate 102 from the back side 102b (e.g., the back surface) to at least the front side 102f (e.g., the front surface) of the substrate 102 (e.g., the DTI structure 130 extends completely through the substrate 102). In a further embodiment, the DTI structure 130 may be formed to penetrate the second gate dielectric structure 116 (e.g., at least partially extending vertically into the second gate dielectric structure 116).

[0133] The DTI structure 130 is formed to extend laterally through the substrate 102. In some embodiments, the DTI structure 130 is formed to extend laterally through the substrate 102 in a closed-loop path. In some embodiments, the DTI structure 130 is formed to laterally surround the photodetector 104. In a further embodiment, the DTI structure 130 is formed to laterally surround the floating diffusion node 106 (and the doped well 108).

[0134] In some embodiments, the process for forming the DTI structure 130 includes depositing a dielectric material on the dielectric layer 706 and filling the trench 1902. In some embodiments, the dielectric material is also formed over the dielectric layer 706 and over the back side 102b of the substrate 102. In some embodiments, the dielectric material may be, or include, for example, oxides (e.g., SiO2), nitrides (e.g., SiN), oxynitrides (e.g., SiON), tetraethyl orthosilicate (TEOS), some other dielectric materials, or combinations thereof. In some embodiments, the dielectric material has a different chemical composition than the dielectric layer 706. Subsequently, a planarization process (e.g., CMP) is performed on the dielectric material to remove the upper portion of the dielectric material, thereby leaving the lower portion of the dielectric material in the trench 1902 as the DTI structure 130.

[0135] like Figure 21 As shown in cross-sectional view 2100, an optical transmission structure 708 is formed along the dielectric layer 706 and the DTI structure 130, or above the dielectric layer 706 and the DTI structure 130. In some embodiments, the process for forming the optical transmission structure 708 includes depositing the optical transmission structure 708 on the dielectric layer 706 and the DTI structure 130. The optical transmission structure 708 can be deposited by, for example, CVD, PVD, ALD, spin coating, sputtering, some other deposition processes, or combinations thereof.

[0136] like Figure 22As shown in cross-sectional view 2200, a metal grid 712 is formed on / above the light transmission structure 708. In some embodiments, the process for forming the metal grid 712 includes forming a patterned masking layer (not shown) on the light transmission structure 708, the patterned masking layer having trenches disposed therein. Subsequently, a metallic material is deposited on the patterned masking layer and in the trenches. The metallic material can be, or includes, for example, aluminum (Al), cobalt (Co), copper (Cu), silver (Ag), gold (Au), tungsten (W), some other metals, or combinations thereof. Subsequently, a planarization process (e.g., CMP etching back process, etc.) is performed on the metallic material to remove the upper portion of the metallic material, thereby leaving the lower portion of the metallic material in the trenches as the metal grid 712. Subsequently, in some embodiments, the masking layer is stripped off.

[0137] Also there Figure 22 As shown in cross-sectional view 2200, a dielectric grid 710 is formed over the light transmission structure 708 and the metal grid 712. The dielectric grid 710 is formed on the metal grid 712. In some embodiments, the process for forming the dielectric grid 710 includes depositing a dielectric material on / over the light transmission structure 708 and the metal grid 712. The dielectric material may be or include, for example, oxides (e.g., SiO2), nitrides (e.g., SiN), carbides (e.g., SiC), high-k dielectrics (e.g., HfO, TaO, etc.), low-k dielectrics, some other dielectrics, or combinations thereof.

[0138] Subsequently, a patterned masking layer is formed over the dielectric material. An etching process is then performed on the dielectric material to remove the unmasked portions, leaving masked portions of the dielectric material as a dielectric grid in appropriate locations. The etching process can be, or includes, for example, wet etching, dry etching, RIE, some other etching processes, or combinations thereof. Subsequently, in some embodiments, the patterned masking layer is stripped.

[0139] like Figure 23 As shown in cross-sectional view 2300, an electromagnetic radiation (EMR) filter 714 (e.g., an infrared filter, a color filter, etc.) is formed on / above the light transmission structure 708 and within the dielectric grid 710. In some embodiments, the process for forming the EMR filter 714 includes depositing a filter material (e.g., by CVD, PVD, ALD, sputtering, spin coating, etc.) on the light transmission structure 708 and within the dielectric grid 710. The filter material is a material that allows the transmission of radiation (e.g., light) with a specific wavelength range while blocking light of wavelengths outside that specific range. Subsequently, in some embodiments, a planarization process (e.g., CMP) may be performed on the EMR filter 714 to planarize the upper surface of the EMR filter 714.

[0140] like Figure 24 As shown in cross-sectional view 2400, a microlens 716 is formed on / above an EMR filter 714. In some embodiments, the microlens 716 can be formed by depositing a microlens material on the EMR filter 714 and dielectric grid 710 (e.g., by CVD, PVD, ALD, sputtering, spin coating, etc.). A microlens template (not shown) having a curved upper surface is patterned on the microlens material. In some embodiments, the microlens template may include photoresist material exposed using a distributed exposure light dose (e.g., for negative photoresist, more light is exposed at the bottom of the curvature and less light is exposed at the top of the curvature), developed, and baked to form a circular shape. The microlens 716 is then formed by selectively etching the microlens material according to the microlens template. In some embodiments, after the formation of the microlens 716, the image sensor is formed (see, for example, the formation of the image sensor). Figures 1A to 1B )Finish.

[0141] For clarity, it should be understood that the spatial relative terms used herein to describe the structures shown in the figures (e.g., above, below, upper, lower, etc.) are generally based on the orientation of such structures as shown in their respective figures. For example, in describing Figure 24 In the structure shown, the microlens 716 can be said to be formed above the EMR filter 714. On the other hand, in the description Figure 7 In the structure shown, the EMR filter 714 can be said to be located on the microlens 716.

[0142] Figure 25 A flowchart 2500 illustrates some embodiments of a method for forming an image sensor including a first gate dielectric structure having a first thickness and a second gate dielectric structure having a second thickness greater than the first thickness. Although Figure 25 The flowchart 2500 is shown and described herein as a series of steps or events; however, it should be understood that the order in which such steps or events are shown should not be interpreted as limiting. For example, some steps may occur in a different order and / or simultaneously with other steps or events in addition to those shown and / or described herein. Furthermore, it may not be necessary to implement all the steps shown herein to implement one or more aspects or embodiments described herein, and one or more steps described herein may be performed in one or more separate steps and / or stages.

[0143] In step 2502, a photodetector is formed in the substrate. Figure 12 A cross-sectional view 1200 is shown, corresponding to some embodiments of step 2502.

[0144] In step 2504, a first gate dielectric structure is formed over the substrate. Figures 13 to 14A series of cross-sectional views 1300-1400 are shown corresponding to some embodiments of step 2504.

[0145] In step 2506, a second gate dielectric structure is formed over the substrate. Figures 13 to 14 A series of cross-sectional views 1300-1400 are shown corresponding to some embodiments of step 2506.

[0146] In step 2508, a gate electrode structure is formed that is at least partially located on the first gate dielectric structure and the second gate dielectric structure. Figure 15 A cross-sectional view 1500 corresponding to some embodiments of step 2508 is shown.

[0147] In step 2510, an interlayer dielectric (ILD) structure is formed over the substrate, the gate electrode structure, the first gate dielectric structure, and the second gate dielectric structure. Figures 16 to 18 A series of cross-sectional views 1600-1800 are shown corresponding to some embodiments of step 2510.

[0148] In step 2512, trenches are formed in the substrate. Figure 19 A cross-sectional view 1900 corresponding to some embodiments of step 2512 is shown.

[0149] In step 2514, a deep trench isolation (DTI) structure is formed in the trench. Figure 20 Cross-sectional view 2000 is shown for some embodiments corresponding to step 2514.

[0150] In step 2516, a microlens is formed on the side of the substrate. Figures 21 to 24 A series of cross-sectional views 2100-2400 are shown corresponding to some embodiments of step 2516.

[0151] In some embodiments, this application provides an image sensor. The image sensor includes a deep trench isolation (DTI) structure disposed in a semiconductor substrate, wherein the DTI structure extends laterally through the semiconductor substrate in a closed-loop path, and wherein a pixel region of the semiconductor substrate is disposed within the inner periphery of the DTI structure. A photodetector is disposed in the pixel region of the semiconductor substrate. A gate electrode structure is partially located above the pixel region of the semiconductor substrate. A first gate dielectric structure is partially located above the pixel region of the semiconductor substrate. A second gate dielectric structure is partially located above the pixel region of the semiconductor substrate, wherein the gate electrode structure is located above portions of the first and second gate dielectric structures, and wherein the thickness of the portion of the second gate dielectric structure is greater than the thickness of the portion of the first gate dielectric structure.

[0152] In some embodiments, a dielectric structure is disposed above a semiconductor substrate, a first gate dielectric structure, a second gate dielectric structure, and a gate electrode structure. A conductive contact is disposed in the dielectric structure and electrically coupled to the gate electrode structure, wherein the conductive contact is located on a portion of the second gate dielectric structure.

[0153] In some embodiments, conductive contacts are disposed within the inner perimeter of the DTI structure.

[0154] In some embodiments, the conductive contacts are located at least partially on the DTI structure.

[0155] In some embodiments, the second gate dielectric structure has a sidewall laterally disposed between a first sidewall of the gate electrode structure and a second sidewall of the gate electrode structure. The first sidewall of the gate electrode structure is opposite to the second sidewall of the gate electrode structure. The first sidewall of the gate electrode structure faces the sidewall of the DTI structure. A conductive contact is laterally disposed between the sidewall of the second gate dielectric structure and the sidewall of the DTI structure.

[0156] In some embodiments, the second gate dielectric structure laterally surrounds the first gate dielectric structure.

[0157] In some embodiments, the outer perimeter of the first gate dielectric structure is disposed within the inner perimeter of the DTI structure.

[0158] In some embodiments, floating diffusion nodes are disposed in the pixel region of the semiconductor substrate, wherein the floating diffusion nodes are disposed within the outer periphery of the first gate dielectric structure.

[0159] In some embodiments, the gate electrode structure has a first portion located above a portion of the first gate dielectric structure. The gate electrode structure has a second portion located above a portion of the second gate dielectric structure. The height of the first portion of the gate electrode structure is greater than the height of the second portion of the gate electrode structure.

[0160] In some embodiments, the sidewall spacer is disposed along the sidewall of the gate electrode structure, wherein a first portion of the sidewall spacer is located on the first gate dielectric structure, wherein a second portion of the sidewall spacer is located on the second gate dielectric structure, and wherein the height of the first portion of the sidewall spacer is greater than the height of the second portion of the sidewall spacer.

[0161] In some embodiments, the semiconductor substrate has a first surface and a second surface opposite to the first surface. The first surface of the semiconductor substrate is perpendicularly disposed between the gate electrode structure and the second surface of the semiconductor substrate. Alternatively, the first surface of the semiconductor substrate is perpendicularly disposed between the surface of the DTI structure and the second surface of the semiconductor substrate.

[0162] In some embodiments, the DTI structure extends vertically from a first surface of the semiconductor substrate through the semiconductor substrate to a second surface of the semiconductor substrate.

[0163] In some embodiments, this application provides an image sensor. The image sensor includes an isolation structure disposed in a semiconductor substrate, wherein the isolation structure extends perpendicularly from a first surface of the semiconductor substrate through the semiconductor substrate to a second surface of the semiconductor substrate opposite to the first surface. A floating diffusion node is disposed in the semiconductor substrate and on the side of the isolation structure. A photodetector is disposed in the semiconductor substrate and laterally disposed between the floating diffusion node and the isolation structure. A gate electrode structure is disposed above the semiconductor substrate and laterally disposed between the floating diffusion node and the photodetector, wherein the first surface of the semiconductor substrate is perpendicularly disposed between the gate electrode structure and the second surface of the semiconductor substrate. A first gate dielectric structure is disposed above the first surface of the semiconductor substrate. A second gate dielectric structure is disposed above the first surface of the semiconductor substrate and on the side of the first gate dielectric structure, wherein the thickness of the second gate dielectric structure is greater than the thickness of the first gate dielectric structure, wherein the second gate dielectric structure is located above the isolation structure, and wherein the gate electrode structure is partially located above the first gate dielectric structure and the second gate dielectric structure.

[0164] In some embodiments, a dielectric structure is disposed above a semiconductor substrate, a first gate dielectric structure, a second gate dielectric structure, and a gate electrode structure. A conductive contact is disposed in the dielectric structure and electrically coupled to the gate electrode structure, wherein the conductive contact is laterally disposed between the sidewall of the second gate dielectric structure and the sidewall of the isolation structure.

[0165] In some embodiments, the first sidewall of the gate electrode structure is substantially aligned with the sidewall of the isolation structure.

[0166] In some embodiments, a first sidewall of the gate electrode structure is opposite to a second sidewall of the gate electrode structure. The first sidewall of the gate electrode structure has a first length. The second sidewall of the gate electrode structure has a second length greater than the first length.

[0167] In some embodiments, a dielectric structure is disposed above a semiconductor substrate, a first gate dielectric structure, a second gate dielectric structure, and a gate electrode structure. Conductive contacts are disposed in the dielectric structure and electrically coupled to the gate electrode structure, wherein the conductive contacts are partially located above the isolation structure.

[0168] In some embodiments, the sidewall of the second gate dielectric structure is laterally disposed between the first sidewall of the gate electrode structure and the second sidewall of the gate electrode structure. The first sidewall of the gate electrode structure is opposite to the second sidewall of the gate electrode structure. The isolation structure is laterally disposed between the sidewall of the second gate dielectric structure and the first sidewall of the gate electrode structure.

[0169] In some embodiments, this application provides a method for forming an image sensor. The method includes forming a photodetector in a semiconductor substrate. A first gate dielectric structure is formed over a first side of the semiconductor substrate. A second gate dielectric structure is formed over the first side of the semiconductor substrate, wherein the second gate dielectric structure is formed to have a thickness greater than that of the first gate dielectric structure. A gate electrode structure is formed, partially over the first gate dielectric structure and partially over the second gate dielectric structure. A trench is formed in the semiconductor substrate exposing a portion of the second gate dielectric structure, wherein the trench is formed from a second side of the semiconductor substrate opposite to the first side of the semiconductor substrate. A back-side deep trench isolation (BDTI) structure is formed in the trench.

[0170] In some embodiments, an interlayer dielectric (ILD) structure is formed over a semiconductor substrate, a first gate dielectric structure, a second gate dielectric structure, and a gate electrode structure. Conductive contacts are formed in the ILD structure and are electrically coupled to the gate electrode structure, wherein the gate electrode structure has opposing sidewalls, and the conductive contacts are laterally formed between the first sidewall of the opposing sidewalls of the gate electrode structure and the sidewall of the second gate dielectric structure, wherein the sidewall of the second gate dielectric structure faces the first gate dielectric structure.

[0171] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand aspects of the invention. Those skilled in the art should understand that they can readily use this invention as a basis to design or modify other processes and structures for performing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the invention, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of the invention.

Claims

1. An image sensor, comprising: A deep trench isolation structure is disposed in a semiconductor substrate, wherein the deep trench isolation structure extends laterally through the semiconductor substrate in a closed-loop path, and wherein a pixel region of the semiconductor substrate is disposed within the inner perimeter of the deep trench isolation structure. A photodetector is disposed in the pixel region of the semiconductor substrate; The gate electrode structure is partially located above the pixel region of the semiconductor substrate; A first gate dielectric structure is partially located above the pixel region of the semiconductor substrate; and A second gate dielectric structure is partially located on the pixel region of the semiconductor substrate, wherein the gate electrode structure is located on the first gate dielectric portion of the first gate dielectric structure and the second gate dielectric portion of the second gate dielectric structure, and wherein the thickness of the second gate dielectric portion of the second gate dielectric structure is greater than the thickness of the first gate dielectric portion of the first gate dielectric structure.

2. The image sensor according to claim 1, further comprising: A dielectric structure is disposed above the semiconductor substrate, the first gate dielectric structure, the second gate dielectric structure, and the gate electrode structure; as well as A conductive contact is disposed in the dielectric structure and electrically coupled to the gate electrode structure, wherein the conductive contact is located on the second gate dielectric portion of the second gate dielectric structure.

3. The image sensor according to claim 2, wherein, The conductive contact is disposed within the inner perimeter of the deep trench isolation structure.

4. The image sensor according to claim 2, wherein, The conductive contact is located at least partially on the deep trench isolation structure.

5. The image sensor according to claim 2, wherein: The second gate dielectric structure has a sidewall that is laterally disposed between the first sidewall of the gate electrode structure and the second sidewall of the gate electrode structure; The first sidewall of the gate electrode structure is opposite to the second sidewall of the gate electrode structure; The first sidewall of the gate electrode structure faces the sidewall of the deep trench isolation structure; as well as The conductive contact is laterally disposed between the sidewall of the second gate dielectric structure and the sidewall of the deep trench isolation structure.

6. The image sensor according to claim 1, wherein, The second gate dielectric structure laterally surrounds the first gate dielectric structure.

7. The image sensor according to claim 1, wherein, The outer perimeter of the first gate dielectric structure is disposed within the inner perimeter of the deep trench isolation structure.

8. The image sensor according to claim 1, further comprising: A floating diffusion node is disposed in the pixel region of the semiconductor substrate, wherein the floating diffusion node is disposed within the outer periphery of the first gate dielectric structure.

9. The image sensor according to claim 1, wherein: The gate electrode structure has a first portion located on the first gate dielectric portion of the first gate dielectric structure; The gate electrode structure has a second portion located above the second gate dielectric portion of the second gate dielectric structure; and The height of the first portion of the gate electrode structure is greater than the height of the second portion of the gate electrode structure.

10. The image sensor according to claim 1, further comprising: A sidewall spacer is disposed along the sidewall of the gate electrode structure, wherein a first portion of the sidewall spacer is located on the first gate dielectric structure, a second portion of the sidewall spacer is located on the second gate dielectric structure, and wherein the height of the first portion of the sidewall spacer is greater than the height of the second portion of the sidewall spacer.

11. The image sensor according to claim 1, wherein: The semiconductor substrate has a first surface and a second surface opposite to the first surface; The first surface of the semiconductor substrate is perpendicularly disposed between the gate electrode structure and the second surface of the semiconductor substrate; as well as The first surface of the semiconductor substrate is perpendicularly disposed between the surface of the deep trench isolation structure and the second surface of the semiconductor substrate.

12. The image sensor according to claim 11, wherein, The deep trench isolation structure extends vertically from the first surface of the semiconductor substrate through the semiconductor substrate to the second surface of the semiconductor substrate.

13. An image sensor, comprising: An isolation structure is disposed in a semiconductor substrate, wherein the isolation structure extends perpendicularly from a first surface of the semiconductor substrate through the semiconductor substrate to a second surface of the semiconductor substrate opposite to the first surface of the semiconductor substrate; A floating diffusion node is disposed on the side of the semiconductor substrate and the isolation structure in the lateral direction. A photodetector is disposed in the semiconductor substrate and laterally between the floating diffusion node and the isolation structure; A gate electrode structure is disposed above the semiconductor substrate and laterally disposed between the floating diffusion node and the photodetector, wherein the first surface of the semiconductor substrate is perpendicularly disposed between the gate electrode structure and the second surface of the semiconductor substrate; A first gate dielectric structure is disposed above the first surface of the semiconductor substrate; and A second gate dielectric structure is disposed above the first surface of the semiconductor substrate and on the side of the first gate dielectric structure, wherein the thickness of the second gate dielectric structure is greater than the thickness of the first gate dielectric structure, wherein the second gate dielectric structure is located above the isolation structure, and wherein the gate electrode structure is partially located above the first gate dielectric structure and the second gate dielectric structure.

14. The image sensor of claim 13, further comprising: A dielectric structure is disposed above the semiconductor substrate, the first gate dielectric structure, the second gate dielectric structure, and the gate electrode structure; as well as A conductive contact is disposed in the dielectric structure and electrically coupled to the gate electrode structure, wherein the conductive contact is laterally disposed between the sidewall of the second gate dielectric structure and the sidewall of the isolation structure.

15. The image sensor according to claim 14, wherein, The first sidewall of the gate electrode structure is aligned with the sidewall of the isolation structure.

16. The image sensor according to claim 15, wherein: The first sidewall of the gate electrode structure is opposite to the second sidewall of the gate electrode structure; The first sidewall of the gate electrode structure has a first length; as well as The second sidewall of the gate electrode structure has a second length greater than the first length.

17. The image sensor of claim 13, further comprising: A dielectric structure is disposed above the semiconductor substrate, the first gate dielectric structure, the second gate dielectric structure, and the gate electrode structure; as well as A conductive contact is disposed in the dielectric structure and electrically coupled to the gate electrode structure, wherein the conductive contact is partially located on the isolation structure.

18. The image sensor according to claim 17, wherein: The sidewall of the second gate dielectric structure is laterally disposed between the first sidewall of the gate electrode structure and the second sidewall of the gate electrode structure; The first sidewall of the gate electrode structure is opposite to the second sidewall of the gate electrode structure; as well as The isolation structure is laterally disposed between the sidewall of the second gate dielectric structure and the first sidewall of the gate electrode structure.

19. A method for forming an image sensor, the method comprising: Forming a photodetector in a semiconductor substrate; A first gate dielectric structure is formed above a first side of the semiconductor substrate; A second gate dielectric structure is formed above the first side of the semiconductor substrate, wherein the second gate dielectric structure is formed to have a thickness greater than that of the first gate dielectric structure; A gate electrode structure is formed that is partially located above the first gate dielectric structure and partially located above the second gate dielectric structure; A trench is formed in the semiconductor substrate to expose a portion of the second gate dielectric structure, wherein the trench is formed from a second side of the semiconductor substrate opposite to the first side of the semiconductor substrate; and A back-side deep trench isolation structure is formed in the trench.

20. The method of claim 19, further comprising: An interlayer dielectric structure is formed over the semiconductor substrate, the first gate dielectric structure, the second gate dielectric structure, and the gate electrode structure; as well as A conductive contact electrically coupled to the gate electrode structure is formed in the interlayer dielectric structure, wherein the gate electrode structure has opposing sidewalls, wherein the conductive contact is laterally formed between a first sidewall of the opposing sidewalls of the gate electrode structure and a sidewall of the second gate dielectric structure, and wherein the sidewall of the second gate dielectric structure faces the first gate dielectric structure.

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