Superjunction Devices and Their Manufacturing Methods

Abstract

This invention discloses a superjunction device. The structure of the superjunction device located in the active region includes: a planar gate structure formed on top of each first conductivity type pillar, the planar gate structure being composed of a first gate dielectric layer and a first gate conductive material layer stacked together; two planar gate structures within the same unit cell, with a second gate dielectric layer disposed between the first gate dielectric layers of the two planar gate structures; a second well region, formed by annealing an ion-implanted region of the second conductivity type with the first side of the planar gate structure as a self-alignment condition; the second well region laterally diffuses to the bottom region of the planar gate structure under the action of the annealing process; and a channel region composed of the second well region covered by the planar gate structure. The self-alignment structure between the second well region and the planar gate structure is used to improve the uniformity of the device. This invention also discloses a method for manufacturing the superjunction device. This invention can improve the uniformity of the device and reduce Cgd.

Description

Technical Field

[0001] This invention relates to the field of semiconductor integrated circuit manufacturing, and in particular to a super junction device; this invention also relates to a method for manufacturing a super junction device. Background Technology

[0002] Existing superjunction devices include a current-flow region (active region), a transition region, and a termination region. A superjunction structure is formed in the current-flow region, consisting of alternating P-type and N-type pillars (PN pillars). Taking a strip-shaped PN pillar structure as an example, each N-type pillar has a planar gate structure above it, which may partially cover the surrounding P-type pillars or not. Each P-type pillar has a P-well above it, containing an N+ source region and a contact hole. The source metal is connected to the source region through the contact hole, which in turn connects to the P-region via a high-concentration P+ contact region. In the transition region, there is a P-ring covering one or more P-type pillars. The P-ring can be fabricated using the same process as the P-well, and it also contains a high-concentration P+ contact region. The formation process, concentration, and junction depth of the P+ contact region in the P-ring are identical to those in the current-flow region.

[0003] In the device structure described above, the width of the P-type well beneath the planar gate structure is actually the channel length of the device. The channel length affects the on-resistance and switching characteristics of the device. In the N-type region between the P-type wells at the bottom of the planar gate structure, N-type impurities are typically injected to reduce on-resistance and form a JFET-resistant region. The width of this JFET-resistant region directly affects the reverse transfer capacitance (Crss) of the device. Crss consists of the gate-drain capacitance (Cgd), which is also the Miller capacitance.

[0004] In existing technologies, Pwells are generally formed after or before the formation of P-type pillars. First, the formation region of the P-type ring in the transition area is defined by photolithography. The width of the P-type ring is 1 micrometer to 50 micrometers. At the same time, the formation region of the P-type well in the current flow region is defined. Then, P-type impurities, such as B or BF2, are implanted through ion implantation, thus forming the P-type well.

[0005] Then, a dielectric protection ring is formed, including: a dielectric film forming the dielectric protection ring, namely the G-field dielectric film, the G-field dielectric film is photolithographically and etched so that the G-field dielectric film only covers the surface of the transition region and the terminal region, while the G-field dielectric film on the surface of the active region is completely removed, thereby forming a dielectric protection ring surrounding the active region.

[0006] The planar gate structure is then formed, including the formation of a gate oxide film and a polysilicon gate. The gate region is defined in the active region by gate photolithography and etching, the gate vertical (Bus) is defined in the transition region, and the gate region is defined in the termination region or there is no gate region in the termination region.

[0007] After the planar gate structure is formed, the overlapping area of ​​the P-type well and the planar gate structure in the active region forms the channel region. The length of the channel region is actually affected by the size of the P-type region formed by the photolithography and etching of the P-type well, as well as the position, i.e., the photolithographic overlay accuracy. It is also affected by the size and position of the polysilicon gate in the active region formed by the photolithography and etching of the polysilicon gate. Therefore, the channel length formed by the existing method has poor consistency, and the width consistency of the anti-JFET region between the channel regions is also poor. This not only affects the consistency of the device's on-resistance and threshold voltage, but also the consistency of the device's Cgd and gate-source capacitance (Cgs). Cgd includes the capacitance formed by the planar gate structure covering the anti-JFET region between the channel regions, and Cgs includes the capacitance formed by the planar gate structure covering the channel region.

[0008] Now combined with the appendix Figure 1 The following is a description of existing superjunction devices:

[0009] like Figure 1 The diagram shown is a schematic diagram of an existing superjunction device. Figure 1 The image only shows the cross-sectional structure of the active region. Taking an N-type superjunction MOSFET as an example, existing superjunction devices include:

[0010] A superjunction structure is formed in the semiconductor substrate 101. The superjunction structure is formed by alternating arrangement of multiple N-type pillars and P-type pillars 103. Each superjunction unit consists of one N-type pillar and one adjacent P-type pillar 103.

[0011] Typically, the semiconductor substrate 101 includes a silicon substrate. Typically, an N-type epitaxial layer 102 is formed on the surface of the semiconductor substrate 101, and the N-type pillars are composed of the N-type epitaxial layer 102 between the P-type pillars 103.

[0012] The structures of superjunction devices located in the active region include:

[0013] A P-type well region 106 is formed on the top of the P-type pillar 103, and the P-type well region 106 extends into the N-type pillars on both sides of the P-type pillar 103. The P-type well region 106 is defined by photolithography and formed by ion implantation.

[0014] A planar gate structure is formed on top of each of the N-type pillars; the planar gate structure is formed by stacking a first gate dielectric layer 104 and a first gate conductive material layer 105.

[0015] Typically, the first gate dielectric layer 104 includes a gate oxide layer. The first gate conductive material layer 105 includes a polysilicon gate.

[0016] The planar gate structure also needs to be patterned using photolithography definition and etching processes.

[0017] The N+ doped source region 107 is self-aligned and formed on the surface of the P-type well region 106 on both sides of the planar gate structure.

[0018] The P-type well region 106 and the planar gate structure need to overlap, and the P-type well region 106 located at the bottom of the planar gate structure forms a channel region. Figure 1 In this context, the length of the channel region, i.e., the channel length, is represented by the Lc surface.

[0019] The region between the P-type well regions 106 at the bottom of the planar gate structure is the region where the JFET effect will occur. The width of this region is Wj. Typically, N-type ion implantation is required in this region to form an anti-JFET region.

[0020] The front-side structure of the superjunction device also includes:

[0021] Interlayer film 108, through contact hole 109; at the bottom of contact hole 109 located at the top of source region 108, a body contact region 110 composed of P-type heavily doped regions is also formed, so that body region 104 is connected to the top contact hole 109 together with source region 108 through body contact region 110.

[0022] The source metal and gate metal are formed by patterning the front metal layer 111.

[0023] The back-side structure of the superjunction device includes:

[0024] The semiconductor substrate 101 is thinned to form a drain region; the drain region is formed directly by thinning the heavily doped semiconductor substrate 101, or the drain region is formed by thinning the semiconductor substrate 101 and then implanting N-type heavily doped backside ions.

[0025] A back metal layer 112 is formed.

[0026] like Figure 2 The diagram shown is a flowchart of a conventional superjunction device manufacturing method. Figure 1 The existing superjunction structure shown; Figure 2The process is represented by photomask layers. Existing methods for manufacturing superjunction devices include the following steps:

[0027] Step S101, which forms the zero-layer mark, requires a combination of photolithography and etching processes. Figure 2 In this context, step S201 is also represented by Zero photo & etch.

[0028] Step S102 is performed to form the JFET-resistant region. This JFET-resistant region needs to be defined using a photolithography process. Figure 2 In this context, step S101 is represented by JFET photo & IMP.

[0029] Step S103 forms a superjunction structure, i.e., forms Figure 1 The P-type pillars 103 shown are formed using a trench etching and filling process. The N-type epitaxial layers 102 between the P-type pillars 103 form N-type pillars. Forming the superjunction structure requires a photomask that defines the trenches. Figure 2 In step S103, Trench photo & etch is used.

[0030] Step S104 is performed to form the P-type well region 106. The P-type well region 106 first requires photolithography to define the formation region, followed by ion implantation. Figure 1 In this context, step S104 is represented by Pwell photo & IMP.

[0031] Step S105 involves forming a dielectric guard ring. This requires the growth of a dielectric guard ring material layer (Gfield). Following this, a photolithography and etching process is performed to remove the material layer of the dielectric guard ring in the active region. The remaining material layer of the dielectric guard ring then forms the dielectric guard ring itself. Therefore, Figure 2 In this context, step S105 is represented by Gfield photo & etch.

[0032] Step S106 forms a planar gate structure. This planar gate structure requires first forming a superimposed structure of a gate oxide layer and a polysilicon gate, followed by photolithography and etching processes to pattern the planar gate structure. Therefore, Figure 2 In this context, step S106 is represented by poly photo & etch.

[0033] Step S107 forms the source region 107. The source region 107 and the planar gate structure are self-aligned within the active region. The source region 107 is an N+ region (Nplus), and the formation process of the source region 107 requires the use of a photomask to define the formation area of ​​the source region 107. Figure 1In this context, step S107 is also represented using Nplus photo & IMP.

[0034] Step S108 includes: forming an interlayer film 108 and forming a contact hole (Cont) 109 through the interlayer film 108. The formation process of the contact hole 109 requires first using photolithography to define the formation area of ​​the contact hole 109, then etching to form the opening of the contact hole 109, and finally filling the opening of the contact hole 109 with metal to form the contact hole. The formation process of the contact hole 109 requires using a photomask to define the formation area of ​​the contact hole 109, therefore... Figure 1 In this context, step S108 is also represented by Cont photo & etch.

[0035] After the opening of the contact hole 109 is opened and before the metal is filled, the step of performing P-type heavily doped ion implantation to form the bulk contact region 211 is also included.

[0036] Step S109 includes: forming a front metal layer 111 and patterning the front metal layer 111 to form source metal and gate metal. The formation process of the front metal layer 111 requires the use of a photomask to define the patterned area of ​​the front metal layer 111. Figure 1 In this context, step S109 is also represented by Metal photo & etch.

[0037] Combination Figure 1 and Figure 2 As shown, the P-type well region 106 needs to be implemented by photolithography and ion implantation. In the photolithography process, the thickness of the photoresist, the exposure intensity, and the development and ion implantation processes will all produce corresponding deviations, which will cause the size of the P-type well region 106 to change, that is, the photolithography and implantation processes will cause size changes. At the same time, the photolithography overlay accuracy will also cause the pattern position of the P-type well region 106 to change.

[0038] Similarly, the planar gate structure needs to be implemented using photolithography and etching. The planar gate structure will also experience dimensional changes due to changes in photolithography and etching process parameters, as well as changes in pattern position due to changes in photolithography overlay precision.

[0039] On the same semiconductor substrate 101, the dimensional changes in the P-type well region 106 due to photolithography and implantation processes, as well as the changes in the pattern position due to photolithographic overlay accuracy parameters, and the dimensional changes in the planar gate structure due to photolithography and etching processes, as well as the changes in the pattern position due to photolithographic overlay accuracy parameters, all cause changes in the channel length Lc. The channel length Lc has a significant impact on the device's on-resistance, threshold voltage, and input capacitance (Cgs), which affects the consistency of device performance; for example, the consistency of channel length Lc, on-resistance, threshold voltage, and Cgs will all deteriorate.

[0040] Because the JFET effect is prone to occur in the N-type region between the channel regions, JFET-resistant implantation is performed to form a JFET-resistant region. The N-type impurity concentration in the JFET-resistant region is higher than that in the N-type epitaxial layer 102, for example, by one order of magnitude or more. The width Wj of the JFET-resistant region directly affects the Cgd value of the device. The width Wj will also change, thus affecting the consistency of the Cgd of the device.

[0041] The following section uses specific parameters to illustrate the adverse effects of existing methods on device consistency:

[0042] Depend on Figure 2As can be seen, the width and position of the P-type well region 106 are determined by the photolithography process of the P-type well region 106. This is because the critical dimension (CD) after photolithography will always vary to some extent with the thickness of the photoresist, the energy of the photolithography, and the development process (e.g., within + / -0.2 micrometers, and related to the size of the photolithographic pattern, process selection, etc.). The position of the pattern will also vary within a certain range due to the overlay accuracy (e.g., 60nm-150nm). Similarly, the width of the polysilicon gate is also related to the photolithography process and etching process of the polysilicon gate, and varies within a certain range. The photolithography overlay accuracy also fluctuates within a certain range. If the photoresist thickness is approximately 1 micrometer and a 248nm lithography machine is used, the single-layer width progress may fluctuate within ±0.1 micrometers. If the overlay progress varies within ±0.06 micrometers, considering the difference between the two lithographic layers, the channel length Lc may vary within ±0.32 micrometers. For a device with a 9-micrometer step, if the polysilicon gate width is set to 7.5 micrometers (already considered in a wide direction), and the single channel length Lc is designed to be 2-3 micrometers, this ±0.32-micrometer fluctuation already has a significant impact on device consistency. If the superjunction step is further reduced, for example, to 5 micrometers, then after deducting the 0.5-micrometer contact hole width and the 0.5-micrometer distance from the contact hole to the polysilicon edge, the entire polysilicon gate width is only 3.5 micrometers. The single-sided channel length Lc will definitely be less than 1.7 micrometers. This ±0.32-micrometer variation will result in very poor consistency.

[0043] This range of variation, even if reduced through optimization of photolithography and etching processes, especially through control of process conditions, comes at the cost of higher manufacturing costs. For example, stricter control over critical dimensions and overlay precision in photolithography increases rework rates, thus raising manufacturing costs. Furthermore, this variation, or rather, this uniformity, is inevitable, and the problem becomes increasingly pronounced as the superjunction step size decreases. Summary of the Invention

[0044] The technical problem to be solved by the present invention is to provide a superjunction device that can improve device uniformity and reduce the gate-drain capacitance of the device. To this end, the present invention also provides a method for manufacturing a superjunction device.

[0045] To solve the above-mentioned technical problems, the superjunction device provided by the present invention includes:

[0046] A superjunction structure is formed in the semiconductor substrate. The superjunction structure is formed by alternating arrangement of a plurality of first conductivity type pillars and second conductivity type pillars. The superjunction unit consists of a first conductivity type pillar and an adjacent second conductivity type pillar.

[0047] The structures of superjunction devices located in the active region include:

[0048] A planar gate structure is formed on top of each of the first conductivity type pillars, the planar gate structure being formed by stacking a first gate dielectric layer and a first gate conductive material layer.

[0049] The same unit cell has two planar gate structures, and a second gate dielectric layer is disposed between the first gate dielectric layers of the two planar gate structures.

[0050] The first side of each of the planar gate structures is close to the second conductive type post, and the second side of each of the planar gate structures is close to the middle region of the first conductive type post.

[0051] The second well region is formed by annealing an ion-implanted region of the second conductivity type with the first side of the planar gate structure as the self-alignment condition; the second well region diffuses laterally to the bottom region of the planar gate structure under the action of the annealing process.

[0052] The channel region is composed of the second well region covered by the planar gate structure, and the self-alignment structure between the second well region and the planar gate structure is used to improve the consistency of the device.

[0053] The surface portion of the drift region doped with the first conductivity type is located between the channel regions, and the second gate dielectric layer covers the surface of the drift region portion. The thickness of the second gate dielectric layer is greater than the thickness of the first gate dielectric layer, which is used to reduce the gate leakage capacitance of the device.

[0054] A further improvement is that the structure of the superjunction device located in the active region further includes:

[0055] The first well region consists of ion implantation regions of the second conductivity type formed on the top of each second conductivity type pillar, and the formation region of the first well region is defined by photolithography.

[0056] In the lateral direction, there is a gap between the first well region and the first side of the planar gate structure, the first well region and the first side of the planar gate structure are aligned, or the first well region extends to the bottom of the planar gate structure.

[0057] The body region is formed by the vertical stacking of the first well region and the second well region. The junction depth of the first well region is greater than that of the second well region, and the doping concentration of the first well region is less than that of the second well region, in order to reduce the leakage current of the device.

[0058] A further improvement is that a dielectric protection ring is formed on the surface of the semiconductor substrate, the dielectric protection ring covering the transition region and the termination region and opening the active region, the area enclosed by the dielectric protection ring being the active region, the transition region surrounding the periphery of the active region, and the termination region surrounding the periphery of the transition region.

[0059] An anti-JFET region is also formed in the active region. The anti-JFET region is composed of an ion implantation region of the first conductivity type formed on the surface of the superjunction structure by ion implantation of the active region with the dielectric guard ring and the second gate dielectric layer as self-alignment conditions.

[0060] The anti-JFET region is used to increase the first conductivity type doping concentration in the first conductivity type doping region to reduce the JFET effect.

[0061] The anti-JFET region is also used in the second conductivity type doping region to compensate for the second conductivity type doping impurities of the first P well in the surface region of the active region, so as to reduce the influence of the first P well on the second conductivity type doping of the surface region of the active region, and make the second conductivity type doping of the channel region determined by the second well region.

[0062] A further improvement is that the second gate dielectric layer and the dielectric protection ring have the same process structure, and the second gate dielectric layer and the dielectric protection ring are formed simultaneously; or, the process structures of the second gate dielectric layer and the dielectric protection ring are independent of each other.

[0063] A further improvement is that, in each of the unit cells, the planar gate structure is an integral structure, and a second gate conductive material layer is formed on the surface of the second gate dielectric layer, the second gate conductive material layer being extended from the first gate conductive material layers on both sides;

[0064] Alternatively, in each of the unit cells, the planar gate structure is a sub-gate structure, a second gate conductive material layer is formed on the surface of the second gate dielectric layer, the second gate conductive material layer and the first gate conductive material layers on both sides are spaced apart, the second gate conductive material layer is connected to the source, or the second gate conductive material layer is a floating structure;

[0065] Alternatively, in each of the unit cells, the planar gate structure is a sub-gate structure, no conductive material layer is formed on the surface of the second gate dielectric layer and the surface of the second gate dielectric layer is directly covered by an interlayer film, and the first gate conductive material layers on both sides of the second gate dielectric layer are spaced apart.

[0066] A further improvement is that a source region heavily doped with a first conductivity type is formed on the surface of the body region, and the source region and the first side of the planar gate structure are self-aligned.

[0067] A further improvement is that, in the lateral direction, the first well region at least covers the center position of the second conductive type pillar and the width of the first well region on both sides of the center position of the second conductive type pillar is 0.2 micrometers or more; or, the width of the first well region covering the second conductive type pillar is 1 micrometer to 2 micrometers or more.

[0068] In the vertical direction, the depth of the first well region is 1 micrometer to 2 micrometers; or, the depth of the first well region is more than 2 micrometers.

[0069] A further improvement is that when the depth of the first well region is 1 micrometer to 2 micrometers, the dielectric protection ring is composed of a thermally oxidized layer formed by a thermal oxidation process or is composed of a thermally oxidized layer formed by a thermal oxidation process and a deposited dielectric layer formed by a deposition process. The thermally oxidized layer of the dielectric protection ring causes the surface of the semiconductor substrate to be consumed. During the removal of the dielectric protection ring in the active region, the surface region of the first well region is removed. The doping concentration of the removed surface region of the first well region is higher than the doping concentration of the bottom retained region, which is used to improve the consistency of the device.

[0070] When the depth of the first well region is 2 micrometers or more, the dielectric protection ring is composed of a thermally oxidized layer formed by a thermal oxidation process, or is composed of a thermally oxidized layer formed by a thermal oxidation process and a deposited dielectric layer formed by a deposition process, or is composed of a deposited dielectric layer formed by a deposition process. The deposited dielectric layer of the dielectric protection ring reduces the thermal process of the device, thereby reducing the specific on-resistance of the device.

[0071] A further improvement is that a second conductivity type ring is formed in the transition region, and the first well region and the second conductivity type ring have the same process structure.

[0072] A further improvement is that the semiconductor substrate includes a silicon substrate;

[0073] A first epitaxial layer doped with a first conductivity type is formed on the surface of the semiconductor substrate;

[0074] The second conductivity type pillar is composed of a second epitaxial layer doped with the second conductivity type and filled in the trench;

[0075] The first conductive type pillar is composed of the first epitaxial layer between the second conductive type pillars;

[0076] The spacing between the bottom surface of the second conductivity type pillar and the top surface of the semiconductor substrate is more than 5 micrometers to improve the body diode characteristics of the device.

[0077] The first gate dielectric layer includes a gate oxide layer;

[0078] The first gate conductive material layer includes a polysilicon gate.

[0079] A further improvement is that the superjunction device includes a superjunction MOSFET or a superjunction IGBT.

[0080] A further improvement is that the superjunction device is an N-type device, with the first conductivity type being N-type and the second conductivity type being P-type; or, the superjunction device is a P-type device, with the first conductivity type being P-type and the second conductivity type being N-type.

[0081] To solve the above-mentioned technical problems, the manufacturing method of the superjunction device provided by the present invention includes the following steps:

[0082] Step 1: Form a superjunction structure in the semiconductor substrate. The superjunction structure is formed by alternating arrangement of multiple first conductivity type pillars and second conductivity type pillars. Each superjunction unit consists of a first conductivity type pillar and an adjacent second conductivity type pillar.

[0083] Step 2: Define the active region on the semiconductor substrate.

[0084] Step 3: Form a planar gate structure in the active region, with each planar gate structure formed on top of each first conductivity type pillar.

[0085] The planar gate structure is composed of a first gate dielectric layer and a first gate conductive material layer stacked together.

[0086] The same unit cell has two planar gate structures, and a second gate dielectric layer is disposed between the first gate dielectric layers of the two planar gate structures.

[0087] The first side of each of the planar gate structures is close to the second conductive type post, and the second side of each of the planar gate structures is close to the middle region of the first conductive type post.

[0088] Step 4: Using the first side of the planar gate structure as the self-alignment condition, perform ion implantation of the second conductivity type to form a second well region. Then, perform annealing on the second well region. Under the action of annealing, the second well region laterally diffuses to the bottom region of the planar gate structure.

[0089] The channel region is composed of the second well region covered by the planar gate structure, and the self-alignment structure between the second well region and the planar gate structure is used to improve the consistency of the device.

[0090] The surface portion of the drift region doped with the first conductivity type is located between the channel regions, and the second gate dielectric layer covers the surface of the drift region portion. The thickness of the second gate dielectric layer is greater than the thickness of the first gate dielectric layer, which is used to reduce the gate leakage capacitance of the device.

[0091] A further improvement is that, after step one is completed, the following step of forming the first well region is also included:

[0092] Photolithography defines the formation region of the first well region, which is located on top of the second conductivity type pillar in the active region.

[0093] The first well region is formed by implanting ions of the second conductivity type.

[0094] The first well region is annealed and advanced; in the lateral direction, the annealed and advanced first well region has a gap between it and the first side of the planar gate structure, the first well region is aligned with the first side of the planar gate structure, or the first well region extends to the bottom of the planar gate structure.

[0095] The body region is formed by the vertical stacking of the first well region and the second well region. The junction depth of the first well region is greater than that of the second well region, and the doping concentration of the first well region is less than that of the second well region, in order to reduce the leakage current of the device.

[0096] A further improvement is that step two includes the following sub-steps:

[0097] A material layer with a dielectric protective ring is formed on the surface of the semiconductor substrate;

[0098] Photolithography defines the formation region of the active region;

[0099] The dielectric protection ring is formed by etching the material layer of the dielectric protection ring. The dielectric protection ring covers the transition region and the terminal region and opens the active region. The area enclosed by the dielectric protection ring is the active region. The transition region surrounds the periphery of the active region, and the terminal region surrounds the periphery of the transition region.

[0100] A further improvement is that the second gate dielectric layer and the dielectric protection ring have the same process structure, and the second gate dielectric layer and the dielectric protection ring are formed simultaneously. After the material layer of the dielectric protection ring is formed, the formation area of ​​the second gate dielectric layer is defined simultaneously in the photolithography process. After etching, only the material layer of the dielectric protection ring in the formation area of ​​the second gate dielectric layer is retained in the active region, and the retained material layer of the dielectric protection ring serves as the second gate dielectric layer.

[0101] Alternatively, the process structures of the second gate dielectric layer and the dielectric protection ring are independent of each other.

[0102] A further improvement is that, in step three, in each of the unit cells, the planar gate structure is an integral structure, and a second gate conductive material layer is formed on the surface of the second gate dielectric layer, the second gate conductive material layer being extended from the first gate conductive material layers on both sides;

[0103] Alternatively, in step three, in each of the unit cells, the planar gate structure is a sub-gate structure, a second gate conductive material layer is formed on the surface of the second gate dielectric layer, the second gate conductive material layer and the first gate conductive material layers on both sides are spaced apart, the second gate conductive material layer and the first gate conductive material layer are formed in the same process and are formed simultaneously, the second gate conductive material layer is connected to the source or the second gate conductive material layer is a floating structure;

[0104] Alternatively, in step three, in each of the unit cells, the planar gate structure is a sub-gate structure, no conductive material layer is formed on the surface of the second gate dielectric layer, the surface of the second gate dielectric layer is directly covered by the interlayer film formed in the subsequent process, and the first gate conductive material layers on both sides of the second gate dielectric layer are spaced apart.

[0105] A further improvement is that, after step two and before step three, the following steps are included to form the JFET-resistant region:

[0106] The active region is formed by performing full first conductivity type ion implantation on the dielectric guard ring and the second gate dielectric layer as self-alignment conditions to form the JFET-resistant region.

[0107] The anti-JFET region is used to increase the first conductivity type doping concentration in the first conductivity type doping region in order to reduce the JFET effect.

[0108] The anti-JFET region is also used in the second conductivity type doping region to compensate for the second conductivity type doping impurities of the first P well in the surface region of the active region, so as to reduce the influence of the first P well on the second conductivity type doping of the surface region of the active region, and make the second conductivity type doping of the channel region determined by the second well region.

[0109] A further improvement is that, after step four, the process further includes: performing ion implantation of heavily doped ions of the first conductivity type in the active region, with the first side of the planar gate structure as the self-alignment condition, to form a source region.

[0110] A further improvement is that, in the lateral direction, the first well region at least covers the center position of the second conductive type pillar and the width of the first well region on both sides of the center position of the second conductive type pillar is 0.2 micrometers or more; or, the width of the first well region covering the second conductive type pillar is 1 micrometer to 2 micrometers or more.

[0111] In the vertical direction, the depth of the first well region is 1 micrometer to 2 micrometers; or, the depth of the first well region is more than 2 micrometers.

[0112] A further improvement is that when the depth of the first well region is 1 micrometer to 2 micrometers, the dielectric protection ring is composed of a thermally oxidized layer formed by a thermal oxidation process or is composed of a thermally oxidized layer formed by a thermal oxidation process and a deposited dielectric layer formed by a deposition process. The thermally oxidized layer of the dielectric protection ring causes the surface of the semiconductor substrate to be consumed. During the removal of the dielectric protection ring in the active region, the surface region of the first well region is removed. The doping concentration of the removed surface region of the first well region is higher than the doping concentration of the bottom retained region, which is used to improve the consistency of the device.

[0113] When the depth of the first well region is 2 micrometers or more, the dielectric protection ring is composed of a thermally oxidized layer formed by a thermal oxidation process, or is composed of a thermally oxidized layer formed by a thermal oxidation process and a deposited dielectric layer formed by a deposition process, or is composed of a deposited dielectric layer formed by a deposition process. The deposited dielectric layer of the dielectric protection ring reduces the thermal process of the device, thereby reducing the specific on-resistance of the device.

[0114] A further improvement is that a second conductivity type ring is formed in the transition region, and the first well region and the second conductivity type ring are formed simultaneously using the same process.

[0115] A further improvement is that the semiconductor substrate includes a silicon substrate;

[0116] A first epitaxial layer doped with a first conductivity type is formed on the surface of the semiconductor substrate;

[0117] The second conductivity type pillar is composed of a second epitaxial layer doped with the second conductivity type and filled in the trench;

[0118] The first conductive type pillar is composed of the first epitaxial layer between the second conductive type pillars;

[0119] The spacing between the bottom surface of the second conductivity type pillar and the top surface of the semiconductor substrate is more than 5 micrometers to improve the body diode characteristics of the device.

[0120] The first gate dielectric layer includes a gate oxide layer;

[0121] The first gate conductive material layer includes a polysilicon gate.

[0122] A further improvement is that, before step three, after the anti-JFET region is formed, the surface of the second conductivity type doped region covered by the anti-JFET region is inverted to the first conductivity type doped.

[0123] A further improvement is that the superjunction device includes a superjunction MOSFET or a superjunction IGBT.

[0124] A further improvement is that the superjunction device is an N-type device, with the first conductivity type being N-type and the second conductivity type being P-type; or, the superjunction device is a P-type device, with the first conductivity type being P-type and the second conductivity type being N-type.

[0125] Unlike existing technologies where the channel region is composed of ion-implanted regions defined by a photomask, the channel region of this invention is composed of a second well region that is self-aligned with the planar gate structure. Since the second well region and the planar gate structure are self-aligned, the second well region does not need to be defined by a photomask. Therefore, the influence of photolithography on the pattern width and photolithography overlay on the pattern position can be eliminated. That is, the length of the channel region formed by the second well region will not be affected by the photolithography process and photolithography overlay accuracy corresponding to the well region. Similarly, the length of the channel region will not be affected by the photolithography and etching process and photolithography overlay accuracy of the polysilicon gate. This can improve the consistency of the channel region length, the consistency of the device on-resistance and threshold voltage, and the consistency of the gate-source capacitance (Cgs). Finally, it can greatly improve the consistency of the device.

[0126] Furthermore, if the second well region, which is self-aligned with the planar gate structure, is used alone as the entire body region, the formation process of the second well region is limited by the planar gate structure, resulting in a shallow depth of the body region formed by using only the second well region, leading to a larger leakage current in the device. To address this, the present invention can also combine the base gate of the second well region with the first well region formed by a photomask before the planar gate structure to form the body region together. This allows the second well region to be used to improve the consistency of the device, while the deeper junction depth and gradual change structure of the first well region can be used to reduce the leakage current of the device.

[0127] Furthermore, after the first well region is introduced into the body region, it extends downwards from the surface of the active region. This first well region on the surface of the active region may then become part of the channel region, affecting the channel length and ultimately the device consistency. To address this new problem, this invention adds an anti-JFET region fully implanted in the active region. Since the anti-JFET region is only located on the surface of the active region and has a first conductivity type doping opposite to that of the first well region, it compensates for the second conductivity type doping impurities on the surface region of the first well region. Typically, the doping concentration of the anti-JFET region is greater than that of the surface region of the first well region. Therefore, before the second well region is formed, the anti-JFET region causes the surface of the second conductivity type doped region in the active region to be inverted to a first conductivity type doping, resulting in the entire surface of the active region being doped with the first conductivity type. This eliminates the adverse effects of the introduction of the first well region on the channel length and doping concentration, improving the device consistency, including the consistency of channel length and threshold voltage.

[0128] The region between the channel regions is N-type doped and serves as the surface portion of the drift region. Since a thicker second gate dielectric layer is placed above part of the surface of the drift region, the capacitance between the planar gate structure and the drift region can be reduced, thereby lowering Cgd. This can improve the device operating frequency and realize a fast superjunction device.

[0129] Meanwhile, the size of Cgd is also related to the width of the drift region located between the channel regions. Under the condition of self-alignment of the first side of the planar gate structure in the second well region and the unit cell, the width of the overlap region of the drift region between the planar gate structure and the channel region is only related to the width of the two planar gate structures in the unit cell. The width of the planar gate structure is affected by the photolithography and etching process of the planar gate structure. The photolithography overlay accuracy of the planar gate structure does not affect the width of the drift region covered by the planar gate structure between the channel regions. That is, it eliminates the influence of the photolithography overlay accuracy of the planar gate structure and the size and overlay accuracy of the second well region on the width of the overlap region of the drift region between the planar gate structure and the channel region in the prior art. Therefore, the consistency of the gate-drain capacitance (Cgd) of the device is also greatly improved.

[0130] In addition, when the junction depth is small, the first well region of the present invention can also remove the surface region with a high doping concentration by means of a thermal oxide layer, such as a thermal oxide layer forming a dielectric protection ring, thereby reducing the adverse effect of the surface region with a high doping concentration in the first well region on the channel region and further improving the consistency of the device.

[0131] When the junction depth of the first well region of the present invention is relatively deep, the doping concentration of the entire first well region is slowed down by utilizing the deeper junction depth. In this way, the doping concentration of the surface region of the first well region is also reduced, thereby reducing the adverse effects of the surface region of the first well region on the channel region and improving the consistency of the device. Attached Figure Description

[0132] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments:

[0133] Figure 1 This is a schematic diagram of an existing superjunction device;

[0134] Figure 2 This is a flowchart of an existing superjunction device manufacturing method;

[0135] Figure 3 This is a schematic diagram of the structure of the superjunction device according to the first embodiment of the present invention;

[0136] Figure 4 This is a schematic diagram of the superjunction device according to the second embodiment of the present invention;

[0137] Figure 5 This is a schematic diagram of the superjunction device according to the third embodiment of the present invention;

[0138] Figure 6 This is a schematic diagram of the structure of the superjunction device according to the fourth embodiment of the present invention;

[0139] Figure 7 This is a schematic diagram of the superjunction device according to the fifth embodiment of the present invention;

[0140] Figure 8 This is a flowchart of the manufacturing method of the superjunction device according to the first embodiment of the present invention;

[0141] Figures 9A-9G This is a schematic diagram of the device structure in each step of the manufacturing method of the superjunction device according to the first embodiment of the present invention. Detailed Implementation

[0142] like Figure 3 The diagram shown is a structural schematic of a superjunction device according to a first embodiment of the present invention; the superjunction device according to the first embodiment of the present invention includes:

[0143] A superjunction structure is formed in the semiconductor substrate 201. The superjunction structure is formed by alternating arrangement of a plurality of first conductivity type pillars and second conductivity type pillars 203. The superjunction unit consists of a first conductivity type pillar and an adjacent second conductivity type pillar 203.

[0144] In a first embodiment of the present invention, the semiconductor substrate 201 includes a silicon substrate. Typically, a first conductivity type epitaxial layer 202 is formed on the surface of the semiconductor substrate 201, and the first conductivity type pillars are composed of the first conductivity type epitaxial layer 202 between second conductivity type pillars 203.

[0145] The spacing between the bottom surface of the second conductivity type pillar 203 and the top surface of the semiconductor substrate 201 is 5 micrometers or more, generally set to 5 micrometers to 10 micrometers, in order to improve the body diode characteristics of the device.

[0146] Figure 3 The image only shows the structure of the superjunction device located in the active region. The structures of the superjunction device located in the active region include:

[0147] A planar gate structure is formed on top of each of the first conductivity type pillars. The planar gate structure is composed of a first gate dielectric layer 206 and a first gate conductive material layer 207 stacked together. Each of the two planar gate structures controls one conductive channel.

[0148] The same unit cell has two planar gate structures, and a second gate dielectric layer 206a is disposed between the first gate dielectric layer 206 of the two planar gate structures.

[0149] The first side of each of the planar gate structures is close to the second conductive type post 203, and the second side of each of the planar gate structures is close to the middle region of the first conductive type post.

[0150] Figure 3 In this process, the stepping of the superjunction unit is the same as that of the unit cell. A unit cell is formed within the width of one superjunction unit. For example, a unit cell is formed in the region between the middle positions of two second conductivity type pillars 203. Obviously, a unit cell includes two symmetrical planar gate structures, and the second gate dielectric layer 206a is disposed between the two planar gate structures.

[0151] In the first embodiment of the present invention, in each of the unit cells, the planar gate structure is an integral structure, and a second gate conductive material layer is formed on the surface of the second gate dielectric layer 206a. The second gate conductive material layer extends from the first gate conductive material layers 207 on both sides. Figure 3 In the diagram, the second gate conductive material layer is also marked with 207. The only difference between the second gate conductive material layer and the first gate conductive material layer 207 is that the second gate conductive material layer is located above the second gate dielectric layer 206a, including the side and top surfaces.

[0152] In some preferred embodiments, the first gate dielectric layer 206 includes a gate oxide layer.

[0153] The first gate conductive material layer 207 includes a polysilicon gate.

[0154] The second well region 2042 is formed by annealing an ion-implanted region of the second conductivity type with the first side of the planar gate structure as the self-alignment condition; the second well region 2042 diffuses laterally to the bottom region of the planar gate structure under the action of the annealing process. The second well region 2042 also diffuses vertically downwards under the action of the annealing process.

[0155] The channel region is composed of the second well region 2042 covered by the planar gate structure, and the self-alignment structure between the second well region 2042 and the planar gate structure is used to improve the consistency of the device. Figure 3 In the diagram, the length of the channel region is represented by Lc, and the length of the channel region is also... Figure 3 The second well region 2042 is located between the two straight lines corresponding to the channel length Lc. A conductive channel is formed after the surface of the channel region is inverted.

[0156] The surface portion of the drift region doped with the first conductivity type is located between the channel regions, and the second gate dielectric layer 206a covers the surface of the drift region portion. The thickness of the second gate dielectric layer 206a is greater than the thickness of the first gate dielectric layer 206, which is used to reduce the gate leakage capacitance of the device. Figure 3 In the first embodiment of the present invention shown, the drift region is composed of the first conductive type pillar between the channel regions and the first conductive type epitaxial layer 202 at the bottom of the first conductive type pillar.

[0157] Because the second well region 2042 is limited by self-alignment with the planar gate structure, the junction depth of the second well region 2042 is relatively shallow. If the second well region 2042 is used alone as the body region 204, a large leakage current will be generated. This situation is only applicable in situations where the leakage current requirement is not high.

[0158] Preferably, to reduce leakage current, the structure of the superjunction device in the active region according to the first embodiment of the present invention further includes:

[0159] The first well region 2041 is composed of ion implantation regions of the second conductivity type formed on the top of each second conductivity type pillar 203, and the formation region of the first well region 2041 is defined by photolithography.

[0160] In the lateral direction, there is a gap between the first well region 2041 and the first side of the planar gate structure, the first well region 2041 and the first side of the planar gate structure are aligned, or the first well region 2041 extends to the bottom of the planar gate structure. Figure 3The image shows an overlap between the first well region 2041 and the planar gate structure.

[0161] The body region 204 is formed by vertically stacking the first well region 2041 and the second well region 2042. The junction depth of the first well region 2041 is greater than that of the second well region 2042, and the doping concentration of the first well is less than that of the second well region 2042, in order to reduce the leakage current of the device. Figure 3 In this context, the first well region 2041 is also denoted by P1 and the second well region 2042 is also denoted by P2.

[0162] In the first embodiment of the present invention, the first well region 2041 is formed by photolithography definition, ion implantation, and annealing. After the annealing is completed, it is ensured that: in the lateral direction, the first well region 2041 covers the center position of the second conductive type pillar 203 and the width of the first well region 2041 on both sides of the center position of the second conductive type pillar 203 is 0.2 micrometers or more; or, the width of the first well region 2041 covering the second conductive type pillar 203 is 1 micrometer to 2 micrometers or more.

[0163] In the vertical direction, the depth of the first well region 2041 is 1 micrometer to 2 micrometers; or, the depth of the first well region 2041 is more than 2 micrometers.

[0164] A dielectric protection ring (not shown) is formed on the surface of the semiconductor substrate 201. The dielectric protection ring covers the transition region and the termination region and opens the active region. The area enclosed by the dielectric protection ring is the active region. The transition region surrounds the periphery of the active region, and the termination region surrounds the periphery of the transition region.

[0165] In the first embodiment of the present invention, the second gate dielectric layer 206a and the dielectric protection ring have the same process structure, and are formed simultaneously. The identical process structure of the second gate dielectric layer 206a and the dielectric protection ring includes that they are made of the same material, such as oxide layers, and have undergone the same process, such as thermal oxidation, photolithography, and etching. In other embodiments, the process structures of the second gate dielectric layer 206a and the dielectric protection ring may be independent of each other. Independent process structures include: the second gate dielectric layer 206a and the dielectric protection ring are made of different materials, requiring different processes for their formation; or the second gate dielectric layer 206a and the dielectric protection ring are made of the same material but have different morphologies or thicknesses, requiring different formation processes.

[0166] In the first embodiment of the present invention, the side of the second gate dielectric layer 206a is a vertical side. The structure with a vertical side can be achieved by dry etching of the second gate dielectric layer 206a and the dielectric protection ring after the material layer is deposited.

[0167] The active region includes the superjunction structure surrounding the dielectric guard ring. Since the first well region 2041 extends downwards from the surface of the active region, a high doping concentration of the first well region 2041 on the surface of the active region may adversely affect the second well region 2042 on the surface of the active region, ultimately affecting the size and doping concentration consistency of the channel region. Therefore, in some preferred embodiments, the following may be further included:

[0168] When the depth of the first well region 2041 is 1 micrometer to 2 micrometers, the dielectric protection ring is composed of a thermal oxide layer formed by a thermal oxidation process or is composed of a thermal oxide layer formed by a thermal oxidation process and a deposited dielectric layer formed by a deposition process. The thermal oxide layer of the dielectric protection ring causes the surface of the semiconductor substrate 201 to be consumed. During the removal of the dielectric protection ring in the active region, the surface area of ​​the first well region 2041 is removed. The doping concentration of the removed surface area of ​​the first well region 2041 is higher than the doping concentration of the bottom retained area, which is used to improve the uniformity of the device.

[0169] When the depth of the first well region 2041 is 2 micrometers or more, the dielectric protection ring is composed of a thermally oxidized layer formed by a thermal oxidation process, or is composed of a thermally oxidized layer formed by a thermal oxidation process and a deposited dielectric layer formed by a deposition process, or is composed of a deposited dielectric layer formed by a deposition process. The deposited dielectric layer of the dielectric protection ring reduces the thermal process of the device, thereby reducing the specific on-resistance of the device.

[0170] An anti-JFET region 205 is also formed in the active region. The anti-JFET region 205 is composed of an ion implantation region of the first conductivity type formed on the surface of the superjunction structure by ion implantation of the active region with the dielectric guard ring and the second gate dielectric layer 206a as self-alignment conditions.

[0171] The anti-JFET region 205 is used to increase the first conductivity type doping concentration in the first conductivity type doping region to reduce the JFET effect.

[0172] The anti-JFET region 205 is also used in the second conductivity type doping region to compensate for the second conductivity type doping impurities of the first well region 2041 on the surface region of the active region, so as to reduce the influence of the first P well on the second conductivity type doping of the surface region of the active region, and make the second conductivity type doping of the channel region determined by the second well region 2042.

[0173] Because the active region includes a superjunction structure, which comprises first conductivity type pillars and second conductivity type pillars 203, the superjunction structure causes the surface of the active region to have first conductivity type doped regions and second conductivity type doped regions distributed thereon. After the first well region 2041 is formed on the surface of the active region, the second conductivity type doped regions on the surface of the active region will increase. Before the first well region 2042 is formed, the anti-JFET region 205 can invert all the second conductivity type doped regions to the first conductivity type. Obviously, this can eliminate the adverse effects of the surface area of ​​the first well region 2041 on the channel region, thereby improving the consistency of the device.

[0174] A source region 208 of a first conductivity type is formed on the surface of the body region 204, and the source region 208 and the first side of the planar gate structure are self-aligned.

[0175] A second conductivity type ring is formed in the transition region, and the first well region 2041 and the second conductivity type ring have the same process structure.

[0176] In the first embodiment of the present invention, the superjunction device includes a superjunction MOSFET. In other embodiments, the superjunction device may also be a superjunction IGBT.

[0177] Depend on Figure 3 As shown, the front-side structure of the superjunction device also includes:

[0178] Interlayer film 209, through contact hole 210; at the bottom of contact hole 210 located at the top of source region 208, a body contact region 211 composed of heavily doped regions of second conductivity type is also formed, so that body region 204 is connected to the top contact hole 210 together with source region 208 through body contact region 211.

[0179] The source metal and gate metal are formed by patterning the front metal layer 212.

[0180] The back-side structure of the superjunction device includes:

[0181] The semiconductor substrate 201 is thinned to form a drain region; the drain region is formed directly by thinning the heavily doped semiconductor substrate 201, or the drain region is formed by backside ion implantation with heavy doping of a first conductivity type after thinning the semiconductor substrate 201.

[0182] A back metal layer 213 is formed on the back side of the drain region, and the drain electrode is composed of the back metal layer 213.

[0183] In the first embodiment of the present invention, the superjunction device is an N-type device, the first conductivity type is N-type, and the second conductivity type is P-type. In other embodiments, the superjunction device may also be a P-type device, with the first conductivity type being P-type and the second conductivity type being N-type.

[0184] Unlike existing technologies where the channel region is composed of ion-implanted regions defined by a photomask, the channel region in the first embodiment of this invention is composed of a second well region 2042 that is self-aligned with the planar gate structure. Since the second well region 2042 and the planar gate structure are self-aligned, the second well region 2042 does not need to be defined by a photomask. Therefore, the influence of photolithography on the pattern width and photolithography overlay on the pattern position can be eliminated. That is, the length of the channel region formed by the second well region 2042 will not be affected by the photolithography process and photolithography overlay accuracy corresponding to the well region. Similarly, the length of the channel region will not be affected by the photolithography and etching process and photolithography overlay accuracy of the polysilicon gate. This can improve the consistency of the channel region length, the consistency of the device on-resistance and threshold voltage, and the consistency of Cgs. Finally, it can greatly improve the consistency of the device.

[0185] Furthermore, if the second well region 2042, which is self-aligned with the planar gate structure, is used alone as the entire body region 204, the formation process of the second well region 2042 will be limited by the planar gate structure, resulting in a shallow depth of the body region 204 formed solely by the second well region 2042, leading to a larger device leakage current. To address this, the first embodiment of the present invention can also use a first well region 2041 formed by a photomask before the base gate of the second well region 2042 is combined with the planar gate structure to form the body region 204. This allows the second well region 2042 to improve device consistency, while the deeper junction depth and gradual change structure of the first well region 2041 can be used to reduce device leakage current.

[0186] Furthermore, after the first well region 2041 is introduced into the body region 204, the first well region 2041 will extend downwards from the surface of the active region. Thus, the first well region 2041 located on the surface of the active region may become part of the channel region, affecting the length of the channel region and ultimately the device consistency. To address this new problem, this invention adds a fully implanted anti-JFET region 205 in the active region. Since the anti-JFET region 205 is only located on the surface of the active region and is doped with the first conductivity type opposite to that of the first well region 2041, it will affect the first conductivity type of the surface region of the first well region 2041. To compensate for the doping of the second conductivity type, the doping concentration of the JFET-resistant region 205 is typically greater than the doping concentration of the surface region of the first well region 2041. Therefore, before the formation of the second well region 2042, the JFET-resistant region 205 will cause the surface of the second conductivity type doped region in the active region to be inverted to the first conductivity type doped, thus making the entire surface of the active region doped with the first conductivity type. This can eliminate the adverse effects of the introduction of the first well region 2041 on the length and doping concentration of the channel region, thereby improving the consistency of the device, including the consistency of the channel length and the consistency of the threshold voltage.

[0187] The region between the channel regions is N-type doped and serves as the surface portion of the drift region. Since the thicker second gate dielectric layer 206a is disposed above part of the surface of the drift region, the capacitance between the planar gate structure and the drift region can be reduced, thereby lowering Cgd. This can improve the device operating frequency and realize a fast superjunction device.

[0188] Meanwhile, the size of Cgd is also related to the width of the drift region located between the channel regions. Under the condition of self-alignment between the second well region 2042 and the first side of the planar gate structure in the unit cell, the width of the overlap region of the drift region between the planar gate structure and the channel region is only related to the width of the two planar gate structures in the unit cell. The width of the planar gate structure is affected by the photolithography and etching process of the planar gate structure. The photolithography overlay accuracy of the planar gate structure does not affect the width of the drift region covered by the planar gate structure between the channel regions. That is, it eliminates the influence of the photolithography overlay accuracy of the planar gate structure and the size and overlay accuracy of the second well region on the width of the overlap region of the drift region between the planar gate structure and the channel region in the prior art. Therefore, the consistency of Cgd of the device is also greatly improved.

[0189] In addition, when the junction depth of the first well region 2041 in the first embodiment of the present invention is small, the surface region with a high doping concentration of the first well region 2041 can be removed by a thermal oxide layer, such as a thermal oxide layer forming a dielectric protection ring, thereby reducing the adverse effect of the surface region with a high doping concentration of the first well region 2041 on the channel region and further improving the consistency of the device.

[0190] When the junction depth of the first well region 2041 in the first embodiment of the present invention is relatively deep, the doping concentration of the entire first well region 2041 is slowed down by utilizing the deeper junction depth. In this way, the doping concentration of the surface region of the first well region 2041 will also be reduced, thereby reducing the adverse effect of the surface region of the first well region 2041 on the channel region and improving the consistency of the device.

[0191] The first embodiment of the present invention also employs a special gate structure, which makes the thickness of the oxide film between the drift region and the gate, i.e., the second gate dielectric layer 206a, on the Si region outside the channel region, i.e., the first conductivity type pillar, significantly higher than that of the gate oxide film, i.e., the first gate dielectric layer 206. This reduces Cgd. For N-type devices, the size of Cgd is mainly related to the width of the N-type region under the device gate. Through the self-alignment of the second well region 2042, the overlap width between the polysilicon gate, i.e., the first gate conductive material layer 207, and the N-type region is only related to the width variation of the polysilicon gate. This eliminates the influence of the polysilicon gate photolithography overlay accuracy and the size and overlay accuracy of the Pwell, which are also present in the prior art, and thus greatly improves the consistency.

[0192] In the first embodiment of the present invention, the first well region 2041 is formed before the polysilicon gate in the process. Different depths can be obtained by adjusting the implantation energy, annealing temperature, and time according to process requirements. Typically, increasing the depth of the first well region 2041 and allowing for a gradual change in impurity concentration can reduce the device's leakage current Ids. Simultaneously, because the impurity concentration of the first well region 2041 can be designed to be relatively low, especially by using a thermal oxide film to create a protective epoxy film, this process adsorbs a significant amount of P-type impurities from the first well region 2041 to the interface between the oxide film and Si, and depletes the higher concentration of surface P-type impurities. Only the P-type impurities pushed into deeper locations remain, further improving device uniformity.

[0193] like Figure 4 The diagram shown is a structural schematic of the superjunction device according to the second embodiment of the present invention. The difference between the superjunction device of the second embodiment of the present invention and the superjunction device of the first embodiment of the present invention is as follows:

[0194] In the second embodiment of the present invention, in each unit cell, the planar gate structure is a segmented gate structure. No conductive material layer is formed on the surface of the second gate dielectric layer 206a, and the surface of the second gate dielectric layer 206a is directly covered by an interlayer film 209. The first gate conductive material layers 207 on both sides of the second gate dielectric layer 206a are spaced apart. Compared with the first embodiment of the present invention, the second embodiment of the present invention can further reduce the parasitic capacitance of the device.

[0195] like Figure 5The diagram shown is a structural schematic of the superjunction device according to the third embodiment of the present invention. The difference between the superjunction device of the third embodiment of the present invention and the superjunction device of the first embodiment of the present invention is as follows:

[0196] In the third embodiment of the present invention, in each unit cell, the planar gate structure is a split-gate structure, and a second gate conductive material layer 207a is formed on the surface of the second gate dielectric layer 206a. The second gate conductive material layer and the first gate conductive material layers 207 on both sides are spaced apart. The second gate conductive material layer 207a is connected to the source or is a floating structure. When the second gate conductive material layer 207a is connected to the source, it becomes a source field plate. Regardless of whether the second gate conductive material layer 207a is a source field plate or a floating structure, it can further reduce Cgd (edge ​​portion) and improve the BVdss or reliability of the device unit cell. Figure 5 In the figure, the second gate conductive material layer is indicated separately by the designation 207a.

[0197] like Figure 6 The diagram shown is a structural schematic of the superjunction device according to the fourth embodiment of the present invention. The difference between the superjunction device of the fourth embodiment of the present invention and the superjunction device of the first embodiment of the present invention is as follows:

[0198] In the fourth embodiment of the present invention, the second gate dielectric layer 206b has a tilted side surface. Although the dielectric protection ring is not shown, it also has a tilted side surface. The structure with tilted side surfaces can be achieved by dry etching followed by wet etching after material layer deposition of the second gate dielectric layer 206b and the dielectric protection ring. Figure 6 In the diagram, the second gate dielectric layer with the inclined side is separately marked with 206b. Figure 6 In the structure shown, the second gate dielectric layer 206b is compatible with the possible morphological requirements of the terminal region for this thick oxide film.

[0199] like Figure 7 The diagram shown is a structural schematic of the superjunction device according to the fifth embodiment of the present invention. The difference between the superjunction device of the fifth embodiment of the present invention and the superjunction device of the fourth embodiment of the present invention is as follows:

[0200] In the fifth embodiment of the present invention, in each unit cell, the planar gate structure is a segmented gate structure. No conductive material layer is formed on the surface of the second gate dielectric layer 206b, and the surface of the second gate dielectric layer 206b is directly covered by an interlayer film 209. The first gate conductive material layers 207 on both sides of the second gate dielectric layer 206b are spaced apart. Compared with the fourth embodiment of the present invention, the fifth embodiment of the present invention can further reduce the parasitic capacitance of the device.

[0201] like Figure 8 The diagram shown is a flowchart of a method for manufacturing a superjunction device according to the first embodiment of the present invention. Figure 8 The process uses photomask layers to represent each step. For example... Figures 9A to 9E The diagram shown is a schematic representation of the device structure in each step of the manufacturing method of the superjunction device according to the first embodiment of the present invention. The manufacturing method of the superjunction device according to the first embodiment of the present invention includes the following steps:

[0202] First, step S201 is performed. Step S201 is used to form the zero-layer mark, which requires a photolithography and etching process. Figure 8 In this context, step S201 is also represented by Zero photo & etch.

[0203] Step 1, such as Figure 9A As shown, a superjunction structure is formed in the semiconductor substrate 201. The superjunction structure is formed by alternating arrangement of a plurality of first conductivity type pillars and second conductivity type pillars 203. The superjunction unit consists of a first conductivity type pillar and an adjacent second conductivity type pillar 203.

[0204] In the first embodiment of the method of the present invention, the semiconductor substrate 201 includes a silicon substrate. Typically, a first conductivity type epitaxial layer 202 is formed on the surface of the semiconductor substrate 201, and the first conductivity type pillars are composed of the first conductivity type epitaxial layer 202 between the second conductivity type pillars 203.

[0205] The spacing between the bottom surface of the second conductivity type pillar 203 and the top surface of the semiconductor substrate 201 is 5 micrometers or more, generally set to 5 micrometers to 10 micrometers, in order to improve the body diode characteristics of the device.

[0206] In the first embodiment of the method of the present invention, the second conductive type pillar 203 is formed by trench etching and trench filling process. Figure 8 Step S202 in the text corresponds to step one. Figure 8 In this context, step S202 is also represented by Trench photo & etch.

[0207] In the method of the first embodiment of the present invention, as follows Figure 9A As shown, after step one is completed, the following steps are also included to form the first well region 2041:

[0208] The formation region of the first well region 2041 is defined by forming a pattern of photoresist 301 using a photolithography process. The first well region 2041 is located on top of the second conductivity type pillar 203 in the active region.

[0209] The first well region 2041 is formed by implanting ions of the second conductivity type.

[0210] The first well region 2041 is annealed and advanced; in the lateral direction, the annealed and advanced first well region 2041 and the first side of the planar gate structure are spaced apart, the first well region 2041 and the first side of the planar gate structure are aligned, or the first well region 2041 extends to the bottom of the planar gate structure.

[0211] In the lateral direction, the first well region 2041 at least covers the center position of the second conductive type pillar 203 and the width of the first well region 2041 on both sides of the center position of the second conductive type pillar 203 is 0.2 micrometers or more; or, the width of the first well region 2041 covering the second conductive type pillar 203 is 1 micrometer to 2 micrometers or more.

[0212] In the vertical direction, the depth of the first well region 2041 is 1 micrometer to 2 micrometers; or, the depth of the first well region 2041 is more than 2 micrometers.

[0213] Preferably, a second conductivity type ring is formed in the transition region, and the first well region 2041 and the second conductivity type ring are formed simultaneously using the same process. Taking an N-type device as an example, the second conductivity type ring is a P-type ring. Figure 8 Step S203 corresponds to the formation process of the P-type ring and the first well region 2041. Figure 8 In this context, step S203 is also represented by Pring photo & IMP, where IMP stands for ion implantation. In other embodiments, it can also be that the second conductivity type ring and the first well region 2041 are formed separately; or, the formation processes of the second conductivity type ring and the first well region 2041 are simultaneously cancelled; or, the formation process of the first well region 2041 is cancelled separately, while the formation process of the second conductivity type ring is retained.

[0214] Step 2: Define an active region on the semiconductor substrate 201.

[0215] In the method of the first embodiment of the present invention, step two includes the following sub-steps:

[0216] like Figure 9B As shown, a material layer (Gfield) 303 with a dielectric protection ring is formed on the surface of the semiconductor substrate 201.

[0217] Photolithography defines the formation region of the active region.

[0218] like Figure 9CAs shown, the dielectric protection ring is formed by etching the material layer 303 of the dielectric protection ring. The dielectric protection ring covers the transition region and the terminal region and opens the active region. The area enclosed by the dielectric protection ring is the active region. The transition region surrounds the periphery of the active region, and the terminal region surrounds the periphery of the transition region.

[0219] In the first embodiment of the present invention, the second gate dielectric layer 206a and the dielectric protection ring have the same process structure, and the second gate dielectric layer 206a and the dielectric protection ring are formed simultaneously. After the material layer of the dielectric protection ring is formed, as shown... Figure 9C As shown, the formation region of the second gate dielectric layer 206a is defined simultaneously in the photolithography process. After etching, only the material layer of the dielectric protection ring in the formation region of the second gate dielectric layer 206a is retained in the active region, and the material layer of the retained dielectric protection ring serves as the second gate dielectric layer 206a.

[0220] In other embodiments, the process structures of the second gate dielectric layer 206a and the dielectric protection ring can be independent of each other.

[0221] Figure 9C The etching process used is only dry etching, resulting in a vertical side surface for the final second gate dielectric layer 206a. Figure 3 , Figure 4 and Figure 5 The superjunction device of the first embodiment, the superjunction device of the second embodiment, and the superjunction device of the third embodiment of the present invention all employ... Figure 9C The second gate dielectric layer 206a is shown.

[0222] In some implementation methods, it is also possible to: Figure 9C The corresponding etching process involves adding a wet etching step after the dry etching is completed, thus forming... Figure 6 and Figure 7 The second gate dielectric layer 206b shown has inclined sides, and this process is suitable for forming Figure 6 and Figure 7 The corresponding super device of the fourth embodiment of the present invention and the superjunction device of the fifth embodiment of the present invention.

[0223] Figure 9AIn the diagram, surface 302 represents the surface of the active region. When the depth of the first well region 2041 is 1 micrometer to 2 micrometers, the doping concentration of the first well region 2041 is relatively high near surface 302. In this case, in some preferred embodiments, the high doping concentration on the surface of the first well region 2041 is removed by means of: the dielectric guard ring is composed of a thermally oxidized layer formed by a thermal oxidation process or is composed of a thermally oxidized layer formed by a thermal oxidation process and a deposited dielectric layer formed by a deposition process, wherein the thermally oxidized layer of the dielectric guard ring causes surface wear on the semiconductor substrate 201. Figure 9B As shown, surface 304 is the bottom surface of the material layer 303 of the dielectric protection ring. Obviously, surface 304 is located below surface 302. The material of the semiconductor substrate 201 between surface 302 and surface 304 is oxidized, so the surface region 2041a of the first well region 2041 is also oxidized.

[0224] During the removal of the dielectric protection ring in the active region, the surface region 2041a of the first well region 2041 is removed. The doping concentration of the removed surface region 2041a of the first well region 2041 is higher than that of the bottom retained region, which is used to improve the uniformity of the device. Figure 9C The image shows the surface of the active region reduced to surface 304.

[0225] In some other preferred embodiments, the depth of the first well region 2041 can be greater than 2 micrometers, after diffusion propulsion. Figure 9A In the vicinity of surface 302, the doping concentration of the first well region 2041 becomes lighter. At this time, the dielectric protection ring is composed of a thermally oxidized layer formed by a thermal oxidation process, or a combination of a thermally oxidized layer formed by a thermal oxidation process and a deposited dielectric layer formed by a deposition process, or a deposited dielectric layer formed by a deposition process. The deposited dielectric layer of the dielectric protection ring reduces the thermal process of the device, thereby lowering the specific on-resistance. That is, in this case, the material layer 303 of the dielectric protection ring has multiple formation processes to choose from. For example, when the material layer 303 of the dielectric protection ring is entirely composed of a deposited dielectric layer, the thermal process of the device is reduced, thus lowering the specific on-resistance.

[0226] Figure 8 Step S204 corresponds to step two. Since the photomask in step two mainly involves the photolithography and etching of the material layer 303 of the dielectric protection ring, i.e., the Gfield, therefore... Figure 8 In this context, step S204 is also represented by Gfield photo & etch.

[0227] like Figure 9DAs shown, in the method of the first embodiment of the present invention, after step two is completed and before step three is performed, the following steps are included to form the JFET-resistant region 205:

[0228] The active region is subjected to full first conductivity type ion implantation to form the JFET-resistant region 205, using the dielectric protection ring and the second gate dielectric layer 206a as self-alignment conditions.

[0229] The anti-JFET region 205 is used to increase the first conductivity type doping concentration in the first conductivity type doping region to reduce the JFET effect.

[0230] The anti-JFET region 205 is also used in the second conductivity type doping region to compensate for the second conductivity type doping impurities of the first P well in the surface region of the active region, so as to reduce the influence of the first P well on the second conductivity type doping of the surface region of the active region, and so that the second conductivity type doping of the channel region is determined by the subsequent second well region 2042.

[0231] Depend on Figure 9D As shown, since the width of the first well region 2041 is greater than the width of the second conductivity type pillar 203, the second conductivity type doped region of the surface area of ​​the active region is the surface area of ​​the first well region 2041, and the first conductivity type doped region of the surface area of ​​the active region is the surface area of ​​the first conductivity type pillar between the first well regions 2041. After the JFET-resistant region 205 is formed, the JFET-resistant region 205 inverts the surface of the second conductivity type doped region to the first conductivity type doped region. In this way, the entire surface area of ​​the active region is doped with the first conductivity type. Taking an N-type device as an example, after the JFET-resistant region 205 is formed, the surface of the active region is N-type doped, which can prevent the P-type doping of the active region from having an adverse effect on the uniformity of the channel region.

[0232] Figure 8 Step S205 in the text corresponds to the formation step of the JFET-resistant region 205. Figure 8 In this context, step S205 is also represented using JFET IMP. Figure 2 As can be seen from the corresponding flowchart, the method of the first embodiment of the present invention has made changes to the process of JFET IMP. JFET IMP no longer needs to use photomask definition, so step S205 is located outside the photomask process.

[0233] Step 3, as follows Figure 9E As shown, a planar gate structure is formed in the active region, and each planar gate structure is formed on top of each first conductivity type pillar; the planar gate structure is formed by stacking a first gate dielectric layer 206 and a first gate conductive material layer 207.

[0234] The same unit cell has two planar gate structures, and a second gate dielectric layer 206a is disposed between the first gate dielectric layer 206 of the two planar gate structures.

[0235] The first side of each of the planar gate structures is close to the second conductive type post 203, and the second side of each of the planar gate structures is close to the middle region of the first conductive type post.

[0236] In the method of the first embodiment of the present invention, the first gate dielectric layer 206 includes a gate oxide layer.

[0237] The first gate conductive material layer 207 includes a polysilicon gate.

[0238] The formation of the planar grid structure includes the following steps:

[0239] like Figure 9E As shown, the first gate dielectric layer 206 and the first gate conductive material layer 207 are sequentially formed over the entire surface of the semiconductor substrate 201.

[0240] like Figure 9F As shown, photolithography defines the formation area of ​​the planar gate structure, and then etching is performed to form the planar gate structure. Figure 9F In this process, a second gate conductive material layer is simultaneously formed on the surface of the second gate dielectric layer 206a between the planar gate structures, and the second gate conductive material layer is located in the extension structure of the first gate conductive material layer 207. Thus, in each unit cell, the planar gate structure is an integral structure. Finally, it can form... Figure 3 The superjunction device of the first embodiment of the present invention is shown.

[0241] If you want to form Figure 4 The superjunction device of the second embodiment of the present invention shown requires that the top region of the second gate dielectric layer 206a be completely opened in the photolithography definition. After etching, there is no conductive material layer on the surface of the second gate dielectric layer 206a. Thus, in each unit cell, the planar gate structure is a sub-gate structure.

[0242] If you want to form Figure 5 The superjunction device of the third embodiment of the present invention shown requires that the second gate dielectric layer 206a also be patterned in the photolithography definition. After etching, a superjunction is formed on the surface of the second gate dielectric layer 206a. Figure 5 The second gate conductive material layer 207a shown is not connected to the first gate conductive material layer 207; thus, in each unit cell, the planar gate structure is a sub-gate structure.

[0243] By combining the formation process of the second gate dielectric layer 206b and the formation process of the planar gate structure, a formation can also be obtained. Figure 6 The superjunction device of the fourth embodiment of the present invention shown is... Figure 7 The process combination of the superjunction device of the fifth embodiment of the present invention is shown.

[0244] Figure 8 Step S206 corresponds to step three, in which a photomask is used to define the polysilicon. Figure 8 In this context, step S206 is also represented by poly photo & etch.

[0245] Step 4, as follows Figure 9G As shown, a second well region 2042 is formed by ion implantation of a second conductivity type with the first side of the planar gate structure as the self-alignment condition. The second well region 2042 is then annealed, and under the action of the annealing process, the second well region 2042 laterally diffuses to the bottom region of the planar gate structure.

[0246] The channel region is composed of the second well region 2042 covered by the planar gate structure, and the self-alignment structure between the second well region 2042 and the planar gate structure is used to improve the consistency of the device.

[0247] The surface portion of the drift region doped with the first conductivity type is located between the channel regions, and the second gate dielectric layer 206a covers the surface of the drift region portion. The thickness of the second gate dielectric layer 206a is greater than the thickness of the first gate dielectric layer 206, which is used to reduce the gate leakage capacitance of the device.

[0248] The body region 204 is formed by vertically stacking the first well region 2041 and the second well region 2042. The junction depth of the first well region 2041 is greater than that of the second well region 2042, and the doping concentration of the first well is less than that of the second well region 2042, in order to reduce the leakage current of the device.

[0249] Figure 8 Step S207 in the text corresponds to step four. Figure 8 In this context, step S207 is also represented using Pwell IMP. Figure 2 As can be seen from the corresponding flowchart, the method of the first embodiment of the present invention has modified the process of Pwell IMP. Pwell IMP no longer needs to use photomask definition, so step S207 is located outside the photomask process.

[0250] Step four also includes:

[0251] like Figure 3As shown, source region 208 is formed by ion implantation of a first conductivity type with the first side of the planar gate structure as the self-alignment condition in the active region. Taking an N-type device as an example, source region 208 is an N+ region (Nplus). Figure 8 Step S208 corresponds to the formation process step of the source region 208. The formation process step of the source region 208 requires the use of a photomask to define the formation area of ​​the source region 208. Figure 8 In this context, step S208 is also represented by Nplusphoto&IMP.

[0252] Next, interlayer membrane 209.

[0253] A contact hole (Cont) 210 is formed through the interlayer film 209. The formation process of the contact hole 210 requires first using a photolithography process to define the formation area of ​​the contact hole 210, then etching to form the opening of the contact hole 210, and finally filling the opening of the contact hole 210 with metal to form the contact hole. Figure 8 Step S209 corresponds to the forming process step of the contact hole 210. In the forming process step of the contact hole 210, a photomask is used to define the forming area of ​​the contact hole 210. Figure 8 In this context, step S209 is also represented by Cont photo & etch.

[0254] A body contact region 211, composed of heavily doped regions of a second conductivity type, is also formed at the bottom of the contact hole 210 located at the top of the source region 208, so that the body region 204 is connected to the top contact hole 210 together with the source region 208 through the body contact region 211. The body contact region 211 is formed by implanting heavily doped ions of the second conductivity type after the opening of the contact hole 210 is opened.

[0255] A front metal layer 212 is formed and patterned to form source metal and gate metal. Figure 8 Step S210 corresponds to the formation process of the front metal layer 212. This formation process requires using a photomask to define the patterned area of ​​the front metal layer 212. Figure 8 In this context, step S210 is also represented by Metal photo & etch.

[0256] In the first embodiment of the method of the present invention, the superjunction device is a superjunction MOSFET. In other embodiments, the superjunction device may also be a superjunction IGBT.

[0257] After completing the front-side process, the following back-side process is also included:

[0258] The semiconductor substrate 201 is thinned to form a drain region; the drain region is formed directly by thinning the heavily doped semiconductor substrate 201, or the drain region is formed by backside ion implantation with heavy doping of a first conductivity type after thinning the semiconductor substrate 201.

[0259] A back metal layer 213 is formed on the back side of the drain region, and the drain electrode is composed of the back metal layer 213.

[0260] In the first embodiment of the method of the present invention, the superjunction device is an N-type device, the first conductivity type is N-type, and the second conductivity type is P-type. In other embodiments, the superjunction device may also be a P-type device, with the first conductivity type being P-type and the second conductivity type being N-type.

[0261] The method of the first embodiment of the present invention will be further described below with reference to specific parameters:

[0262] Taking a 600V N-type superjunction MOSFET as an example, a superjunction (SJ) structure with a step size of 9 micrometers is adopted, the top trench width is set to 4 micrometers, and the width of the top N-type epitaxial layer is 5 micrometers.

[0263] Semiconductor substrate 201 is a high-concentration substrate with a resistivity of 0.001-0.003 Ohm·cm.

[0264] The first conductivity type epitaxial layer, i.e., the N-type epitaxial layer 202, can be configured as follows:

[0265] The thickness of the N-type epitaxial layer 202 can be 50 micrometers or other values ​​within the range of 45-55 micrometers.

[0266] If the trench of the second conductivity type pillar, i.e., the P-type pillar 203, is very close to vertical, for example, with an inclination angle between 89 and 90 degrees, then the N-type epitaxial layer 202 can be a single-layer N-type epitaxial layer with a resistivity of 1-1.5 ohm·cm.

[0267] If the P-type trench has a certain tilt angle, such as between 88 and 89 degrees, then epitaxial layers with different resistivity can be designed based on the center value of the trench tilt angle. The main goal is to achieve a better charge balance in both the upper and lower regions of the trench, thereby obtaining a higher breakdown voltage (BVdss) or a better balance between BVdss and specific on-resistance (Rsp). For example, one embodiment of the P-type trench of the device involves first depositing a 20-30 μm N-type epitaxial layer with a resistivity of 1.5 ohm·cm on a high-concentration N-type substrate, followed by depositing a 30-20 μm thick N-type epitaxial layer with a resistivity of 1.25 ohm·cm, maintaining the total thickness of the N-type epitaxial layer at 50 μm.

[0268] For P-type trenches with a certain tilt angle, another epitaxial design approach is to use a PN structure with continuously varying N-type impurity concentration. For example, for a device with a 40-micron thick P-type pillar, a 10-micron thick 1-ohm-cm resistivity substrate can be deposited first on a high-concentration N-type substrate, followed by a 40-micron thick N-type epitaxial layer with continuously varying N-type impurity concentration. The resistivity variation of the N-type epitaxial layer is designed to balance the PN structure on each horizontal plane. This involves calculating the N-type impurity concentration at the top and bottom to achieve charge balance, based on the center value of the P-type pillar tilt angle. The resistivity at other locations in the middle then varies linearly between these two values. The P-type impurity concentration is kept consistent throughout the trench because the P-type pillar is larger at the top, requiring a higher N-type impurity concentration and lower resistivity for charge balance; conversely, it is smaller at the bottom, requiring a lower N-type impurity concentration and higher resistivity for charge balance. Therefore, the N-type resistivity can increase linearly from the top to the bottom of the PN pillar.

[0269] Step one, the process for forming the superjunction structure, mainly involves forming P-type pillars 203, including trench photolithography and etching, trench P-type epitaxial filling, and planarization.

[0270] A dielectric film can be deposited on the N-type epitaxial layer 202 first. This dielectric film can be a single oxide film, such as an oxide film with a thickness of more than 1 micrometer. This oxide film can be used as a hard mask during trench etching. After the trench is formed, an oxide film of a certain thickness will remain, such as an oxide film with a thickness of 0.1-0.2 micrometers. During the CMP process after the epitaxial filling is completed, this oxide film serves as a protective layer for the N-type epitaxy during CMP, so that the SI at this location will not be defective due to the CMP process, causing leakage or quality problems.

[0271] The dielectric film here can also consist of an oxide film with a thickness of 0.1-0.15 micrometers, a SiN film with a thickness of 0.1-0.2 micrometers, and an oxide film with a thickness greater than 1 μm on top. This allows for better control of uniformity during fabrication: for example, after trench etching is completed, at least some SiN is left on the oxide film below it. Before epitaxial growth, the SiN is removed. This results in good uniformity of the oxide film before epitaxial growth, which also improves the uniformity of CMP.

[0272] A further improvement to the above-mentioned multilayer film structure is that the first oxide film is formed by thermal oxidation, which further improves the uniformity.

[0273] In the P-type filling process, if the trench is very vertical, such as 89-90 degrees, then an epitaxial layer with a single impurity concentration can be used. If the P-type trench has a certain tilt angle, such as between 88-89 degrees, regardless of whether the N-type epitaxial layer uses a single resistivity or two resistivities, the P-type impurity concentration in the trench can be divided into different segments according to the requirements of optimal charge balance. That is, P-type epitaxial layers with different resistivities are used. For example, if the N-type epitaxial layer 202 is a single layer, then a high-concentration, low-resistivity P-type epitaxial layer can be filled at the bottom of the trench, and a higher-resistivity P-type epitaxial layer can be filled at the top of the trench. If the N-type impurity concentration has been set to continuously vary the resistivity according to the trench tilt angle, then a single resistivity can be used for the P-type epitaxial layer. The goal is to obtain the optimal balance between BVdss and Rsp.

[0274] In the process steps of forming the first well region 2041 and the P-ring: the P-ring of the transition region is defined by P-ring photolithography, and the area of ​​the first well region 2041 is also defined. The P-ring surrounds the active region of the chip, and its width can be from 1 micrometer to 50 micrometers. When the gate bus is wide, the P-ring can also be widened because it does not bring additional chip area increase. When the gate bus is small or even some areas do not have a gate bus, the P-ring can also be reduced in size, and the design can be considered in terms of EAS capability requirements. The first well region 2041 can overlap with the subsequent active region polygate, or it can be aligned with the polygate, or even have a certain distance from the polygate, as long as it is ensured that when the final process is completed, the first well region 2041 must cover the top 1-2 micrometers of the P-type pillar 203, or more, or at least cover the top 1-2 micrometers of the P-type pillar 203 vertically, and at least cover the area of ​​0.2 micrometers to the left and right of the center of the trench laterally.

[0275] The impurity implanted into the P-type ring can be B, BF2, or a combination thereof. The energy can be selected from 30 keV to 2 meV, depending on the required depth of the P-type 203 column to be covered, and the temperature and time of the subsequent thermal process. The dosage can be 5E12-5E13 atoms / cm². 2 A design for B 60keV 1E13 / cm 2 The impurity injected was B, the injection energy was 60 keV, and the injection dose was 1E13 / cm. 2 .

[0276] Step two in forming the dielectric protection ring includes:

[0277] The dielectric guard ring will cover the transition region and the terminal region except for the outermost N+ region, which is not necessarily required and will be removed in the active region. In some embodiments, the material layer 303 of the dielectric guard ring is formed by thermal oxidation at a temperature of 850°C-1050°C and a thickness of 8000 angstroms to 10000 angstroms, or at least partially formed by a thermal oxide film. In this way, while pushing the P-type impurities of the previously implanted first well region 2041 into the Si depth direction, a portion of the surface Si, for example 3500 angstroms-4000 Å, containing the implanted P-type impurities, is also oxidized.

[0278] By using dielectric protection ring photolithography and etching, the surface material layer 303 in the active region is at least completely removed.

[0279] In the step of forming the JFET-resistant region 205:

[0280] After the dielectric guard ring photolithography and etching are completed, the dielectric guard ring is used as a mask to perform comprehensive JFET-resistant implantation on at least the active region, forming a high-concentration N-type JFET-resistant region 205. The implanted N-type impurities can be phosphorus or arsenic. The main purpose is to create a region on the silicon wafer surface with a higher concentration of N-type epitaxial impurities than the N-type epitaxial impurities, reducing the device's Rsp. Here, this process can simultaneously compensate for the P-type impurities on the surface of the first well region 2041, making the entire surface of the active region N-type. This reduces the impact of the first well region 2041 process on the device surface, that is, it reduces the impact of the critical dimensions and overlay accuracy of the first well region 2041 photolithography on the device's threshold voltage (Vth) and other performance characteristics.

[0281] The process parameters for forming the planar gate structure and the second well region 2042 are as follows:

[0282] A gate oxide film, i.e., the first gate dielectric layer 206, is formed, and polysilicon, i.e., the first gate conductive material layer 207, is formed. A polysilicon gate pattern is then formed through photolithography and etching, such as... Figure 3 As shown, there are two dielectric film thickness structures under the gate, namely, between two adjacent P-type pillars, there are at least two polysilicon gate segments, below which is a thin gate oxide film, namely the first gate dielectric layer 206, for example... And at least part of the drift region has a greater than [missing information - likely a number] between the polysilicon gate and the drift region. The dielectric film, namely the second gate dielectric layer 206a, significantly reduces Cgd.

[0283] The thickness of the polysilicon gate, i.e., the first gate conductive material layer 207, can be set to...

[0284] Subsequently, impurities are implanted into the end of the polysilicon gate for a self-aligned second well region 2042.

[0285] Ion implantation in this second well region 2042 is self-aligned with a polysilicon gate, and the impurity is B, BF2, or a combination thereof. For example, the implanted impurity is set to B, and the implantation energy is 60keV-150keV. Preferably, the implanted impurity is B, the implantation energy is 120keV, and the implantation dose is 1E14-2E14 / cm. 2 To obtain devices with Vth in the range of 2-4V.

[0286] The thickness of the gate oxide film is set here to It uses thermal oxidation film and is manufactured at a temperature of 850℃-1050℃.

[0287] The polysilicon gate is an in-situ doped high-concentration N-type polysilicon with a thickness of 6000 angstroms.

[0288] After the second well region 2042 is injected, it is pushed to the required lateral and longitudinal positions by an annealing process at 1000℃-1150℃ for 30-180 minutes.

[0289] The formation process of the source region 208 includes:

[0290] After the polycrystalline electrode is formed, at least the source region 10 of the device is formed by N+ photolithography and ion implantation. At the same time, a terminal N+ region can be formed in the outermost region of the terminal. The terminal peripheral N+ region can be used to prevent surface inversion in the terminal region, which improves the stability of the breakdown characteristics of the device. The terminal peripheral N+ region can also be omitted.

[0291] N+ injection in the source region 208 can generally be achieved through AS or Phos injection, or a combination thereof. Injection conditions are typically 30-100 keV and 1-5 E15 / cm². 2 It can be activated through a thermal process at 9000-1050℃ after injection.

[0292] The process for forming the interlayer membrane 209 and the contact hole 210 includes:

[0293] An interlayer film 209 is deposited, which can be a combination of an undoped oxide film and a BPSG film. Then, the openings of contact holes 210 are formed through photolithography and etching. After forming the openings of contact holes 210, high-concentration P implantation is performed to form a bulk contact region 211 composed of a high-concentration P-type region, ensuring good ohmic contact between the metal and the bulk region 204. The implanted impurities in this bulk contact region 211 can be B or BF2, with the implantation energy set to 20-60 keV and the dose set to 1E13-3E15 / cm. 2 After ion implantation, activation can be achieved through a thermal process at temperatures of 690-900℃.

[0294] During the etching of the opening of the contact hole 210, silicon in the high concentration region of N+ impurities at the bottom of the interlayer film 209 can also be etched away. The etching amount can be between 2000 angstroms and 4000 angstroms, depending on the N+ implantation conditions, i.e., the implantation energy and dose. Generally, the thickness of the interlayer film is 6000-10000 angstroms.

[0295] The formation process of the interlayer film 209, contact hole 210 and front metal layer 212 includes:

[0296] An interlayer film 209 is deposited, which can be a combination of an undoped oxide film and a BPSG film. Then, the openings of contact holes 210 are formed through photolithography and etching. After forming the openings of contact holes 210, high-concentration P implantation is performed to form a bulk contact region 211 composed of a high-concentration P-type region, ensuring good ohmic contact between the metal and the bulk region 204. The implanted impurities in this bulk contact region 211 can be B or BF2, with the implantation energy set to 20-60 keV and the dose set to 1E13-3E15 / cm. 2 After ion implantation, activation can be achieved through a thermal process at temperatures of 690-900℃.

[0297] During the etching of the opening of the contact hole 210, silicon in the high concentration region of N+ impurities at the bottom of the interlayer film 209 can also be etched away. The etching amount can be between 2000 angstroms and 4000 angstroms, depending on the N+ implantation conditions, i.e., the implantation energy and dose. Generally, the thickness of the interlayer film is 6000-10000 angstroms.

[0298] The metal filling the opening of contact hole 210 can be Ti, TiN, or W, followed by etching back or CMP. Then, AlSi is deposited on the front side of the silicon wafer to form a front metal layer 212. In a preferred embodiment, the width of contact hole 210 is set to 0.5 micrometers, the thickness of interlayer film 209 is set to 8000-10000 angstroms, and the opening of contact hole 210 is formed by filling with Ti / TiN and W followed by etching back or CMP.

[0299] If the contact hole 210 is large enough, Ti, TiN, AlCu, AlSiCu, or AlSiCu deposition can be used to directly fill the opening of the contact hole 210 and form the front metal layer 212. Then, photolithography of the front metal layer 212 is performed to form the source metal and gate metal of the active region. The thickness of the barrier layer can be Ti... and TiN The thickness of AlCu or AlSiCu metal is typically 4-6 μm.

[0300] The back side of the silicon wafer 201 is then thinned, and a back metal layer 213 is deposited on the back side to form the drain.

[0301] This completes the formation of a superjunction MOSFET device.

[0302] In some embodiments, after the front metal layer 212 of the silicon wafer, i.e., the semiconductor substrate 201, is formed, a passivation film can be deposited, photolithographically etched, and etched, or polyimide photolithography can be added, followed by back-side thinning and deposition of the back metal layer 213, thereby further improving the reliability of the device. The passivation film thickness is generally... It can be an oxide film, SIN, SION, or a combination thereof. Polyimide is generally 5-10 micrometers thick after high-temperature baking. Both the passivation film and polyimide mainly cover the terminal area and the boundary with the front metal layer 212, generally covering 5-10 micrometers, and forming a 0-10 micrometer protection at the outermost edge of the dicing groove.

[0303] In one improved embodiment of the method, the following process parameters can be used:

[0304] In the formation process of the first well region 2041, the photoresist is used with a thickness of more than 3 micrometers, and the P-type implantation of the first well region 2041 is 1.5-2 MeV, so that the peak concentration of ion implantation is located more than 1 micrometer away from the Si surface. This ensures that the junction depth of the first well region 2041 is at least more than 2 micrometers, which can reduce the leakage current Idss of the device.

[0305] In one improved embodiment of the method, the following process parameters can be used:

[0306] After the P-type implantation of the first well region 2041 is completed and before the formation of the dielectric protection ring, a high-temperature push-well process is added, such as annealing at a temperature of 1000-1150℃ for 30-180 minutes. This pushes the depth of the first well region 2041 to a position 2 micrometers or deeper from the Si surface, and reduces and gradually modulates the distribution of P-type well impurities in the depth direction, further reducing the leakage current Ids of the device and improving the characteristics of the device's body diode.

[0307] In one improved embodiment of the method, the following process parameters can be used:

[0308] In the formation process of the first well region 2041, the photoresist is made with a thickness of more than 3 micrometers. The P-type implantation of the first well region 2041 is 1.5-2 MeV, so that the peak concentration of ion implantation is more than 1 micrometer away from the Si surface, thereby maintaining the junction depth of the minimum Pwell greater than 2 micrometers. At the same time, the material layer of the dielectric protection ring is a deposited dielectric film instead of a thermal oxide film, which reduces the thermal process of the process and improves the Rsp of the device.

[0309] In one improved embodiment of the method, the following process parameters can be used:

[0310] After the P-type implantation of the first well region 2041 is completed and before the formation of the dielectric protection ring, a high-temperature push-well process is added, such as annealing at a temperature of 1000-1150℃ for 30-180 minutes. This pushes the depth of the first well region 2041 to a position 2 micrometers or deeper from the Si surface, and reduces and gradually modulates the distribution of P-type well impurities in the depth direction, further reducing the leakage current Ids of the device and improving the characteristics of the body diode. Simultaneously, the dielectric protection ring uses a deposited dielectric film instead of a thermally oxidized film, thus reducing the thermal processes in the manufacturing process.

[0311] In one improved embodiment of the method, the following process parameters can be used:

[0312] In the formation process of the first well region 2041, the overlap between the first well region 2041 and the polysilicon gate can be set between 0.32 and 0.5 micrometers. This ensures that under normal process control, there is an overlap of greater than or equal to 0 micrometers between the first well region 2041 and the polysilicon gate of all units, which can improve the consistency of the leakage current Idss of the device.

[0313] In one improved embodiment of the method, the following process parameters can be used:

[0314] In step four, ion implantation in the second well region 2042 can employ high-energy implantation, such as B ion implantation with an energy higher than 1 MeV. Increasing the implantation energy can increase the effective channel length of the device and reduce the leakage current Idss.

[0315] In one improved embodiment of the method, the following process parameters can be used:

[0316] The process of forming the first well region 2041 is cancelled. Figure 8 In step S203, only the second well region 2042 formed in the self-aligned process is used as the body region. At this time, the leakage current ids of the device will increase, but the consistency of switching characteristics, Vth, on-resistance (Rdson) will be further improved.

[0317] In one improved embodiment of the method, the following process parameters can be used:

[0318] The formation process of the first well region 2041 is cancelled, but the process is retained. Figure 8In step S203, a P-type ring is formed only in the transition region. The first well region 2041 is not formed in the active region. Instead, a second well region 2042 is formed in the self-aligned process as the body region. In this case, the leakage current ids of the device will increase, but the consistency of switching characteristics, Vth, Rdson, etc. will be further improved.

[0319] The present invention has been described in detail above through specific embodiments, but these are not intended to limit the invention. Many modifications and improvements can be made by those skilled in the art without departing from the principles of the invention, and these should also be considered within the scope of protection of the present invention.

Claims

1. A superjunction device, comprising: Comprise: A super junction structure is formed in a semiconductor substrate, the super junction structure is formed by a plurality of first conductive type pillars and second conductive type pillars arranged alternately, a super junction unit is composed of one first conductive type pillar and one adjacent second conductive type pillar; The structure of the super junction device in the active region comprises: A planar gate structure is formed on the top of each first conductive type pillar, the planar gate structure is composed of a first gate dielectric layer and a first gate conductive material layer; There are two planar gate structures in the same unit cell, and a second gate dielectric layer is arranged between the first gate dielectric layers of the two planar gate structures; The first side of each planar gate structure is close to the second conductive type pillar, and the second side of each planar gate structure is close to the middle region of the first conductive type pillar; A second well region is composed of a second conductive type ion implantation region with the first side of the planar gate structure as a self-alignment condition after annealing treatment; the second well region laterally diffuses to the bottom region of the planar gate structure under the action of annealing treatment; The channel region is composed of the second well region covered by the planar gate structure, and the self-alignment structure between the second well region and the planar gate structure is used to improve the consistency of the device; The surface part of the first conductive type doped drift region is located between the channel regions, the second gate dielectric layer is covered on the surface part of the drift region, and the thickness of the second gate dielectric layer is greater than the thickness of the first gate dielectric layer, which is used to reduce the gate-drain capacitance of the device; The structure of the super junction device in the active region further comprises: A first well region is composed of a second conductive type ion implantation region formed on the top of each second conductive type pillar, and the formation region of the first well region is defined by photolithography; In the lateral direction, there is a spacing between the first well region and the first side of the planar gate structure, the first well region and the first side of the planar gate structure are aligned, or the first well region extends to the bottom of the planar gate structure; The body region is composed of the longitudinal superposition of the first well region and the second well region, the junction depth of the first well region is greater than the junction depth of the second well region, and the doping concentration of the first well region is less than the doping concentration of the second well region, which is used to reduce the leakage current of the device.

2. The superjunction device of claim 1, wherein: A dielectric guard ring is formed on the surface of the semiconductor substrate, the dielectric guard ring covers the transition region and the terminal region and opens the active region, the area surrounded by the dielectric guard ring is the active region, the transition region surrounds the side of the active region, and the terminal region surrounds the side of the transition region; An anti-JFET region is also formed in the active region, the anti-JFET region is composed of a first conductive type ion implantation region formed on the surface of the super junction structure by full first conductive type ion implantation on the active region with the dielectric guard ring and the second gate dielectric layer as self-alignment conditions; The anti-JFET region is used to increase the first conductive type doping concentration of the first conductive type doped region, and to reduce the JFET effect. The anti-JFET region is used for compensating the second-conductivity-type doping impurities of the first well region of the active region surface area, so as to reduce the influence of the first well region on the second-conductivity-type doping of the active region surface area, and make the second-conductivity-type doping of the channel region determined by the second well region.

3. The superjunction device of Claim 2, wherein: The process structure of the second gate dielectric layer and the dielectric protection ring is the same, and the second gate dielectric layer and the dielectric protection ring are formed simultaneously; or the process structure of the second gate dielectric layer and the dielectric protection ring is independent of each other.

4. The superjunction device of claim 1, wherein: In each of the unit cells, the planar gate structure is an integral structure, a second gate conductive material layer is formed on the surface of the second gate dielectric layer, and the second gate conductive material layer is extended from the first gate conductive material layers on both sides; Or, in each of the unit cells, the planar gate structure is a split-gate structure, a second gate conductive material layer is formed on the surface of the second gate dielectric layer, and the second gate conductive material layer and the first gate conductive material layers on both sides have a spacing, the second gate conductive material layer is connected with the source or the second gate conductive material layer is in a floating structure; Or, in each of the unit cells, the planar gate structure is a split-gate structure, no conductive material layer is formed on the surface of the second gate dielectric layer, and the surface of the second gate dielectric layer is directly covered by an interlayer film, and the first gate conductive material layers on both sides of the second gate dielectric layer have a spacing.

5. The superjunction device of claim 2, wherein: A first-conductivity-type heavily doped source region is formed on the surface of the body region, and the source region is self-aligned with the first side surface of the planar gate structure.

6. The superjunction device of Claim 2, wherein: In the lateral direction, the first well region covers at least the center position of the second-conductivity-type pillar and the width of the first well region on both sides of the center position of the second-conductivity-type pillar is greater than or equal to 0.2 microns; or the first well region covers the second-conductivity-type pillar with a width greater than or equal to 1 micron. In the longitudinal direction, the depth of the first well region is 1-2 microns; or the depth of the first well region is greater than 2 microns.

7. The superjunction device of claim 6, wherein: When the depth of the first well region is 1-2 microns, the dielectric protection ring is composed of a thermal oxide layer formed by a thermal oxidation process or is composed of a thermal oxide layer formed by a thermal oxidation process and a deposited dielectric layer formed by a deposition process, the thermal oxide layer of the dielectric protection ring causes the surface of the semiconductor substrate to be consumed, and the surface area of the first well region is removed in the dielectric protection ring removal process of the active region, the doping concentration of the removed surface area of the first well region is higher than that of the bottom reserved area, and the device consistency is improved; When the depth of the first well region is greater than 2 microns, the dielectric protection ring is composed of a thermal oxide layer formed by a thermal oxidation process or is composed of a thermal oxide layer formed by a thermal oxidation process and a deposited dielectric layer formed by a deposition process or is composed of a deposited dielectric layer formed by a deposition process, and the deposited dielectric layer of the dielectric protection ring reduces the thermal process of the device, so as to reduce the specific on-resistance of the device.

8. The superjunction device of Claim 7, wherein: A second conductive type ring is formed in the transition region, and the first well region and the second conductive type ring have the same process structure.

9. The superjunction device as described in claim 1, characterized in that: The semiconductor substrate comprises a silicon substrate; A first epitaxial layer doped with a first conductive type is formed on the surface of the semiconductor substrate; The second conductive type column is composed of a second epitaxial layer doped with a second conductive type filled in the trench; The first conductive type column is composed of the first epitaxial layer between the second conductive type columns; The distance between the bottom surface of the second conductive type column and the top surface of the semiconductor substrate is greater than or equal to 5 microns, so as to improve the body diode characteristics of the device; The first gate dielectric layer comprises a gate oxide layer; The first gate conductive material layer comprises a polysilicon gate.

10. The superjunction device of any of claims 1 to 9, wherein: The super junction device comprises a super junction MOSFET or a super junction IGBT.

11. The superjunction device of claim 10, wherein: The super junction device is an N-type device, the first conductive type is N-type, and the second conductive type is P-type; or the super junction device is a P-type device, the first conductive type is P-type, and the second conductive type is N-type.

12. A method of manufacturing a super junction device, the method comprising: The method comprises the following steps: Step one: forming a super junction structure in a semiconductor substrate, the super junction structure is formed by a plurality of first conductive type columns and second conductive type columns arranged alternately, and a super junction unit is composed of one first conductive type column and one adjacent second conductive type column; Step two: defining an active region on the semiconductor substrate; Step three: forming a planar gate structure in the active region, each planar gate structure is formed on the top of each first conductive type column; The planar gate structure is composed of a first gate dielectric layer and a first gate conductive material layer; There are two planar gate structures in the same unit cell, and a second gate dielectric layer is arranged between the first gate dielectric layers of the two planar gate structures; The first side surface of each planar gate structure is close to the second conductive type column, and the second side surface of each planar gate structure is close to the middle region of the first conductive type column; Step four: performing ion implantation of the second conductive type with the first side surface of the planar gate structure as a self-alignment condition to form a second well region, and performing annealing treatment on the second well region, the second well region laterally diffuses to the bottom region of the planar gate structure under the action of the annealing treatment; The channel region is composed of the second well region covered by the planar gate structure, and the self-alignment structure between the second well region and the planar gate structure is used to improve the consistency of the device; The surface part of the first conductive type doped drift region is located between the channel regions, the second gate dielectric layer is covered on the surface part of the drift region, and the thickness of the second gate dielectric layer is greater than the thickness of the first gate dielectric layer, which is used to reduce the gate-drain capacitance of the device; After step one is completed, the following step of forming a first well region is further included: Photolithography defines the formation region of the first well region, and the first well region is located on the top of the second conductive type column in the active region; Second conductive type ion implantation is performed to form the first well region; The first well region is annealed to advance, and in the lateral direction, the first well region after annealing advancement and the first side of the planar gate structure have a spacing, are aligned, or the first well region extends to the bottom of the planar gate structure; The body region is formed by the longitudinal superposition of the first well region and the second well region, the first well region has a larger junction depth than the second well region, and the first well region has a smaller doping concentration than the second well region, so as to reduce the leakage current of the device.

13. The method of fabricating a superjunction device of claim 12, wherein: Step two includes the following sub-steps: forming a material layer of the dielectric protection ring on the surface of the semiconductor substrate; photolithography defines the formation area of the active region; etching the material layer of the dielectric protection ring to form the dielectric protection ring, the dielectric protection ring covers the transition region and the terminal region and opens the active region, the area surrounded by the dielectric protection ring is the active region, the transition region surrounds the periphery of the active region, and the terminal region surrounds the periphery of the transition region.

14. The method of fabricating a superjunction device of claim 13, wherein: The process structure of the second gate dielectric layer and the dielectric protection ring is the same, and the second gate dielectric layer and the dielectric protection ring are formed at the same time. After forming the material layer of the dielectric protection ring, the formation area of the second gate dielectric layer is defined at the same time in the photolithography process. After etching, only the material layer of the dielectric protection ring in the formation area of the second gate dielectric layer in the active region is retained, and the material layer of the dielectric protection ring is used as the second gate dielectric layer; Alternatively, the process structure of the second gate dielectric layer and the dielectric protection ring is independent of each other.

15. The method of fabricating a super junction device of claim 12, wherein: In step three, in each of the unit cells, the planar gate structure is an integral structure, a second gate conductive material layer is formed on the surface of the second gate dielectric layer, and the second gate conductive material layer is extended from the first gate conductive material layers on both sides; Alternatively, in step three, in each of the unit cells, the planar gate structure is a split gate structure, a second gate conductive material layer is formed on the surface of the second gate dielectric layer, and the second gate conductive material layer and the first gate conductive material layers on both sides have a spacing. The formation process of the second gate conductive material layer and the first gate conductive material layer is the same and is formed at the same time. The second gate conductive material layer is connected to the source or the second gate conductive material layer is in a floating structure; Alternatively, in step three, in each of the unit cells, the planar gate structure is a split gate structure, and no conductive material layer is formed on the surface of the second gate dielectric layer. The surface of the second gate dielectric layer is directly covered by an interlayer film formed in a subsequent process. The first gate conductive material layers on both sides of the second gate dielectric layer have a spacing.

16. The method of fabricating a superjunction device of claim 14, wherein: After step two is completed and before step three is performed, the following step of forming an anti-JFET region is included: comprehensive first-conductive-type ion implantation is performed on the active region with the dielectric protection ring and the second gate dielectric layer as self-alignment conditions to form the anti-JFET region; The anti-JFET region is used to increase the first-conductive-type doping concentration of the first-conductive-type doped region and to reduce the JFET effect; The anti-JFET region is used to compensate the second-conductivity-type doping impurities of the first well region of the active region surface area, so as to reduce the influence of the first well region on the second-conductivity-type doping of the active region surface area, and make the second-conductivity-type doping of the channel region determined by the second well region.

17. The method of fabricating a superjunction device of claim 16, wherein: The fourth step further comprises: performing ion implantation of first-conductivity-type heavy doping in the active region to form a source region with the first side of the planar gate structure as a self-alignment condition.

18. The method of fabricating a super junction device of claim 16, wherein: In the lateral direction, the first well region covers at least a center position of the second-conductivity-type pillar and a width of the first well region on both sides of the center position of the second-conductivity-type pillar is greater than 0.2 microns; or the first well region covers a width of the second-conductivity-type pillar and the width is greater than 1 micron. In the longitudinal direction, a depth of the first well region is 1-2 microns; or the depth of the first well region is greater than 2 microns.

19. The method of fabricating a superjunction device of claim 18, wherein: When the depth of the first well region is 1-2 microns, the dielectric protection ring is composed of a thermal oxide layer formed by a thermal oxidation process or is composed of a thermal oxide layer formed by a thermal oxidation process and a deposited dielectric layer formed by a deposition process; the thermal oxide layer of the dielectric protection ring causes consumption of the surface of the semiconductor substrate, and the surface area of the first well region is removed in the dielectric protection ring removal process of the active region; the doping concentration of the removed surface area of the first well region is higher than that of the bottom reserved area, so as to improve the consistency of the device. When the depth of the first well region is greater than 2 microns, the dielectric protection ring is composed of a thermal oxide layer formed by a thermal oxidation process or is composed of a thermal oxide layer formed by a thermal oxidation process and a deposited dielectric layer formed by a deposition process or is composed of a deposited dielectric layer formed by a deposition process; the deposited dielectric layer of the dielectric protection ring reduces the thermal process of the device, so as to reduce the specific on-resistance of the device.

20. The method of fabricating a superjunction device of claim 18, wherein: The second-conductivity-type ring is formed in the transition region, and the first well region and the second-conductivity-type ring are simultaneously formed by using the same process.

21. The method of fabricating a super junction device of claim 12, wherein: The semiconductor substrate comprises a silicon substrate. A first-conductivity-type doped first epitaxial layer is formed on the surface of the semiconductor substrate. The second-conductivity-type pillar is composed of a second-conductivity-type doped second epitaxial layer filled in a trench. The first-conductivity-type pillar is composed of the first epitaxial layer between the second-conductivity-type pillars. The distance between the bottom surface of the second-conductivity-type pillar and the top surface of the semiconductor substrate is greater than 5 microns, so as to improve the body diode characteristics of the device. The first gate dielectric layer comprises a gate oxide layer. The first gate conductive material layer comprises a polysilicon gate.

22. The method of fabricating a super junction device of claim 16, wherein: Before the third step, after the anti-JFET region is formed, the surface of the second-conductivity-type doped region in the covered area is inverted to first-conductivity-type doping by the anti-JFET region.

23. The method of fabricating a superjunction device of any of claims 12 to 22, wherein: The super-junction device comprises a super-junction MOSFET or a super-junction IGBT.

24. The method of fabricating a superjunction device of claim 23, wherein: The super-junction device is an N-type device, the first conductivity type is N type, and the second conductivity type is P type; or, the super-junction device is a P-type device, the first conductivity type is P type, and the second conductivity type is N type. The super-junction device is an N-type device, the first conductivity type is N type, and the second conductivity type is P type; or, the super-junction device is a P-type device, the first conductivity type is P type, and the second conductivity type is N type.

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