A planar structure ultra-low capacitance bidirectional TVS structure

Abstract

The application discloses a kind of plane structure ultra-low capacitance bidirectional TVS structure, belong to field, including substrate layer, first epitaxial layer, second epitaxial layer, P well, N1 area, N2 area, N3 area, N4 area, P1 area, P2 area, P3 area, isolation groove, metal layer, passivation layer and dielectric layer;First epitaxial layer is located on substrate layer, second epitaxial layer is located on first epitaxial layer;P well is formed in second epitaxial layer, P1 area and P2 area, N1 area and N2 area are all formed in second epitaxial layer;P3 area, N3 area and N4 area are all formed in P well;Isolation groove penetrates first epitaxial layer and second epitaxial layer, and its bottom is in substrate layer;Dielectric layer is covered on the surface of second epitaxial layer, and opening is provided on N+ area and P+ area, N1 area and P2 area, N2 area and N3 area, N4 area and P3 area are all connected by metal layer;Passivation layer covers the dielectric layer and part of metal layer.In the application, TVS module uses flyback structure, greatly reduces clamping voltage and leakage parameter, and improves the overall overcurrent capacity of chip.

Description

Technical Field

[0001] The present invention relates to the technical field of surge protection devices, and in particular to a planar ultra-low capacitance bidirectional TVS structure. Background Art

[0002] With the rapid development of communication technology, transmission speeds are increasing. Currently, the widely used USB 3.0 and USB 3.1 interfaces have theoretical transmission speeds reaching or exceeding 5.0 Gbps. As chips commonly used for ESD protection in interfaces, applications have placed higher requirements on the parasitic capacitance parameters of TVS chips to avoid data loss and ensure proper circuit operation, as well as their surge protection capabilities.

[0003] The currently more commonly used ultra-low capacitance TVS structure is generally a vertical structure processed by a buried layer plus high-resistance epitaxial method. This has great constraints on the overall process difficulty and processing cycle. The increased difficulty in controlling the secondary epitaxial process will also affect the device performance. Summary of the Invention

[0004] The object of the present invention is to provide a planar ultra-low capacitance bidirectional TVS structure to realize an ultra-low capacitance TVS device with a low clamping voltage.

[0005] To solve the above technical problems, the present invention provides a planar ultra-low capacitance bidirectional TVS structure, including a substrate layer, a first epitaxial layer, a second epitaxial layer, a P well, an N1 region, an N2 region, an N3 region, an N4 region, a P1 region, a P2 region, a P3 region, an isolation trench, a metal layer, a passivation layer and a dielectric layer;

[0006] The first epitaxial layer is located on the substrate layer, and the second epitaxial layer is located on the first epitaxial layer;

[0007] The P well is formed in the second epitaxial layer, the P1 region and the P2 region, the N1 region and the N2 region are all formed in the second epitaxial layer; the P3 region, the N3 region and the N4 region are all formed in the P well;

[0008] The isolation trench penetrates the first epitaxial layer and the second epitaxial layer, and the bottom of the isolation trench is located in the substrate layer;

[0009] The dielectric layer covers the surface of the second epitaxial layer and is provided with openings on the N+ region and the P+ region. The N1 region and the P2 region, the N2 region and the N3 region, and the N4 region and the P3 region are all connected through a metal layer; the passivation layer covers the dielectric layer and part of the metal layer.

[0010] In one embodiment, the substrate layer is a P-type lightly doped material with a resistivity of 50-3000 ohm.cm, which is obtained by doping boron into silicon material.

[0011] In one embodiment, the first epitaxial layer is a heavily doped N-type epitaxial layer, and the second epitaxial layer is a lightly doped N-type epitaxial layer.

[0012] In one embodiment, the conductivity type of the P-well is P-type, the implanted element is boron, the implanted dose is 1.0E13-5.0E14, and the diffusion temperature is 1000° C.-1200° C.

[0013] In one embodiment, the N1 region, the N2 region, the N4 region and the N5 region are the same, the implanted element is phosphorus or arsenic, the implantation dose is 1.0E15-1.0E16, and the diffusion temperature is 900°C-1150°C.

[0014] In one embodiment, the P1 region, the P2 region, and the P3 region are the same, the implanted element is boron, the implanted dose is 1.0E15-1.0E16, and the diffusion temperature is 900° C.-1150° C.

[0015] In one embodiment, the isolation trench is filled with an electrically insulating medium having a width of 0.5-2.0 um and a depth of 5-30 um, which penetrates the first epitaxial layer and the second epitaxial layer to reach the substrate layer, thereby achieving physical isolation of each module through the isolation trench.

[0016] In one embodiment, the dielectric layer is SiO2 or Si3N4 or a combination thereof; the passivation layer is SiO2 or Si3N4 or a combination thereof.

[0017] In one embodiment, the metal layer is a conductive material with a thickness of 2-5 μm, using AlSiCu or Al, and Ti or Ti / TiN is pre-deposited on the interface with the semiconductor.

[0018] In the planar ultra-low capacitance bidirectional TVS structure provided by the present invention, the structure eliminates the buried layer processing process by designing the epitaxial wafer surface junction, making the overall design simpler and significantly reducing the process difficulty. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 It is a cross-sectional schematic diagram of a planar ultra-low capacitance bidirectional TVS structure provided by the present invention.

[0020] Figure 2 This is a schematic diagram of the electrical connection of a planar ultra-low capacitance bidirectional TVS structure provided by the present invention.

[0021] Figure 3 is a I-V curve schematic diagram of a planar structure ultra-low capacitance bidirectional TVS structure provided by the present application. DETAILED DESCRIPTION

[0022] The present application provides a planar structure ultra-low capacitance bidirectional TVS structure, which is further described in detail below in combination with the drawings and specific embodiments. The advantages and features of the present application will be more apparent according to the following description. It should be noted that the drawings are very simplified and use non-precise proportions, which are only used to facilitate and clarify the purpose of assisting the description of the embodiments of the present application.

[0023] The present application provides a planar structure ultra-low capacitance bidirectional TVS structure, which is further described in detail below in combination with the drawings and specific embodiments. The advantages and features of the present application will be more apparent according to the following description. It should be noted that the drawings are very simplified and use non-precise proportions, which are only used to facilitate and clarify the purpose of assisting the description of the embodiments of the present application. Figure 1 The present application provides a planar structure ultra-low capacitance bidirectional TVS structure, which is further described in detail below in combination with the drawings and specific embodiments. The advantages and features of the present application will be more apparent according to the following description. It should be noted that the drawings are very simplified and use non-precise proportions, which are only used to facilitate and clarify the purpose of assisting the description of the embodiments of the present application.

[0024] The substrate layer is a P-type lightly doped material with a resistivity of 50-3000 ohm.cm, and is made by doping the silicon material with boron. The first epitaxial layer is a heavily doped N-type epitaxial layer, and the second epitaxial layer is a lightly doped N-type epitaxial layer. The conductivity type of the P-well is P-type, the implanted element is boron, the implantation dose is 1.0E13-5.0E14, and the diffusion temperature is 1000°C-1200°C. The conductivity type of the N+ region is N-type, the implanted element is phosphorus or arsenic, the implantation dose is 1.0E15-1.0E16, and the diffusion temperature is 900°C-1150°C. The conductivity type of the P+ region is P-type, the implanted element is boron, the implantation dose is 1.0E15-1. 0E16, the diffusion temperature is 900℃-1150℃; the isolation groove is filled with an electrically insulating dielectric with a width of 0.5-2.0um and a depth of 5-30um, penetrating the first epitaxial layer and the second epitaxial layer to reach the substrate layer, and the physical isolation of each module is achieved through the isolation groove; the dielectric layer is SiO2 or Si3N4 or a combination of the two; the metal layer is a conductive material with a thickness of 2-5um, using AlSiCu or Al, and Ti or Ti / TiN is pre-deposited on the semiconductor contact interface; the N1 region and the P2 region are connected to form a positive electrode through a metal layer, and the P1 region is connected to the P3 region and the N4 region through a metal layer to form a negative electrode, and the metal wiring of each region is connected as follows Figure 2 As shown; the passivation layer is SiO2 or Si3N4 or a combination of the two.

[0025] The IV curve of the planar ultra-low capacitance bidirectional TVS structure of the present invention is as follows: Figure 3 As shown in the figure, the TVS module uses a flyback structure, which can significantly reduce the clamping voltage and leakage parameters, and improve the overall overcurrent capability of the chip; the process adopts a repeated unit structure, and the interpolation index can be designed according to the parameter requirements, which can meet the parameter requirements of various chips.

[0026] The above description is only a description of the preferred embodiments of the present invention and does not limit the scope of the present invention. Any changes and modifications made by ordinary technicians in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A planar ultra-low capacitance bidirectional TVS structure, characterized in that: It includes a substrate layer, a first epitaxial layer, a second epitaxial layer, a P well, an N1 region, an N2 region, an N3 region, an N4 region, a P1 region, a P2 region, a P3 region, an isolation trench, a metal layer, a passivation layer and a dielectric layer; The first epitaxial layer is located on the substrate layer, and the second epitaxial layer is located on the first epitaxial layer; The P well is formed in the second epitaxial layer, the P1 region and the P2 region, the N1 region and the N2 region are all formed in the second epitaxial layer; the P3 region, the N3 region and the N4 region are all formed in the P well; The isolation trench penetrates the first epitaxial layer and the second epitaxial layer, and the bottom of the isolation trench is located in the substrate layer; The dielectric layer covers the surface of the second epitaxial layer and is provided with openings on the N+ region and the P+ region. The N1 region and the P2 region, the N2 region and the N3 region, and the N4 region and the P3 region are all connected through a metal layer; the passivation layer covers the dielectric layer and part of the metal layer.

2. The planar ultra-low capacitance bidirectional TVS structure according to claim 1, wherein: The substrate layer is a P-type lightly doped material with a resistivity of 50-3000 ohm.cm, and is obtained by doping boron into silicon material.

3. The planar ultra-low capacitance bidirectional TVS structure according to claim 1, wherein: The first epitaxial layer is a heavily doped N-type epitaxial layer, and the second epitaxial layer is a lightly doped N-type epitaxial layer.

4. The planar ultra-low capacitance bidirectional TVS structure according to claim 1, wherein: The conductivity type of the P-well is P-type, the implanted element is boron, the implanted dose is 1.0E13-5.0E14, and the diffusion temperature is 1000° C.-1200° C.

5. The planar ultra-low capacitance bidirectional TVS structure according to claim 1, wherein: The N1 region, the N2 region, the N4 region and the N5 region are the same, the implanted element is phosphorus or arsenic, the implantation dose is 1.0E15-1.0E16, and the diffusion temperature is 900°C-1150°C.

6. The planar ultra-low capacitance bidirectional TVS structure according to claim 1, wherein: The P1 region, the P2 region and the P3 region are the same, the implanted element is boron, the implanted dose is 1.0E15-1.0E16, and the diffusion temperature is 900° C.-1150° C.

7. The planar ultra-low capacitance bidirectional TVS structure according to claim 1, wherein: The isolation trench is filled with an electrical insulating medium with a width of 0.5-2.0 um and a depth of 5-30 um, which penetrates the first epitaxial layer and the second epitaxial layer to reach the substrate layer, and the physical isolation of each module is achieved through the isolation trench.

8. The planar ultra-low capacitance bidirectional TVS structure according to claim 1, wherein: The dielectric layer is SiO2 or Si3N4 or a combination of the two; the passivation layer is SiO2 or Si3N4 or a combination of the two.

9. The planar ultra-low capacitance bidirectional TVS structure according to claim 1, wherein: The metal layer is a conductive material with a thickness of 2-5 μm, using AlSiCu or Al, and Ti or Ti / TiN is pre-deposited on the interface with the semiconductor.

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