Boron arsenide resonant tunneling diode and manufacturing method thereof

Abstract

The present invention discloses a boron arsenide resonant tunneling diode, which primarily addresses the problems of existing gallium nitride resonant tunneling diodes, such as asymmetric band structures, lack of bidirectionally symmetrical differential negative resistance characteristics, and low peak current and peak-to-valley current ratios. The device comprises a substrate, an epitaxial layer, an emitter ohmic contact layer, a first isolation layer, a first barrier layer, a quantum well layer, a second barrier layer, a second isolation layer, a collector ohmic contact layer, and a collector; a ring-shaped emitter is disposed on the emitter ohmic contact layer. The first and second barrier layers are made of boron arsenide material of equal thickness, the emitter and collector ohmic contact regions are made of n-type boron gallium indium arsenide material of equal composition and thickness, the first and second isolation layers and the quantum well layer are made of boron gallium indium arsenide material of equal composition, and the substrate is a high-thermal-conductivity boron arsenide single crystal. The device has no spontaneous polarization effect and exhibits bidirectionally symmetrical differential negative resistance, with a high peak current and peak-to-valley current ratio. It can be used in terahertz wave sources and digital logic circuits.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor devices, and in particular relates to a boron arsenide resonant tunneling diode, which can be used in high-frequency terahertz wave sources and high-speed digital logic circuits. Background Art

[0002] A resonant tunneling diode is a high-speed nanoelectronic device that uses the quantum physics mechanism of resonant tunneling to achieve differential negative resistance, thereby enabling operation in the terahertz band. It has enormous application potential in terahertz radar, broadband communications, digital logic, and storage circuits. Current resonant tunneling diodes are typically made of GaAs or GaN materials. Due to limitations in GaAs material performance, the output power of GaAs-based resonant tunneling diodes is only a few microwatts, which cannot meet the output power requirements of practical applications. Compared to GaAs, GaN materials have significant advantages in bandgap width, saturated electron velocity, breakdown field strength, and high-temperature resistance. Theoretically, resonant tunneling diodes with milliwatt or even watt-level output power can be achieved.

[0003] Conventional GaN resonant tunneling diode structures, such as Figure 1 As shown, it includes substrate, GaN epitaxial layer, n + GaN emitter ohmic contact layer, first GaN isolation layer, first AlGaN barrier layer, GaN quantum well layer, second AlGaN barrier layer, second GaN isolation layer, n + GaN collector ohmic contact layer and collector electrode, in n + A ring-shaped emitter electrode is provided on the GaN emitter ohmic contact layer. This type of GaN-based resonant tunneling diode has a relatively low oscillation frequency and peak current. Furthermore, the spontaneous polarization effect generated by the nitride material's non-centrosymmetric structure leads to an asymmetric device band structure, creating a charge accumulation region on the emitter side and a wide depletion region on the collector side. Consequently, the device has low peak-to-valley current and cannot achieve the differential negative resistance effect of bidirectional symmetric tunneling.

[0004] In order to obtain high peak current and improve peak-to-valley current ratio, patent document No. 202110335747.2 discloses a ScAlN / GaN double-barrier resonant tunneling diode and its manufacturing method, which improves the conventional GaN-based resonant tunneling diode. The structure is as follows Figure 2 As shown, the device includes a substrate, GaN Epitaxial layer, n + GaN emitter ohmic contact layer, GaN isolation layer, first ScAlN barrier layer, GaN quantum well layer, second ScAlN barrier layer, InN isolation layer, n + InN collector ohmic contact layer and collector electrode, in n+ A ring-shaped emitter electrode is provided on the GaN emitter ohmic contact layer. However, this device still has the following shortcomings:

[0005] First, GaN and ScAlN materials have a strong spontaneous polarization effect. The energy band in the GaN quantum well tilts due to the polarization effect, forming a ladder barrier together with the emitter barrier. Electrons tunneling from the emitter need to pass through this ladder barrier, which increases the thickness of the emitter effective barrier. This not only causes the emitter barrier transmission coefficient to decrease, but also causes the total transmission coefficient and the device peak current and peak-to-valley current ratio to decrease, and it is difficult to achieve a dual-region differential negative resistance characteristic. At the same time, the spontaneous polarization effect will cause the device energy band to be asymmetric, resulting in a depletion region on the collector side of the resonant tunneling diode, which reduces the reverse bias electron tunneling probability and greatly weakens the differential negative resistance characteristic under reverse bias, making it difficult to achieve a bidirectional symmetric differential negative resistance characteristic.

[0006] Second, since ScAlN is a transition metal nitride material, it is not compatible with the growth pattern of GaN materials when grown using molecular beam epitaxy, resulting in a rough and uneven interface of the ScAlN / GaN / ScAlN double-barrier quantum well. The high-density dislocations in the active region of the device act as scattering centers and leakage channels, ultimately reducing the peak current of the device, increasing the valley current, and degrading the differential negative resistance effect. At the same time, the discrete energy levels in the quantum well will generate a large peak voltage, resulting in high power consumption of the device. Summary of the Invention

[0007] The purpose of the present invention is to address the deficiencies of the above-mentioned existing technologies and propose a boron arsenide resonant tunneling diode and a method for manufacturing the same, so as to eliminate the spontaneous polarization effect, weaken the charge accumulation region on the emitter side, reduce the charge depletion region on the collector side, and realize and enhance the symmetric characteristics of bidirectional resonant tunneling.

[0008] To achieve the above object, the technical solution of the present invention is implemented as follows:

[0009] 1. A boron arsenide resonant tunneling diode, comprising, from bottom to top, a substrate, an epitaxial layer, an emitter ohmic contact layer, a first isolation layer, a first barrier layer, a quantum well layer, a second barrier layer, a second isolation layer, a collector ohmic contact layer, and a collector electrode, wherein both sides of the first isolation layer are annular emitter electrodes, and a passivation layer is wrapped around the epitaxial layer to the collector electrode, characterized in that:

[0010] The substrate is made of boron arsenide single crystal material with high thermal conductivity to improve the heat dissipation performance of the device;

[0011] The epitaxial layer is made of BAs material;

[0012] The first barrier layer and the second barrier layer are made of BAs material with the same thickness;

[0013] The quantum well layer uses B x Ga y In z As material, where 0 < x < 1, 0 ≤ y < 1, 0 ≤ z < 1, and x + y + z = 1;

[0014] The first isolation layer and the second isolation layer use B with the same composition and the same thickness x Ga y In z As, where 0 < x < 1, 0 ≤ y < 1, 0 ≤ z < 1, and x + y + z = 1;

[0015] The emitter ohmic contact layer and the collector ohmic contact layer use n-type B with the same composition, the same thickness, and a doping concentration of 1×10 19 cm -3 -5×10 20 cm -3 between x Ga y In z As, where 0 < x < 1, 0 ≤ y < 1, 0 ≤ z < 1, and x + y + z = 1.

[0016] Furthermore, the thickness of the epitaxial layer is 1000 nm - 6000 nm.

[0017] Furthermore, the thicknesses of the first barrier layer, the quantum well layer, and the second barrier layer are all 1 nm - 3 nm.

[0018] Furthermore, the thicknesses of the first isolation layer and the second isolation layer are all 4 nm - 20 nm.

[0019] Furthermore, the thicknesses of the emitter ohmic contact layer and the collector ohmic contact layer are all 50 nm - 200 nm.

[0020] Furthermore, the passivation layer uses any one of SiN material, Al2O3 material, and HfO2 material.

[0021] 2. A manufacturing method of a boron arsenide resonant tunneling diode, characterized by comprising the following steps:

[0022] 1) Use chemical vapor transport method to epitaxially grow a 1000 nm - 6000 nm BAs epitaxial layer on a boron arsenide substrate;

[0023] 2) Use chemical vapor transport method to grow a layer with a thickness of 50 nm - 200 nm and a doping concentration of 1×10 19 cm -3 -5×10 20 cm -3n-type B x Ga y In z As emitter ohmic contact layer;

[0024] 3) Using chemical vapor transport method in n-type B x Ga y In z A B with a thickness of 4nm-20nm is grown on the As emitter ohmic contact layer. x Ga y In z As the first isolation layer;

[0025] 4) Using chemical vapor transport method in B x Ga y In z A first BAs barrier layer with a thickness of 1 nm to 3 nm is grown on the first As isolation layer;

[0026] 5) Using chemical vapor transport to grow B with a thickness of 1nm-3nm on the first BAs barrier layer x Ga y In z As quantum well layer;

[0027] 6) Using chemical vapor transport method in B x Ga y In z A second BAs barrier layer with a thickness of 1nm-3nm is grown on the As quantum well layer;

[0028] 7) Using chemical vapor transport to grow B with a thickness of 4nm-20nm in the second BAs barrier layer x Ga y In z As the second isolation layer;

[0029] 8) Using chemical vapor transport method in B x Ga y In Z The second As isolation layer is grown with a thickness of 50nm-200nm and a doping concentration of 1×10 19 cm -3 -5×10 20 cm -3 n-type B x Ga y In z As collector ohmic contact layer;

[0030] 9) Using a photolithography process to form a mesa isolation pattern on the collector ohmic contact layer; then using the photoresist as a mask, using an inductively coupled plasma etching process to etch along the mask 300nm-600nm to form a circular mesa isolation shallow trench from the collector ohmic contact layer to the BAs epitaxial layer;

[0031] 10) Using a photolithography process, a circular pattern is formed on the collector ohmic contact layer, and a Ti / Au / Ni metal layer is evaporated on the circular pattern using a photoresist as a mask to form a collector;

[0032] 11) Using the collector metal as a mask, an inductively coupled plasma etching process is used to etch the emitter ohmic contact layer to form a cylindrical mesa with a diameter of 1 μm to 10 μm from the first isolation layer to the collector;

[0033] 12) using a photolithography process to form a ring-shaped emitter electrode pattern on the emitter ohmic contact layer outside the cylindrical mesa; then using the photoresist as a mask, using electron beam evaporation to evaporate a Ti / Au / Ni metal layer to form an emitter electrode on the electrode pattern;

[0034] 13) Depositing a passivation layer with a thickness of 50 nm to 300 nm on the entire upper surface of the epitaxial material using a plasma enhanced chemical vapor deposition method or an atomic layer deposition process;

[0035] 14) using a photolithography process to form a collector electrode through-hole pattern with a diameter of 0.5 μm to 9 μm on the cylindrical mesa passivation layer; then using a photoresist as a mask and using a reactive ion etching method to form a collector electrode through-hole on the cylindrical mesa passivation layer;

[0036] 15) using a photolithography process to form an emitter through-hole pattern on the passivation layer; then using a photoresist as a mask and using a reactive ion etching method to form an emitter electrode through-hole on the passivation layer;

[0037] 16) Using a photolithography process, an emitter pad pattern and a collector pad pattern are formed on the passivation layer; then, using the photoresist as a mask, an Au metal layer is evaporated on the pattern by electron beam evaporation to form an emitter pad and a collector pad interconnected with the emitter electrode and the collector electrode, respectively, to complete the device preparation.

[0038] Compared with the prior art, the present invention has the following advantages:

[0039] 1. The present invention adopts BAs as the double barrier layer in the active area, and utilizes the characteristics of no spontaneous polarization and high electron mobility of the BAs material itself to eliminate the quantum well band tilt, avoid the formation of a charge accumulation region in the emitter and a charge depletion region in the collector, increase the device emitter transmission coefficient and collector transmission coefficient, realize and enhance the symmetric characteristics of bidirectional resonant tunneling, and improve the device peak current and peak-to-valley current ratio.

[0040] 2. The present invention uses BAs material with a high saturation electron velocity for the double barrier layer in the active area, which can increase the peak current of the device. At the same time, since the quantum well layer uses BGaInAs material, the degree of freedom of device structure design can be increased by adjusting the composition of the quantum well layer, thereby achieving effective control of the differential negative resistance effect. In addition, the substrate uses BAs single crystal material with high thermal conductivity, which can significantly improve the heat dissipation characteristics of the device and reduce the junction temperature of the active area of ​​the device.

[0041] 3. Since the present invention adopts a material system without polarization effect, the discrete energy level spacing in the quantum well is small, which can achieve low peak voltage and device power consumption.

[0042] 4. The BAs material used in the first and second barrier layers of the present invention has a larger bandgap width and higher breakdown field strength than traditional GaAs materials, which can achieve regulation of quantum well depth in a wider range, thereby effectively reducing the non-resonant tunneling current component and improving the peak-to-valley current ratio and working reliability of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] Figure 1 This is a structural diagram of an existing gallium nitride resonant tunneling diode;

[0044] Figure 2 This is a structural diagram of an existing ScAlN / GaN double-barrier resonant tunneling diode;

[0045] Figure 3 is a structural diagram of a boron arsenide resonant tunneling diode of the present invention;

[0046] Figure 4 It is a schematic diagram of the process of manufacturing a boron arsenide-based resonant tunneling diode according to the present invention.

[0047] Specific implementation cases

[0048] Reference Figure 3 The boron arsenide resonant tunneling diode of the present invention includes a substrate 1, an epitaxial layer 2, an emitter ohmic contact layer 3, a first isolation layer 4, a first barrier layer 5, a quantum well layer 6, a second barrier layer 7, a second isolation layer 8, a collector ohmic contact layer 9, a collector electrode 10, an emitter electrode 11, and a passivation layer 12.

[0049] The substrate 1 is made of boron arsenide single crystal material with high thermal conductivity;

[0050] The epitaxial layer 2 is made of BAs material, which is located on the boron arsenide substrate 1 and has a thickness of 1000 nm - 6000 nm;

[0051] The emitter ohmic contact layer 3 is made of B 19 cm -3 -5×10 20 cm -3 doped Ga x Ga y In z As material with a component range of 0 < x < 1, 0 ≤ y < 1, 0 ≤ z < 1, and satisfying x + y + z = 1, and a thickness of 50 nm - 200 nm. The emitter ohmic contact layer 3 is located on the BAs epitaxial layer 2;

[0052] The first isolation layer 4 is made of B x Ga y In z [[ID=X]] x As material with a component range of 0 < x < 1, 0 ≤ y < 1, 0 ≤ z < 1, and a thickness of 4 nm - 20 nm, and is located on the emitter ohmic contact layer 3;

[0053] The first barrier layer 5 is made of BAs material, which is located on the first isolation layer 4 and has a thickness of 1 nm - 3 nm;

[0054] The quantum well layer 6 is B x Ga y In z As with a component range of 0 < x < 1, 0 ≤ y < 1, 0 ≤ z < 1, and satisfying x + y + z = 1, and a thickness of 1 nm - 3 nm, and is located on the first barrier layer 5;

[0055] The second barrier layer 7 is made of BAs material, which is located on the quantum well layer 6 and has a thickness of 1 nm - 3 nm; <X

[0056] The second isolation layer 8 is located on the second barrier layer 7 and is made of B x Ga y In z As material with the same composition and thickness as the first isolation layer 4;

[0057] The collector ohmic contact layer 9 is located on the second isolation layer 8 and is made of B x Ga y In z As material with the same composition, doping concentration, and thickness as the emitter ohmic contact layer 3;

[0058] The collector electrode 10 is located on the collector ohmic contact layer 9; It should be noted that there seems to be an error in the original text where the variable 'x' in the component range of some layers is repeated in the translation for simplicity. You may need to adjust it according to the actual situation. Also, the tag x is repeated in the original text, which might be a mistake.

[0059] The annular emitter electrode 11 is located outside the first isolation layer 4;

[0060] The passivation layer 12 is made of any one of SiN, Al 2 O 3 and HfO 2 materials, and has a thickness of 50 nm to 300 nm. The passivation layer 12 wraps around the entire upper surface of the epitaxial material from the first isolation layer 4 to the collector electrode 10 .

[0061] Reference Figure 4 The present invention provides the following three embodiments for making a boron arsenide resonant tunneling diode.

[0062] In the first embodiment, the first barrier layer and the second barrier layer are made of BAs on a boron arsenide single crystal substrate, and the first and second isolation layers and the quantum well layer are made of B 0.2 Ga 0.8 As boron arsenide resonant tunneling diode.

[0063] Step 1: grow the BAs epitaxial layer, such as Figure 4 (a).

[0064] A 1000 nm thick BAs epitaxial layer 2 was grown on a boron arsenide single crystal substrate 1 using chemical vapor transport. The process conditions were:

[0065] Iodine gas is used as the transmission agent, the ratio of high-purity boron to high-purity arsenic is 1:1.5, the temperature of the high-temperature zone is 880°C, and the crystallization temperature of the crystallization zone is 800°C.

[0066] Step 2: Grow n-type B 0.2 Ga 0.8 As emitter ohmic contact layer, such as Figure 4 (b).

[0067] Using chemical vapor transport, a 50 nm thick BAs epitaxial layer with a doping concentration of 1×10 19 cm -3 n-type B 0.2 Ga 0.8 As emitter ohmic contact layer 3, its process conditions are:

[0068] Iodine gas is used as a transmission agent, the ratio of high-purity boron, gallium, and arsenic source materials is 0.2:0.8:1.5, and a total amount of 1‰ of Si is added during the reaction. The temperature in the high-temperature zone is 880°C, and the crystallization temperature in the crystallization zone is 800°C.

[0069] Step 3: Growth B 0.2 Ga 0.8 As the first isolation layer, such as Figure 4 (c).

[0070] Using chemical vapor transport, in n-type B 0.2 Ga 0.8 As emitter ohmic contact layer 3 is grown with a thickness of 4nm B 0.2 Ga 0.8 As the first isolation layer 4, its process conditions are:

[0071] Iodine gas is used as a transmission agent, the ratio of high-purity boron, gallium, and arsenic source materials is 0.2:0.8:1.5, the temperature of the high-temperature zone is 880°C, and the crystallization temperature of the crystallization zone is 800°C.

[0072] Step 4: grow the first BAs barrier layer, such as Figure 4 (d).

[0073] Using chemical vapor transport, 0.2 Ga 0.8 The As first isolation layer 4 is grown into a first BAs barrier layer 5 with a thickness of 1 nm, and the process conditions are:

[0074] Iodine gas is used as the transmission agent, the ratio of high-purity boron to high-purity arsenic is 1:1.5, the temperature of the high-temperature zone is 880°C, and the crystallization temperature of the crystallization zone is 800°C.

[0075] Step 5: Growth B 0.2 Ga 0.8 As quantum well layer, such as Figure 4 (e).

[0076] Using chemical vapor transport, a 1 nm thick B layer is grown on the first BAs barrier layer 5. 0.2 Ga 0.8 The process conditions of the As quantum well layer 6 are as follows:

[0077] Iodine gas is used as a transmission agent, the ratio of high-purity boron, gallium, and arsenic source materials is 0.2:0.8:1.5, the temperature of the high-temperature zone is 880°C, and the crystallization temperature of the crystallization zone is 800°C.

[0078] Step 6: grow the second BAs barrier layer, such as Figure 4 (f).

[0079] Using chemical vapor transport, 0.2 Ga 0.8 A second BAs barrier layer 7 with a thickness of 1 nm is grown on the As quantum well layer 6, and the process conditions are as follows:

[0080] Iodine gas is used as the transmission agent, the ratio of high-purity boron to high-purity arsenic is 1:1.5, the temperature of the high-temperature zone is 880°C, and the crystallization temperature of the crystallization zone is 800°C.

[0081] Step 7: Growth B 0.2Ga 0.8 As the second isolation layer, such as Figure 4 (g).

[0082] A 4 nm thick B layer is grown on the second BAs barrier layer 7 using a chemical vapor transport method. 0.2 Ga 0.8 As the second isolation layer 8, its process conditions are:

[0083] Iodine gas is used as a transmission agent, the ratio of high-purity boron, gallium, and arsenic source materials is 0.2:0.8:1.5, the temperature of the high-temperature zone is 880°C, and the crystallization temperature of the crystallization zone is 800°C.

[0084] Step 8: Growth of n-type B 0.2 Ga 0.8 As collector ohmic contact layer, such as Figure 4 (h).

[0085] Using chemical vapor transport, 0.2 Ga 0.8 The As second isolation layer 8 is grown with a doping concentration of 1×10 19 cm -3 , n-type B with a thickness of 50nm 0.2 Ga 0.8 As collector ohmic contact layer 9, its process conditions are:

[0086] Iodine gas is used as a transmission agent, the ratio of high-purity boron, gallium, and arsenic source materials is 0.2:0.8:1.5, and the Si content added during the reaction is 1‰ of the total amount. The temperature in the high-temperature zone is 880°C, and the crystallization temperature in the crystallization zone is 800°C.

[0087] Step 9, in n-type B 0.2 Ga 0.8 The As collector ohmic contact layer 9 is subjected to photoresist coating, photolithography, development, and etching to form a grid-like mesa isolation with a depth of 300 nm. Figure 4 (i).

[0088] 9.1) Using photolithography to form mesa isolation patterns:

[0089] 9.1a) Spin-coat AZ5214 photoresist at a speed of 500 rad / min and an acceleration of 1000 rad. 2 / Spin coating for 3s at 1000 rad / min; then at a speed of 4000 rad / min and an acceleration of 2000 rad 2 Spin coating at 30 s / min, and then bake at 95 °C for 90 s;

[0090] 9.1b) Using photolithography, the n-type B 0.2 Ga 0.8Exposure treatment of AZ5214 photoresist on the As collector ohmic contact layer;

[0091] 9.1c) Develop the exposed photoresist using RZX-3038 developer for 45 seconds to form a grid-like mesa isolation pattern.

[0092] 9.2) Using an inductively coupled plasma etching process, using a photoresist mask and the grid-like mesa isolation pattern as a mask, etch the epitaxial material to form a grid-like circular mesa isolation shallow trench with a depth of 300 nm from the collector ohmic contact layer to the BAs epitaxial layer. The process conditions are:

[0093] The Cl2 gas flow rate is 10 sccm, the BCl3 gas flow rate is 25 sccm, and the etching time is 300 s.

[0094] Step 10, in n-type B 0.2 Ga 0.8 As collector ohmic contact layer 9 is formed on the collector, such as Figure 4 (j).

[0095] 10a1) In n-type B 0.2 Ga 0.8 Spin-coat PMMA A4 photoresist on the As collector ohmic contact layer: first spin at a speed of 500 rad / min and an acceleration of 1000 rad 2 / Spin coating for 3s at 1000 rad / min; then at a speed of 4000 rad / min and an acceleration of 2000 rad 2 Spin coating at 300 nm / min for 30 seconds, and then bake at 180°C for 90 seconds;

[0096] 10a2) using a photolithography process, setting an electron dose ratio of 750, and exposing the PMMA A4 photoresist;

[0097] 10a3) developing the exposed photoresist for 120 seconds using a solution of tetramethyl dipentyl ketone and isopropyl alcohol in a ratio of 3:1, and then fixing the exposed photoresist with isopropyl alcohol for 30 seconds to form a circular collector pattern having a diameter of 1 μm;

[0098] 10a4) Using electron beam evaporation method, on the collector pattern according to Ti / Au / Ni metals with thicknesses of 20 / 80 / 50 nm were evaporated at a rate and then soaked in acetone solution to form collector electrodes.

[0099] Step 11, etching the cylindrical mesa, such as Figure 4 (k).

[0100] Using the collector metal as a mask, an inductively coupled plasma etching process is used to etch the emitter ohmic contact layer to form a cylindrical mesa with a diameter of 1 μm from the first isolation layer to the collector.

[0101] The process conditions are: Cl2 gas flow rate is 10 sccm, BCl3 gas flow rate is 25 sccm, and etching time is 300 s.

[0102] Step 12: Make a ring emitter electrode, such as Figure 4 (l).

[0103] 12.1) In n-type B 0.2 Ga 0.8 Spin-coat AZ5214 photoresist on the As emitter ohmic contact layer 3, first at a speed of 500 rad / min and an acceleration of 1000 rad 2 / Spin coating at 4000 rad / min for 3s; then at a speed of 4000 rad / min and an acceleration of 2000 rad 2 Spin coating at 30 s / min, and then bake at 95 °C for 90 s;

[0104] 12.2) Using optical lithography, the n-type B 0.2 Ga 0.8 The AZ5214 photoresist on the As emitter ohmic contact layer 3 is exposed;

[0105] 12.3) The exposed photoresist is developed with RZX-3038 developer for 45 seconds to form a ring-shaped emitter electrode pattern whose inner circumference is 5 μm from the cylindrical mesa.

[0106] 12.4) Using electron beam evaporation, with the annular emitter electrode pattern as a mask, an n-type B 0.2 Ga 0.8 As emitter ohmic contact layer 3 according to Ti / Au metal with a thickness of 20 / 80 nm is evaporated at a rate of 100 nm and then immersed in acetone solution to form an emitter electrode 11, the inner circumference of which is 5 μm away from the cylindrical table.

[0107] Step 13: deposit a SiN passivation layer, such as Figure 4 (m).

[0108] A 300 nm thick SiN passivation layer 12 is deposited on the entire upper surface of the sample using plasma enhanced chemical vapor deposition. The process conditions are:

[0109] The time is 60s, the pressure is 2200mTorr, the temperature is 350℃, the SiH4 flow rate is 13.5sccm, the NH3 flow rate is 10sccm, and the N2 flow rate is 1000sccm.

[0110] Step 14: Prepare collector electrode through-holes on the passivation layer, such as Figure 4 (n).

[0111] 14.1) Photolithography to form collector electrode through-hole pattern:

[0112] 14.1a) Spin-coat PMMAA4 photoresist onto the SiN passivation layer 12, i.e., first spin-coat at a speed of 500 rad / min and an acceleration of 1000 rad. 2 / Spin coating at 4000 rad / min for 3s; then at a speed of 4000 rad / min and an acceleration of 2000 rad 2 Spin coating at 30 s / min, and then baking at 180 °C for 90 s;

[0113] 14.1b) Expose PMMA A4 photoresist using electron beam lithography, setting the electron dose ratio to 750.

[0114] 14.1c) The exposed photoresist is first developed with a 3:1 solution of tetramethyl dipentyl ketone and isopropyl alcohol for 120 seconds, followed by fixing with isopropyl alcohol for 30 seconds to form a collector electrode through-hole pattern.

[0115] 14.2) Using the photoresist as a mask, use reactive ion etching to etch the passivation layer down to the collector electrode metal surface, forming a collector electrode through-hole with a diameter of 0.5 μm. The process conditions are:

[0116] The pressure is 1500mTorr, the power is 200W, the SF6 flow rate is 8sccm, the CHF3 flow rate is 10sccm, and the He flow rate is 150sccm.

[0117] Step 15: Prepare an emitter electrode through hole on the passivation layer, such as Figure 4 (o).

[0118] 15.1) Photolithography to form emitter electrode through-hole pattern:

[0119] 15.1a) Spin-coat AZ5214 photoresist onto the passivation layer at a speed of 500 rad / min and an acceleration of 1000 rad. 2 / Spin coating at 4000 rad / min for 3s; then at a speed of 4000 rad / min and an acceleration of 2000 rad 2 The mixture was rotated at 3000 nm / min for 30 seconds and then dried at 95°C for 90 seconds.

[0120] 15.1b) Expose the AZ5214 photoresist on the passivation layer using conventional optical lithography.

[0121] 15.1c) Develop the exposed photoresist with RZX-3038 developer for 45 seconds to form a circular pattern with an inner diameter slightly smaller than the emitter electrode.

[0122] 15b) Reactive ion etching is used to etch the passivation layer to the metal surface of the emitter electrode using a photoresist as a mask to form an emitter electrode through hole. The process conditions are:

[0123] The pressure is 1500mTorr, the power is 200W, the SF6 flow rate is 8sccm, the CHF3 flow rate is 10sccm, and the He flow rate is 150sccm.

[0124] Step 16: Lead out the emitter electrode Pad and the collector electrode Pad through the emitter electrode through hole and the collector electrode through hole respectively, as shown in FIG. Figure 4 (p).

[0125] 16a) Photolithography to form emitter electrode metal Pad patterns and collector electrode metal Pad patterns:

[0126] 16a1) Spin-coat AZ5214 photoresist on the emitter and collector through-holes at a speed of 500 rad / min and an acceleration of 1000 rad. 2 / Spin coating at 4000 rad / min for 3s; then at a speed of 4000 rad / min and an acceleration of 2000 rad 2 Spin coating at 30 s / min, and then bake at 95 °C for 90 s;

[0127] 16a2) exposing the AZ5214 photoresist using a conventional optical lithography method;

[0128] 16a3) developing the exposed photoresist with RZX-3038 developer for 45 seconds to form an emitter electrode metal pad pattern and a collector electrode metal pad pattern;

[0129] 16b) Using electron beam evaporation, Ti / Au metal with a thickness of 20 / 80 nm is evaporated at a rate of , and then immersed in acetone to form an emitter electrode Pad and a collector electrode Pad interconnected with the emitter electrode and the collector electrode, respectively, to complete the device fabrication.

[0130] In the second embodiment, the first barrier layer and the second barrier layer are made of BAs on a boron arsenide single crystal substrate, and the first and second isolation layers and the quantum well layer are made of B 0.3 In 0.7 As boron arsenide resonant tunneling diode.

[0131] Step 1: grow a BAs epitaxial layer, such as Figure 4 (a).

[0132] A BAs epitaxial layer 2 with a thickness of 3000 nm was grown on a boron arsenide single crystal substrate 1 using a chemical vapor transport method, with iodine gas as the transport agent, a ratio of high-purity boron to high-purity arsenic of 1:1.5, a temperature of the high-temperature zone of 890°C, and a crystallization temperature of the crystallization zone of 810°C.

[0133] Step 2: Grow n-type B 0.3 In 0.7 As emitter ohmic contact layer, such as Figure 4 (b).

[0134] Iodine gas was used as the transport agent, the ratio of high-purity boron, indium, and arsenic source materials was 0.2:1:1.5, and 1.5‰ of Si was added during the reaction. The temperature of the high-temperature zone was 890℃, and the crystallization temperature of the crystallization zone was 810℃. A 100nm thick BAs epitaxial layer 2 was grown by chemical vapor transport with a doping concentration of 1×10 20 cm -3 n-type B 0.3 In 0.7 As emitter ohmic contact layer 3.

[0135] Step 3, growing B 0.3 In 0.7 As the first isolation layer, such as Figure 4 (c).

[0136] Iodine gas was used as the transport agent, the ratio of high-purity boron, indium, and arsenic source materials was 0.2:1:1.5, the temperature of the high-temperature zone was 890°C, and the crystallization temperature of the crystallization zone was 810°C. Chemical vapor transport was used to prepare n-type B 0.3 In 0.7 A 10 nm thick B is grown on the As emitter ohmic contact layer 3. 0.3 In 0.7 As first isolation layer 4.

[0137] Step 4, grow the first BAs barrier layer, such as Figure 4 (d).

[0138] Iodine gas was used as the transport agent, the ratio of high-purity boron to high-purity arsenic was 1:1.5, the temperature of the high-temperature zone was 890°C, and the crystallization temperature of the crystallization zone was 810°C. 0.3 In 0.7 A first BAs barrier layer 5 with a thickness of 2 nm is grown on the first As isolation layer 4 .

[0139] Step 5, Growth B 0.3 In 0.7 As quantum well layer, such as Figure 4 (e).

[0140] Iodine gas was used as the transport agent, the ratio of high-purity boron, indium, and arsenic source materials was 0.2:1:1.5, the temperature of the high-temperature zone was 890°C, and the crystallization temperature of the crystallization zone was 810°C. A B with a thickness of 2 nm was grown on the first BAs barrier layer 5 using chemical vapor transport. 0.3 In 0.7 As quantum well layer 6.

[0141] Step 6: grow the second BAs barrier layer, such as Figure 4 (f).

[0142] Iodine gas was used as the transport agent, the ratio of high-purity boron to high-purity arsenic was 1:1.5, the temperature of the high-temperature zone was 890°C, and the crystallization temperature of the crystallization zone was 810°C. 0.3 In 0.7 A second BAs barrier layer 7 with a thickness of 2 nm is grown on the As quantum well layer 6 .

[0143] Step 7, Growth B 0.3 In 0.7 As the second isolation layer, such as Figure 4 (g).

[0144] Iodine gas is used as a transport agent, the ratio of high-purity boron, indium, and arsenic source materials is 0.2:1:1.5, the temperature of the high-temperature zone is 890°C, and the crystallization temperature of the crystallization zone is 810°C. A B with a thickness of 10 nm is grown on the second BAs barrier layer 7 using chemical vapor transport. 0.3 In 0.7 As second isolation layer 8.

[0145] Step 8: Grow n-type B 0.3 In 0.7 As collector ohmic contact layer, such as Figure 4 (h).

[0146] Iodine gas was used as the transport agent, the ratio of high-purity boron, indium, and arsenic source materials was 0.2:1:1.5, and 1.5‰ of Si was added during the reaction. The temperature of the high-temperature zone was 890℃, and the crystallization temperature of the crystallization zone was 810℃. The chemical vapor transport method was used to prepare the B 0.3 In 0.7 The As second isolation layer 8 is grown with a thickness of 100 nm and a doping concentration of 1×10 20 cm -3 n-type B 0.3 In 0.7 As collector ohmic contact layer 9.

[0147] Step 9, in n-type B0.3 In 0.7 The As collector ohmic contact layer is formed by photolithography, development and etching to form a grid-like mesa isolation shallow groove with a depth of 500nm. Figure 4 (i).

[0148] 9a) Using photolithography to form mesa isolation patterns:

[0149] The specific implementation of this step is the same as step 9.1) of Example 1.

[0150] 9b) Etching to form mesa isolation:

[0151] The n-type B was etched by inductively coupled plasma etching with photoresist as mask and Cl2 gas flow rate of 10 sccm and BCl3 gas flow rate of 25 sccm. 0.3 In 0.7 From the As collector ohmic contact layer to the BAs epitaxial layer, a grid-like circular mesa isolation shallow trench with a depth of 500nm is formed.

[0152] Step 10, in n-type B 0.3 In 0.7 As collector ohmic contact layer is formed on the collector, such as Figure 4 (j).

[0153] 10a) In n-type B 0.3 In 0.7 PMMA A4 photoresist was spin-coated twice on the AS collector ohmic contact layer: the first time at a speed of 500 rad / min and an acceleration of 1000 rad 2 / Spin coating for 3s at 1000 rad / min; the second time at a speed of 4000 rad / min and an acceleration of 2000 rad 2 Spin coating at 300 nm / min for 30 seconds, and then bake at 180°C for 90 seconds;

[0154] 10b) using a photolithography process, setting an electron dose ratio of 750, and exposing the PMMA A4 photoresist;

[0155] 10c) The exposed photoresist is first developed with a solution of tetramethyl dipentyl ketone and isopropyl alcohol in a ratio of 3:1 for 120 seconds, and then fixed with isopropyl alcohol for 30 seconds to form a circular collector pattern with a diameter of 5 μm.

[0156] 10d) Using electron beam evaporation method, on the collector pattern according to Ti / Au / Ni metals with thicknesses of 20 / 80 / 50 nm were evaporated at a rate and then soaked in acetone solution to form collector electrodes.

[0157] Step 11, etching to form a cylindrical mesa with a diameter of 5 μm from the collector to the first isolation layer, as shown in FIG. Figure 4 (k).

[0158] The collector electrode was used as a mask, and the process conditions of Cl2 gas flow rate was set to 10 sccm, BCl3 gas flow rate was set to 25 sccm, and etching time was set to 150 s. The inductively coupled plasma etching method was used to etch the n-type B 0.3 In 0.7 As emitter ohmic contact layer, forming a cylindrical mesa with a diameter of 5 μm.

[0159] Step 12, in n-type B 0.3 In 0.7 A ring-shaped emitter electrode with an inner circumference of 8 μm from the cylindrical table is formed on the As emitter ohmic contact layer. Figure 4 (l).

[0160] The specific implementation of this step is the same as step 12 of the first embodiment.

[0161] Step 13, depositing an Al2O3 dielectric passivation layer, such as Figure 4 (m).

[0162] An atomic layer deposition process was used with the following process conditions: time of 40s, pressure of 2000mTorr, temperature of 300℃, Al(CH3)3 flow rate of 850sccm, H2O flow rate of 350sccm, and N2 flow rate of 1000sccm. A 100nm thick Al2O3 dielectric passivation layer was deposited on the entire surface of the sample.

[0163] Step 14: Prepare a collector electrode through hole with a diameter of 4 μm on the Al2O3 dielectric passivation layer, as shown in FIG. Figure 4 (n).

[0164] 14a) Photolithography to form collector electrode through-hole pattern:

[0165] The specific implementation of this step is the same as step 14.1) of Example 1.

[0166] 14b) Etching to form collector electrode through-holes:

[0167] Using photoresist as a mask, reactive ion etching method was adopted with the process conditions of pressure of 1500mTorr, power of 200W, SF6 flow rate of 8sccm, CHF3 of 10sccm, and He flow rate of 150sccm to etch the Al2O3 dielectric passivation layer to the collector electrode metal surface, forming a collector electrode through hole with a diameter of 4μm.

[0168] Step 15, prepare an emitter electrode through hole on the Al2O3 dielectric passivation layer, such as Figure 4 (o).

[0169] 15a) Photolithography to form emitter electrode through-hole pattern:

[0170] The specific implementation of this step is the same as step 15.1) of Example 1.

[0171] 15b) Etching to form an emitter electrode through hole

[0172] Using photoresist as a mask, reactive ion etching method is adopted with the process conditions of pressure of 1500mTorr, power of 200W, SF6 flow rate of 8sccm, CHF3 of 10sccm, and He flow rate of 150sccm to etch the Al2O3 dielectric passivation layer to the metal surface of the emitter electrode to form an emitter electrode through hole.

[0173] Step 16: Lead out the emitter electrode Pad and the collector electrode Pad on the emitter electrode through hole and the collector electrode through hole respectively, and complete the device manufacturing, such as Figure 4 (p).

[0174] The specific implementation of this step is the same as step 16 of the first embodiment.

[0175] In the third embodiment, the first barrier layer and the second barrier layer are made of BAs, the first and second isolation layers, and the quantum well layer are made of B on a boron arsenide single crystal substrate. 0.1 Ga 0.7 In 0.2 As Boron Arsenide-based resonant tunneling diode.

[0176] Step A, growing a BAs epitaxial layer, such as Figure 4 (a).

[0177] A BAs epitaxial layer 2 with a thickness of 6000 nm was grown on a boron arsenide single crystal substrate 1 using chemical vapor transport, with iodine gas as the transport agent, a ratio of high-purity boron to high-purity arsenic of 1:1.5, a temperature of 900°C in the high-temperature zone, and a crystallization temperature of 820°C in the crystallization zone.

[0178] Step B, growing n-type B 0.1 Ga 0.7 In 0.2 As emitter ohmic contact layer, such as Figure 4 (b).

[0179] The chemical vapor transport method was used. Under the following process conditions, iodine gas was used as the transport agent, the ratio of high-purity boron, gallium, indium, and arsenic source materials was 0.2:1:0.4:1.5, and 2‰ of Si was doped during the reaction. The temperature of the high-temperature zone was 900℃, and the crystallization temperature of the crystallization zone was 820℃. A 200nm thick BAs epitaxial layer with a doping concentration of 5×10 20 cm -3 n-type B 0.1 Ga 0.7 In 0.2 As emitter ohmic contact layer 3.

[0180] Step C, Growth B 0.1 Ga 0.7 In 0.2 As the first isolation layer, such as Figure 4 (c).

[0181] Using chemical vapor transport, with iodine gas as the transport agent, the ratio of high-purity boron, gallium, indium, and arsenic source materials is 0.2:1:0.4:1.5, the temperature of the high temperature zone is 900℃, and the crystallization temperature of the crystallization zone is 820℃, the process conditions are as follows: 0.1 Ga 0.7 In 0.2 A 20 nm thick B is grown on the As emitter ohmic contact layer 3. 0.1 Ga 0.7 In 0.2 As first isolation layer 4.

[0182] Step D, growing the first BAs barrier layer, such as Figure 4 (d).

[0183] Using chemical vapor transport method, with iodine gas as the transmission agent, the ratio of high-purity boron to high-purity arsenic is 1:1.5, the temperature of the high-temperature zone is 900℃, and the crystallization temperature of the crystallization zone is 820℃. 0.1 Ga 0.7 In 0.2 A first BAs barrier layer 5 with a thickness of 3 nm is grown on the first As isolation layer 4 .

[0184] Step E, Growth B 0.1 Ga 0.7 In 0.2 As quantum well layer, such as Figure 4 (e).

[0185] Using chemical vapor transport, iodine gas was used as the transport agent, the ratio of high-purity boron, gallium, indium, and arsenic source materials was 0.2:1:0.4:1.5, the temperature of the high-temperature zone was 900°C, and the crystallization temperature of the crystallization zone was 820°C. Under the process conditions, a 3nm thick B was grown on the first BAs barrier layer 5. 0.1 Ga 0.7 In 0.2 As quantum well layer 6.

[0186] Step F, growing a second BAs barrier layer, such as Figure 4 (f).

[0187] Using chemical vapor transport method, with iodine gas as the transmission agent, the ratio of high-purity boron to high-purity arsenic is 1:1.5, the temperature of the high-temperature zone is 900℃, and the crystallization temperature of the crystallization zone is 820℃. 0.1 Ga 0.7 In 0.2 A second BAs barrier layer 7 with a thickness of 3 nm is grown on the As quantum well layer 6 .

[0188] Step G, Growth B 0.1 Ga 0.7 In 0.2 As the second isolation layer, such as Figure 4 (g).

[0189] Using chemical vapor transport, iodine gas is used as a transport agent, the ratio of high-purity boron, gallium, indium, and arsenic source materials is 0.2:1:0.4:1.5, the temperature of the high temperature zone is 900℃, and the crystallization temperature of the crystallization zone is 820℃. Under the process conditions, a 20nm thick B layer is grown on the second BAs barrier layer 7. 0.1 Ga 0.7 In 0.2 As second isolation layer 8.

[0190] Step H, growing n-type B 0.1 Ga 0.7 In 0.2 As collector ohmic contact layer, such as Figure 4 (h).

[0191] The chemical vapor transport method was used, with iodine gas as the transport agent, the ratio of high-purity boron, gallium, indium, and arsenic source materials being 0.2:1:0.4:1.5, and 2‰ of Si being added during the reaction, the temperature of the high-temperature zone being 900℃, and the crystallization temperature of the crystallization zone being 820℃. 0.1 Ga 0.7 In 0.2 The As second isolation layer 8 is grown with a thickness of 200 nm and a doping concentration of 5×10 20 cm -3 n-type B0.1 Ga 0.7 In 0.2 As collector ohmic contact layer 9.

[0192] Step I, in n-type B 0.1 Ga 0.7 In 0.2 The As collector ohmic contact layer is formed by photolithography, development and etching to form a grid-like mesa isolation shallow groove with a depth of 600nm. Figure 4 (i).

[0193] First, a mesa isolation pattern is formed by photolithography. The specific implementation of this step is the same as step 9.1) of the first embodiment.

[0194] Secondly, the mesa isolation is formed by etching, that is, using the photoresist as a mask, the inductively coupled plasma etching method is used, and the process conditions of Cl2 gas flow rate of 10sccm, BCl3 gas flow rate of 25sccm, and etching time of 420s are used to etch the epitaxial material to form n-type B 0.1 Ga 0.7 In 0.2 A grid-like mesa isolation shallow trench with a depth of 600nm is formed from the As collector ohmic contact layer to the BAs epitaxial layer.

[0195] Step J, in n-type B 0.1 Ga 0.7 In 0.2 As collector ohmic contact layer to make collector, such as Figure 4 (j).

[0196] First, in n-type B 0.1 Ga 0.7 In 0.2 PMMA A4 photoresist was spin-coated on the As collector ohmic contact layer and the spin-coated layer was rotated at a speed of 500 rad / min and an acceleration of 1000 rad. 2 / Spin coating for 3s at 1000 rad / min; then at a speed of 4000 rad / min and an acceleration of 2000 rad 2 Spin coating at 300 nm / min for 30 seconds, and then bake at 180°C for 90 seconds;

[0197] Next, a photolithography process was used to expose PMMA A4 photoresist with an electron dose ratio of 750. The exposed photoresist was developed with a 3:1 solution of tetramethyl dipentyl ketone and isopropyl alcohol for 120 seconds and then fixed with isopropyl alcohol for 30 seconds, forming a circular collector pattern with a diameter of 10 μm.

[0198] Then, electron beam evaporation was used to form a circular collector pattern. Ti / Au / Ni metals with thicknesses of 20 / 80 / 50 nm were evaporated at a rate and then soaked in acetone solution to form collector electrodes.

[0199] Step K, etching to form a cylindrical mesa, such as Figure 4 (k).

[0200] The collector electrode was used as a mask and an inductively coupled plasma etching method was used. Under the process conditions of Cl2 gas flow rate of 10 sccm, BCl3 gas flow rate of 25 sccm and etching time of 150 s, the n-type B 0.1 Ga 0.7 In 0.2 As collector ohmic contact layer to n-type B 0.1 Ga 0.7 In 0.2 As emitter ohmic contact layer, forming a cylindrical mesa with a diameter of 10μm.

[0201] Step L, in n-type B 0.1 Ga 0.7 In 0.2 A ring-shaped emitter electrode with an inner circumference of 10 μm from the cylindrical table is formed on the As emitter ohmic contact layer. Figure 4 (l).

[0202] The specific implementation of this step is the same as step 12 of the first embodiment.

[0203] Step M, depositing a HfO2 dielectric passivation layer on the entire upper surface of the sample, such as Figure 4 (m).

[0204] Using the atomic layer deposition process, a 50nm thick HfO2 dielectric passivation layer was deposited on the entire surface area of ​​the sample under the process conditions of time of 70s, temperature of 280℃, ethylmethylamine hafnium flow rate of 1200sccm, H2O flow rate of 110sccm, and N2 flow rate of 1000sccm.

[0205] Step N, prepare a collector electrode through hole with a diameter of 9 μm on the HfO2 dielectric passivation layer, as shown in FIG. Figure 4 (n).

[0206] First, the collector electrode through-hole pattern is formed by photolithography using the same steps as step 14.1) of embodiment 1;

[0207] Then, using the photoresist as a mask, the process conditions are set as follows: pressure of 1500mTorr, power of 200W, SF6 flow rate of 8sccm, CHF3 of 10sccm, and He flow rate of 150sccm. Reactive ion etching is used to etch the HfO2 passivation layer to the collector electrode metal surface to form a collector electrode through-hole with a diameter of 9μm.

[0208] Step O, perform photolithography and etching on the HfO2 dielectric passivation layer to form an emitter electrode via hole, as shown in Figure 4 (o).

[0209] First, perform photolithography to form the emitter electrode via hole pattern using the same steps as in step 15.1) of Example 1;

[0210] Then, using the photoresist as a mask, under the process conditions of a pressure of 1500 mTorr, a power of 200 W, an SF6 flow rate of 8 sccm, a CHF3 flow rate of 10 sccm, and a He flow rate of 150 sccm, adopt the reactive ion etching method to etch the HfO2 passivation layer to the emitter electrode metal surface to form the emitter electrode via hole.

[0211] Step P, lead out the emitter electrode Pad and the collector electrode Pad on the emitter electrode via hole and the collector electrode via hole respectively to complete the device fabrication, as shown in Figure 4 (p).

[0212] The specific implementation of this step is the same as that of step sixteen in Example 1.

[0213] The above description is only three specific examples of the present invention and does not constitute any limitation to the present invention. Obviously, for professionals in the field, after understanding the content and principle of the present invention, various modifications and changes in form and details may be made without departing from the principle and structure of the present invention. For example, the materials used for the quantum well layer, isolation layer, and ohmic contact layer, in addition to B 0.2 Ga 0.8 As, B 0.3 In 0.7 As, B 0.1 Ga 0.7 In 0.2 As used in this example, B, Ga, In materials with component ranges of 0 < x < 1, 0 ≤ y < 1, 0 ≤ z < 1, and satisfying x + y + z = 1 can also be used. x Ga y In z As, but these modifications and changes based on the idea of the present invention are still within the scope of the claims of the present invention.

Claims

1. A boron arsenide resonant tunneling diode, comprising, from bottom to top, a substrate (1), an epitaxial layer (2), an emitter ohmic contact layer (3), a first isolation layer (4), a first barrier layer (5), a quantum well layer (6), a second barrier layer (7), a second isolation layer (8), a collector ohmic contact layer (9), and a collector electrode (10), wherein an annular emitter electrode (11) is provided on both sides of the first isolation layer (4), and a passivation layer (12) is wrapped around the outside of the epitaxial layer (2) to the collector electrode (10), characterized in that: The substrate (1) is made of a boron arsenide single crystal material with high thermal conductivity to improve the heat dissipation performance of the device; The epitaxial layer (2) is made of BAs material; The first barrier layer (5) and the second barrier layer (7) are made of BAs material with the same thickness; The quantum well layer (6) uses B x Ga y In z As material, where 0 < x < 1, 0 ≤ y < 1, 0 ≤ z < 1, and x + y + z = 1; The first isolation layer (4) and the second isolation layer (8) are made of B with the same composition and the same thickness. x Ga y In z As, where 0 < x < 1, 0 ≤ y < 1, 0 ≤ z < 1, and x + y + z = 1; The emitter ohmic contact layer (3) and the collector ohmic contact layer (9) are made of n-type B 19 cm -3 -5×10 20 cm -3 between Ga x Ga y In z As, where 0 < x < 1, 0 ≤ y < 1, 0 ≤ z < 1, and x + y + z = 1.

2. The boron arsenide resonant tunneling diode according to claim 1, wherein: The epitaxial layer (2) has a thickness of 1000nm-6000nm.

3. The boron arsenide resonant tunneling diode according to claim 1, wherein: The first barrier layer (5), the quantum well layer (6), and the second barrier layer (7) all have thicknesses of 1 nm to 3 nm.

4. The boron arsenide resonant tunneling diode according to claim 1, wherein: The first isolation layer (4) and the second isolation layer (8) both have a thickness of 4 nm to 20 nm.

5. The boron arsenide resonant tunneling diode according to claim 1, wherein: The emitter ohmic contact layer (3) and the collector ohmic contact layer (9) both have a thickness of 50 nm to 200 nm.

6. The boron arsenide resonant tunneling diode according to claim 1, wherein: The passivation layer (12) is made of any one of SiN material, Al2O3 material and HfO2 material.

7. A method for manufacturing a boron arsenide resonant tunneling diode, characterized in that: The steps include: 1) epitaxially growing a BAs epitaxial layer (2) having a thickness of 1000 nm to 6000 nm on a boron arsenide substrate (1) using a chemical vapor transport method; 2) Using chemical vapor transport to grow a 50nm-200nm thick BAs epitaxial layer (2) with a doping concentration of 1×10 19 cm -3 -5×10 20 cm -3 n-type B x Ga y In z As emitter ohmic contact layer (3); 3) Using chemical vapor transport method in n-type B x Ga y In z A B layer with a thickness of 4 nm to 20 nm is grown on the As emitter ohmic contact layer (3). x Ga y In z As first isolation layer (4); 4) Using chemical vapor transport method in B x Ga y In z A first BAs barrier layer (5) with a thickness of 1 nm to 3 nm is grown on the As first isolation layer (4); 5) Using chemical vapor transport method to grow B with a thickness of 1nm-3nm on the first BAs barrier layer (5) x Ga y In z As quantum well layer (6); 6) Using chemical vapor transport method in B x Ga y In z A second BAs barrier layer (7) with a thickness of 1 nm to 3 nm is grown on the As quantum well layer (6); 7) Using chemical vapor transport method to grow B with a thickness of 4nm-20nm on the second BAs barrier layer (7) x Ga y In z As second isolation layer (8); 8) Using chemical vapor transport method in B x Ga y In Z The second As isolation layer (8) is grown to a thickness of 50 nm to 200 nm and a doping concentration of 1×10 19 cm -3 -5×10 20 cm -3 n-type B x Ga y In z As collector ohmic contact layer (9); 9) forming a mesa isolation pattern on the collector ohmic contact layer (9) using a photolithography process; Then, using the photoresist as a mask, an inductively coupled plasma etching process is used to etch 300nm-600nm along the mask to form a circular mesa isolation shallow groove from the collector ohmic contact layer (9) to the BAs epitaxial layer (2); 10) using a photolithography process to form a circular pattern on the collector ohmic contact layer (9), and using a photoresist as a mask, evaporating a Ti / Au / Ni metal layer on the circular pattern by an electron beam evaporation method to form a collector (10); 11) using the collector (10) metal as a mask, etching to the emitter ohmic contact layer (3) using an inductively coupled plasma etching process to form a cylindrical mesa with a diameter of 1 μm to 10 μm from the first isolation layer (4) to the collector (10); 12) using a photolithography process to photoetch a ring-shaped emitter (11) electrode pattern on the emitter ohmic contact layer (3) outside the cylindrical mesa; then using a photoresist as a mask, evaporating a Ti / Au / Ni metal layer by electron beam evaporation to form an emitter electrode (11) on the electrode pattern; 13) using plasma enhanced chemical vapor deposition or atomic layer deposition to deposit a passivation layer (12) with a thickness of 50 nm to 300 nm on the entire upper surface area of ​​the epitaxial material; 14) using a photolithography process to form a collector electrode through-hole pattern with a diameter of 0.5 μm to 9 μm on the cylindrical mesa passivation layer (12); then using a photoresist as a mask and using a reactive ion etching method to form a collector electrode through-hole on the cylindrical mesa passivation layer; 15) using a photolithography process to form an emitter through-hole pattern on the passivation layer (12); then using a photoresist as a mask and using a reactive ion etching method to form an emitter electrode through-hole on the passivation layer; 16) Using a photolithography process, an emitter pad pattern and a collector pad pattern are formed on the passivation layer (12); then, using a photoresist as a mask, an Au metal layer is evaporated on the pattern using an electron beam evaporation method to form an emitter pad and a collector pad interconnected with the emitter electrode and the collector electrode, respectively, to complete the device preparation.

8. The method according to claim 7, wherein The chemical vapor transport method of step (1), step (4) and step (6) has the following process conditions: Iodine gas is used as a transmission agent, the ratio of high-purity boron to high-purity arsenic is 1:1.5, the temperature of the high-temperature zone is 880°C to 900°C, and the crystallization temperature of the crystallization zone is 800°C to 820°C.

9. The method according to claim 7, wherein The chemical vapor transport method of step (2), step (3), step (5), step (7) and step (8) has the following process conditions: Iodine gas is used as a transmission agent, and the ratio of high-purity boron, gallium, indium, and arsenic source materials is B:Ga:In:As (0.1-1):(0-1):(0-1):1.

5. The temperature of the high-temperature zone is 880-900°C, and the crystallization temperature of the crystallization zone is 800-820°C.

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