Solar cell and preparation method thereof, photovoltaic module

Abstract

The embodiment of the present application relates to a solar cell and a preparation method thereof, and a photovoltaic module. The solar cell comprises: a substrate, a first surface of the substrate comprises a first part and a second part arranged alternately, the first part is concave relative to the second part toward the second surface of the substrate; a first tunneling layer, covering the first part, the surface of the first tunneling layer facing the first part has a first texture structure, the surface of the first tunneling layer away from the first part has a second texture structure, the flatness of the second texture structure is greater than the flatness of the first texture structure, the first texture structure comprises a polishing surface and a plurality of spaced convex structures located on the polishing surface, and the area occupied by the plurality of convex structures on the polishing surface is not greater than 1 / 2 of the area of ​​the polishing surface; a first doped conductive layer, covering the surface of the first tunneling layer away from the substrate; and a first electrode, electrically contacting the first doped conductive layer. The embodiment of the present application is conducive to improving the photoelectric conversion efficiency of the solar cell.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of solar cells, and in particular to a solar cell and a method for preparing the same, and a photovoltaic module. Background Art

[0002] Solar cells have good photoelectric conversion capabilities. At present, tunneling layers and doped conductive layers are prepared on the surface of the substrate to inhibit carrier recombination on the surface of the substrate in the solar cell and enhance the passivation effect on the substrate. Among them, the tunneling layer has a good chemical passivation effect, and the doped conductive layer has a good field passivation effect. In addition, in order to transmit and collect the photogenerated carriers generated by the solar cell, electrodes electrically contacting the doped conductive layer are also prepared to collect the photogenerated carriers.

[0003] The number of photogenerated carriers is related to the absorption utilization rate of the substrate to the incident light. The higher the absorption utilization rate of the substrate to the incident light, the more photogenerated carriers are generated, thereby improving the photoelectric conversion performance of the solar cell.

[0004] However, the photoelectric conversion performance of solar cells is poor. Summary of the invention

[0005] The embodiments of the present application provide a solar cell and a method for preparing the same, and a photovoltaic module, which are at least beneficial to improving the photoelectric conversion efficiency of the solar cell.

[0006] An embodiment of the present application provides a solar cell, comprising: a substrate, having a first surface and a second surface relative to each other, the first surface comprising a first portion and a second portion arranged alternately, the first portion being recessed relative to the second portion toward the second surface; a first tunneling layer, covering the first portion, the surface of the first tunneling layer facing the first portion having a first texture structure, the surface of the first tunneling layer away from the first portion having a second texture structure, the flatness of the second texture structure being greater than the flatness of the first texture structure, the first texture structure comprising a polishing surface and a plurality of spaced convex structures located on the polishing surface, the area occupied by the plurality of convex structures on the polishing surface being no greater than 1 / 2 of the area of ​​the polishing surface; a first doped conductive layer, covering the surface of the first tunneling layer away from the substrate; and a first electrode, electrically contacting the first doped conductive layer.

[0007] In addition, the protrusion structure includes any one of a first pyramid structure or a first platform protrusion structure.

[0008] In addition, the ratio of the area occupied by the plurality of protrusion structures on the polishing surface to the area of ​​the polishing surface is 1:11 to 1:2.

[0009] In addition, the protrusion structure is a first pyramid structure, and the second texture structure includes: a second platform protrusion structure.

[0010] In addition, the recessed depth of the first portion is 1 μm to 5 μm.

[0011] In addition, a width of the first electrode in a first direction is smaller than a width of the first doped conductive layer in the first direction, and the first direction is parallel to the first portion and perpendicular to an extension direction of the first electrode.

[0012] In addition, a ratio of a width of the first doped conductive layer in the first direction to a width of the first electrode in the first direction is less than or equal to 3.

[0013] In addition, it also includes a first passivation layer, wherein the first passivation layer covers the first doped conductive layer and the second portion of the first surface, and the first electrode penetrates the first passivation layer and is in electrical contact with the first doped conductive layer.

[0014] In addition, the second portion of the first surface has a third texture structure including a second pyramid structure.

[0015] In addition, the doping element type of the first doped conductive layer is different from the doping element type of the substrate.

[0016] In addition, the material of the first doped conductive layer includes at least one of amorphous silicon, polycrystalline silicon, and silicon carbide.

[0017] In addition, the solar cell also includes: an emitter layer, the emitter layer is located in the substrate, facing the second part, and the substrate exposes the top surface of the emitter layer, the top surface of the emitter layer is in contact with the surface of the first passivation layer facing the substrate, and the doping element type of the emitter layer is different from the doping element type of the substrate.

[0018] In addition, the solar cell further comprises: a second tunneling layer located on the second surface; and a second doped conductive layer located on a surface of the second tunneling layer away from the substrate.

[0019] In addition, the type of doping element of the second doped conductive layer is the same as the type of doping element of the substrate.

[0020] In addition, the material of the second doped conductive layer includes at least one of amorphous silicon, polycrystalline silicon, and silicon carbide.

[0021] Correspondingly, an embodiment of the present application also provides a photovoltaic module, including a battery string, which is formed by connecting multiple solar cells described in any of the above items; an encapsulation layer, which is used to cover the surface of the battery string, and a cover plate is used to cover the surface of the encapsulation layer away from the battery string.

[0022] Correspondingly, an embodiment of the present application also provides a method for preparing a solar cell, comprising: providing an initial substrate having an initial first surface and a second surface relative to each other; etching the initial substrate from the initial first surface to convert the initial first surface into a first surface, wherein the first surface has a first portion and a second portion arranged alternately, the first portion is recessed relative to the second portion toward the second surface, and the remaining initial substrate forms a substrate; forming a first tunneling layer, wherein the first tunneling layer covers the first portion, the surface of the first tunneling layer facing the first portion has a first texture structure, the surface of the first tunneling layer away from the first portion has a second texture structure, the flatness of the second texture structure is greater than the flatness of the first texture structure, the first texture structure includes a polishing surface and a plurality of spaced protruding structures located on the polishing surface, the area occupied by the plurality of protruding structures on the polishing surface is not greater than 1 / 2 of the area of ​​the polishing surface; forming a first doped conductive layer, wherein the first doped conductive layer covers the surface of the first tunneling layer away from the substrate; forming a first electrode, wherein the first electrode is electrically in contact with the first doped conductive layer.

[0023] In addition, the method for forming the first part and the second part includes: forming a mask layer on the initial first surface, the mask layer having a first opening, the first opening exposing a portion of the initial first surface; etching the initial first surface along the first opening to form an initial first groove in the initial substrate, and converting the initial first surface into the first surface; performing a polishing process on the side walls and bottom wall of the initial first groove so that the side walls and bottom wall of the initial first groove have a polished surface to form an initial second groove; performing a texturing process on the bottom wall and side walls of the initial second groove to form a groove, the bottom wall and side walls of the groove having the first texture structure; removing the mask layer, the first surface corresponding to the groove is the first part, and the part other than the groove is the second part.

[0024] In addition, a texturing process is performed on the bottom wall and the side wall of the initial second groove to form the first texture structure, and the method includes: performing a cleaning process on the bottom wall and the side wall of the initial second groove; preparing a texturing additive mother liquor, wherein the texturing additive mother liquor includes sodium dodecylbenzene sulfonate and polyvinyl pyrrolidone, and the mass ratio of the sodium dodecylbenzene sulfonate to the polyvinyl pyrrolidone is 0.1 to 20; providing deionized water, and adding the texturing additive mother liquor and sodium hydroxide to the deionized water to prepare an etching solution, wherein the volume ratio of the texturing additive mother liquor to the deionized water is 0.002 to 0.003, and the mass ratio of the sodium hydroxide to the deionized water is 0.03 to 0.1; and using the etching solution to clean the bottom wall and the side wall of the initial second groove to form the first texture structure.

[0025] In addition, the method for forming the first tunneling layer includes: using a deposition process to form an initial first tunneling layer on the sidewalls and bottom wall of the groove, and the two opposite surfaces of the initial first tunneling layer have the first texture structure with the same morphology as the sidewalls and bottom wall of the groove; performing a polishing process on the surface of the initial first tunneling layer away from the substrate, and the surface of the initial first tunneling layer away from the substrate processed by the polishing process has the second texture structure to form the first tunneling layer.

[0026] The technical solution provided by the embodiment of the present application has at least the following advantages:

[0027] In the technical solution of the solar cell provided in the embodiment of the present application, the first part of the first surface is set to be recessed toward the second surface relative to the second part, that is, a groove is formed on the first surface of the substrate. The first tunneling layer and the first doped conductive layer covering the first part are equivalent to covering the side walls and bottom walls of the groove. Since the groove has a large surface area, the surface area of ​​the formed tunneling layer and the doped conductive layer can be increased. The first electrode is in electrical contact with the doped conductive layer, so that the tunneling layer and the doped conductive layer surround the first electrode, which has a good passivation effect on the high recombination loss caused by the contact between the first electrode and the doped conductive layer, improves the filling factor, and further improves the photoelectric conversion performance of the solar cell. The first tunneling layer and the first doped conductive layer are not set on the second part, which can avoid the parasitic absorption of the incident light by the first doped conductive layer on the second part, further improving the absorption utilization rate of the incident light.

[0028] In addition, the first tunneling layer and the first doped conductive layer located on the side wall of the groove formed by the first part are not directly exposed to the incident light, and thus will not cause excessive parasitic absorption. While passivating the high recombination loss of the first electrode, it is possible to ensure a high absorption utilization rate of the incident light, increase the number of carriers, and further enhance the photoelectric conversion capacity of the solar cell.

[0029] In addition, the flatness of the second texture structure is set to be greater than the flatness of the first texture structure, that is, the flatness of the surface of the first tunneling layer away from the first part is greater than the flatness of the surface of the first tunneling layer facing the first part, so that the contact interface between the first doped conductive layer and the first tunneling layer is relatively flat, which can enhance the field passivation effect of the first doped conductive layer. The surface of the first tunneling layer facing the first part is a composite morphology of a polished surface and a small number of protruding structures located on the polished surface. The presence of the protruding structure is conducive to increasing the contact area between the tunneling layer and the substrate, increasing the tunneling interface, and facilitating the tunneling of carriers. The polished surface has a large area, which can ensure that the interface between the first tunneling layer and the first part is relatively flat, and enhance the passivation ability of the first tunneling layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] One or more embodiments are exemplarily described by pictures in the corresponding drawings, and these exemplifications do not constitute limitations on the embodiments. Unless otherwise stated, the pictures in the drawings do not constitute proportional limitations.

[0031] Figure 1 A schematic diagram of a cross-sectional structure of a solar cell provided in one embodiment of the present application;

[0032] Figure 2 An electron microscope image of a first texture structure in a solar cell provided in one embodiment of the present application;

[0033] Figure 3 A schematic diagram of a cross-sectional structure of another solar cell provided in one embodiment of the present application;

[0034] Figure 4 A schematic diagram of carrier transmission in another solar cell provided in an embodiment of the present application;

[0035] Figure 5 A schematic cross-sectional structure diagram of a photovoltaic module provided in another embodiment of the present application;

[0036] Figure 6 A schematic cross-sectional structure diagram corresponding to the step of providing a substrate in a method for preparing a solar cell provided in one embodiment of the present application;

[0037] Figure 7 A schematic cross-sectional structure diagram corresponding to a step of forming an emitter in a method for preparing a solar cell provided in an embodiment of the present application;

[0038] Figure 8 A schematic cross-sectional structure diagram corresponding to the step of forming a mask layer in a method for preparing a solar cell provided in the present application;

[0039] Fig. 9A schematic cross-sectional structure diagram corresponding to a step of forming an initial first groove in a method for preparing a solar cell provided in an embodiment of the present application;

[0040] Fig.10 A schematic cross-sectional structure diagram corresponding to a step of forming an initial second groove in a method for preparing a solar cell provided in an embodiment of the present application;

[0041] Fig.11 A schematic cross-sectional structure diagram corresponding to a step of forming a groove in a method for preparing a solar cell provided in an embodiment of the present application;

[0042] Fig.12 A schematic cross-sectional structure diagram corresponding to a step of forming an initial first tunneling layer in a method for preparing a solar cell provided in an embodiment of the present application;

[0043] Fig.13 A schematic cross-sectional structure diagram corresponding to a step of forming a first tunneling layer in a method for preparing a solar cell provided in an embodiment of the present application;

[0044] Fig.14 A schematic cross-sectional structure diagram corresponding to the step of forming a first doped conductive layer in a method for preparing a solar cell provided in one embodiment of the present application;

[0045] Fig.15 A schematic cross-sectional structure diagram corresponding to the step of forming a second tunneling layer and a second doped conductive layer in a method for preparing a solar cell provided in one embodiment of the present application;

[0046] Fig.16 A schematic cross-sectional structure diagram corresponding to the step of forming a first passivation layer in another method for preparing a solar cell provided in an embodiment of the present application;

[0047] Fig.17 A schematic cross-sectional structure diagram corresponding to the step of forming a second passivation layer in another method for preparing a solar cell provided in an embodiment of the present application. DETAILED DESCRIPTION

[0048] As can be seen from the background technology, current solar cells have a problem of low photoelectric conversion efficiency.

[0049] The embodiment of the present application provides a solar cell, wherein the first part of the first surface is set to be concave relative to the second part toward the second surface, so that the surface area of ​​the tunnel layer and the doped conductive layer covering the surface of the first part is larger, and the first electrode is in electrical contact with the doped conductive layer, so that the tunnel layer and the doped conductive layer surround the first electrode, and play a good passivation effect on the high recombination loss caused by the contact between the first electrode and the doped conductive layer. The flatness of the surface of the first tunnel layer away from the first part is set to be greater than the flatness of the surface of the first tunnel layer facing the first part, so that the contact interface between the first doped conductive layer and the first tunnel layer is relatively flat, which can enhance the field passivation effect of the first doped conductive layer. The surface of the first tunnel layer facing the first part is a composite morphology of a polished surface and a small number of protruding structures located on the polished surface. The presence of the protruding structure is conducive to increasing the contact area between the tunnel layer and the substrate, increasing the tunnel interface, and facilitating the tunneling of carriers. The area of ​​the polished surface is large, which can ensure that the interface between the first tunnel layer and the first part is relatively flat, and enhance the passivation ability of the first tunnel layer.

[0050] The following will describe the various embodiments of the present application in detail with reference to the accompanying drawings. However, it will be appreciated by those skilled in the art that in the various embodiments of the present application, many technical details are provided in order to enable the reader to better understand the present application. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solution claimed in the present application can be implemented.

[0051] Figure 1 A schematic diagram of the cross-sectional structure of a solar cell provided in one embodiment of the present application.

[0052] refer to Figure 1 The solar cell comprises: a substrate 100, having a first surface and a second surface opposite to each other, the first surface comprising a first portion 10 and a second portion 11 arranged alternately, the first portion 10 being concave toward the second surface relative to the second portion 11. The solar cell further comprises: a first tunneling layer 110, covering the first portion 10, the surface of the first tunneling layer 110 facing the first portion 10 having a first texture structure, the surface of the first tunneling layer 110 away from the first portion 10 having a second texture structure, the flatness of the second texture structure being greater than the flatness of the first texture structure, the first texture structure comprising a polishing surface 1 and a plurality of spaced convex structures 2 located on the polishing surface 1, the area occupied by the plurality of convex structures 2 on the polishing surface 1 being no greater than 1 / 2 of the area of ​​the polishing surface 1. The solar cell further comprises: a first doped conductive layer 120, covering the surface of the first tunneling layer 110 away from the substrate 100. The solar cell further comprises: a first electrode 130, electrically contacting the first doped conductive layer 120.

[0053] The first electrode 130 penetrates a portion of the thickness of the first doped conductive layer 120 and is in electrical contact with the first doped conductive layer 120. The photogenerated carriers generated in the substrate 100 are transmitted from the substrate 100 to the first doped conductive layer 120 and then to the first electrode 130. The first electrode 130 is used to collect the photogenerated carriers.

[0054] The first portion 10 of the first surface is recessed relative to the second portion 11 toward the second surface to form a groove, and the first tunneling layer 110 and the first doped conductive layer 120 covering the first portion 10 are equivalent to covering the sidewalls and bottom walls of the groove. Since the groove has a large surface area, the tunneling layer and the doped conductive layer covering the sidewalls of the groove have a large surface area, and the first electrode 130 is in electrical contact with the doped conductive layer, so that the tunneling layer and the doped conductive layer surround the first electrode 130, which has a good passivation effect on the high recombination loss caused by the contact between the first electrode 130 and the doped conductive layer, improves the filling factor, and thus can improve the photoelectric conversion performance of the solar cell. Since the first tunneling layer 110 and the first doped conductive layer 120 are not provided in the second portion 11, the problem of parasitic absorption of the incident light by the first doped conductive layer 120 in the second portion 11 can be avoided, and the absorption utilization rate of the incident light by the substrate 100 is improved.

[0055] The first tunneling layer 110 and the first doped conductive layer 120 located on the side walls and the bottom wall of the groove formed by the first part 10 are not directly exposed to the incident light, thereby avoiding excessive parasitic absorption of the incident light. While increasing the surface area of ​​the first tunneling layer 110 and the first doped conductive layer 120 to improve the high recombination loss of the first electrode 130, the substrate 100 has a high absorption utilization rate for the incident light, which can increase the number of carriers, improve the fill factor, increase the open circuit voltage and short circuit current, and improve the photoelectric conversion performance of the solar cell.

[0056] The surface of the first tunneling layer 110 facing the first portion 10 has a first texture structure, and the surface of the first tunneling layer 110 away from the first portion 10 has a second texture structure. In other words, the surface morphology of the first tunneling layer 110 facing the first portion 10 is the morphology of the first texture structure, and the surface morphology of the first tunneling layer 110 away from the first portion 10 is the morphology of the second texture structure. The flatness of the second texture structure is greater than the flatness of the first texture structure, that is, the flatness of the surface of the first tunneling layer 110 away from the first portion 10 is greater than the flatness of the surface of the first tunneling layer 110 facing the first portion 10.

[0057] That is, the surface flatness of the first tunneling layer 110 away from the first portion 10 is relatively high. Since the first doped conductive layer 120 contacts the surface of the first tunneling layer 110 away from the first portion 10, the contact interface between the first doped conductive layer 120 and the first tunneling layer 110 is relatively flat, which can enhance the field passivation effect of the first doped conductive layer 120. The surface of the first tunneling layer 110 facing the first portion 10 is a composite morphology of a polished surface 1 and a small number of protruding structures 2 located on the polished surface 1. The presence of the protruding structures 2 is conducive to increasing the contact area between the tunneling layer and the substrate 100, increasing the tunneling interface, and facilitating the tunneling of carriers. The polished surface 1 has a large area, which can ensure that the interface between the first tunneling layer 110 and the first portion 10 is relatively flat, thereby enhancing the passivation ability of the first tunneling layer 110. In some embodiments, the material of the first tunneling layer 110 includes at least one of silicon oxide, aluminum oxide, silicon nitride, silicon oxynitride, amorphous silicon, or polycrystalline silicon.

[0058] It can be understood that the flatness of the first texture structure refers to the difference in distance between the vertex of the relatively protruding structure and the relatively flat surface on the surface of the first tunneling layer 110 facing the first part 10, and the smaller the difference in distance is, the higher the flatness is; the flatness of the second texture structure refers to the difference in distance between the vertex of the relatively protruding structure and the relatively flat surface on the surface of the second tunneling layer away from the first part 10, and the smaller the difference in distance is, the higher the flatness is.

[0059] The substrate 100 is used to receive incident light and generate photogenerated carriers. In some embodiments, the substrate 100 may be a silicon substrate, and the material of the silicon substrate may include at least one of single crystal silicon, polycrystalline silicon, amorphous silicon, or microcrystalline silicon. In some embodiments, the material of the substrate 100 may also be silicon carbide, an organic material, or a multi-component compound. The multi-component compound may include, but is not limited to, perovskite, gallium arsenide, cadmium telluride, copper indium selenide, and the like.

[0060] In some embodiments, both the first surface and the second surface can be used to receive incident light or reflected light. In some embodiments, the second surface can be a light-receiving surface, and the first surface can be a backlight surface. In some embodiments, the first surface can be a light-receiving surface, and the second surface can be a backlight surface. The light-receiving surface refers to a surface that directly receives incident light.

[0061] In some embodiments, the solar cell may be a TOPCON (Tunnel Oxide Passivated Contact) cell.

[0062] In some embodiments, the substrate 100 has a doping element, and the doping element type is N-type or P-type. The N-type element can be a V-group element such as phosphorus (P), bismuth (Bi), antimony (Sb), or arsenic (As), and the P-type element can be a III-group element such as boron (B), aluminum (Al), gallium (Ga), or gallium (In). For example, when the substrate 100 is a P-type substrate, the doping element type inside it is P-type. Alternatively, when the substrate 100 is an N-type substrate, the doping element type inside it is N-type.

[0063] refer to Figure 2 , Figure 2 An electron microscope image of a first texture structure in a solar cell provided in an embodiment of the present application. In some embodiments, the ratio of the area occupied by the plurality of protrusion structures 2 on the polishing surface 1 to the area of ​​the polishing surface 1 is 1:11 to 1:2, for example, 1:4 to 1:3, 1:5 to 1:4, 1:6 to 1:5, 1:7 to 1:6, 1:8 to 1:7, 1:9 to 1:8, 1:10 to 1:9 or 1:11 to 1:10.

[0064] Within the above range, the total area occupied by the multiple protrusion structures 2 on the polishing surface 1 is small, so that the roughness of the first texture structure is not too large, and the flatness of the surface of the first tunneling layer 110 facing the first part 10 is not too small, avoiding the problem of weakening the chemical passivation ability of the first tunneling layer 110 to the first part 10 due to the uneven contact interface between the first tunneling layer 110 and the first part 10. On the other hand, within the above range, the total area occupied by the multiple protrusion structures 2 on the polishing surface 1 is not too small, and the specific surface area of ​​the surface of the first tunneling layer 110 facing the first part 10 can be appropriately increased, the contact area between the first tunneling layer 110 and the first part 10 is increased, and the tunneling interface of the carriers is increased, which is conducive to enhancing the collection ability of the first electrode 130 for the carriers.

[0065] The polishing surface 1 in the embodiment of the present application refers to a flat surface.

[0066] refer to Figure 1 as well as Figure 3 In some embodiments, the protrusion structure 2 includes any one of a first pyramid structure or a first platform protrusion structure.

[0067] refer to Figure 1 as well as Figure 2 In some embodiments, the protrusion structure 2 includes a first pyramid structure, and the first pyramid structure has a larger specific surface area. Setting the protrusion structure 2 as the first pyramid structure can increase the specific surface area of ​​the first tunneling layer 110 toward the surface of the first part 10, thereby increasing the contact area between the first tunneling layer 110 and the first part 10, thereby increasing the tunneling channel of the carriers.

[0068] In some embodiments, the first pyramid structure may be a tetrahedron, a nearly tetrahedron, a pentahedron, or a nearly pentahedron.

[0069] refer to Figure 3 In some embodiments, the protrusion structure 2 is a first platform protrusion structure, and the first platform protrusion structure is the base part of the pyramid structure, that is, the bottom structure remaining after the pyramid structure removes the top part. In this way, the top of the protrusion structure 2 is relatively flat, which can increase the contact area between the first tunneling layer 110 and the first part 10 and ensure that the contact interface between the first tunneling layer 110 and the first part 10 is relatively flat.

[0070] In some embodiments, the protrusion structure 2 may also be a platform-like protrusion structure, the top surface of the platform-like protrusion structure may be a plane or an inclined surface, and the bottom surface of the platform-like protrusion structure may be a polygonal plane, for example, a quadrilateral plane or a pentagonal plane.

[0071] In some embodiments, the protrusion structure 2 may be located only on the bottom wall of the groove formed by the first portion 10, and the side wall of the groove formed by the first portion 10 may be the polishing surface 1. In some embodiments, the protrusion structure 2 may also be located on the bottom wall and side wall of the groove formed by the first portion 10.

[0072] In some embodiments, the protrusion structure 2 is a first pyramid structure, and the second texture structure includes: a second platform protrusion structure. The second platform protrusion structure can be a tower base structure remaining after removing the top part of the first pyramid structure, that is, compared with the first pyramid structure, the top surface of the second platform protrusion structure is smaller than the bottom surface, so that the flatness of the second texture structure is higher, and the one-dimensional size of the bottom surface of the second platform protrusion structure is larger than the one-dimensional size of the bottom surface of the protrusion structure 2, so that the protrusion degree of the second platform protrusion structure is not too high, which is conducive to the second texture structure to form a higher flatness.

[0073] It is understandable that the area of ​​the second texture structure except the second platform protrusion structure can be a polished surface, and the total area of ​​the bottom surfaces of all the second platform protrusion structures is not greater than the total area of ​​the polished surface, further increasing the flatness of the second texture structure.

[0074] In some embodiments, the second texture structure may also be entirely polished surfaces, that is, entirely flat surfaces.

[0075] refer to Figure 1In some embodiments, the depression depth d of the first portion 10 is 1 μm to 5 μm, for example, 1 μm to 1.5 μm, 1.5 μm to 2 μm, 2 μm to 2.5 μm, 2.5 μm to 3 μm, 3 μm to 3.5 μm, 3.5 μm to 4 μm, 4 μm to 4.5 μm or 4.5 μm to 5 μm. The depression depth d of the first portion 10 refers to the depression depth of the first portion 10 toward the second surface compared to the second portion 11. Within the above range, the depression depth of the first portion 10 is large, so that the first portion 10 has a large surface area, so that the first tunneling layer 110 and the first doped conductive layer 120 formed on the first portion 10 have a large area, which can improve the effect of passivating the high recombination loss of the first electrode 130 to a certain extent. It can also increase the tunneling interface between the first tunneling layer 110 and the substrate 100. In addition, within the above range, the depth of the depression of the first portion 10 is not too large, which can prevent the substrate 100 from being seriously damaged and avoid excessive defects in the substrate 100. On the other hand, it can prevent the first doped conductive layer 120 formed on the first portion 10 from being too thick due to the depression depth of the first portion 10 being too large, so that the parasitic absorption of the incident light by the first doped conductive layer 120 is too large.

[0076] The first portion 10 is recessed relative to the second portion 11 toward the second surface to form a groove, and the groove has an opening away from the second surface. In some embodiments, the bottom wall of the groove can be a plane, and the side wall of the groove is perpendicular to the bottom wall of the groove. In some embodiments, the bottom of the groove can also have a curvature, that is, the first portion 10 can be an elliptical parabola.

[0077] In some embodiments, the width of the first electrode 130 in the first direction X is smaller than the width of the first doped conductive layer 120 in the first direction X, and the first direction X is parallel to the first portion 10 and perpendicular to the extension direction of the first electrode 130. In this way, it can be ensured that the first electrode 130 is covered by the first doped conductive layer 120, and the contact area between the first electrode 130 and the first doped conductive layer 120 is increased, thereby reducing the contact resistance between the first electrode 130 and the first doped conductive layer 120, and improving the rate at which carriers are transmitted to the first electrode 130.

[0078] In some embodiments, the material of the first electrode 130 may be a metal material, for example, any one of silver, nickel, aluminum or copper.

[0079] In some embodiments, the ratio of the width of the first doped conductive layer 120 in the first direction X to the width of the first electrode 130 in the first direction X is less than or equal to 3, for example, it can be 1.1, 1.3, 1.5, 1.7, 2, 2.2, 2.5, 2.8 or 3. Within the above range, the ratio of the width of the first doped conductive layer 120 to the width of the first electrode 130 along the first direction X is large, which can ensure that the first electrode 130 is covered by the first doped conductive layer 120. In addition, the width of the first doped conductive layer 120 is set to be large, so that in the process of actually forming the first electrode 130, it is possible to avoid the problem that the material forming the first electrode 130 diffuses in the first doped conductive layer 120 along the first direction X when burning through the first doped conductive layer 120 due to process deviation, thereby causing the actual width of the formed first electrode 130 to be greater than the first doped conductive layer 120, thereby increasing the process window for forming the first electrode 130.

[0080] In addition, within the above range, the width of the first doped conductive layer 120 along the first direction X is not too large compared with the first electrode 130, which can prevent the first doped conductive layer 120 from receiving too much incident light due to the excessive width of the first doped conductive layer 120, thereby causing the first doped conductive layer 120 to have a large parasitic absorption.

[0081] In some embodiments, the doping element type of the first doped conductive layer 120 is different from the doping element type of the substrate 100. That is, the first doped conductive layer 120 and the substrate 100 form a PN junction. In some embodiments, the doping element type of the substrate 100 is P-type, and the doping element type of the first doped conductive layer 120 is N-type, and the N-type doping element can be a V-group element such as phosphorus (P), bismuth (Bi), antimony (Sb), or arsenic (As). In some embodiments, the doping element type of the substrate 100 is N-type, and the doping element type of the first doped conductive layer 120 is P-type, and the P-type doping element can be a III-group element such as boron (B), aluminum (Al), gallium (Ga), or gallium (In).

[0082] In some embodiments, the material of the first doped conductive layer 120 includes at least one of amorphous silicon, polycrystalline silicon, and silicon carbide.

[0083] refer to Figure 1In some embodiments, the first passivation layer 150 is further included. The first passivation layer 150 covers the first doped conductive layer 120 and the second portion 11 of the first surface. The first electrode 130 penetrates the first passivation layer 150 and is in electrical contact with the first doped conductive layer 120. The first passivation layer 150 can directly contact the second portion 11. The first passivation layer 150 can have a good passivation effect on the first surface, for example, it can better chemically passivate the dangling bonds on the first surface, reduce the defect state density on the first surface, and inhibit carrier recombination on the first surface.

[0084] In some embodiments, the first passivation layer 150 is a single-layer structure, and the material of the first passivation layer 150 can be one of silicon oxide, aluminum oxide, silicon nitride, or silicon oxynitride. In some embodiments, the first passivation layer 150 is a multi-layer structure, and the material of the first passivation layer 150 can be at least one of silicon oxide, aluminum oxide, silicon nitride, or silicon oxynitride.

[0085] refer to Figure 4 In some embodiments, the solar cell further comprises: an emitter layer 140, the emitter layer 140 is located in the substrate 100, facing the second portion 11, and the substrate 100 exposes the top surface of the emitter layer, the top surface of the emitter layer 140 contacts the surface of the first passivation layer 150 facing the substrate 100, and the doping element type of the emitter layer 140 is different from the doping element type of the substrate 100. The emitter layer 140 and the substrate 100 have different doping elements, and form a PN junction with the substrate 100. In some embodiments, the doping element type of the substrate 100 is P-type, and the doping element type of the emitter is N-type, and the N-type doping element can be a V-group element such as phosphorus (P), bismuth (Bi), antimony (Sb), or arsenic (As). In some embodiments, the doping element type of the substrate 100 is N-type, and the doping element type of the emitter is P-type, and the P-type doping element can be a III-group element such as boron (B), aluminum (Al), gallium (Ga), or gallium (In).

[0086] In some embodiments, the material of the emitter layer 140 may be the same as that of the substrate 100. For example, it may be a silicon substrate, and the material of the silicon substrate may include at least one of single crystal silicon, polycrystalline silicon, amorphous silicon, or microcrystalline silicon, or may also be silicon carbide, an organic material, or a multi-component compound. The multi-component compound may include, but is not limited to, materials such as perovskite, gallium arsenide, cadmium telluride, and copper indium selenide.

[0087] In some embodiments, the doping element type of the first doped conductive layer 120 is different from the doping element type of the substrate 100 to form a PN junction, and the emitter and the substrate 100 also form a PN junction, so that the area of ​​the PN junction is larger, thereby being able to convert more incident light into photogenerated carriers.

[0088] In some embodiments, the second portion 11 of the first surface has a third texture structure, and the third texture structure includes a second pyramid structure. The second pyramid structure can be a tetrahedron, a nearly tetrahedron, a pentahedron, or a nearly pentahedron.

[0089] In some embodiments, the number of the second pyramid structures is multiple, and the multiple second pyramid structures are arranged at intervals. The second pyramid structure makes the second portion 11 of the first surface have a velvet structure. The second pyramid structure is a tetrahedral structure or a pentahedral structure, which makes the second pyramid structure have a good reflection ability for the incident light. When the light irradiates the second surface, the incident light reflected by the second pyramid structure will be reflected multiple times between two adjacent second pyramid structures. Finally, most of the reflected light will be absorbed and utilized by the substrate 100 again, thereby enhancing the utilization rate of the substrate 100 for the incident light.

[0090] refer to Figure 1 , Figure 3 as well as Figure 4 In some embodiments, the solar cell further comprises: a second tunneling layer 160, located on the second surface; and a second doped conductive layer 170, located on the surface of the second tunneling layer 160 away from the substrate 100. The second tunneling layer 160 has a chemical passivation effect on the second surface, reduces the defect state density of the second surface, and inhibits carrier recombination on the second surface.

[0091] In some embodiments, the material of the second tunneling layer 160 includes at least one of silicon oxide, aluminum oxide, silicon nitride, silicon oxynitride, amorphous silicon, or polysilicon.

[0092] In some embodiments, the doping element type of the second doped conductive layer 170 is the same as the doping element type of the substrate 100. In some embodiments, the doping element type of the second doped conductive layer 170 and the doping element type of the substrate 100 are both P-type, and the P-type doping element may be a III-group element such as boron (B), aluminum (Al), gallium (Ga), or gallium (In). In some embodiments, the doping element type of the second doped conductive layer 170 and the doping element type of the substrate 100 are both N-type, and the N-type doping element type may be a V-group element such as phosphorus (P), bismuth (Bi), antimony (Sb), or arsenic (As).

[0093] In some embodiments, the doping element concentration of the second doped conductive layer 170 is greater than the doping element concentration of the substrate 100, which can form a high-low junction between the second doped conductive layer 170 and the substrate 100, and form a concentration gradient of the same element, thereby producing a barrier effect on carriers and achieving selective transmission of carriers.

[0094] In some embodiments, the material of the second doped conductive layer 170 includes at least one of amorphous silicon, polysilicon, and silicon carbide.

[0095] In some embodiments, the second passivation layer 180 is further included, and the second passivation layer 180 is located on the surface of the second doped conductive layer 170 away from the substrate 100. The second passivation layer 180 is used to have a good passivation effect on the second surface of the substrate 100, reduce the defect state density of the second surface, and better inhibit the carrier recombination on the back of the substrate 100. The second passivation layer 180 can also have a good anti-reflection effect, which is beneficial to reduce the reflection of the incident light and improve the utilization rate of the incident light.

[0096] In some embodiments, the second passivation layer 180 is a single-layer structure, and the material of the second passivation layer 180 can be one of silicon oxide, aluminum oxide, silicon nitride, or silicon oxynitride. In some embodiments, the second passivation layer 180 is a multi-layer structure, and the material of the second passivation layer 180 can be at least one of silicon oxide, aluminum oxide, silicon nitride, or silicon oxynitride.

[0097] In some embodiments, the second electrode 190 is further included. The second electrode 190 is located on the second surface of the substrate 100 . The second electrode 190 penetrates the second passivation layer 180 and is in electrical contact with the second doped conductive layer 170 .

[0098] In some embodiments, the material of the second electrode 190 may be metal, such as copper, silver, nickel or aluminum.

[0099] In the solar cell provided in the above embodiment, the first part 10 is recessed toward the second surface relative to the second part 11, so that the surface area of ​​the tunneling layer and the doped conductive layer covering the surface of the first part 10 is larger, and the tunneling layer and the doped conductive layer can surround the first electrode 130, which has a good passivation effect on the high recombination loss caused by the contact between the first electrode 130 and the doped conductive layer. The flatness of the surface of the first tunneling layer 110 away from the first part 10 is greater than the flatness of the surface of the first tunneling layer 110 facing the first part 10, so that the contact interface between the first doped conductive layer 120 and the first tunneling layer 110 is relatively flat, which can enhance the field passivation effect of the first doped conductive layer 120. The surface of the first tunneling layer 110 facing the first part 10 is a composite morphology of a polished surface 1 and a small number of protruding structures 2 located on the polished surface 1. The presence of the protruding structures 2 is beneficial to increasing the contact area between the tunneling layer and the substrate 100, increasing the tunneling interface, and facilitating the tunneling of carriers. The polished surface 1 has a large area, which can ensure that the interface between the first tunneling layer 110 and the first part 10 is relatively flat, thereby enhancing the passivation ability of the first tunneling layer 110.

[0100] Accordingly, another aspect of the present application embodiment further provides a photovoltaic assembly, referring to Figure 5 The photovoltaic module includes: a battery string, which is formed by connecting multiple solar cells 101 provided in the above embodiments; an encapsulation layer 102, which is used to cover the surface of the battery string; and a cover plate 103, which is used to cover the surface of the encapsulation layer 102 away from the battery string. The solar cells 101 are electrically connected in the form of a whole piece or multiple pieces to form multiple battery strings, and the multiple battery strings are electrically connected in series and / or in parallel.

[0101] In some embodiments, multiple battery strings can be electrically connected through a conductive tape 104. The encapsulation layer 102 covers the surface and back of the substrate 100 of the solar cell 101. The encapsulation layer 102 can be an organic encapsulation film such as an ethylene-vinyl acetate copolymer (EVA) film, a polyethylene octene co-elastomer (POE) film, a polyethylene terephthalate (PET) film, or a polyvinyl butyral (PVB) film. In some embodiments, the cover plate 103 can be a glass cover plate, a plastic cover plate, or the like with a light-transmitting function. The surface of the cover plate 103 facing the encapsulation layer 102 can be a concave-convex surface, thereby increasing the utilization rate of the incident light.

[0102] Accordingly, an embodiment of the present application further provides a method for preparing a solar cell, comprising:

[0103] refer to Figure 6 , providing an initial substrate 20 having an initial first surface 3 and a second surface 4 opposite to each other.

[0104] The initial substrate 20 is used to receive incident light and generate photogenerated carriers. In some embodiments, the initial substrate 20 may be a silicon substrate, and the material of the initial substrate 20 may include at least one of single crystal silicon, polycrystalline silicon, amorphous silicon, or microcrystalline silicon.

[0105] In some embodiments, the initial substrate 20 may be an N-type semiconductor substrate, and the doping element of the substrate 100 may be any one of phosphorus, arsenic, or antimony.

[0106] In some embodiments, the initial substrate 20 may also be a P-type semiconductor substrate, and the doping element of the initial substrate 20 may be any one of boron, gallium, or indium.

[0107] In some embodiments, a doping process, such as an ion implantation process, may be performed on the initial substrate 20 to diffuse doping elements into the initial substrate 20 .

[0108] In some embodiments, the initial first surface 3 may be subjected to a texturing process to form a velvet structure on the initial first surface 3. In some embodiments, the initial first surface 3 may include a pyramid structure. Forming a velvet structure on the first surface of the substrate 100 may enhance the parasitic absorption capability of the first surface to incident light.

[0109] In some embodiments, the solar cell formed is a TOPCON cell.

[0110] refer to Figure 7 In some embodiments, the method for preparing a solar cell includes: forming an emitter layer 140 in a substrate 100, wherein the substrate 100 exposes a top surface of the emitter layer 140, and the top surface of the emitter layer 140 coincides with the initial first surface 3. The doping element type of the emitter layer 140 is opposite to the doping element type of the substrate 100, and forms a PN junction with the substrate 100.

[0111] In some embodiments, the method of forming the emitter layer 140 may include: performing a diffusion process on the initial first surface 3 of the initial substrate 20 to diffuse the doping element into a portion of the initial substrate 20 to form the emitter layer 140. In some embodiments, the diffusion process may be an ion implantation process.

[0112] In some embodiments, when the initial substrate 20 is an N-type substrate, the initial first surface 3 may be subjected to a boron diffusion treatment, and when the initial substrate 20 is a P-type substrate, the initial first surface 3 may be subjected to a phosphorus diffusion treatment.

[0113] refer to Figures 8 to 11 The initial substrate 20 is etched from the initial first surface 3 to transform the initial first surface 3 into a first surface, the first surface having alternatingly arranged first portions 10 and second portions 11, the first portions 10 being recessed relative to the second portions 11 toward the second surface 4, and the remaining initial substrate 20 forms a substrate 100.

[0114] That is, the initial first surface 3 is etched to remove a portion of the initial substrate 20 , and the remaining portion of the initial substrate 20 forms the substrate 100 , and the initial first surface 3 after etching forms the first surface.

[0115] In some embodiments, the method of forming the first portion 10 and the second portion 11 includes:

[0116] refer to Figure 8 A mask layer 30 is formed on the initial first surface 3, wherein the mask layer 30 has a first opening 31, and the first opening 31 exposes a portion of the initial first surface 3. The mask layer 30 can protect the initial first surface 3 that does not need to be etched.

[0117] In some embodiments, the method of forming the mask layer 30 may include: forming the initial mask layer 30 on the initial first surface 3 by a deposition process, wherein the deposition process may be any one of atomic layer deposition and chemical vapor deposition. In some embodiments, the material of the initial mask layer 30 may be silicon oxide.

[0118] In some embodiments, the initial mask layer 30 may be etched using a photolithography process to form a first opening 31 in the initial mask layer 30 .

[0119] refer to Fig. 9 After forming the first opening 31, the initial first surface 3 is etched along the first opening 31 to form an initial first groove 21 in the initial substrate 20, and the initial first surface 3 is converted into the first surface. In some embodiments, the initial first groove 21 can be formed in the initial substrate 20 by mechanical etching, chemical etching or laser etching.

[0120] In some embodiments, a chemical etching method may be used to form an initial first groove 21 in the initial substrate 20, and the chemical etching method may include: cleaning the initial first surface 3 exposed by the first opening 31 with an etching liquid, and etching the initial substrate 20 from the initial first surface 3. In some embodiments, the etching liquid may include a hydrofluoric acid solution, and the etching time is controlled within 0.5 min to 5 min. In some embodiments, the mass fraction of the hydrofluoric acid solution may be 2% to 5%.

[0121] In some embodiments, before forming the initial first groove 21, an emitter layer 140 is formed in the initial substrate 20. In the step of forming the initial first groove 21, the emitter layer 140 facing the first opening 31 is removed, and the emitter layer 140 facing the mask layer 30 is retained.

[0122] refer to Fig.10 , the sidewalls and bottom wall of the initial first groove 21 are polished so that the sidewalls and bottom wall of the initial first groove 21 have a polished surface, forming the initial second groove 22. It can be understood that the bottom wall and sidewall of the initial first groove 21 formed by etching the initial first surface 3 along the first opening 31 will have an uneven morphology. In order to subsequently form a composite morphology of the polished surface 1 and the protruding structure 2 on the bottom wall and sidewall of the initial first groove 21, it is necessary to perform a polishing process on the sidewalls and bottom wall of the initial first groove 21 to preliminarily form a polished surface, and the polished surface is a flat surface.

[0123] In some embodiments, the polishing process is an alkali polishing process. In some embodiments, the alkali polishing process may include: using an alkali solution to clean the side walls and bottom walls of the initial first groove 21; using a spray method to drop microdrops of the alkali solution onto the side walls and bottom walls of the initial first groove 21 for roughening, and then pre-cleaning with hydrofluoric acid; using a polishing liquid to polish the side walls and bottom walls of the initial first groove 21. In some embodiments, the concentration of the polishing liquid is 0.5% to 5%, the polishing temperature is 50°C to 80°C, and the polishing time is 20s to 1000s. By controlling the polishing time and the polishing temperature within the above range, the morphology of the side walls and bottom walls of the initial second groove 22 can be made to meet expectations. In some embodiments, the polishing liquid can be a NaOH solution, and in some embodiments, the polishing liquid can also be a KOH solution. Finally, the side walls and bottom walls of the initial second groove 22 after polishing are washed and dried.

[0124] refer to Fig.11 After forming the initial second groove 22, the bottom wall and side wall of the initial second groove 22 are subjected to a texturing process to form a groove 23. The bottom wall and side wall of the groove 23 have a first texture structure. The first texture structure includes a polishing surface 1 and a plurality of spaced protruding structures 2 located on the polishing surface 1. The area occupied by the plurality of protruding structures 2 on the polishing surface 1 is not greater than 1 / 2 of the area of ​​the polishing surface 1.

[0125] In some embodiments, the bottom wall and the side wall of the initial second groove 22 are subjected to a texturing process to form a first texture structure, and the method includes:

[0126] First, a cleaning process is performed on the bottom wall and the side wall of the initial second groove 22. In some embodiments, the entire substrate 100 can be immersed in deionized water and treated with an ultrasonic process for 2 minutes to 5 minutes to remove dirt on the surface of the substrate 100.

[0127] Next, a texturing additive mother liquor is prepared, the texturing additive mother liquor includes sodium dodecylbenzene sulfonate and polyvinyl pyrrolidone, and the mass ratio of sodium dodecylbenzene sulfonate to polyvinyl pyrrolidone is 0.1-20, for example, it can be 0.1-0.5, 0.5-1, 1-3, 3-5, 5-8, 8-10, 10-12, 12-15, 15-17, 17-18, 18-19 or 19-20. In some embodiments, based on the mass ratio of sodium dodecylbenzene sulfonate to polyvinyl pyrrolidone, 0.2g-2g of sodium dodecylbenzene sulfonate and 0.1g-2g of polyvinyl pyrrolidone can be selected and added to 1000ml of deionized water to prepare the texturing additive mother liquor.

[0128] Next, deionized water is provided, and a texturing additive mother solution and sodium hydroxide are added to the deionized water to prepare an etching solution, wherein the volume ratio of the texturing additive mother solution to the deionized water is 0.002 to 0.003, for example, 0.002 to 0.0021, 0.0021 to 0.0023, 0.0023 to 0.0024, 0.0024 to 0.0025, 0.0025 to 0.0026, 0.00 26~0.0027, 0.0027~0.0028, 0.0028~0.0029 or 0.0029~0.003; the mass ratio of sodium hydroxide to deionized water is 0.03~0.1, for example, it can be 0.03~0.04, 0.04~0.05, 0.05~0.06, 0.06~0.07, 0.07~0.08, 0.08~0.09 or 0.09~0.1. In some embodiments, based on the volume ratio of the texturing additive mother liquor to the deionized water, 1L~1.5L of the texturing additive mother liquor can be added to 500L of deionized water. In some embodiments, based on the mass ratio of sodium hydroxide to deionized water, 35kg of sodium hydroxide can be added to 500L of deionized water.

[0129] The bottom wall and the side wall of the initial second groove 22 are cleaned with an etching solution to form a first texture structure. The first texture structure etched with the etching solution of the above ratio has a polishing surface 1 and a first pyramid structure located on the polishing surface 1 .

[0130] In some embodiments, the polished surface of the initial second groove 22 can be etched into a first texture structure by using the etching solution configured in the above ratio. In some embodiments, the bottom wall and side wall of the initial second groove 22 can be cleaned with the etching solution for 2 minutes to 50 minutes at a temperature of 75° C. to 90° C. to ensure that the formed first texture structure meets expectations.

[0131] In some embodiments, if the raised structure 2 is a first platform raised structure, after the step of using an etching solution to clean the bottom wall and side wall of the initial second groove 22 to form a first pyramid structure, a polishing process can be used to remove the top of the first pyramid structure, and the remaining base of the first pyramid structure forms a first platform raised structure. In some embodiments, the method of removing the top of the first pyramid structure using a polishing process may include: polishing the bottom wall and side wall of the groove 23 using a polishing liquid. In some embodiments, the concentration of the polishing liquid is 0.5% to 3%, the polishing temperature is 50°C to 80°C, and the polishing time is 10s to 500s. By controlling the polishing time and the polishing temperature within the above range, the top of the first pyramid structure can be removed. In some embodiments, the polishing liquid can be a NaOH solution, and in some embodiments, the polishing liquid can also be a KOH solution.

[0132] refer to Figure 12 to Figure 13 In some embodiments, after the groove 23 is formed, a first tunneling layer 110 is formed, the first tunneling layer 110 covers the first portion 10, the surface of the first tunneling layer 110 facing the first portion 10 has a first texture structure, and the surface of the first tunneling layer 110 away from the first portion 10 has a second texture structure, and the flatness of the second texture structure is greater than the flatness of the first texture structure.

[0133] In some embodiments, a method of forming the first tunneling layer 110 includes:

[0134] refer to Fig.12 An initial first tunneling layer 32 is formed on the sidewalls and bottom wall of the groove 23 by a deposition process, and two opposite surfaces of the initial first tunneling layer 32 have a first texture structure with the same morphology as the sidewalls and bottom wall of the groove 23 .

[0135] In some embodiments, before forming the initial first tunneling layer 32 , the mask layer 30 may not be removed, so as to prevent the initial first tunneling layer 32 from being formed on the second portion 11 .

[0136] In some embodiments, the formed initial first tunneling layer 32 is also located on the surface of the mask layer 30. In subsequent steps, the initial first tunneling layer 32 located on the surface of the mask layer 30 may be removed, and the initial first tunneling layer 32 is only formed in the groove 23. In some embodiments, a deposition process, such as an atomic layer deposition process or a chemical vapor deposition process, may be used to form the initial first tunneling layer 32. Since the initial first tunneling layer 32 is formed by a deposition process, the surface of the initial first tunneling layer 32 facing the first portion 10 and the surface away from the first portion 10 both have the same morphology as the first texture structure.

[0137] In some embodiments, the material of the initial first tunneling layer 32 includes at least one of silicon oxide, aluminum oxide, silicon nitride, silicon oxynitride, amorphous silicon, or polysilicon.

[0138] refer to Fig.13 , a polishing process is performed on the surface of the initial first tunneling layer 32 away from the substrate 100, and the surface of the initial first tunneling layer 32 away from the substrate 100 after the polishing process has a second texture structure, forming the first tunneling layer 110. Since the polishing process is not performed on the surface of the initial first tunneling layer 32 facing the substrate 100, the surface of the first tunneling layer 110 facing the substrate 100 has the same first texture structure as the bottom wall and the side wall of the groove 23.

[0139] In some embodiments, the second texture structure formed may be a second platform protrusion structure, and the area other than the second platform protrusion structure in the second texture structure may be a polished surface. In some embodiments, the method for forming the second protrusion structure 2 may refer to the process method for forming the first platform protrusion structure, which will not be described in detail below.

[0140] In some embodiments, the second texture structure formed may also be all polished surfaces, that is, all flat surfaces. In some embodiments, the method of forming the second texture structure as a polished surface can refer to the process method of forming the initial second groove 22 using a polishing process, which will not be repeated below.

[0141] refer to Fig.14 After forming the first tunneling layer 110 , a first doped conductive layer 120 is formed, and the first doped conductive layer 120 covers the surface of the first tunneling layer 110 away from the substrate 100 .

[0142] In some embodiments, before the step of forming the first doped conductive layer 120 , the first tunneling layer 110 located on the surface of the mask layer 30 is not removed, so that the formed first doped conductive layer 120 will not be located in the second portion 11 .

[0143] In some embodiments, the method of forming the first doped conductive layer 120 may include: forming a first doped layer on the surface of the first tunneling layer 110 and the surface of the first tunneling layer 110 located on the mask layer 30 by a deposition process, and during the deposition process, implanting doping elements into the first doped layer by an in-situ deposition process to form an original first doped conductive layer 120. The deposition process and the process of implanting doping elements are performed simultaneously, which can save process time and improve process efficiency.

[0144] After the doping element is implanted into the first doped layer, the original first doped conductive layer 120 is annealed to form the first doped conductive layer 120. After the annealing process, the doping element in the original first doped conductive layer 120 can be activated to form an activated doping element.

[0145] In some embodiments, during the process of implanting the doping element into the first doping layer, the concentration of the implanted doping element is controlled to be 1×10 20 atom / cm 3 ~1×10 21 atom / cm 3 .

[0146] In some embodiments, the doping element type injected into the first doping layer is different from the doping element type of the substrate 100 to form a PN junction with the substrate 100. In some embodiments, the doping element type of the substrate 100 is P-type, and the doping element type of the emitter is N-type, and the N-type doping element can be a V-group element such as phosphorus (P), bismuth (Bi), antimony (Sb), or arsenic (As). In some embodiments, the doping element type of the substrate 100 is N-type, and the doping element type of the emitter is P-type, and the P-type doping element can be a III-group element such as boron (B), aluminum (Al), gallium (Ga), or gallium (In).

[0147] In some embodiments, the material of the first doped layer may be any one of amorphous silicon, polycrystalline silicon, microcrystalline silicon, or silicon carbide.

[0148] It is not difficult to find that the first doped layer is formed on the surface of the first tunneling layer 110 away from the substrate 100, and since the surface of the first tunneling layer 110 away from the substrate 100 has a second texture structure, the second texture structure has a high flatness, so that the first doped layer is formed on a relatively flat surface, which can improve the uniformity of the formed first doped layer, thereby improving the passivation ability of the formed first doped conductive layer 120.

[0149] It is worth noting that the formed first doped conductive layer 120 is also located on the surface of the first tunneling layer 110 on the mask layer 30. In some embodiments, after the first doped conductive layer 120 is formed, the first doped conductive layer 120 located on the mask layer 30, the first tunneling layer 110 located on the mask layer 30, and the mask layer 30 are removed, so that the formed first tunneling layer 110 and the first doped conductive layer 120 are located in the groove 23. In some embodiments, an acid pickling process can be used to remove the first doped conductive layer 120 located on the mask layer 30, the first tunneling layer 110 located on the mask layer 30, and the mask layer 30. For example, a hydrofluoric acid solution or a hydrochloric acid solution can be used to clean the first doped conductive layer 120 located on the mask layer 30, the first tunneling layer 110 located on the mask layer 30, and the mask layer 30, so as to remove the first doped conductive layer 120 located on the mask layer 30, the first tunneling layer 110 located on the mask layer 30, and the mask layer 30.

[0150] refer to Fig.15In some embodiments, the method for preparing a solar cell further includes: forming a second tunneling layer 160 on the second surface 4 of the substrate 100. In some embodiments, the second tunneling layer 160 may be formed on the second surface 4 by a deposition process, and the deposition process may be any one of an atomic layer deposition process and a chemical vapor deposition process. In some embodiments, the material of the second tunneling layer 160 may be at least one of silicon oxide, aluminum oxide, silicon nitride, silicon oxynitride, amorphous silicon, or polycrystalline silicon.

[0151] In some embodiments, after forming the second tunneling layer 160 , a second doped conductive layer 170 is formed on a surface of the second tunneling layer 160 away from the substrate 100 .

[0152] The method for forming the second doped conductive layer 170 may include: forming a second doped layer on the surface of the second tunneling layer 160 by a deposition process, and during the deposition process, implanting doping elements into the second doped layer by an in-situ deposition process to form an original second doped conductive layer 170 .

[0153] After the doping elements are implanted into the second doped layer, an annealing process is performed on the original second doped conductive layer 170 to form the second doped conductive layer 170 .

[0154] In some embodiments, the doping element type injected into the second doping layer is the same as the doping element type of the substrate 100. In some embodiments, the doping element type of the second doped conductive layer 170 and the doping element type of the substrate 100 are both P-type, and the P-type doping element can be a III-group element such as boron (B), aluminum (Al), gallium (Ga), or gallium (In). In some embodiments, the doping element type of the second doped conductive layer 170 and the doping element type of the substrate 100 are both N-type, and the N-type doping element type can be a V-group element such as phosphorus (P), bismuth (Bi), antimony (Sb), or arsenic (As).

[0155] In some embodiments, the material of the second doped layer may be any one of amorphous silicon, polycrystalline silicon, microcrystalline silicon, or silicon carbide.

[0156] refer to Fig.16 In some embodiments, the method for preparing a solar cell further includes: forming a first passivation layer 150, wherein the first passivation layer 150 covers the first doped conductive layer 120 and the second portion 11 of the first surface. In some embodiments, an emitter layer 140 is also formed in the substrate 100, and the top surface of the emitter layer 140 overlaps with the second portion 11, and the first passivation layer 150 is located on the top surface of the emitter layer 140 and the top surface of the first doped conductive layer 120.

[0157] In some embodiments, the emitter layer 140 may not be formed in the substrate 100 , and the first passivation layer 150 is in direct contact with the second portion 11 .

[0158] In some embodiments, the first passivation layer 150 may be a single-layer structure. In some embodiments, the first passivation layer 150 may also be a multi-layer structure.

[0159] In some embodiments, the first passivation layer 150 is a single-layer structure, and the material of the first passivation layer 150 can be one of silicon oxide, aluminum oxide, silicon nitride, or silicon oxynitride. In some embodiments, the first passivation layer 150 is a multi-layer structure, and the material of the first passivation layer 150 can be at least one of silicon oxide, aluminum oxide, silicon nitride, or silicon oxynitride.

[0160] In some embodiments, the method of forming the first passivation layer 150 may include: forming the first passivation layer 150 on the surface of the doped conductive layer by using a PECVD (Plasma Enhanced Chemical Vapor Deposition) method.

[0161] refer to Fig.17 In some embodiments, the method further includes: forming a second passivation layer 180 on the surface of the second doped conductive layer 170, and the second passivation layer 180 can have a better passivation effect. In some embodiments, the second passivation layer 180 can be a single-layer structure. In some implementations, the second passivation layer 180 can also be a multi-layer structure.

[0162] In some embodiments, the second passivation layer 180 is a single-layer structure, and the material of the second passivation layer 180 can be one of silicon oxide, aluminum oxide, silicon nitride, or silicon oxynitride. In some embodiments, the second passivation layer 180 is a multi-layer structure, and the material of the second passivation layer 180 can be at least one of silicon oxide, aluminum oxide, silicon nitride, or silicon oxynitride.

[0163] In some embodiments, a PECVD process may be used to form the second passivation layer 180 on the emitter surface.

[0164] refer to Figure 3 The method for preparing a solar cell further includes: forming a first electrode 130, wherein the first electrode 130 is in electrical contact with the first doped conductive layer 120. In some embodiments, the first electrode 130 penetrates the first passivation layer 150 and is in electrical contact with the first doped conductive layer 120.

[0165] In some embodiments, the method for forming the first electrode 130 includes: printing a conductive paste on the surface of the first passivation layer 150 directly opposite to the first doped conductive layer 120, for example, the conductive paste may be printed by a screen printing process, and the conductive paste may include at least one of silver, aluminum, copper, tin, gold, lead or nickel. The conductive paste on the surface of the first passivation layer 150 is subjected to a sintering process so that the conductive paste penetrates into the first passivation layer 150 and a portion of the doped conductive layer to form an electrical contact with the doped conductive layer.

[0166] In some embodiments, the method further includes forming a second electrode 190, wherein the second electrode 190 penetrates the second passivation layer 180 and electrically contacts the second doped conductive layer 170. In some embodiments, the process of forming the second electrode 190 may be the same as the process of forming the first electrode 130, and reference may be made to the above description of the method of forming the first electrode 130.

[0167] Although the present application is disclosed as above with preferred embodiments, it is not intended to limit the claims. Any technical personnel in this field may make several possible changes and modifications without departing from the concept of the present application. Therefore, the scope of protection of the present application shall be based on the scope defined by the claims of the present application.

[0168] Those skilled in the art will appreciate that the above-mentioned embodiments are specific examples for implementing the present application, and in practical applications, various changes may be made to the embodiments in form and detail without departing from the spirit and scope of the present application. Any person skilled in the art may make various changes and modifications without departing from the spirit and scope of the present application, and therefore the scope of protection of the present application shall be subject to the scope defined in the claims.

Claims

1. A solar cell, characterized in that: include: A substrate having a first surface and a second surface opposite to each other, wherein the first surface includes first portions and second portions arranged alternately, and the first portions are recessed relative to the second portions toward the second surface; a first tunneling layer, covering the first portion, wherein a surface of the first tunneling layer facing the first portion has a first texture structure, and a surface of the first tunneling layer away from the first portion has a second texture structure, the flatness of the second texture structure is greater than the flatness of the first texture structure, and the first texture structure includes a polishing surface and a plurality of spaced convex structures located on the polishing surface, and an area occupied by the plurality of convex structures on the polishing surface is not greater than 1 / 2 of an area of ​​the polishing surface; A first doped conductive layer covering a surface of the first tunneling layer away from the substrate; A first electrode is electrically contacted with the first doped conductive layer.

2. The solar cell according to claim 1, characterized in that The protrusion structure includes any one of a first pyramid structure or a first platform protrusion structure.

3. The solar cell according to claim 1 or 2, characterized in that: The ratio of the area occupied by the plurality of protrusion structures on the polishing surface to the area of ​​the polishing surface is 1:11-1:

2.

4. The solar cell according to claim 1, characterized in that The protrusion structure is a first pyramid structure, and the second texture structure includes: a second platform protrusion structure.

5. The solar cell according to claim 1, characterized in that: The depression depth of the first portion is 1 μm to 5 μm.

6. The solar cell according to claim 1 or 5, characterized in that: The width of the first electrode in a first direction is smaller than the width of the first doped conductive layer in the first direction. The first direction is parallel to the first portion and perpendicular to an extension direction of the first electrode.

7. The solar cell according to any one of claims 6, characterized in that A ratio of a width of the first doped conductive layer in the first direction to a width of the first electrode in the first direction is less than or equal to 3.

8. The solar cell according to claim 1, characterized in that The invention also includes a first passivation layer, wherein the first passivation layer covers the first doped conductive layer and the second portion of the first surface, and the first electrode penetrates the first passivation layer and is in electrical contact with the first doped conductive layer.

9. The solar cell according to claim 8, characterized in that The second portion of the first surface has a third texture structure including a second pyramid structure.

10. The solar cell according to claim 8, characterized in that The doping element type of the first doped conductive layer is different from the doping element type of the substrate.

11. The solar cell according to claim 10, characterized in that The material of the first doped conductive layer includes at least one of amorphous silicon, polycrystalline silicon, and silicon carbide.

12. The solar cell according to claim 8 or 10, characterized in that: Also includes: An emitter layer, wherein the emitter layer is located in the substrate and is directly opposite to the second portion, and the substrate exposes a top surface of the emitter layer, the top surface of the emitter layer is in contact with a surface of the first passivation layer facing the substrate, and a doping element type of the emitter layer is different from a doping element type of the substrate.

13. The solar cell according to claim 1 or 10, characterized in that: The solar cell further comprises: A second tunneling layer, located on the second surface; The second doped conductive layer is located on a surface of the second tunneling layer away from the substrate.

14. The solar cell according to claim 13, characterized in that: The doping element type of the second doped conductive layer is the same as the doping element type of the substrate.

15. The solar cell according to claim 14, characterized in that: The material of the second doped conductive layer includes at least one of amorphous silicon, polycrystalline silicon, and silicon carbide.

16. A photovoltaic module, characterized in that: include: A battery string, wherein the battery string is formed by connecting a plurality of solar cells according to any one of claims 1 to 15; An encapsulation layer, the encapsulation layer is used to cover the surface of the battery string; A cover plate is used to cover a surface of the packaging layer away from the battery string.

17. A method for preparing a solar cell, characterized in that: include: Providing an initial substrate having an initial first surface and a second surface that are opposite to each other; Etching the initial substrate from the initial first surface to transform the initial first surface into a first surface, wherein the first surface has first portions and second portions arranged alternately, the first portions are recessed relative to the second portions toward the second surface, and the remaining initial substrate forms a substrate; forming a first tunneling layer, wherein the first tunneling layer covers the first portion, a surface of the first tunneling layer facing the first portion has a first texture structure, a surface of the first tunneling layer away from the first portion has a second texture structure, the flatness of the second texture structure is greater than the flatness of the first texture structure, the first texture structure comprises a polishing surface and a plurality of spaced convex structures located on the polishing surface, and an area occupied by the plurality of convex structures on the polishing surface is not greater than 1 / 2 of an area of ​​the polishing surface; forming a first doped conductive layer, wherein the first doped conductive layer covers a surface of the first tunneling layer away from the substrate; A first electrode is formed, the first electrode being in electrical contact with the first doped conductive layer.

18. The method for preparing a solar cell according to claim 17, characterized in that: The method of forming the first part and the second part comprises: forming a mask layer on the initial first surface, wherein the mask layer has a first opening, and the first opening exposes a portion of the initial first surface; Etching the initial first surface along the first opening to form an initial first groove in the initial substrate and transform the initial first surface into the first surface; Performing a polishing process on the sidewalls and the bottom wall of the initial first groove so that the sidewalls and the bottom wall of the initial first groove have a polished surface to form an initial second groove; Performing a texturing process on the bottom wall and the side wall of the initial second groove to form a groove, wherein the bottom wall and the side wall of the groove have the first texture structure; The mask layer is removed, the first surface corresponding to the groove is the first portion, and the portion other than the groove is the second portion.

19. The method for preparing a solar cell according to claim 18, characterized in that: The method of performing a texturing process on the bottom wall and the side wall of the initial second groove to form the first texture structure comprises: Performing a cleaning process on the bottom wall and side wall of the initial second groove; Prepare a texturing additive mother solution, wherein the texturing additive mother solution comprises sodium dodecylbenzene sulfonate and polyvinyl pyrrolidone, and the mass ratio of the sodium dodecylbenzene sulfonate to the polyvinyl pyrrolidone is 0.1-20; Providing deionized water, adding the texturing additive mother solution and sodium hydroxide to the deionized water to prepare an etching solution, wherein the volume ratio of the texturing additive mother solution to the deionized water is 0.002-0.003, and the mass ratio of the sodium hydroxide to the deionized water is 0.03-0.1; The etching solution is used to clean the bottom wall and the side wall of the initial second groove to form the first texture structure.

20. The method for preparing a solar cell according to claim 19, characterized in that: The method of forming the first tunneling layer includes: Forming an initial first tunneling layer on the sidewall and bottom wall of the groove by a deposition process, wherein two opposite surfaces of the initial first tunneling layer have the first texture structure with the same morphology as the sidewall and bottom wall of the groove; A polishing process is performed on the surface of the initial first tunneling layer away from the substrate, and the surface of the initial first tunneling layer away from the substrate processed by the polishing process has the second texture structure to form the first tunneling layer.

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