Connector and setting method for the same

Abstract

The present disclosure provides a connector provided with a plurality of differential pair interfaces, each differential pair interface being subject to interference from a plurality of adjacent differential pair interfaces as aggressor differential pair interfaces, wherein at least one of the plurality of adjacent differential pair interfaces is left vacant to reduce the interference on the victim differential pair interface.

Description

Technical Field

[0001] This disclosure relates to the field of circuits, and more specifically, to the connection arrangements of connectors. Background Technology

[0002] High-speed signal connectors are indispensable key components of electronic devices, significantly impacting the overall signal transmission quality of the entire data communication system. In artificial intelligence (AI) applications, dealing with massive amounts of data requires sufficiently high data throughput for real-time processing; therefore, connectors play a crucial role in data transmission.

[0003] The 1x, 4x, 8x, and 16x PCIe connectors are very successful, and their robust, durable, and low-cost PCIe slots are widely used in servers and AI applications. However, these connectors are only suitable for lower frequencies, and due to the 1.0mm pin pitch, the signal density is low, making them inadequate when facing higher speeds and higher signal densities.

[0004] The Gen Z connector has a pin pitch of 0.6mm, which is 67% higher than the 1.0mm pitch of the PCIe slot. Even compared to the 0.85mm pitch of the DDR4 / 5 connector, it offers a 40% improvement in signal density.

[0005] Gen-Z connectors are available in 1C, 2C, 4C, 4C HP, and 4C+ specifications. Each "C" in Gen-Z contains 8 differential pairs, i.e., 4 transmit / receive channels. Specifically, Gen-Z 1C is equivalent to PCIe 4x, Gen-Z 2C is equivalent to PCIe 8x, and Gen-Z 4C is equivalent to PCIe 16x. The Gen-Z Scalable Connector Specification 1.1 is the standard protocol for Gen-Z, which defines the pin specifications of the connector.

[0006] High-speed signals, especially 112Gbps high-speed SerDes signals, are easily affected during transmission. Crosstalk is one of the most significant factors affecting high-speed data transmission. Crosstalk is an unwanted energy level generated when one signal (hereinafter referred to as the attacking line) couples to another signal (hereinafter referred to as the victim line). According to Maxwell's laws, wherever there is current, there will be a magnetic field; interference between magnetic fields is the source of crosstalk. This induced signal can lead to data loss and transmission errors. These data transmission errors are particularly pronounced for high-speed data transmission. Summary of the Invention

[0007] One object of this disclosure is to provide a connector capable of reducing port device interference and a method for setting the connector.

[0008] According to a first aspect of this disclosure, a connector is provided having a plurality of differential pair interfaces, each differential pair interface being interfered with as a victim differential pair interface by a plurality of neighboring differential pair interfaces being attack differential pair interfaces, wherein at least one of the plurality of neighboring differential pair interfaces is left unused to reduce interference to the victim differential pair interface.

[0009] According to a second aspect of this disclosure, a circuit board is provided, including the connector described above.

[0010] According to a third aspect of this disclosure, an electronic device is provided, including a circuit board as described above.

[0011] According to a fourth aspect of this disclosure, a method for configuring a connector is provided, the connector having a plurality of differential pair interfaces, each differential pair interface being interfered with as a victim differential pair interface by a plurality of neighboring differential pair interfaces being attack differential pair interfaces, the method comprising: idling at least one neighboring differential pair interface of the plurality of neighboring differential pair interfaces to reduce interference to the victim differential pair interface.

[0012] The beneficial effects of this disclosure include, at least, reducing the negative impact of crosstalk to an acceptable level by optimizing wiring while making the most of the high-speed connector pin resources. Attached Figure Description

[0013] The above and other objects, features, and advantages of this disclosure will become readily apparent from the following detailed description of exemplary embodiments with reference to the accompanying drawings. In the drawings, several embodiments of this disclosure are illustrated by way of example and not limitation, and like or corresponding reference numerals denote like or corresponding parts, wherein:

[0014] Figure 1a This illustrates a conventional wiring method for a connection;

[0015] Figure 1b A schematic diagram of a connector containing two implicit differential pair interfaces is shown.

[0016] Figure 2 A schematic diagram showing a differential pair interface being left idle according to one embodiment of the present disclosure is shown;

[0017] Figure 3 A schematic diagram showing an attack differential pair interface being left idle according to one embodiment of the present disclosure is shown;

[0018] Figure 4aA schematic diagram showing an attack differential pair interface being left idle according to one embodiment of the present disclosure is shown;

[0019] Figure 4b A more detailed schematic diagram of the interface connection method of the Gen-Z connector is shown;

[0020] Figure 5 A schematic diagram showing an attack differential pair interface being left idle according to one embodiment of the present disclosure is shown;

[0021] Figure 6 A schematic diagram of the pinout of a CDFP connector according to one embodiment of the present disclosure is shown; and

[0022] Figure 7 A schematic diagram of a connector having a multi-row, multi-column interface according to one embodiment of the present disclosure is shown. Detailed Implementation

[0023] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0024] Figure 1a This illustrates a standard wiring method for a connection. It should be understood that, in this document, differential pairs and differential pair interfaces can be used equivalently. A differential pair interface refers to the interface within the connector used for wiring, while a differential pair refers to the differential pair wire connected to the differential pair interface. In this document, differential pairs and differential pair interfaces can be used equivalently.

[0025] like Figure 1a As shown, a typical high-speed connector can have multiple differential pair interfaces, such as differential pair interface 1 to differential pair interface 26, and each differential pair interface has a ground terminal next to it, such as ground terminal A1_SE, B1_SE, etc. Figure 1a In the high-speed connector shown, all differential pairs are connected, while the single-ended interfaces A42_SE and B42_SE at the bottom of the connector can be connected or left unconnected. Single-ended interfaces are not the focus of this application and will not be discussed further here. With this connection method, each differential pair is more susceptible to interference from adjacent differential pairs. For example, differential pair 3 is more susceptible to interference from differential pairs 1, 5, 2, 4, and 6. The interference is greatest when all differential pairs are connected, thus affecting data transmission quality, which is particularly pronounced in high-speed data transmission.

[0026] To overcome the defect of compromised data transmission quality, according to a first aspect of this disclosure, a connector is provided, the connector having a plurality of differential pair interfaces, each differential pair interface being interfered with as a victim differential pair interface by a plurality of neighboring differential pair interfaces being an attack differential pair interface, wherein at least one of the plurality of neighboring differential pair interfaces is left unused to reduce interference to the victim differential pair interface.

[0027] For ease of description, any differential pair interface can be referred to as a "victim" differential pair interface, which means that the victim differential pair interface will be affected or interfered with by other differential pair interfaces; the differential pair interfaces adjacent to the victim differential pair interface can be referred to as "attacking" differential pair interfaces, which means that these attacking differential pair interfaces will affect or interfere with the aforementioned victim differential pair interface.

[0028] At least one attack differential pair interface can be left unused, thereby reducing the negative impact or interference of the attack differential pair interface on the victim differential pair interface. Each additional unused attack differential pair interface reduces the negative impact on the victim differential pair interface, but also decreases the utilization rate of the interfaces in the connector. Therefore, using appropriate wiring methods helps to appropriately reduce interference to the victim differential pair interface while efficiently utilizing the differential pair interfaces.

[0029] It should be understood that, for ease of description, the term "adjacent" will be used in the following text. According to one embodiment of this disclosure, when the connector interface is arranged in a two-column layout, the attack differential pair interface (or the adjacent differential pair interface of the victim differential pair interface) includes: a same-side attack differential pair interface located on the same side as the victim differential pair interface and adjacent to the victim differential pair interface; an opposite attack differential pair interface located on the opposite side of the victim differential pair interface; and an opposite attack differential pair interface located on the same side as the opposite attack differential pair interface and adjacent to the opposite attack differential pair interface. It should be understood that "opposite" here is merely a general description and does not necessarily mean that the opposite attack differential pair interface is on a straight line; this will be illustrated with examples later.

[0030] Specifically, with Figure 1a Taking differential pair interface 3 as the victim differential pair interface as an example, differential pair interfaces 1, 5, 2, 4, and 6 are relatively close to the victim differential pair interface 3, and their impact on the victim differential pair interface 3 is more obvious. Therefore, differential pair interfaces 1, 5, 2, 4, and 6 can be referred to as the "neighboring" differential pair interfaces or attack differential pair interfaces of the victim differential pair interface 3.

[0031] More specifically, differential pair interface 1 and differential pair interface 5 are located on the same side as the victim differential pair interface 3 and are adjacent to the victim differential pair interface, which is referred to herein as the same-side attack differential pair interface; differential pair interface 4 is located on the opposite side of the victim differential pair interface 3, which is referred to herein as the opposite-side attack differential pair interface; differential pair interfaces 2 and 6 are located on the same side as the opposite-side attack differential pair interface 4 and are adjacent to the opposite-side attack differential pair interface 4, which is referred to herein as the opposite-side attack differential pair interface.

[0032] It should be noted that the differential pair interface at the connector end, such as differential pair interface 1, as the victim differential pair interface, can have three explicit proximity attack differential pair interfaces, namely differential pair interface 2, differential pair interface 3, and differential pair interface 4. Differential pair interface 3 is located on the same side as the victim differential pair interface 1 and is adjacent to the victim differential pair interface; this can also be referred to as the same-side attack differential pair interface in this document. Differential pair interface 2 is located on the opposite side of the victim differential pair interface 1; this can also be referred to as the opposite-side attack differential pair interface in this document. Differential pair interface 4 is located on the same side as the opposite-side attack differential pair interface 2 and is adjacent to the opposite-side attack differential pair interface 2; this can also be referred to as the opposite-side attack differential pair interface in this document. In fact, the victim differential pair interface 1 can also be considered to have two implicit attack differential pair interfaces 0 and 0' (e.g., Figure 1b (As shown). It can be assumed that these two implicit attack differential pairs, interfaces 0 and 0', remain empty and therefore do not interfere with the victim differential pair interface 1.

[0033] According to one embodiment of this disclosure, a portion of the same-side attack differential pair interface includes a first same-side attack differential pair interface and a second same-side attack differential pair interface; a portion of the opposite-side attack differential pair interface includes a first opposite-side attack differential pair interface and a second opposite-side attack differential pair interface.

[0034] Based on the description above, it can be seen that for the victim differential pair interface located at the connector end, there is one same-side attack differential pair interface, one opposite-side attack differential pair interface, and one opposite-side attack differential pair interface. For the other part of the victim differential pair interfaces located outside the connector end, there can be two same-side attack differential pairs, one opposite-side attack differential pair interface, and two opposite-side attack differential pairs.

[0035] Figure 2 A schematic diagram showing a differential pair interface being left idle according to one embodiment of the present disclosure is shown.

[0036] like Figure 2 As shown, with differential pair interface 3 as the victim differential pair interface, according to the above-described scheme of this disclosure, at least one of the adjacent differential pair interfaces 1, 5, 2, 4, and 6 needs to be left vacant. Figure 2 In this example, differential pair interface 5 is left empty.

[0037] Since differential pair interface 5 is empty, other differential pairs that use differential pair interface 5 as their neighboring differential pair interface do not need to be empty. That is, differential pair interface 3, differential pair interface 7, differential pair interface 4, differential pair interface 6, and differential pair interface 8 do not need to be empty.

[0038] Next, at least one differential pair interface among differential pair interfaces 9-14 needs to be left unused. Figure 2 In this example, differential pair interface 12 is left unused. However, it should be understood that other differential pair interfaces 9-14 can also be left unused.

[0039] Next, at least one differential pair interface among differential pair interfaces 15-20 needs to be left idle. Figure 2 In this example, differential pair interface 17 is left unused. However, it should be understood that other differential pair interfaces 15-20 can also be left unused.

[0040] Next, at least one differential pair interface among differential pair interfaces 21-26 needs to be left unused. Figure 2 In this example, differential pair interface 24 is left empty. However, it should be understood that other differential pair interfaces 21-26 can also be left empty.

[0041] The single-ended interfaces A42_SE and B42_SE can be left unused or connected.

[0042] It is necessary to understand that Figure 2 The connection method shown is merely an example. Any connection method that leaves one of the five adjacent differential pair interfaces of a differential pair interface idle is within the scope of protection of this disclosure.

[0043] According to one embodiment of this disclosure, at least two of the attack differential pair interfaces are left vacant, thereby further reducing interference from the attack differential pair interfaces to the victim differential pair interfaces.

[0044] Figure 3 A schematic diagram is shown showing an attack differential pair interface being left idle according to one embodiment of the present disclosure.

[0045] like Figure 3As shown, in the differential pair interfaces on the left side of the connector, every other differential pair interface has two unused differential pair interfaces. Specifically, differential pair interfaces 3 and 5 are unused, differential pair interfaces 9 and 11 are unused, differential pair interfaces 15 and 17 are unused, and differential pair interfaces 21 and 23 are unused. With this configuration, if the differential pair interfaces on the right side are used as victim differential pair interfaces, then each victim differential pair interface has at least two unused attack differential pair interfaces.

[0046] According to one embodiment of this disclosure, at least one of the first same-side attack differential pair interface and the second same-side attack differential pair interface is left unused; and at least one of the opposite-side attack differential pair interface, the first opposite-side attack differential pair interface and the second opposite-side attack differential pair interface is left unused.

[0047] Figure 4a A schematic diagram is shown showing an attack differential pair interface being left idle according to one embodiment of the present disclosure.

[0048] like Figure 4a As shown, if differential pair interface 3 is used as the victim differential pair interface, then at least one of the adjacent differential pair interfaces 1 and 5 can be left vacant (in... Figure 4a Differential pair interface 5 is left unused), and at least one of differential pair interfaces 2, 4, and 6 can be left unused (in... Figure 4a (Differential pair interface 4 is left unused); with differential pair interface 9 as the victim differential pair interface, then at least one of the adjacent differential pair interfaces 7 and 11 can be left unused (in... Figure 4a Differential pair interface 11 is left unused), and at least one of differential pair interfaces 8, 10, and 12 can be left unused (in... Figure 4a Differential pair interface 10 is left unused; however, if differential pair interface 7 is used as the victim differential pair interface, differential pair 9 does not need to be left unused since differential pair interface 5 is already unused; furthermore, differential pair interface 10 is already unused, therefore differential pair interfaces 6 and 8 do not need to be left unused. And so on, ensuring that at least two of the five adjacent attack differential pair interfaces for each differential pair interface are left unused, thus reducing interference to the victim differential pair interface.

[0049] In summary, this means that every two sets of differential pairs are left unused. This wiring method can minimize interference between adjacent differential pairs while making full use of pin resources.

[0050] Figure 4a A general connection method for a differential pair interface according to one embodiment of the present disclosure is shown. Figure 4b A more detailed schematic diagram of the interface connection method of the Gen-Z connector is shown.

[0051] like Figure 4bAs shown, with Figure 4a Similarly, differential pair interfaces 5, 11, 17, and 23 are left unused, as are differential pair interfaces 4, 10, 16, and 22. If differential pair interface 3 is the victim differential pair interface, then its adjacent differential pair interfaces 5 and 4 are left unused; if differential pair interface 7 is the victim differential pair interface, then its adjacent differential pair interfaces 5 and 10 are left unused; and if differential pair interface 9 is the victim differential pair interface, then its adjacent differential pair interfaces 10 and 11 are left unused. And so on, ensuring that at least two of the five attack differential pair interfaces adjacent to each differential pair interface are left unused, thus reducing interference to the victim differential pair interface.

[0052] Figure 5 A schematic diagram is shown showing an attack differential pair interface being left idle according to one embodiment of the present disclosure.

[0053] like Figure 5 As shown, differential pair interfaces 5, 9, 13, 15, and 21 are left unused, as are differential pair interfaces 4, 10, 14, 22, and 24. In this embodiment, when differential pair interface 3 is used as the victim differential pair interface, its adjacent differential pair interfaces 5 and 4 are left unused; when differential pair interface 7 is used as the victim differential pair interface, its adjacent differential pair interfaces 5, 9, and 10 are left unused. It should be noted that when differential pair interface 17 is used as the victim differential pair, since it has two ground terminals (A28_GND and A29_GND) between it and differential pair interface 19, both sides of differential pair interfaces 17 and 19 have complete ground shields. Therefore, it is equivalent to having an interface left unused between differential pair interfaces 17 and 19, and the crosstalk between them can be ignored. Only the case of several differential pair interfaces is described here; other differential pair interfaces are similar, so they will not be described again here.

[0054] As can be seen from the above-described scheme of this disclosure, in a connector, one, two, and / or three, or even more, adjacent attack differential pair interfaces can be left vacant. Of course, users can choose the specific number of differential pair interfaces to be left vacant according to their actual needs.

[0055] The above description uses the GEN Z connector as an example. This connection method can be used for other connectors with dual-row interfaces. For example, the SlimSAS connector also has a similar dual-row interface layout, so the above solution can also be used for wiring.

[0056] It should be noted that although some connectors have a multi-row layout, the wiring between their two-row interfaces can still refer to the above wiring scheme because the rows are far apart.

[0057] Figure 6A schematic diagram of the pinout of a CDFP connector according to one embodiment of the present disclosure is shown.

[0058] like Figure 6 As shown, the CDFP connector comprises four rows, A through D, each including a differential pair interface and a ground terminal, and one end of the connector has a terminal for connecting single-ended signals. Although this CDFP connector has four rows, wiring between rows A and B, and between rows C and D, can be routed using a dual-row interface configuration. Figure 6 As shown, the differential pair interfaces in the solid-line ellipse represent connected differential pair interfaces, while the differential pair interfaces in the dashed-line ellipse represent unused differential pair interfaces. Figure 6 In this application, the distance between row B and row C is relatively large, so there is no need to consider the interference between them. Therefore, although the CDFP connector is a multi-row structure in hardware, its connection method can still refer to that of a two-row connector.

[0059] The above text describes connectors including dual-row interfaces. In practice, many connectors also feature a planar interface layout, such as Z-pack connectors or ExaMAX connectors. The following text will use the ExaMAX connector as an example.

[0060] Figure 7 A schematic diagram of a connector having a multi-row, multi-column interface according to one embodiment of the present disclosure is shown.

[0061] like Figure 7 As shown, the connector exemplarily includes 10 columns (represented as columns 1-10) of differential pair interfaces, each column including 4 differential pair interfaces (represented as AD), and each column having one single-ended interface. The single-ended interfaces are arranged crosswise at the top and bottom of each column for connecting some less important signals (the single-ended interfaces are not the focus of this application, so they will not be described in detail here).

[0062] exist Figure 7 In the connector structure shown, in order to reduce interference between adjacent differential pair interfaces, some differential pair interfaces can be selectively left unused.

[0063] First, for the sake of clarity, this application will first describe... Figure 7 The attack differential of the connector structure shown is used to define and interpret the interface.

[0064] According to one embodiment of this disclosure, when the connector interface is arranged in at least three rows and three columns, the attack differential pair interface includes: a column-in attack differential pair interface that is in the same column as the victim differential pair interface and adjacent to the victim differential pair interface; a front column attack differential pair interface that is in front of the victim differential pair interface and adjacent to the victim differential pair interface; and a rear column attack differential pair interface that is in the rear column of the victim differential pair interface and adjacent to the victim differential pair interface.

[0065] like Figure 7 As shown, each differential pair is represented by a rectangle, with the grounding terminals between the rectangles. It is important to understand that this application primarily focuses on the victimized differential pairs located in the middle of a multi-row, multi-column differential pair interface (i.e., surrounded by eight adjacent differential pairs). Differential pairs located at the edges of the connector are not the focus of this application, as these edge interfaces naturally have fewer attacking differential pairs. In this case, it can still be assumed that other attacking differential pairs virtually exist around some edge-side differential pairs.

[0066] Specifically, with Figure 7 If differential pair interface A in the first column is the victim differential pair interface, then its adjacent differential pair interfaces include: differential pair interface B in the first column and differential pair interfaces A and B in the second column.

[0067] by Figure 7 If the differential pair interface C in the first column is the victim differential pair interface, then its adjacent differential pair interfaces include: differential pair interfaces B and D in the first column, and differential pair interfaces B, C, and D in the second column.

[0068] by Figure 7 If differential pair interface A in column 2 is the victim differential pair interface, then its adjacent differential pair interfaces include: differential pair interfaces A and B in column 1, differential pair interface B in column 2, and differential pair interfaces A and B in column 3.

[0069] According to one embodiment of this disclosure, a portion of the co-column attack differential pair interface includes: a first co-column attack differential pair interface and a second co-column attack differential pair interface; a portion of the front-column attack differential pair interface includes: a first front-column attack differential pair interface, a second front-column attack differential pair interface, and a third front-column attack differential pair interface; and a portion of the back-column attack differential pair interface includes: a first back-column attack differential pair interface, a second back-column attack differential pair interface, and a third back-column attack differential pair interface. Differential pair interfaces located outside the edge typically have eight adjacent differential pair interfaces.

[0070] by Figure 7 The difference pair interface B in column 6 (e.g.) Figure 7If the differential pair interface circled by the ellipse in the image is taken as the victim differential pair interface, then it has eight adjacent differential pair interfaces, namely: differential pair interfaces A and C, which are in the 6th column, the same as the victim differential pair interface; differential pair interfaces A, B, and C, which are in the 5th column before the victim differential pair interface; and differential pair interfaces A, B, and C, which are in the 7th column after the victim differential pair interface.

[0071] As described above, a differential pair interface typically has eight adjacent differential pair interfaces (or attack differential pair interfaces), and is therefore susceptible to interference from signals originating from these eight adjacent differential pair interfaces. According to one embodiment of this disclosure, at least three of the attack differential pair interfaces are left unused.

[0072] It is important to understand that having at least three attack differential pairs is merely a preferred scenario, not a requirement.

[0073] There are several ways to leave at least three adjacent differential pairs of interfaces for each victim differential pair empty, for example, using Figure 7 The difference pair interface B in column 6 (e.g.) Figure 7 If the differential pair interface circled by the ellipse in the middle is taken as the victim differential pair interface, then at least three of the differential pair interfaces A, B and C in column 5, differential pair interfaces A, B and C in column 7, and differential pair interfaces A and C in column 6 can be left empty.

[0074] According to one embodiment of this disclosure, at least one of the first co-row attack differential pair interface and the second co-row attack differential pair interface is left unused; at least one of the first front-row attack differential pair interface, the second front-row attack differential pair interface and the third front-row attack differential pair interface is left unused; and / or at least one of the first back-row attack differential pair interface, the second back-row attack differential pair interface and the third back-row attack differential pair interface is left unused.

[0075] According to this implementation method, continue to refer to Figure 7 .exist Figure 7 In the diagram, dashed boxes represent empty differential pair interfaces, while solid boxes represent non-empty differential pair interfaces. (Still using...) Figure 7 The difference pair interface B in column 6 (e.g.) Figure 7 The differential pair interface circled by the ellipse in the image is designated as the victim differential pair interface. Differential pair interface C in column 5 is left empty, differential pair interface C in column 7 is left empty, and differential pair interface A in column 6 is left empty. Similarly, using... Figure 7In this configuration, differential pair interface C in column 6 is designated as the victim differential pair interface, while differential pair interface C in column 5, column 7, and column 6 are all left empty. It should be noted that, for example, if differential pair interface A in column 5 is designated as the victim differential pair interface, then differential pair interfaces A in columns 4 and 6, which are its adjacent differential pair interfaces, are left empty. Since differential pair interface A is located at the edge of the connector, there is naturally one less attack differential pair interface above differential pair interface A in column 5.

[0076] and Figure 7 There are various types of similar connectors, such as Z-pack connectors or ExaMAX connectors, which can all be used. Figure 7 The connection method shown.

[0077] This disclosure also provides a method for setting up a connector, the connector being provided with a plurality of differential pair interfaces, each differential pair interface being interfered with by a plurality of neighboring differential pair interfaces being attacked differential pair interfaces as a victim differential pair interface, the method comprising: idling at least one neighboring differential pair interface of the plurality of neighboring differential pair interfaces to reduce interference to the victim differential pair interface.

[0078] According to one embodiment of this disclosure, when the connector interface is arranged in a two-column layout, the attack differential pair interface includes: a same-side attack differential pair interface located on the same side as the victim differential pair interface and adjacent to the victim differential pair interface; an opposite attack differential pair interface located on the opposite side of the victim differential pair interface; and an opposite attack differential pair interface located on the same side as the opposite attack differential pair interface and adjacent to the opposite attack differential pair interface.

[0079] According to one embodiment of this disclosure, a portion of the same-side attack differential pair interface includes a first same-side attack differential pair interface and a second same-side attack differential pair interface; a portion of the opposite-side attack differential pair interface includes a first opposite-side attack differential pair interface and a second opposite-side attack differential pair interface.

[0080] According to one embodiment of this disclosure, at least two of the attack differential pair interfaces are left unused.

[0081] According to one embodiment of this disclosure, at least one of the first same-side attack differential pair interface and the second same-side attack differential pair interface is left vacant; and at least one of the opposite-side attack differential pair interface, the first opposite-side attack differential pair interface and the second opposite-side attack differential pair interface is left vacant.

[0082] According to one embodiment of this disclosure, the connector is a GEN Z connector, a SlimSAS connector, or a CDFP connector.

[0083] According to one embodiment of this disclosure, when the connector interface is arranged in at least three rows and three columns, the attack differential pair interface includes: a column-in attack differential pair interface that is in the same column as the victim differential pair interface and adjacent to the victim differential pair interface; a front column attack differential pair interface that is in front of the victim differential pair interface and adjacent to the victim differential pair interface; and a rear column attack differential pair interface that is in the rear column of the victim differential pair interface and adjacent to the victim differential pair interface.

[0084] According to one embodiment of this disclosure, a portion of the same-column attack differential pair interface includes: a first same-column attack differential pair interface and a second same-column attack differential pair interface; a portion of the front-column attack differential pair interface includes: a first front-column attack differential pair interface, a second front-column attack differential pair interface and a third front-column attack differential pair interface; and a portion of the back-column attack differential pair interface includes: a first back-column attack differential pair interface, a second back-column attack differential pair interface and a third back-column attack differential pair interface.

[0085] According to one embodiment of this disclosure, at least three of the attack differential pair interfaces are left idle.

[0086] According to one embodiment of this disclosure, at least one of the first co-row attack differential pair interface and the second co-row attack differential pair interface is left idle; at least one of the first front-row attack differential pair interface, the second front-row attack differential pair interface and the third front-row attack differential pair interface is left idle; and / or at least one of the first back-row attack differential pair interface, the second back-row attack differential pair interface and the third back-row attack differential pair interface is left idle.

[0087] According to one embodiment of this disclosure, the connector is a Z-pack connector or an ExaMAX connector.

[0088] According to the technical solution disclosed herein, by selective routing, the negative impact of crosstalk can be reduced to an acceptable level while making full use of the pin resources of high-speed connectors. The technical solution disclosed herein can also be extended to all high-speed connectors. While the pin definitions of high-speed connectors may differ, the distribution of differential pairs is consistent. This selective routing can suppress the effects of crosstalk to a certain extent, thus ensuring the transmission quality of high-speed signals while effectively utilizing connector resources.

[0089] This disclosure also provides a circuit board including the connectors described above.

[0090] This disclosure also provides an electronic device including the circuit board as described above.

[0091] Electronic devices or apparatuses include data processing devices, robots, computers, printers, scanners, tablet computers, smart terminals, mobile phones, dashcams, navigators, sensors, cameras, servers, cloud servers, cameras, camcorders, projectors, watches, headphones, mobile storage, wearable devices, vehicles, home appliances, and / or medical devices.

[0092] The means of transportation include airplanes, ships and / or vehicles; the household appliances include televisions, air conditioners, microwave ovens, refrigerators, rice cookers, humidifiers, washing machines, lights, gas stoves, and range hoods; the medical equipment includes MRI scanners, ultrasound scanners and / or electrocardiographs.

[0093] It should be noted that, for the sake of simplicity, the foregoing method embodiments are all described as a series of actions. However, those skilled in the art should understand that this disclosure is not limited to the described order of actions, as some steps may be performed in other orders or simultaneously according to this disclosure. Furthermore, those skilled in the art should also understand that the embodiments described in the specification are optional embodiments, and the actions and modules involved are not necessarily essential to this disclosure.

[0094] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0095] In the embodiments provided in this disclosure, it should be understood that the disclosed apparatus can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the displayed or discussed mutual couplings, direct couplings, or communication connections may be through some interfaces; indirect couplings or communication connections between devices or units may be electrical, optical, acoustic, magnetic, or other forms.

[0096] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0097] Furthermore, the functional units in the various embodiments disclosed herein can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software program module.

[0098] If the integrated unit is implemented as a software program module and sold or used as an independent product, it can be stored in a computer-readable storage device (CMD). Based on this understanding, when the technical solution disclosed herein can be embodied in the form of a software product, the computer software product is stored in a storage device and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this disclosure. The aforementioned storage device includes various media capable of storing program code, such as a USB flash drive, read-only memory (ROM), random access memory (RAM), portable hard drive, magnetic disk, or optical disk.

[0099] The embodiments of this disclosure have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this disclosure. The descriptions of the above embodiments are only for the purpose of helping to understand the methods and core ideas of this disclosure. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this disclosure. Therefore, the content of this specification should not be construed as a limitation of this disclosure.

Claims

1. A connector having a plurality of differential pair interfaces, each differential pair interface acting as a victim differential pair interface being interfered with by a plurality of neighboring differential pair interfaces acting as attack differential pair interfaces, wherein, At least one of the plurality of adjacent differential pair interfaces is left unused to reduce interference to the victim differential pair interface.

2. The connector according to claim 1, wherein, When the connector interface is a two-column layout, the attack differential pair interface includes: Same-side attack differential pair interface that is on the same side as the victim differential pair interface and adjacent to the victim differential pair interface; The opposite attack differential pair interface is located on the side opposite the victim differential pair interface; and The opposite attack differential pair interface is located on the same side as the opposite attack differential pair interface and is adjacent to the opposite attack differential pair interface.

3. The connector according to claim 2, wherein, A portion of the same-side attack differential pair interface includes a first same-side attack differential pair interface and a second same-side attack differential pair interface; a portion of the opposite-side attack differential pair interface includes a first opposite-side attack differential pair interface and a second opposite-side attack differential pair interface.

4. The connector according to claim 2, wherein, At least two of the attack differential pairs are left unused.

5. The connector according to claim 3, wherein, At least one of the first same-side attack differential pair interface and the second same-side attack differential pair interface is left idle; and At least one of the opposite attack differential pair interface, the first opposite attack differential pair interface, and the second opposite attack differential pair interface is left unused.

6. The connector according to any one of claims 2-5, wherein, The connector is a GEN Z connector, a SlimSAS connector, or a CDFP connector.

7. The connector according to claim 1, wherein, When the connector interface has a layout of at least three rows and three columns, the attack differential pair interface includes: Attack differential pair interfaces that are in the same column as the victim differential pair interface and adjacent to the victim differential pair interface; The front-row attack differential pair interface that is in the front row of the victim differential pair interface and adjacent to the victim differential pair interface; and The attack differential pair interface is located in the back row of the victim differential pair interface and is adjacent to the victim differential pair interface.

8. The connector according to claim 7, wherein, A portion of the co-op attack differential pair interface includes: a first co-op attack differential pair interface and a second co-op attack differential pair interface; A portion of the front-row attack differential pair interface includes: a first front-row attack differential pair interface, a second front-row attack differential pair interface, and a third front-row attack differential pair interface; and A portion of the back-row attack differential pair interface includes: a first back-row attack differential pair interface, a second back-row attack differential pair interface, and a third back-row attack differential pair interface.

9. The connector according to claim 7, wherein, At least three of the attack differential pair interfaces are left unused.

10. The connector according to claim 8, wherein, At least one of the first co-op attack differential pair interface and the second co-op attack differential pair interface is left empty; At least one of the first front-row attack differential pair interface, the second front-row attack differential pair interface, and the third front-row attack differential pair interface is left empty; and / or At least one of the first back-row attack differential pair interface, the second back-row attack differential pair interface, and the third back-row attack differential pair interface is left unused.

11. The connector according to any one of claims 7-10, wherein, The connector is either a Z-pack connector or an ExaMAX connector.

12. A circuit board comprising the connector as described in any one of claims 1-11.

13. An electronic device comprising the circuit board as claimed in claim 12.

14. A method of arranging a connector, the connector being provided with a plurality of differential pair interfaces, each differential pair interface being interfered with as a victim differential pair interface by a plurality of neighboring differential pair interfaces being attack differential pair interfaces, the method comprising: At least one of the plurality of adjacent differential pair interfaces is left unused to reduce interference to the victim differential pair interface.

15. The method according to claim 14, wherein, When the connector interface is a two-column layout, the attack differential pair interface includes: Same-side attack differential pair interface that is on the same side as the victim differential pair interface and adjacent to the victim differential pair interface; The opposite attack differential pair interface is located on the side opposite the victim differential pair interface; and The opposite attack differential pair interface is located on the same side as the opposite attack differential pair interface and is adjacent to the opposite attack differential pair interface.

16. The method according to claim 15, wherein, A portion of the same-side attack differential pair interface includes a first same-side attack differential pair interface and a second same-side attack differential pair interface; a portion of the opposite-side attack differential pair interface includes a first opposite-side attack differential pair interface and a second opposite-side attack differential pair interface.

17. The method according to claim 15, wherein, Leave at least two of the attack differential pair interfaces empty.

18. The method according to claim 16, wherein, Leave at least one of the first same-side attack differential pair interface and the second same-side attack differential pair interface empty; and Leave at least one of the opposite attack differential pair interface, the first opposite attack differential pair interface, and the second opposite attack differential pair interface empty.

19. The method according to any one of claims 15-18, wherein, The connector is a GEN Z connector, a SlimSAS connector, or a CDFP connector.

20. The method of claim 14, wherein when the connector interface is a layout of at least three rows and three columns, the attack differential pair interface comprises: Attack differential pair interfaces that are in the same column as the victim differential pair interface and adjacent to the victim differential pair interface; The front-row attack differential pair interface is located at the front of the victim differential pair interface and is adjacent to the victim differential pair interface. as well as The attack differential pair interface is located in the back row of the victim differential pair interface and is adjacent to the victim differential pair interface.

21. The method according to claim 20, wherein, A portion of the co-op attack differential pair interface includes: a first co-op attack differential pair interface and a second co-op attack differential pair interface; A portion of the front-row attack differential pair interface includes: a first front-row attack differential pair interface, a second front-row attack differential pair interface, and a third front-row attack differential pair interface; and A portion of the back-row attack differential pair interface includes: a first back-row attack differential pair interface, a second back-row attack differential pair interface, and a third back-row attack differential pair interface.

22. The method according to claim 20, wherein, Leave at least three of the attack differential pair interfaces empty.

23. The method according to claim 21, wherein, Leave at least one of the first co-op attack differential pair interface and the second co-op attack differential pair interface empty; Leave at least one of the first front-row attack differential pair interface, the second front-row attack differential pair interface, and the third front-row attack differential pair interface empty; and / or Leave at least one of the first back-row attack differential pair interface, the second back-row attack differential pair interface, and the third back-row attack differential pair interface empty.

24. The method according to any one of claims 20-23, wherein, The connector is either a Z-pack connector or an ExaMAX connector.

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