Multi-phase interleaved parallel buck hysteresis comparator control chip and power supply system

Abstract

The present invention provides a multi-phase interleaved parallel buck hysteresis comparator control chip and power supply system, comprising: a buck converter, a detection circuit, a driver, a hysteresis comparator, and a threshold width control circuit; the buck converter, the detection circuit, the driver, the hysteresis comparator, and the threshold width control circuit are provided in multiple numbers and correspond to each other; the multi-phase buck converters are designed to be connected in parallel; the first input terminal of the hysteresis comparator is connected to the threshold median value, and the output terminal is connected to the driver input terminal; the driver output terminal is connected to the buck converter drive input terminal; the output terminals of the multi-phase buck converters are connected to serve as voltage output terminals; the node between the hysteresis comparator and the driver is also connected to the input terminal of the threshold width control circuit; the second input terminal of the hysteresis comparator is also connected to the output terminal of the threshold width control circuit, and the output of the threshold width control circuit is used as half of the threshold width to participate in the control. The present invention has a controllable threshold width, achieving a fixed switching frequency and interleaved parallel connection.

Description

Technical Field

[0001] The present invention relates to the field of power supplies, and in particular to a multi-phase interleaved parallel buck hysteresis comparison control chip and a power supply system. Background Art

[0002] With the rapid development of the Internet, communications and integrated circuits, the extensive application of various dedicated chips and microprocessors, such as CPU, MCU, etc., has put forward higher requirements on the load range and dynamic response of power supply.

[0003] To increase load range, modern CPU power supply systems typically employ a multi-phase parallel buck converter structure. Compared to in-phase parallel operation, interleaved parallel operation effectively reduces output voltage ripple and output capacitance, facilitating miniaturization and integration of power supplies. To improve dynamic response, hysteresis comparator control eliminates the bandwidth limitations of traditional linear control, accelerating dynamic response. However, the switching frequency of traditional hysteresis comparator control is not fixed, making the generated electromagnetic interference difficult to eliminate with EMI filters.

[0004] The currently available hysteresis comparison control methods are as follows Figure 1 As shown, the power stage utilizes a four-phase parallel buck converter. Each phase consists of a PMOS and NMOS switch, an inductor L, and an inductor L. The detection stage comprises a detection resistor Rf and a detection capacitor Cf. The control stage comprises a delay phase-locked loop (DLL) and a hysteresis comparator. The hysteresis comparator consists of two conventional comparators and an RS flip-flop.

[0005] The above scheme adopts the master-slave control method, and the four-phase parallel buck converter is divided into the master phase, slave phase 1, slave phase 2 and slave phase 3. In the master phase, the inductor L and the equivalent series resistance R of the inductor are SL , detection resistor R f and detection capacitance C f In meeting R f C f < <L / R SL Under the condition of , the detection circuit generates a feedback voltage v in phase with the inductor current. fb The feedback voltage is input to the hysteresis comparator and is compared with the upper threshold V H =V ref +ΔV and lower threshold V L =V ref -ΔV comparison generates the main phase drive signal V dM . Where V ref The master phase drive signal is input into the DLL to generate slave phase drive signals V with phase differences of 90°, 180°, and 270°. d1 ,V d2 and Vd3 , thus realizing four-phase interleaved parallel control.

[0006] Traditional interleaved parallel circuits use a master-slave control method, which is highly dependent on the master phase. A master phase failure will cause the slave phases to malfunction. Furthermore, the hysteresis comparator control with a fixed threshold width causes the switching frequency to vary with the input and output voltages, hindering EMI filter design. Summary of the Invention

[0007] The present invention provides a multi-phase interleaved parallel buck hysteresis comparison control chip and power supply system to solve the problems in the prior art of high dependence on main phase control and switching frequency changes with input and output voltages.

[0008] In order to solve the above technical problems, the present invention is achieved through the following technical solutions:

[0009] According to a first aspect of the present invention, there is provided a multi-phase interleaved parallel buck hysteresis comparison control chip, comprising: a buck converter, a detection circuit, a driver, a hysteresis comparator, and a threshold width control circuit;

[0010] The number of the buck converters is multi-phase, the number of the drivers is multiple, the number of the hysteresis comparators is multiple, the number of the detection circuits is multiple, and the number of the threshold width control circuits is multiple, and the hysteresis controllers, the threshold width control circuits, the drivers, the detection circuits, and the buck converters are in one-to-one correspondence;

[0011] The multi-phase buck converters are designed to be connected in parallel;

[0012] The first input terminal of the hysteresis comparator is connected to the threshold median value, the output terminal of the hysteresis comparator is connected to the input terminal of the driver; the output terminal of the driver is connected to the driving input terminal of the buck converter;

[0013] The output terminals of the multi-phase buck converters are directly or indirectly connected as voltage output terminals;

[0014] The node between the hysteresis comparator and the driver is also connected to the input end of the threshold width control circuit; the second input end of the hysteresis comparator is also connected to the output end of the threshold width control circuit, and the output of the threshold width control circuit serves as half of the threshold width of the hysteresis comparator;

[0015] The threshold width control circuit includes: a phase frequency detector and a charge pump; the input end of the phase frequency detector serves as the input end of the threshold width control circuit, the output end of the phase frequency detector is connected to the input end of the charge pump, and the output end of the charge pump serves as the output end of the threshold width control circuit;

[0016] The buck converter includes: a MOS transistor switch and an inductor; the input end of the MOS transistor switch serves as the driving input end of the buck converter, the output end of the MOS transistor switch is connected to one end of the inductor, and the other end of the inductor serves as the output end of the buck converter;

[0017] The detection circuit is connected in parallel to both ends of the inductor. The detection circuit is configured to generate a feedback voltage in phase with the current of the inductor. The feedback voltage is connected to the third input terminal of the hysteresis comparator.

[0018] Preferably, the reference voltage serves as the threshold median.

[0019] Preferably, the method further comprises: a first voltage loop, wherein the output of the first voltage loop serves as the threshold median;

[0020] The first input terminal of the first voltage loop is connected to a reference voltage, and the second input terminal of the first voltage loop is connected to the voltage output terminal.

[0021] Preferably, the first voltage loop includes: a first error amplifier;

[0022] The first input terminal of the first voltage loop is connected to the reference voltage, and the second input terminal of the first voltage loop is connected to the voltage output terminal. Specifically, the positive input terminal of the first error amplifier is connected to the reference voltage, and the negative input terminal of the first error amplifier is connected to the voltage output terminal.

[0023] The output of the first error amplifier serves as the output of the first voltage loop.

[0024] Preferably, the method further comprises: a first current balancing loop, wherein the output of the first current balancing loop is superimposed with a reference voltage as the threshold median value;

[0025] There are multiple first current sharing rings, each of which corresponds to the buck converter; and the multiple first current sharing rings are connected in parallel via a current sharing bus.

[0026] The input end of the first current sharing ring is connected to the output end of the buck converter.

[0027] Preferably, the first current sharing loop includes: a first current sharing resistor and a second error amplifier;

[0028] The input end of the first current sharing loop is connected to the output end of the buck converter. Specifically, the positive input end of the second error amplifier is connected to the output end of the buck converter through the first current sharing resistor, and the negative input end of the second error amplifier is connected to the output end of the buck converter.

[0029] The output of the second error amplifier serves as the output of the first current sharing loop.

[0030] Preferably, the device further comprises: a second voltage loop and a second current sharing loop, wherein the output of the second voltage loop is superimposed on the output of the second current sharing loop as the threshold median;

[0031] The first input terminal of the second voltage loop is connected to the reference voltage, and the second input terminal of the second voltage loop is connected to the voltage output terminal;

[0032] There are multiple second current sharing rings, each corresponding to the buck converter; the multiple second current sharing rings are connected in parallel via a current sharing bus;

[0033] The input end of the second current sharing loop is connected to the output end of the buck converter.

[0034] Preferably, the second voltage loop includes: a third error amplifier;

[0035] The first input terminal of the second voltage loop is connected to the reference voltage, and the second input terminal of the second voltage loop is connected to the voltage output terminal. Specifically, the positive input terminal of the third error amplifier is connected to the reference voltage, and the negative input terminal of the third error amplifier is connected to the voltage output terminal.

[0036] The output of the third error amplifier serves as the output of the second voltage loop.

[0037] Preferably, the second current sharing loop includes: a second current sharing resistor and the fourth error amplifier;

[0038] The input end of the second current sharing loop is connected to the output end of the buck converter. Specifically, the positive input end of the fourth error amplifier is connected to the output end of the buck converter through the second current sharing resistor, and the negative input end of the fourth error amplifier is connected to the output end of the buck converter.

[0039] The output of the fourth error amplifier serves as the output of the second current sharing loop.

[0040] According to a second aspect of the present invention, a power supply system is provided, comprising: the multi-phase interleaved parallel buck hysteresis comparison control chip described in any one of the above items.

[0041] The multi-phase interleaved parallel buck hysteresis comparator control chip and power supply system provided by the present invention adopt multi-phase parallel buck converters and, through the design of a frequency detector, a phase detector, and a charge pump threshold width control circuit, achieve controllable threshold width of the hysteresis comparator and achieve frequency synchronization of the drive signal with the external clock signal, thereby realizing interleaved parallel connection, solving the problems of unstable switching frequency and high dependence on main phase control in the prior art.

[0042] In an optional solution of the present invention, the error between the reference voltage and the output voltage is amplified and compensated by a voltage loop, and introduced into the threshold median of the hysteresis comparator, thereby eliminating the steady-state error of the output voltage.

[0043] In an optional solution of the present invention, the current difference between each phase is amplified and compensated by a current sharing loop and introduced into the threshold median value of the hysteresis comparator of each phase, thereby eliminating the difference in the average value of the inductor current of each phase. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0045] Figure 1 A circuit diagram of a buck converter in the prior art;

[0046] Figure 2 Schematic diagram of a multi-phase interleaved parallel buck hysteresis comparator control chip according to an embodiment of the present invention;

[0047] Figure 3 is a circuit diagram of a threshold width control circuit according to an embodiment of the present invention;

[0048] Figure 4 This is a circuit diagram of a multi-phase interleaved parallel buck hysteresis comparison control chip according to an embodiment of the present invention;

[0049] Figures 5a-5d A schematic diagram of phase difference and frequency difference when a threshold width control circuit according to an embodiment of the present invention is in operation;

[0050] Figure 6 Schematic diagram of a multi-phase interleaved parallel buck hysteresis comparator control chip according to another embodiment of the present invention;

[0051] Figure 7 Schematic diagram of a multi-phase interleaved parallel buck hysteresis comparator control chip according to another embodiment of the present invention;

[0052] Figure 8 Schematic diagram of a multi-phase interleaved parallel buck hysteresis comparator control chip according to another embodiment of the present invention;

[0053] Description of reference numerals:

[0054] 11- Hysteresis comparator,

[0055] 12-Drive,

[0056] 13-buck converter,

[0057] 14-Detection circuit,

[0058] 15-Threshold width control circuit. DETAILED DESCRIPTION

[0059] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0060] In the description of the specification of the present invention, it should be understood that the orientations or positional relationships indicated by the terms "upper part", "lower part", "upper end", "lower end", "lower surface", "upper surface", etc. are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention.

[0061] In the description of the present invention, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, features specified as "first" or "second" may explicitly or implicitly include one or more of such features.

[0062] In the description of the present invention, "plurality" means multiple, such as two, three, four, etc., unless otherwise clearly defined.

[0063] In the description of the present invention, unless otherwise specified or limited, the term "connection" and other terms should be understood in a broad sense. For example, it can mean fixed connection, detachable connection, or integration; it can mean mechanical connection, electrical connection, or mutual communication; it can mean direct connection or indirect connection through an intermediate medium; it can mean internal communication between two elements or interaction between two elements. For those skilled in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0064] The following specific embodiments are used to describe the technical solution of the present invention in detail. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described in detail in some embodiments.

[0065] In one embodiment, a multi-phase interleaved parallel buck hysteresis comparator control chip is provided, which includes: a hysteresis comparator 11, a driver 12, a buck converter 13, a detection circuit 14, and a threshold width control circuit 15. Figure 2 The number of buck converters 13 is multi-phase, the number of drivers 12 is multiple, the number of hysteresis comparators 11 is multiple, the number of threshold width control circuits 15 is multiple, and the number of detection circuits 14 is multiple. The hysteresis comparators 11, threshold width control circuits 15, drivers 12, and detection circuits 14 correspond to the buck converters 13 one by one. The multi-phase buck converters are designed to be connected in parallel.

[0066] The first input terminal of the hysteresis comparator 11 is connected to the threshold value, and the output terminal V dM The output of the driver 12 is connected to the drive input of the buck converter 13; the output of the multi-phase buck converter is directly or indirectly connected as the voltage output terminal V out The node between the hysteresis comparator 11 and the driver 12 is also connected to the input of the threshold width control circuit 15; the second input of the hysteresis comparator 11 is also connected to the output of the threshold width control circuit 15, and the output Vcp of the threshold width control circuit 15 serves as half of the threshold width of the hysteresis comparator.

[0067] The threshold width control circuit 15 includes: a phase frequency detector (PFD), a charge pump (CP), please refer to Figure 3 、 Figure 4 The input of the phase frequency detector is used as the input of the threshold width control circuit, the output of the phase frequency detector is connected to the input of the charge pump, and the output of the charge pump is used as the output of the threshold width control circuit. In a certain phase control, the phase frequency detector identifies the driving signal V d The phase difference with the external clock signal CLK is used to control the charge and discharge of the charge pump. The output voltage V CP It participates in the control as half of the threshold width of the hysteresis comparator. When the threshold width control circuit is working, the phase difference Δφ=φ CLK -φs and frequency difference Δf=f CLK -fs as Figures 5a-5d As shown in the figure, in terms of frequency and phase, there are four relationships between the drive signal and the external clock at a certain moment t0: (1) the drive signal phase leads and the frequency is high; (2) the drive signal phase leads and the frequency is low; (3) the drive signal phase lags and the frequency is high; (4) the drive signal phase lags and the frequency is low. By charging and discharging the charge pump to change the threshold width, and then adjusting the switching frequency to eliminate the phase difference and frequency difference, the drive signal and the external clock signal are synchronized at the same frequency. After the adjustment is completed, the effect of fixed switching frequency and staggered parallel connection is achieved.

[0068] Buck converter includes: MOS tube switch, inductor L, please refer to Figure 4 The input end of the MOS tube switch serves as the input end of the buck converter. The output end of the MOS tube switch is connected to one end of the inductor L, and the other end of the inductor L serves as the output end of the buck converter. The detection circuit is connected in parallel at both ends of the inductor L. The detection circuit is configured to generate a feedback voltage V in phase with the inductor current. fb , the feedback voltage is connected to the second input terminal of the hysteresis comparator 11.

[0069] In one embodiment, the detection circuit includes: a detection resistor R f , detection capacitance C f , please refer to Figure 4 Detection resistor R f Connect one end of the inductor L to the detection resistor R f The other end is connected to the detection capacitor C f One end of the detection capacitor C f The other end of the inductor L is connected to the other end of the detection resistor R f and the detection capacitor C f The node between is the feedback voltage V fb Output end.

[0070] above Figure 2 In the embodiment, the buck converter is taken as an example of two phases. In different embodiments, it can also be more than two phases. The setting principle is the same as that of the two-phase parallel buck converter, which will not be repeated here.

[0071] above Figure 3 In the embodiment, the buck converter takes four phases as an example. In different embodiments, it can be two phases, three phases, or more than four phases. The setting principle is the same as that of the four-phase parallel buck converter and will not be repeated here.

[0072] In one embodiment, the MOS transistor switch can be a switch composed of PMOS and NMOS, please refer to Figure 4 .

[0073] In one embodiment, the hysteresis comparator can be a hysteresis comparator composed of two comparators and an RS trigger, see Figure 4 .

[0074] In one embodiment, the reference voltage V ref As the median threshold, please refer to Figure 2 、 Figure 4 .

[0075] The threshold median value of the existing hysteresis comparator is fixed. Due to the parasitic equivalent resistance of the power inductor and the switch, the output voltage of the buck converter changes with the load current, and the output voltage has a steady-state error. To solve this problem, in one embodiment, the multi-phase interleaved parallel buck hysteresis comparator control chip also includes: a first voltage loop, the output V ev As the median threshold, please refer to Figure 6 The first input terminal of the first voltage loop is connected to the reference voltage V ref The second input terminal of the first voltage loop is connected to the voltage output terminal V out The error between the reference voltage and the output voltage is amplified and compensated by the voltage loop and introduced into the threshold median of the hysteresis comparator, thereby eliminating the steady-state error of the output voltage. In this embodiment, the multi-phase buck converter shares the same first voltage loop, please refer to Figure 7 .

[0076] In one embodiment, the first voltage loop includes: a first error amplifier Amp, see Figure 6 The first input terminal of the first voltage loop is connected to the reference voltage, and the second input terminal of the first voltage loop is connected to the voltage output terminal. Specifically: the positive input terminal of the first error amplifier is connected to the reference voltage V ref , the inverting input terminal of the first error amplifier is connected to the voltage output terminal V out The output of the first error amplifier serves as the output of the first voltage loop.

[0077] In the multi-phase parallel scheme of master-slave control in the prior art, the drive signal of the slave phase depends on the master phase control. The differences in the circuit parameters and layout of each phase will cause the average value of the inductor current of each phase to be different, affecting the working life of the circuit. In order to solve this problem, in one embodiment, the multi-phase interleaved parallel buck hysteresis comparison control chip also includes: a first current sharing loop, the output V eb The superimposed reference voltage is used as the threshold median value. Please refer to Figure 7 There are multiple first current-sharing loops, each corresponding to a buck converter. These loops are connected in parallel via a current-sharing busbar. The input of each first current-sharing loop is connected to the output of the buck converter. The current difference between the current-sharing busbar and each phase is amplified and compensated, and then introduced into the median threshold of each phase's hysteresis comparator, eliminating differences in the average inductor current across each phase.

[0078] In one embodiment, the first current sharing loop includes: a first current sharing resistor Rb, a second error amplifier Amp, please refer to Figure 7The input of the first current sharing loop is connected to the output of the buck converter. Specifically, the positive input of the second error amplifier is connected to the output of the buck converter through the first current sharing resistor, and the negative input of the second error amplifier is connected to the output of the buck converter. The output of the second error amplifier serves as the output of the first current sharing loop.

[0079] In one embodiment, the multi-phase interleaved parallel buck hysteresis comparison control chip further includes: a second voltage loop and a second current sharing loop. The output of the second voltage loop is superimposed on the output of the second current sharing loop as the threshold median value. Please refer to Figure 8 , which can simultaneously solve the problem of steady-state error of output voltage and different average values ​​of inductor current in each phase. The first input terminal of the second voltage loop is connected to the reference voltage V ref The second input terminal of the second voltage loop is connected to the voltage output terminal V out There are multiple second current sharing rings, each corresponding to a buck converter. Multiple second current sharing rings are connected in parallel via a current sharing busbar CSB. The input end of the second current sharing ring is connected to the output end of the buck converter. In this embodiment, the multi-phase buck converter shares the same second voltage ring. Please refer to Figure 8 .

[0080] In one embodiment, the second voltage loop includes: a third error amplifier Amp, see Figure 8 The first input terminal of the second voltage loop is connected to the reference voltage, and the second input terminal of the second voltage loop is connected to the voltage output terminal. Specifically, the positive input terminal of the third error amplifier is connected to the reference voltage, and the negative input terminal of the third error amplifier is connected to the voltage output terminal; the output of the third error amplifier serves as the output of the second voltage loop.

[0081] In one embodiment, the second current balancing loop includes: a second current balancing resistor R b 、The fourth error amplifier Amp, please refer to Figure 8 The input end of the second current sharing loop is connected to the output end of the buck converter. Specifically, the positive input end of the fourth error amplifier is connected to the output end of the buck converter through the second current sharing resistor, and the negative input end of the fourth error amplifier is connected to the output end of the buck converter. The output of the fourth error amplifier serves as the output of the second current sharing loop.

[0082] In one embodiment, a power supply system is provided, comprising: the multi-phase interleaved parallel buck hysteresis comparison control chip described in any of the above embodiments.

[0083] Throughout this specification, references to terms such as "one embodiment," "an example," "a specific implementation," or "an example" indicate that the specific features, structures, materials, or characteristics described in conjunction with that embodiment or example are included in at least one embodiment or example of the present invention. In this specification, schematic representations of these terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

[0084] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A multi-phase interleaved parallel buck hysteresis comparator control chip, characterized in that: include: Buck converter, detection circuit, driver, hysteresis comparator, threshold width control circuit; The number of the buck converters is multi-phase, the number of the drivers is multiple, the number of the hysteresis comparators is multiple, the number of the detection circuits is multiple, and the number of the threshold width control circuits is multiple, and the hysteresis comparators, the threshold width control circuits, the drivers, the detection circuits, and the buck converters are in one-to-one correspondence; The multi-phase buck converters are designed to be connected in parallel; The first input terminal of the hysteresis comparator is connected to the threshold median value, the output terminal of the hysteresis comparator is connected to the input terminal of the driver; the output terminal of the driver is connected to the driving input terminal of the buck converter; The output terminals of the multi-phase buck converters are directly or indirectly connected as voltage output terminals; The node between the hysteresis comparator and the driver is also connected to the input end of the threshold width control circuit; the second input end of the hysteresis comparator is also connected to the output end of the threshold width control circuit, and the output of the threshold width control circuit serves as half of the threshold width of the hysteresis comparator; The threshold width control circuit includes: a phase frequency detector and a charge pump; the input end of the phase frequency detector serves as the input end of the threshold width control circuit, the output end of the phase frequency detector is connected to the input end of the charge pump, and the output end of the charge pump serves as the output end of the threshold width control circuit; The buck converter includes: a MOS transistor switch and an inductor; the input end of the MOS transistor switch serves as the driving input end of the buck converter, the output end of the MOS transistor switch is connected to one end of the inductor, and the other end of the inductor serves as the output end of the buck converter; The detection circuit is connected in parallel to both ends of the inductor. The detection circuit is configured to generate a feedback voltage in phase with the current of the inductor. The feedback voltage is connected to the third input terminal of the hysteresis comparator.

2. The multi-phase interleaved parallel buck hysteresis comparator control chip according to claim 1, characterized in that: The reference voltage serves as the median of the threshold.

3. The multi-phase interleaved parallel buck hysteresis comparator control chip according to claim 1, characterized in that: Also includes: a first voltage loop, wherein the output of the first voltage loop serves as the threshold median; The first input terminal of the first voltage loop is connected to a reference voltage, and the second input terminal of the first voltage loop is connected to the voltage output terminal.

4. The multi-phase interleaved parallel buck hysteresis comparator control chip according to claim 3, characterized in that: The first voltage loop includes: a first error amplifier; The first input terminal of the first voltage loop is connected to the reference voltage, and the second input terminal of the first voltage loop is connected to the voltage output terminal. Specifically, the positive input terminal of the first error amplifier is connected to the reference voltage, and the negative input terminal of the first error amplifier is connected to the voltage output terminal. The output of the first error amplifier serves as the output of the first voltage loop.

5. The multi-phase interleaved parallel buck hysteresis comparator control chip according to claim 1, characterized in that: Also includes: a first current balancing loop, wherein an output of the first current balancing loop superimposed with a reference voltage serves as the threshold median; There are multiple first current sharing rings, each of which corresponds to the buck converter; and the multiple first current sharing rings are connected in parallel via a current sharing bus. The input end of the first current sharing loop is connected to the output end of the buck converter.

6. The multi-phase interleaved parallel buck hysteresis comparison control chip according to claim 5, characterized in that: The first current sharing loop includes: a first current sharing resistor and a second error amplifier; The input end of the first current sharing loop is connected to the output end of the buck converter. Specifically, the positive input end of the second error amplifier is connected to the output end of the buck converter through the first current sharing resistor, and the negative input end of the second error amplifier is connected to the output end of the buck converter. The output of the second error amplifier serves as the output of the first current sharing loop.

7. The multi-phase interleaved parallel buck hysteresis comparator control chip according to claim 1, characterized in that: Also includes: a second voltage loop and a second current sharing loop, wherein the output of the second voltage loop is superimposed on the output of the second current sharing loop as the threshold median; The first input terminal of the second voltage loop is connected to the reference voltage, and the second input terminal of the second voltage loop is connected to the voltage output terminal; There are multiple second current sharing rings, each corresponding to the buck converter; the multiple second current sharing rings are connected in parallel via a current sharing bus; The input end of the second current sharing loop is connected to the output end of the buck converter.

8. The multi-phase interleaved parallel buck hysteresis comparator control chip according to claim 7, characterized in that: The second voltage loop includes: a third error amplifier; The first input terminal of the second voltage loop is connected to the reference voltage, and the second input terminal of the second voltage loop is connected to the voltage output terminal. Specifically, the positive input terminal of the third error amplifier is connected to the reference voltage, and the negative input terminal of the third error amplifier is connected to the voltage output terminal. The output of the third error amplifier serves as the output of the second voltage loop.

9. The multi-phase interleaved parallel buck hysteresis comparison control chip according to claim 7, characterized in that: The second current sharing loop includes: a second current sharing resistor and a fourth error amplifier; The input end of the second current sharing loop is connected to the output end of the buck converter. Specifically, the positive input end of the fourth error amplifier is connected to the output end of the buck converter through the second current sharing resistor, and the negative input end of the fourth error amplifier is connected to the output end of the buck converter. The output of the fourth error amplifier serves as the output of the second current sharing loop.

10. A power supply, characterized in that: include: The multi-phase interleaved parallel buck hysteresis comparison control chip according to any one of claims 1 to 9.

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