A high-gain miniaturized millimeter-wave low-noise amplifier

Abstract

This invention discloses a high-gain, miniaturized millimeter-wave low-noise amplifier. It includes an input matching network, a noise level circuit, a gain stage circuit, and an output matching network. The low-noise amplifier uses a series gate inductor for noise matching and wide-bandwidth input impedance matching. The gain stage employs a slow-wave transmission line feedback mechanism to achieve high gain and wide bandwidth, and miniaturization is achieved through a spiral inductor and a slow-wave transmission line. The output matching network uses an L-shaped matching network. Unlike traditional inductors or transmission lines, this invention uses a slow-wave transmission line for feedback, achieving high gain while also possessing foldable characteristics and allowing the same inductance value to be achieved with a shorter length, thereby reducing chip area and manufacturing costs.

Description

Technical Field

[0001] This invention relates to the field of millimeter-wave integrated circuits, and more particularly to a high-gain miniaturized millimeter-wave low-noise amplifier. Background Technology

[0002] To meet the growing demands for data transmission and wireless communication, millimeter-wave technology is attracting increasing attention and showing promising development prospects, such as in high-data-rate communication, security inspection, spectroscopy, and radar applications. Within the millimeter-wave frequency band, the D-band (110-170 GHz) is considered a strong candidate for next-generation (6G) communication. Current CMOS processes have cutoff frequencies exceeding 200 GHz, enabling the fabrication of D-band circuits. CMOS technology, with its high integration, low cost, and low power consumption, offers significant advantages in implementing D-band systems.

[0003] Low-noise amplifiers (LNOA) are typically the first stage in the receiving channel. Their function is to amplify the signal received by the antenna. They need to possess high gain, low noise, high linearity, and a large dynamic range to ensure excellent performance of the receiving channel. Currently, the main LNOA structures used are common-gate, common-source, and cascode-source structures. In the D-band, the gain of the common-gate structure is too low to achieve a high-gain, low-noise amplifier. Limited by the low supply voltage of high-node technology, the cascode-source structure cannot achieve good linearity. Therefore, how to achieve a high-gain, miniaturized LNOA based on a common-source structure has become one of the urgent problems to be solved. Summary of the Invention

[0004] Technical problem: To address the issues of low gain and large area in the aforementioned D-band amplifiers, a high-gain miniaturized millimeter-wave low-noise amplifier is proposed, which can effectively improve the amplifier's gain and reduce the circuit area.

[0005] Technical solution: A high-gain miniaturized millimeter-wave low-noise amplifier, comprising an input matching network, a noise level circuit, a gain level circuit, and an output matching network;

[0006] The input matching network consists of a first input matching network capacitor and a gate inductor; one end of the first input matching network capacitor is connected to the input terminal of the low noise amplifier, and the other end is connected to the gate inductor, and the other end of the gate inductor is connected to the gate of the first transistor.

[0007] The noise level circuit consists of a first transistor, a second transistor, a first drain inductor, a second drain inductor, a first interstage matching capacitor, a second interstage matching capacitor, a first resistor, and a second resistor. The sources of the first and second transistors are grounded, and their drains are connected to the first and second drain inductors, respectively. The other ends of the first and second drain inductors are connected to the power supply. The drain of the first transistor is also connected to the first interstage matching capacitor. The other end of the first interstage matching capacitor is connected to the gate of the second transistor. One end of the first and second resistors is connected to the first and second bias voltages, respectively, and the other end is connected to the gates of the first and second transistors, respectively.

[0008] The gain stage circuit consists of a third transistor, a fourth transistor, a fifth transistor, a third main drain inductor, a third secondary drain inductor, a fourth main drain inductor, a fourth secondary drain inductor, a fifth main drain inductor, a fifth secondary drain inductor, a third interstage matching capacitor, a fourth interstage matching capacitor, a first feedback transmission line, a first feedback capacitor, a second feedback transmission line, a second feedback capacitor, a third feedback transmission line, a third feedback capacitor, a third resistor, a fourth resistor, and a fifth resistor. The sources of the third, fourth, and fifth transistors are grounded, and their drains are connected to the third, fourth, and fifth transistors first. The secondary drain inductor is connected to the third, fourth, and fifth main drain inductors at the other end. The other end of the main drain inductor is connected to the power supply. The first, second, and third feedback transmission lines are connected in series with the first, second, and third feedback capacitors, respectively. Then, one end of each line is connected to the gate of the third, fourth, and fifth transistors, and the other end is connected to the connection point of the third, fourth, and fifth main drain inductors and the drain of the third, fourth, and fifth secondary drain inductors. One end of the third, fourth, and fifth resistors is connected to the third, fourth, and fifth bias voltages, respectively, and the other end is connected to the gate of the third, fourth, and fifth transistors, respectively.

[0009] The output matching network uses a series capacitor. One end of the output matching network capacitor is connected to the connection point of the fifth main drain inductor and the fifth secondary drain inductor, and the other end is connected to the output.

[0010] In the gain stage circuit, the first, second, and third feedback transmission lines are all implemented by slow wave transmission lines. The slow wave transmission line is a coplanar waveguide structure with a bottom-layer gate shielding layer, which makes full use of the multi-layer metal layers in the CMOS back-end process. The thick metal at the center top layer is used as the signal line, and the stacked structure of the top layer metal connected to the bottom layer metal through through holes on both sides serves as the ground line. Several metal gates are designed using the bottom layer metal below the signal line and between the two ground lines on both sides. They are arranged regularly perpendicular to the signal transmission direction to form a shielding layer. The two sides of the metal gates are connected to the ground line and grounded.

[0011] The feedback network in the gain stage circuit includes a feedback transmission line and a feedback capacitor.

[0012] The slow-wave transmission line feedback transmission line is implemented using metal lines in integrated circuit technology, and is monolithically integrated using integrated circuit technology.

[0013] Beneficial Effects: The advantages of this invention lie in providing a high-gain, miniaturized millimeter-wave low-noise amplifier, including an input matching network, a noise level circuit, a gain stage circuit, and an output matching network. In the gain stage circuit, a slow-wave transmission line is used to achieve feedback and boost the gain. This design combines the foldable characteristics of a transmission line with higher inductance and quality factor than transmission lines of the same width and length, effectively improving gain while reducing chip area and manufacturing costs. Attached Figure Description

[0014] Figure 1 This is a circuit diagram of the low-noise amplifier in this invention;

[0015] Figure 2 This is a plan view of the feedback transmission line in this invention;

[0016] Figure 3 This is a cross-sectional view of the feedback transmission line in this invention;

[0017] Figure 4 A schematic diagram of a traditional microstrip line inductor structure with the same inductance value;

[0018] Figure 5 The reflection coefficient of the input port of the low-noise amplifier in this invention;

[0019] Figure 6 This is a simulation result of the low-noise amplifier gain in this invention;

[0020] Figure 7 The figure shows the simulation results of the noise figure of the low-noise amplifier in this invention.

[0021] The diagram shows: first input matching network capacitor (Cin), gate inductor (Lg), first transistor (M1), second transistor (M2), first drain inductor (Ld1), second drain inductor (Ld2), first interstage matching capacitor (C1), second interstage matching capacitor (C2), first resistor (R1), second resistor (R2), third transistor (M3), fourth transistor (M4), fifth transistor (M5), third main drain inductor (Ld3), third secondary drain inductor (Ld3'), and fourth main drain inductor (Ld4). The following components are included: fourth auxiliary drain inductor (Ld4'), fifth main drain inductor (Ld5), fifth auxiliary drain inductor (Ld5'), third interstage matching capacitor (C3), fourth interstage matching capacitor (C4), first feedback transmission line (TL1), first feedback capacitor (Cf1), second feedback transmission line (TL2), second feedback capacitor (Cf2), third feedback transmission line (TL3), third feedback capacitor (Cf3), third resistor (R3), fourth resistor (R4), fifth resistor (R5), and output matching network capacitor (Cout). Detailed Implementation

[0022] The present invention will be further explained below with reference to the accompanying drawings and embodiments. The embodiments of the present invention include, but are not limited to, the following embodiments.

[0023] This embodiment provides a high-gain, miniaturized millimeter-wave low-noise amplifier, such as... Figure 1 As shown, it consists of an input matching network, a noise level circuit, a gain level circuit, and an output matching network.

[0024] The input matching network consists of a first input matching network capacitor Cin and a gate inductor Lg; one end of the first input matching network capacitor Cin is connected to the input terminal IN of the low noise amplifier, and the other end is connected to the gate inductor Lg, and the other end of the gate inductor Lg is connected to the gate of the first transistor M1.

[0025] The noise level circuit consists of a first transistor M1, a second transistor M2, a first drain inductor Ld1, a second drain inductor Ld2, a first interstage matching capacitor C1, a second interstage matching capacitor C2, a first resistor R1, and a second resistor R2. The sources of the first and second transistors M1 and M2 are grounded, and their drains are connected to the first and second drain inductors Ld1 and Ld2, respectively. The other ends of the first and second drain inductors Ld1 and Ld2 are connected to the power supply VDD. The drain of the first transistor M1 is also connected to the first interstage matching capacitor C1. The other end of the first interstage matching capacitor C1 is connected to the gate of the second transistor M2. One end of the first and second resistors R1 and R2 are connected to the first and second bias voltages Vbias1 and Vbias2, respectively, and the other end is connected to the gates of the first and second transistors M1 and M2, respectively.

[0026] The gain stage circuit consists of a third transistor M3, a fourth transistor M4, a fifth transistor M5, a third main drain inductor Ld3, a third secondary drain inductor Ld3', a fourth main drain inductor Ld4, a fourth secondary drain inductor Ld4', a fifth main drain inductor Ld5, a fifth secondary drain inductor Ld5', a third interstage matching capacitor C3, a fourth interstage matching capacitor C4, a first feedback transmission line TL1, a first feedback capacitor Cf1, a second feedback transmission line TL2, a second feedback capacitor Cf2, a third feedback transmission line TL3, a third feedback capacitor Cf3, a third resistor R3, a fourth resistor R4, and a fifth resistor R5. The sources of the third, fourth, and fifth transistors M3, M4, and M5 are grounded, and their drains are first connected to the third, fourth, and fifth secondary drain inductors Ld3', Ld4', and Ld5', and then connected to the third, fourth, and fifth secondary drain inductors... The other end of the secondary drain inductor is connected to the third, fourth, and fifth main drain inductors Ld3, Ld4, and Ld5. The other end of the main drain inductor is connected to the power supply VDD. The first, second, and third feedback transmission lines TL1, TL2, and TL3 are connected in series with the first, second, and third feedback capacitors Cf1, Cf2, and Cf3, respectively. Then, one end of each line is connected to the gate of the third, fourth, and fifth transistors M3, M4, and M5, and the other end is connected to the connection point of the third, fourth, and fifth main drain inductors Ld3, Ld4, and Ld5 and the drain is first connected to the third, fourth, and fifth secondary drain inductors Ld3', Ld4', and Ld5'. One end of the third, fourth, and fifth resistors R3, R4, and R5 is connected to the third, fourth, and fifth bias voltages Vbias3, Vbias4, and Vbias5, respectively, and the other end is connected to the gate of the third, fourth, and fifth transistors M3, M4, and M5, respectively.

[0027] In the gain stage circuit, the first, second, and third feedback transmission lines TL1, TL2, and TL3 are all implemented using slow-wave transmission lines. These slow-wave transmission lines have thick ground layers on both sides, with a bottom metal layer stacked to a top metal layer. Below the transmission lines are gates composed of the bottom metal layer. The feedback network in the gain stage circuit includes the feedback transmission lines TL1, TL2, and TL3, and feedback capacitors Cf1, Cf2, and Cf3. The feedback capacitors serve to isolate DC current in the feedback loop.

[0028] The output matching network uses a series capacitor. One end of the output matching network capacitor Cout is connected to the connection point of the fifth main drain inductor Ld5 and the fifth secondary drain inductor Ld5', and the other end is connected to the output OUT.

[0029] In terms of working principle, this invention provides a high-gain, miniaturized millimeter-wave low-noise amplifier. In the gain stage circuit, a slow-wave transmission line is used to achieve feedback and boost the gain. This design combines the foldable characteristics of a transmission line with higher inductance and quality factor than transmission lines of the same width and length, effectively increasing gain while reducing chip area and manufacturing costs. More specifically:

[0030] To achieve a high-gain, low-power, low-noise amplifier, the required transistors in the circuit are small, resulting in a large inductor value in the feedback loop and high requirements for the inductor's quality factor. While traditional spiral inductors can achieve high inductance, they have low self-resonant frequencies, large footprints, and are not conducive to layout. Traditional microstrip lines, although foldable, offer relatively small achievable inductance values. This invention utilizes a slow-wave transmission line to replace the traditional spiral inductor, possessing both the foldability of traditional transmission lines and achieving high inductance, significantly reducing the chip area. Simultaneously, the feedback transmission line implemented with a slow-wave transmission line has a high self-resonant frequency and high quality factor, achieving a significant gain improvement.

[0031] Based on the above working principle, this embodiment designs and simulates the above circuit using 28nm CMOS technology, verifying the practicality of the present invention.

[0032] Figure 2 This is a plan view of the slow-wave transmission line that implements the feedback transmission line in this invention. Figure 3 This is a cross-sectional view of the slow-wave transmission line used to implement the feedback transmission line in this invention. The slow-wave transmission line has a width of 3.1 μm and a length of 95 μm. Figure 4 The diagram shows the structure of a traditional microstrip line with the same inductance. As can be seen, the length of a traditional microstrip line is 140µm for the same width. The feedback transmission line implemented using a slow-wave transmission line reduces the length by 32%.

[0033] Figure 5 The input port reflection coefficient of the designed low-noise amplifier is given, which is less than -10dB in the frequency range of 126-167GHz, and the relative bandwidth reaches 29.3%. Figure 6 The gain of this low-noise amplifier is given; at 140 GHz, the gain of the amplifier is 17.2 dB. Figure 7 The noise figure curve of the low-noise amplifier is presented, showing that the minimum noise figure is achieved at 140 GHz, with a minimum value of 8.8 dB.

[0034] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A high-gain compact millimeter-wave low-noise amplifier characterized by comprising: It includes an input matching network, a noise level circuit, a gain stage circuit, and an output matching network connected in sequence; the gain stage circuit is composed of a third transistor (M3), a fourth transistor (M4), a fifth transistor (M5), a third main drain inductor (Ld3), a third secondary drain inductor (Ld3'), a fourth main drain inductor (Ld4), a fourth secondary drain inductor (Ld4'), a fifth main drain inductor (Ld5), a fifth secondary drain inductor (Ld5'), a third interstage matching capacitor (C3), a fourth interstage matching capacitor (C4), a first feedback transmission line (TL1), a first feedback capacitor (Cf1), a second feedback transmission line (TL2), a second feedback capacitor (Cf2), a third feedback transmission line (TL3), a third feedback capacitor (Cf3), a third resistor (R3), a fourth resistor (R4), and a fifth resistor (R5); The sources of the third, fourth, and fifth transistors (M3, M4, and M5) are grounded. The drains of the third, fourth, and fifth transistors (M3, M4, and M5) are connected to one end of the third, fourth, and fifth secondary drain inductors (Ld3', Ld4', and Ld5'), respectively. The other ends of the third, fourth, and fifth secondary drain inductors are connected to one end of the third, fourth, and fifth main drain inductors (Ld3, Ld4, and Ld5), respectively. The other ends of the third, fourth, and fifth main drain inductors are all connected to the power supply (VDD). The connection point of the third main drain inductor (Ld3) and the third secondary drain inductor (Ld3') is connected to one end of the third interstage matching capacitor (C3), and the other end of the third interstage matching capacitor (C3) is connected to the gate of the fourth transistor (M4); the connection point of the fourth main drain inductor (Ld4) and the fourth secondary drain inductor (Ld4') is connected to one end of the fourth interstage matching capacitor (C4), and the other end of the fourth interstage matching capacitor (C4) is connected to the gate of the fifth transistor (M5); The first feedback transmission line (TL1) is connected in series with the first feedback capacitor (Cf1), with one end connected to the gate of the third transistor (M3) and the other end connected to the connection point of the third main drain inductor (Ld3) and the third secondary drain inductor (Ld3'); the second feedback transmission line (TL2) is connected in series with the second feedback capacitor (Cf2), with one end connected to the gate of the fourth transistor (M4) and the other end connected to the connection point of the fourth main drain inductor (Ld4) and the fourth secondary drain inductor (Ld4'); the third The feedback transmission line (TL3) is connected in series with the third feedback capacitor (Cf3). One end of the feedback transmission line (TL3) is connected to the gate of the fifth transistor (M5), and the other end is connected to the connection point of the fifth main drain inductor (Ld5) and the fifth secondary drain inductor (Ld5'). One end of the third, fourth, and fifth resistors (R3, R4, R5) is connected to the third, fourth, and fifth bias voltages (Vbias3, Vbias4, Vbias5) respectively, and the other end is connected to the gate of the third, fourth, and fifth transistors (M3, M4, M5) respectively. The first, second, and third feedback transmission lines (TL1, TL2, and TL3) in the gain stage circuit are all implemented using slow wave transmission lines.

2. The high-gain miniaturized millimeter-wave low-noise amplifier according to claim 1, characterized in that, The input matching network consists of a first input matching network capacitor (Cin) and a gate inductor (Lg); one end of the first input matching network capacitor (Cin) is connected to the input terminal (IN) of the low noise amplifier, and the other end is connected to the gate inductor (Lg); the other end of the gate inductor (Lg) is connected to the gate of the first transistor (M1). The noise level circuit consists of a first transistor (M1), a second transistor (M2), a first drain inductor (Ld1), a second drain inductor (Ld2), a first interstage matching capacitor (C1), a second interstage matching capacitor (C2), a first resistor (R1), and a second resistor (R2). The sources of the first and second transistors (M1 and M2) are grounded, and their drains are connected to the first and second drain inductors (Ld1 and Ld2), respectively. The other ends of the first and second drain inductors (Ld1 and Ld2) are connected to the power supply (VDD). The drain of the first transistor (M1) is also connected to the first interstage matching capacitor (C1). The other end of the first interstage matching capacitor (C1) is connected to the gate of the second transistor (M2). One end of the first and second resistors (R1 and R2) is connected to the first and second bias voltages (Vbias1 and Vbias2), respectively, and the other end is connected to the gates of the first and second transistors (M1 and M2), respectively. The output matching network uses a series capacitor. One end of the output matching network capacitor (Cout) is connected to the connection point of the fifth main drain inductor (Ld5) and the fifth secondary drain inductor (Ld5'), and the other end is connected to the output (OUT).

3. The high-gain miniaturized millimeter-wave low-noise amplifier according to claim 1, characterized in that, The slow wave transmission line is a coplanar waveguide structure with a bottom layer of grid shielding, including multiple metal layers. The thick metal in the center top layer is used as a signal line, and the two sides are connected to the bottom layer of metal through through holes to form a stacked structure as ground lines. Several metal grids are designed in the bottom layer of metal below the signal line and between the two ground lines. They are arranged regularly perpendicular to the signal transmission direction to form a shielding layer. The two sides of the metal grids are connected to the ground lines and grounded.

4. The high-gain miniaturized millimeter-wave low-noise amplifier according to claim 1, characterized in that, The feedback network in the gain stage circuit includes first, second, and third feedback transmission lines (TL1, TL2, TL3) and first, second, and third feedback capacitors (Cf1, Cf2, Cf3).

5. The high-gain miniaturized millimeter-wave low-noise amplifier according to claim 1, characterized in that, The first, second, and third feedback transmission lines (TL1, TL2, and TL3) are all implemented using metal lines in integrated circuit technology and are monolithically integrated using integrated circuit technology.

6. A method for implementing the high-gain miniaturized millimeter-wave low-noise amplifier according to any one of claims 1-5, characterized in that, The aforementioned low-noise amplifier is implemented using CMOS technology.

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