Reference sampling phase-locked loop applied to low-voltage mode

Abstract

The application discloses a reference sampling phase-locked loop applied to a low-voltage mode, comprising a reference sampling phase detector, a low-pass filter, a voltage-controlled oscillator, a frequency divider module, a clock generator and a high-level voltage boosting inverter connected in sequence. On the basis of the existing reference sampling phase-locked loop, the high-level voltage boosting inverter is added, the sampling and holding switch is optimized, the on-resistance of the sampling switch is greatly reduced, the time constant of sampling under low voltage is reduced, the normal sampling and holding functions of the sampler under low voltage are ensured, meanwhile, a larger sampling capacitor is allowed to be used to improve noise, the normal sampling work and superior clock jitter performance of the phase-locked loop under low voltage are realized; and the low-pass filter is added to the output end of the reference sampling phase detector, a high-frequency pole is introduced, the reference spur is improved without affecting the phase margin, and the performance of the circuit is improved.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor integrated circuit technology, and specifically relates to a reference sampling phase-locked loop applied in low-voltage mode. Background Technology

[0002] To meet the demands of ever-increasing communication data transmission, phase-locked loops (PLLs) with better spectral purity are presenting new dimensions. Performance metrics such as clock jitter, spurious emissions, phase noise, power consumption, and area are all critical. Traditional charge-pump phase-locked loops (CPPLLs) struggle to meet these stringent requirements. To achieve better jitter performance, the dead time must be set smaller to reduce in-band phase noise (IPN). However, this is limited by its over-reliance on advanced processes, which comes at the cost of significant power consumption and filter area. Furthermore, matching the charge pump is difficult to achieve at low voltages. Sub-sampling phase-locked loops (SSPLLs) offer better jitter performance, but their limited number of dividers and structural stability issues due to high-frequency operation make them less practical.

[0003] The emergence of the Reference Sampling Phase-Locked Loop (RSPLL) solved the aforementioned problems. Its high loop gain and simple loop structure made it possible to replace the CPCPLL. Furthermore, the sampling phase of the RSPLL operates near the reference frequency, further enhancing its structural robustness, and it can be locked without additional auxiliary loops. However, designing a low-jitter, low-power RSPLL in 180nm CMOS technology is challenging.

[0004] In terms of power consumption, one effective method is to reduce the supply voltage. However, this also leads to a significant degradation in circuit performance, resulting in a smaller gain factor for the phase detector, increased phase noise of the VCO, and increased on-resistance R of the sampler when operating at low voltage. ON The sampling time constant τ increases, even due to the inherent V of the MOSFET under low voltage. TH This causes the tube to enter the subsaturation region, which greatly reduces the sampling accuracy. Furthermore, the on-resistance R... ON The sampling time constant varies with Vin, making it inaccurate and preventing the sampler from performing its normal sample-and-hold function. Consequently, the reference sampling phase-locked loop (PLL) cannot function properly. Furthermore, only a smaller sampling capacitor can be used to maintain the sampling time constant, which is much smaller than the reference period τ = R*C << T. REFThis leads to a deterioration of sampling thermal noise. Furthermore, under low-voltage operation, the reduction in power consumption of digital circuits comes at the cost of reduced operating speed, which prevents the frequency divider from performing its normal frequency division function at high frequencies, thus limiting the operating frequency of the phase-locked loop. Summary of the Invention

[0005] To address the aforementioned problems in the prior art, this invention provides a reference sampling phase-locked loop (PLL) applied in low-voltage mode. The technical problem to be solved by this invention is achieved through the following technical solution:

[0006] A reference sampling phase-locked loop for low-voltage mode includes a reference sampling phase detector, a low-pass filter, a voltage-controlled oscillator, a frequency divider module, a clock generator, and a high-level boost inverter connected in sequence.

[0007] The reference sampling phase detector is used to analyze the input reference signal f. ref Sample-and-hold tracking is performed to obtain the sampled output voltage V. smp ;

[0008] The low-pass filter is used to filter the sampled output voltage V. smp After performing low-pass filtering, the voltage signal V with reduced ripple is obtained. c ;

[0009] The voltage-controlled oscillator is used to adjust the voltage signal V. c Generate output signal f out And serve as the output signal of the entire reference sampling phase-locked loop;

[0010] The frequency divider module is used to divide the output signal f out Frequency division is performed to obtain the frequency-divided output signal f. div ;

[0011] The clock generator is used to divide the frequency output signal f. div Perform timing processing to output the first narrow pulse signal V1 and the second narrow pulse signal V2;

[0012] The high-level boost inverter is used to boost the first narrow pulse signal V1 and the second narrow pulse signal V2 to obtain the first feedback clock signal CK1 and the second feedback clock signal CK2, which are then fed back to the reference sampling phase detector until the output signal f is obtained. out and the reference signal f ref The phases are equal to achieve the phase locking function of the phase-locked loop.

[0013] In one embodiment of the present invention, the reference sampling phase detector includes a first sampling switch, a second sampling switch, a first sampling capacitor, and a second sampling capacitor; wherein,

[0014] The first sampling switch and the second sampling switch are connected in series, and the first terminal of the first sampling switch is used as the reference signal f. ref The second terminal of the second sampling switch serves as the input terminal of the reference sampling phase detector;

[0015] The first sampling capacitor is connected between the second terminal of the first sampling switch and the ground terminal, and the second sampling capacitor is connected between the second terminal of the second sampling switch and the ground terminal;

[0016] The first sampling switch is turned on or off according to the first feedback clock signal CK1, and the second sampling switch is turned on or off according to the second feedback clock signal CK2.

[0017] In one embodiment of the present invention, the low-pass filter is a passive filter, a switched capacitor filter, or an active filter.

[0018] In one embodiment of the present invention, the frequency divider module includes a first frequency divider and a second frequency divider; the input terminal of the first frequency divider is connected to the output terminal of the voltage-controlled oscillator, and the output terminal of the second frequency divider is connected to the input terminal of the clock generator; wherein...

[0019] The first frequency divider is an injection-locked frequency divider, a current-mode logic frequency divider, a true single-phase clock trigger frequency divider, or a Miller frequency divider.

[0020] In one embodiment of the present invention, the first frequency divider is a current-mode logic quad divider, used to divide the output signal f out Perform a frequency division by four to obtain the frequency-divided output signal f1;

[0021] The second frequency divider is a multi-mode programmable frequency divider, used to divide the four-way frequency-divided output signal f1 to obtain the frequency-divided output signal f, which serves as the feedback signal of the phase-locked loop. div .

[0022] In one embodiment of the present invention, the clock generator is a two-phase non-overlapping clock generator, used to divide the output signal f. div Timing processing is performed to generate a first narrow pulse signal V1 and a second narrow pulse signal V2, which are two non-overlapping phases operating at the frequency division.

[0023] In one embodiment of the present invention, the high-level boost inverter includes a first MOSFET, a second MOSFET, a third MOSFET, a fourth MOSFET, a first capacitor, a second capacitor, and an inverter, wherein,

[0024] The drains of both the first MOSFET and the second MOSFET are connected to the power supply.

[0025] The gate of the first MOS transistor is connected to the source of the second MOS transistor, the source of the third MOS transistor, and the first plate of the second capacitor, respectively.

[0026] The source of the first MOS transistor is connected to the gate of the second MOS transistor and the first plate of the first capacitor;

[0027] The drain of the third MOS transistor is connected to the drain of the fourth MOS transistor; the gate of the third MOS transistor is connected to the gate of the fourth MOS transistor, the second plate of the first capacitor, and the input terminal of the inverter.

[0028] The source of the fourth MOS transistor is connected to the ground terminal;

[0029] The second plate of the second capacitor is connected to the output terminal of the inverter;

[0030] The gate of the third MOS transistor serves as the input terminal of the high-level boost inverter, and the drain of the third MOS transistor serves as the output terminal of the high-level boost inverter.

[0031] The beneficial effects of this invention are:

[0032] 1. Based on the existing reference sampling phase-locked loop, this invention adds a high-level boost inverter, optimizes the sampling and holding switch, greatly reduces the on-resistance of the sampling switch, reduces the sampling time constant under low voltage, ensures the normal sampling and holding function of the sampler under low voltage, and allows the use of a larger sampling capacitor to improve noise, thus realizing the normal sampling operation of the phase-locked loop under low voltage and excellent clock jitter performance.

[0033] 2. The reference sampling phase-locked loop proposed in this invention improves the reference spurious emissions and enhances the circuit performance by adding a low-pass filter to the output of the reference sampling phase detector and introducing high-frequency poles without affecting the phase margin.

[0034] 3. This invention uses a current-mode logic quad divider to reduce the operating frequency required by the multi-mode programmable divider, solving the problem of reduced divider operating speed due to low-voltage operation, and realizing normal operation of the reference sampling phase-locked loop under low voltage and superior spurious and clock jitter performance.

[0035] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0036] Figure 1 This is a structural block diagram of a reference sampling phase-locked loop applied in low-voltage mode provided by an embodiment of the present invention;

[0037] Figure 2This is a detailed structural diagram of a reference sampling phase-locked loop applied in low-voltage mode, provided by an embodiment of the present invention;

[0038] Figure 3 This is a circuit diagram of the reference sampling phase detector provided in an embodiment of the present invention;

[0039] Figure 4 This is a comparison diagram of the on-resistance of a traditional RSPD and the RSPD of this invention;

[0040] Figure 5 This is a PVT simulation result diagram of the on-resistance of the sampling switch driven by HBINV provided in an embodiment of the present invention;

[0041] Figure 6 This is a circuit diagram and tuning curve diagram of a voltage-controlled oscillator provided in an embodiment of the present invention;

[0042] Figure 7 This is a circuit diagram of the frequency divider module provided in an embodiment of the present invention;

[0043] Figure 8 This is a circuit diagram of a high-level boost inverter provided in an embodiment of the present invention;

[0044] Figure 9 This is a waveform diagram of the input and output of a high-level boost inverter provided in an embodiment of the present invention. Detailed Implementation

[0045] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0046] Example 1

[0047] Please see Figure 1 , Figure 1 This is a structural block diagram of a reference sampling phase-locked loop applied in low-voltage mode provided by an embodiment of the present invention. It includes a reference sampling phase detector (RSPD), a low-pass filter (LPF), a voltage-controlled oscillator (VCO), a frequency divider module (DIV), a clock generator, and a high-level boost inverter (HBINV) connected in sequence.

[0048] The reference sampling phase detector is used to sample the input reference signal f. ref Sample-and-hold tracking is performed to obtain the sampled output voltage V. smp ;

[0049] A low-pass filter is used to sample the output voltage V. smp After performing low-pass filtering, the voltage signal V with reduced ripple is obtained. c ;

[0050] A voltage-controlled oscillator is used to determine the voltage signal V. c Generate output signal f out And serve as the output signal of the entire reference sampling phase-locked loop;

[0051] The frequency divider module is used to divide the output signal f out Frequency division is performed to obtain the frequency-divided output signal f. div ;

[0052] The clock generator is used to divide the output signal f. div Perform timing processing to output the first narrow pulse signal V1 and the second narrow pulse signal V2;

[0053] The high-level boost inverter is used to boost the first narrow pulse signal V1 and the second narrow pulse signal V2, corresponding to the first feedback clock signal CK1 and the second feedback clock signal CK2, which are then fed back to the reference sampling phase detector until the output signal f is obtained. out and reference signal f ref The phases are equal to achieve the phase locking function of the phase-locked loop.

[0054] For details, please see Figure 2 , Figure 2 This is a detailed structural diagram of a reference sampling phase-locked loop (RSPD) applied in low-voltage mode, provided by an embodiment of the present invention. The sampling input terminal of the RSPD is connected to the input reference signal f. ref The two clock signal inputs are connected to the outputs of the two Nonoverlap Clock Generation circuits, and the sampling output is connected to the input of the LPF. The input of the LPF is connected to the sampling output of the RSPD, and its output is connected to the control voltage input of the VCO. The control voltage input of the VCO is connected to the output of the LPF, and its output is connected to the input of the DIV circuit. The VCO's output signal f... out The clock signal is used as the output of the phase-locked loop. The output of DIV is connected to the input of the clock generator, and the two non-overlapping two-phase outputs are respectively connected to the inputs of the two identical HBINVs. The inputs of the two identical HBINVs are respectively connected to the two non-overlapping two-phase outputs of the clock generator, and the outputs are respectively connected to the two feedback clock signal inputs of RSPD.

[0055] This invention adds a high-level boost inverter to the existing reference sampling phase-locked loop, optimizes the sampling and holding switch, greatly reduces the on-resistance of the sampling switch, reduces the time constant of sampling under low voltage, ensures the normal sampling and holding function of the sampler under low voltage, and allows the use of a larger sampling capacitor to improve noise, thus realizing normal sampling operation of the phase-locked loop under low voltage and excellent clock jitter performance.

[0056] For further details, please see Figure 3 , Figure 3 This is a circuit diagram of a reference sampling phase detector provided in an embodiment of the present invention. In this embodiment, the reference sampling phase detector includes a first sampling switch S1, a second sampling switch S2, and a first sampling capacitor C. S Second sampling capacitor C H ;in,

[0057] The first sampling switch S1 and the second sampling switch S2 are connected in series, and the first terminal of the first sampling switch S1 is used as the reference signal f. ref The input terminal of the second sampling switch S2 is used as the output terminal of the reference sampling phase detector;

[0058] First sampling capacitor C S The second sampling capacitor C is connected between the second terminal of the first sampling switch S1 and the ground terminal. H Connected between the second terminal of the second sampling switch S2 and the ground terminal;

[0059] The first sampling switch S1 is turned on or off according to the first feedback clock signal CK1, and the second sampling switch S2 is turned on or off according to the second feedback clock signal CK2.

[0060] Specifically, in this embodiment, MOS transistors NM1 and NM2 are used as the first sampling switch S1 and the second sampling switch S2, respectively.

[0061] The working principle of the RSPD provided in this embodiment is as follows:

[0062] The first feedback clock signal CK1 and the second feedback clock signal CK2, operating at the MMDIV output frequency, are used as sampling signals, f ref As the input reference signal, the first sampling switch S1 and the second sampling switch S2 are sampling switches for master-slave two-stage sampling, respectively, and the first sampling capacitor C S Second sampling capacitor C H These are the sampling capacitors for the master and slave sampling stages, and the sampled output signal V. S and sampled output signal V H These are the sampled output signals from the master and slave sampling stages, respectively. The feedback clock signals CK1 and CK2 and the reference signal f are also included. refThe phase difference represents the phase difference between the feedback signal and the reference signal of the reference sampling phase-locked loop. It is converted into a voltage signal by the tracking and holding sampler. Reference sampling means that the sampling frequency is the reference frequency.

[0063] When the rising edge of the first feedback clock signal CK1 crosses zero and the reference signal f ref When the rising edge is aligned, the phase difference is 0, and the second feedback clock signal CK2 samples the output signal V of the main sampler. S Further sampling yields the sampled output signal V. H At this time, the sampled output signal V H The voltage value after passing through the LPF is equal to the control voltage required after the voltage-controlled oscillator is locked.

[0064] When the first feedback clock signal CK1 and the second feedback clock signal CK2 lag behind the reference signal f ref At this point, the phase difference is not zero, and the resulting sampled output signal V H The voltage value after passing through the LPF is less than the control voltage required after the voltage-controlled oscillator is locked.

[0065] When the first feedback clock signal CK1 and the second feedback clock signal CK2 lead the reference signal f ref At this point, the phase difference is not zero, and the resulting sampled output signal V H The voltage value after passing through the LPF is greater than the control voltage required after the voltage-controlled oscillator is locked.

[0066] For further details, please continue to see Figure 2 The output of the RSPD is connected to an LPF for sampling the output signal V. smp After low-pass filtering, the corresponding voltage signal V is obtained. c .

[0067] Optionally, the LPF in this embodiment can be a passive filter, a switched capacitor filter, or an active filter; no limitation is imposed here. Optionally, the low-pass filter can be a first-order low-pass filter, or it can be a low-pass filter of other orders; the specific order is not limited here.

[0068] In this embodiment, as Figure 2 As shown, the LDF includes a filter resistor R3 and a filter capacitor C3. One end of resistor R3 is connected to the output terminal of RSPD, and the other end is grounded through capacitor C3. The common terminal of resistor R3 and capacitor C3 serves as the output terminal of the LDF, used to output the voltage signal V with reduced ripple. c .

[0069] This embodiment adds an LPF at the output of the RSPD to introduce high-frequency poles, thereby improving reference spurious emissions and enhancing the performance of the reference sampling phase-locked loop without affecting the phase margin. The specific principle is as follows: Let the LPF be a first-order filter with the following transfer function: Then high-frequency poles are introduced. Where s is the complex frequency, R3 is the filter resistor, and C3 is the filter capacitor, to achieve the function of low-pass filtering. Then, at the high-frequency pole ω... p At that frequency, the slope of the amplitude curve changes by an additional -20 dB / dec, thus enhancing the suppression of high-frequency noise. Assume a loop contains a zero ω. z and the two poles ω p1 ω p2 Then the phase margin is:

[0070]

[0071] As can be seen from the phase margin formula PM, when the high-frequency pole ω p Much larger than the phase-locked loop bandwidth ω c When, the high-frequency pole ω p It does not affect the phase margin of the phase-locked loop.

[0072] To verify the beneficial effects of the circuit of this invention, the on-resistance of a traditional RSPD and the RSPD designed in this embodiment are compared below. Furthermore, the PVT of the on-resistance of the sampling switch driven by HBINV is simulated, and the results are as follows: Figure 4 and Figure 5 As shown, where, Figure 4 The comparison diagram of the on-resistance of the conventional RSPD and the RSPD provided in the embodiment of the present invention shows that the on-resistance of the RSPD proposed in this invention is much smaller than that of the conventional RSPD. Figure 5 The PVT simulation results for the on-resistance of the sampling switch driven by HBINV are shown. It can be seen that the on-resistance of the sampling switch can be maintained at a low resistance state in the range of 0.1-0.9V.

[0073] For further details, please see Figure 6 , Figure 6 This is a circuit diagram and tuning curve of a voltage-controlled oscillator provided in an embodiment of the present invention. To achieve oscillation stability, this embodiment employs a complementary cross-coupled NMOS and PMOS VCO, such as... Figure 6 The left figure is shown in the diagram. Simultaneously, the tail current source was removed to obtain a larger amplitude, thereby reducing phase noise. The VCO tuning curve is shown in the diagram. Figure 6 As shown in the right figure, it can be seen that the VCO used has good frequency continuity and linearity in the range of 4.02 to 5.09 GHz.

[0074] In this embodiment, the frequency divider module includes a first frequency divider and a second frequency divider; the input terminal of the first frequency divider is connected to the output terminal of the voltage-controlled oscillator, and the output terminal of the second frequency divider is connected to the input terminal of the clock generator; wherein,

[0075] The first frequency divider can be an injection-locked frequency divider, a current-mode logic frequency divider, a true single-phase clock trigger frequency divider, or a Miller frequency divider.

[0076] Alternatively, as one implementation method, such as Figure 7 As shown, the first frequency divider in this embodiment is a current-mode logic quad-divider (CML_DIV4) used to divide the output signal f. out The frequency is divided by four to obtain a divided-frequency output signal f1; the second frequency divider is a multimode programmable frequency divider (MMDIV) used to divide the divided-frequency output signal f1 to obtain a divided-frequency output signal f that serves as the phase-locked loop feedback signal. div .

[0077] This invention employs a current-mode logic quad divider to reduce the operating frequency required by the multi-mode programmable divider, solving the problem of reduced divider operating speed due to low-voltage operation. It also enables the reference sampling phase-locked loop to operate normally under low voltage and achieves superior spurious and clock jitter performance.

[0078] Furthermore, it should be noted that the clock generator in this embodiment is a two-phase nonoverlap clock generator, whose input is connected to the output of MMDIV and whose output is connected to the two HBINVs respectively.

[0079] Specifically, the Nonoverlap Clock Generation performs timing processing on the frequency division output signal to obtain a first two-phase non-overlapping narrow pulse signal V1 and a second two-phase non-overlapping narrow pulse signal V2; the first two-phase non-overlapping narrow pulse signal V1 is boosted by the corresponding HBINV to obtain a first feedback clock signal CK1; the second two-phase non-overlapping narrow pulse signal V2 is boosted by the corresponding HBINV to obtain a second feedback clock signal CK2; the first feedback clock signal CK1 and the second feedback clock signal CK2 are respectively input to the two feedback clock signal input terminals of RSPD.

[0080] In this embodiment, the first two-phase non-overlapping narrow pulse signal V1 and the second two-phase non-overlapping narrow pulse signal V2 operate at the frequency division, and the first feedback clock signal CK1 and the second feedback clock signal CK2 are two-phase non-overlapping narrow pulse signals with high swing amplitude obtained under low voltage.

[0081] For further details, please see Figure 8 , Figure 8 This is a circuit diagram of a high-level boost inverter provided in an embodiment of the present invention, which includes a first MOSFET M1, a second MOSFET M2, a third MOSFET M3, a fourth MOSFET M4, a first capacitor C1, a second capacitor C2, and an inverter, wherein...

[0082] The drains of the first MOSFET M1 and the second MOSFET M2 are both connected to the power supply.

[0083] The gate of the first MOSFET M1 is connected to the source of the second MOSFET M2, the source of the third MOSFET M3, and the first plate of the second capacitor C2, respectively.

[0084] The source of the first MOSFET M1 is connected to the gate of the second MOSFET M2 and the first plate of the first capacitor C1;

[0085] The drain of the third MOSFET M3 is connected to the drain of the fourth MOSFET M4; the gate of the third MOSFET M3 is connected to the gate of the fourth MOSFET M4, the second plate of the first capacitor C1, and the input terminal of the inverter.

[0086] The source of the fourth MOSFET M4 is connected to the ground terminal;

[0087] The second plate of the second capacitor C2 is connected to the output terminal of the inverter.

[0088] The gate of the third MOSFET M3 serves as the input terminal of the high-level boost inverter, and the drain of the third MOSFET M3 serves as the output terminal of the high-level boost inverter.

[0089] The working principle of HBINV in this embodiment is as follows:

[0090] HBINV boosts the high level of the feedback clock signal when the power supply voltage is low, significantly reducing the on-resistance R of the sampling switches S1 and SS2 in the reference sampling phase detector RSPD. ON This makes the time constant τ = R of the sampling switch and sampling capacitor. ON *C S Much smaller than the reference clock period T REF This enables normal sampling functionality. The same sampling switch size achieves a smaller R0. ON This allows for the use of larger capacitors to reduce sampling noise caused by the sampling capacitor, achieving superior in-band noise performance at low voltage.

[0091] like Figure 9 The input / output waveforms of HBINV are shown below. First, determine the potentials at points a and b. Assume both a and b are 0. When the rising edge of the IN signal arrives, the voltage across the capacitor will not change abruptly. The voltage at point a will rise, turning on transistor M2 and charging capacitor C2. The voltage at point b will begin to rise, turning on transistor M1 and charging capacitor C1. This process is positive feedback. Eventually, the charging process brings the voltages at points a and b to VDD. At this point, the charging preparation process is complete. When the rising edge of the IN signal arrives again, the voltage at point a will rise to 2*VDD. Although the potential at point b is momentarily lowered, transistor M2 remains on, charging capacitor C2 until the potential at point b reaches VDD. Similarly, when the falling edge of the IN signal arrives, the voltage at point b will rise to (1+m)*VDD. The potential at point a will momentarily lower, but transistor M1 remains on, charging capacitor C1. １ Charging brings the potential at point a to VDD. Therefore, under normal operating conditions, V... a V b One is VDD, and the other is a voltage higher than VDD. Their input and output waveforms are as follows: Figure 9 As shown.

[0092] The voltage boost factor m is approximately:

[0093]

[0094] ① When the input IN of HBINV changes from "0" to "VDD", M4 goes from off to on, and M3 goes from on to off. The output OUT is discharged and eventually becomes 0. Simultaneously, V... a The voltage bootstrap effect of capacitor C1 achieves 2*VDD, V b Reset to VDD.

[0095] ② When the input IN of HBINV changes from "VDD" to "0", M4 changes from on to off, and M3 changes from off to on. Simultaneously, V... a The voltage is reset to VDD. Because transistor M3 is on and there is no discharge path for output OUT, V... b The high-level voltage (1+m)*VDD is achieved through the voltage bootstrap effect of capacitor C2, and at the same time, the output OUT is charged to the high-level voltage (1+m)*VDD, thus realizing the high-level boost function of HBINV.

[0096] In this embodiment, HBINV is used to reduce the on-resistance R of the sampling switch. ON This enables the sampler to maintain normal sampling and holding functionality under low voltage conditions. The specific principle is as follows:

[0097] The on-resistance of the sampling switch is:

[0098]

[0099] Where, μ n For electron mobility, C ox The capacitance per unit area of ​​the gate oxide layer. V represents the aspect ratio of the sampling switch. GS V is the gate-source voltage of the MOSFET in the sampling switch, which is also the sampling voltage of the sampler. TH This represents the threshold voltage of the MOSFET in the sampling switch. HBINV increases V in the formula by boosting the sampling voltage. GS This reduces the on-resistance R. ON .

[0100] When the sampling switch is turned on, the time required for the output voltage to rise from zero to the maximum input level is the speed measurement standard, which can be expressed by the time constant τ = R. ON *C S To describe, C S The value of the sampling capacitor is τ. If the sampling speed is not fast enough, that is, if the time constant τ is not much smaller than the sampling time, the input signal cannot be completely sampled within the sampling time, leading to distortion of the sampled output. According to the formula for the time constant τ, without changing the sampling capacitor C... S When the on-resistance R is reduced, ON The sampling rate can be increased to achieve normal sampling functionality. In RSPLL, the sampling time is typically the reference period or the high-level pulse width of the sampled signal.

[0101] The on-resistance R of the sampling switch ON Introduced resistive thermal noise Where K is the Boltzmann constant, T is the temperature, and C is the temperature. S Let be the size of the sampling capacitor. To reduce noise, the sampling capacitor must be large enough, but this will cause a time constant τ = R. ON *C S The increase in resistance R reduces the sampling rate. ON Noise can be reduced by increasing the sampling capacitor without increasing the time constant τ.

[0102] The working principle of the low-jitter RSPLL overall architecture applied in low-voltage mode provided in this embodiment is as follows:

[0103] First, the high-swing two-phase non-overlapping narrow pulse signals CK1 and CK2, boosted by HBINV, are used to input the reference signal f via RSPD. ref Sample-and-hold tracking is performed to obtain the sampled output voltage V. smp The LPF samples the output signal V. smp After performing low-pass filtering, the voltage signal V with reduced ripple is obtained.c The filter's output voltage V c The output frequency of the VCO is controlled by the control voltage of the VCO, resulting in the output signal f. out The output signal f of the oscillator out After being divided by four by CML_DIV4, the divided-four output signal f1 is obtained. The divided-four output signal f1 is then divided by the multi-mode programmable frequency divider MMDIV to obtain the divided-frequency output signal f, which serves as the feedback signal for the phase-locked loop. div The frequency-divided output signal FDIV undergoes timing processing by the Nonoverlap Clock Generation to generate two non-overlapping narrow pulse signals V1 and V2 operating at the divided frequency. These two non-overlapping narrow pulse signals V1 and V2 are then boosted by the HBINV to obtain high-swing two-phase non-overlapping narrow pulse signals CK1 and CK2 at low voltage. The phase-locked loop (PLL) operates cyclically through negative feedback, following the above process, until the VCO output voltage f is achieved. out and input reference signal f ref When the phases are equal, the phase-locked loop (PLL) achieves its phase-locking function.

[0104] This invention adds a high-level boost inverter to the existing reference sampling phase-locked loop, optimizes the sampling and holding switch, greatly reduces the on-resistance of the sampling switch, reduces the time constant of sampling under low voltage, ensures the normal sampling and holding function of the sampler under low voltage, and allows the use of a larger sampling capacitor to improve noise, thus realizing normal sampling operation of the phase-locked loop under low voltage and excellent clock jitter performance.

[0105] This invention utilizes a 0.18μm CMOS process to fabricate a reference sampling phase-locked loop with an operating frequency of 4.02GHz-5.09GHz, an operating voltage of 1V-1.8V, a clock jitter of 168fs, and a reference spurious signal of -76dBc, achieving superior performance with low voltage, low spurious signal, and low jitter.

[0106] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A reference sampling phase-locked loop applied in a low-voltage mode, characterized in that, It includes a reference sampling phase detector, a low-pass filter, a voltage-controlled oscillator, a frequency divider module, a clock generator, and a high-level boost inverter connected in sequence. The reference sampling phase discriminator is used for sampling and holding tracking of the input reference signal to obtain a sampling output voltage ; The low pass filter is used to low pass filter the sampled output voltage to obtain a voltage signal with reduced ripple ; The voltage-controlled oscillator is used to adjust according to the voltage signal. Generate output signal And serve as the output signal of the entire reference sampling phase-locked loop; The frequency divider module is used to divide the output signal Frequency division is performed to obtain the frequency-divided output signal. ; The clock generator is used to divide the frequency output signal. Perform timing processing to output the first narrow pulse signal. Second narrow pulse signal ; The high-level boost inverter is used to process the first narrow pulse signal. and the second narrow pulse signal The voltage is boosted, which corresponds to the first feedback clock signal. Second feedback clock signal And feed it back to the reference sampling phase detector until the output signal and the reference signal The phases are equal to achieve the phase locking function of the phase-locked loop; The high-level boost inverter includes a first MOS transistor ( ), second MOS transistor ( ), third MOS transistor ( ), fourth MOS transistor ( ), first capacitor ( ), second capacitor ( ) and inverter, where, The first MOS transistor ( The drain of the second MOS transistor and the second MOS transistor The drains of all components are connected to the power supply. The first MOS transistor ( The gates of the two transistors are respectively connected to the gates of the second MOS transistor. The source of the third MOS transistor. The source of the second capacitor and the second capacitor The first plate of the electrode; The first MOS transistor ( The source of ) is connected to the second MOS transistor ( The gate of ) and the first capacitor ( The first plate of the electrode; The third MOS transistor ( The drain of the fourth MOS transistor is connected to the fourth MOS transistor. The drain of the third MOS transistor; The gates of the four MOS transistors are respectively connected to the gates of the four MOS transistors. The gate of ) and the first capacitor ( The second electrode plate and the input terminal of the inverter; The fourth MOS transistor ( The source terminal of the device is connected to the ground terminal; The second capacitor ( The second electrode plate is connected to the output terminal of the inverter; The third MOS transistor ( The gate of the third MOS transistor serves as the input terminal of the high-level boost inverter. The drain of the inverter is used as the output terminal of the high-level boost inverter.

2. The reference sampling phase-locked loop applied in low-voltage mode according to claim 1, characterized in that, The reference sampling phase detector includes a first sampling switch ( ), second sampling switch ( ), first sampling capacitor ( ) and second sampling capacitor ( );in, The first sampling switch ( ) and the second sampling switch ( ) in series, and the first sampling switch ( The first end of the signal is used as the reference signal. The input terminal, the second sampling switch ( The second end serves as the output of the reference sampling phase detector; The first sampling capacitor ( ) connected to the first sampling switch ( Between the second terminal of the second sampling capacitor and the ground terminal, the second sampling capacitor ( ) connected to the second sampling switch ( The second terminal of the device is connected to the grounding terminal; The first sampling switch ( According to the first feedback clock signal To enable or disable the second sampling switch ( According to the second feedback clock signal Enables turning on or off.

3. The reference sampling phase-locked loop applied in low-voltage mode according to claim 1, characterized in that, The low-pass filter is a passive filter, a switched-capacitor filter, or an active filter.

4. The reference sampling phase-locked loop applied in low-voltage mode according to claim 1, characterized in that, The frequency divider module includes a first frequency divider and a second frequency divider; the input terminal of the first frequency divider is connected to the output terminal of the voltage-controlled oscillator, and the output terminal of the second frequency divider is connected to the input terminal of the clock generator; wherein... The first frequency divider is an injection-locked frequency divider, a current-mode logic frequency divider, a true single-phase clock trigger frequency divider, or a Miller frequency divider.

5. The reference sampling phase-locked loop applied in low-voltage mode according to claim 4, characterized in that, The first frequency divider is a current-mode logic 4-divider, used to divide the output signal. Perform a frequency division by four to obtain the frequency division output signal. ; The second frequency divider is a multi-mode programmable frequency divider, used to divide the frequency by four to output the signal. Frequency division is performed to obtain the frequency-divided output signal, which serves as the feedback signal for the phase-locked loop. .

6. The reference sampling phase-locked loop applied in low-voltage mode according to claim 1, characterized in that, The clock generator is a two-phase non-overlapping clock generator, used to divide the output signal. Timing processing is performed to generate a first narrow pulse signal of two non-overlapping phases operating at the frequency division. Second narrow pulse signal .

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