A SAR-type ADC based on voltage recovery and a calibration method thereof
By adopting a voltage-compensated SAR ADC structure and calibration method, the error problem of SAR ADC under changes in manufacturing process and environment is solved, self-calibration and performance stability are achieved, linearity is improved and calibration circuit area is reduced.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2023-03-10
- Publication Date
- 2026-05-15
AI Technical Summary
Existing SAR ADCs suffer from problems such as binary voltage errors in the capacitor array and linearity degradation caused by environmental changes due to limitations in manufacturing processes. Their performance is unstable, especially in special environments such as high and low temperatures, high and low voltages, and radiation resistance.
It adopts a voltage-compensated SAR-type ADC structure, which includes a CADC circuit, a comparator, successive approximation logic and a calibration logic module. It uses bridging capacitors and compensation capacitor arrays to extract and compensate for error voltages, and maintains chip performance consistency in any environment through self-calibration methods.
It achieves self-calibration in any environment, improving the robustness and linearity of the ADC, while reducing the area of the calibration circuit and increasing the calibration range.
Smart Images
Figure CN116318144B_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of analog-to-digital conversion technology, specifically relating to a voltage-compensated SAR ADC and its calibration method. Background Technology
[0002] As a key chip for quantizing analog signals, ADC has attracted the attention and research of researchers and engineers. Thanks to the development of advanced processes, the process has now entered the nanometer level. As a traditional ADC architecture, SAR ADC can benefit more from the process progress. Compared with other ADC structures, SAR ADC has a smaller area and lower power consumption.
[0003] like Figure 1 The diagram shows a block diagram of a SAR ADC, which mainly includes a CDAC circuit, a comparator, and successive approximation logic. The CDAC circuit embeds a sampling circuit. Successive approximation uses a binary search method to quantize the input voltage. After sampling the input voltage, the capacitor array in the CDAC circuit generates binary voltages sequentially from the high-order capacitors to the low-order capacitors and compares them with the input voltage signal. After n comparisons, one voltage quantization is completed.
[0004] Due to limitations in manufacturing processes, the binary voltage generated by the capacitors in the capacitor array does not strictly adhere to a two-fold relationship; instead, an error voltage exists. Therefore, calibration is required to compensate for this error voltage and improve the matching between capacitors. Furthermore, to cope with special application scenarios, such as high and low temperatures, high and low voltages, and radiation resistance, the linearity of the SAR ADC deteriorates with environmental changes. Therefore, self-calibration technology is needed. When the system senses a change in the environment, it can perform a self-calibration of the SAR ADC to maintain consistent chip performance. Summary of the Invention
[0005] To address the above technical problems, this invention proposes a voltage-compensated SAR ADC and its calibration method.
[0006] The technical solution of this invention is:
[0007] A voltage-compensated SAR-type ADC includes a CADC circuit module, a comparator, successive approximation logic and calibration logic modules, and a calibration compensation circuit module. The CADC circuit module comprises n branches, each consisting of a capacitor and a switch connected in series. One end of all capacitors is connected to form a voltage divider port of the CADC circuit module, which is connected to a power supply. This port is also connected to the positive input terminals of the calibration compensation circuit module and the comparator, respectively. The switch in each branch of the CADC circuit module is connected to a reference voltage or ground under the control of an enable terminal. The negative input terminal of the comparator... The common-mode voltage of the ADC is connected, and the output of the comparator is connected to the input of the successive approximation logic and calibration logic module. The calibration compensation circuit module includes a bridging capacitor and a compensation capacitor array. One end of the bridging capacitor is connected to a port of the CADC circuit module, and the other end of the bridging capacitor is connected to one end of the compensation capacitor array, which is grounded. The output of the successive approximation logic and calibration logic module is connected to the enable terminals of all switches in the CADC circuit module and the switches of the compensation capacitor array. The successive approximation logic and calibration logic module is used to control the calibration compensation circuit module to extract the error voltage.
[0008] In the above scheme, the sampling circuit is embedded in the CDAC circuit, and the successive approximation and calibration logic generates n and m control lines, which are respectively connected to the switches of the capacitor array in the CDAC circuit and the capacitor compensation array switches in the calibration compensation circuit. The calibration compensation circuit mainly consists of bridging capacitor C. b and compensation capacitor array C comp Bridge capacitor C b Used for coefficient reduction, this segmented capacitor structure can reduce the area of the capacitor array while improving the compensation accuracy of the compensation capacitor array. Compensation capacitor array C comp It is used to extract the error voltage of each capacitor in the CDAC circuit during measurement, and to provide compensation voltage during normal operation.
[0009] A calibration method for a voltage-compensated SAR-type ADC includes:
[0010] To extract the error voltage of all n capacitors in the CADC circuit module, specifically: first, control the ADC to enter the sampling state, and simultaneously adjust the current calibration capacitor C. i Connect to a reference voltage, which is less than the current capacitor C. i The capacitance values C1 to C i-1 Grounded, greater than the current capacitance C i Capacitance C i+1 ~C n Ground; then put the ADC into conversion state, while simultaneously setting the current calibration capacitor C. i Grounded, less than the current capacitance C i Capacitors with capacitance values C1 to C i-1Connect to a reference voltage, which is greater than the current capacitor C. i Capacitance C i+1 ~C n Still grounded; if the current capacitor C i With low-segment capacitors C1 to C i-1 If there is a capacitance mismatch value ΔC, the voltage appearing at the voltage divider port after the switch represents the voltage represented by the capacitance mismatch value ΔC, thus extracting the current capacitance C. i Error voltage V res,i traverse C1 to C n The total error voltage is V. res,1 ~V res,n ;
[0011] The obtained error voltage is stored in a register;
[0012] Under normal operating conditions, the input voltage is sampled, and voltage comparison is performed using a compensation capacitor array. When the comparator output is high, the error voltage codeword stored in the register is used to compensate for the negative error voltage -V of the currently used capacitor using the calibration compensation capacitor array. res,i When the comparator output is low, the error voltage codeword stored in the register is used to compensate the positive error voltage V of the currently used capacitor using the calibration compensation capacitor array. res,i .
[0013] The beneficial effects of this invention are as follows: This invention provides a voltage-compensated SAR-type ADC structure and calibration method. This is a self-calibration method that requires no external signal and can initiate calibration at any time to perform ADC self-calibration. It is suitable for any environment and improves robustness. This method utilizes capacitor switching to obtain the error magnitude of individual capacitors in the capacitor array, thereby compensating for the error voltage caused by mismatch under normal operating conditions, improving the linearity of the ADC. Simultaneously, by using bridging capacitors to scale the capacitor array of the compensation circuit, the area of the calibration circuit can be reduced, while the calibration range can be increased. Attached Figure Description
[0014] Figure 1 This is a block diagram of the SAR ADC.
[0015] Figure 2 This is a block diagram of a self-calibrating SAR ADC.
[0016] Figure 3 This is based on the calibration principle. Detailed Implementation
[0017] The invention will now be further described with reference to the accompanying drawings.
[0018] This invention proposes a voltage-compensated SAR-type ADC structure and calibration method, such as... Figure 2 The diagram shows the structural block diagram of a calibrated SAR ADC. Compared to traditional SAR ADC structures, this invention requires an additional calibration compensation circuit and calibration logic. The calibration compensation circuit mainly consists of a bridging capacitor C. b and compensation capacitor array C comp Bridge capacitor C b Used for coefficient reduction, this segmented capacitor structure can reduce the area of the capacitor array while improving the compensation accuracy of the compensation capacitor array. Compensation capacitor array C comp It is used to extract the error voltage of each capacitor in the CDAC circuit during measurement, and to provide compensation voltage during normal operation. The calibration logic circuit is used to control the state of the capacitor array in the calibration compensation circuit, and this circuit is implemented through digital synthesis.
[0019] This invention also proposes a voltage-compensated SAR-type ADC calibration method, the calibration principle of which is as follows:
[0020] Figure 3 The diagram shows the waveform of a single voltage quantization operation. Assuming that only the third capacitor in the entire CDAC has an error, it can be seen from the diagram that due to the error, the voltage generated by the CDAC during the third comparison does not follow a double relationship, but instead has an error voltage ΔV compared to the actual generated voltage. This invention obtains the error voltage ΔV through a switching method, stores this error voltage, and finally compensates for it during normal operation using a calibration compensation capacitor array.
[0021] The SAR ADC self-calibration steps of this invention are as follows:
[0022] Measurement status:
[0023] Shorting the ADC input and using the SAR logic circuit puts the ADC into sampling mode, while simultaneously setting the current calibration C... i The capacitor is connected to Vref, which is less than the current capacitor C. i Capacitors with capacitance values C1 to C i-1 Connect to GND, which is greater than the current capacitor C. i Capacitance C i+1 ~C n Connect to GND;
[0024] The ADC enters the conversion state, and simultaneously changes the current calibration value. i The capacitor is connected to GND, and its capacitance is less than the current capacitance C. i Capacitors with capacitance values C1 to C i-1 Connect Vref, which is greater than the current capacitance C. i Capacitance C i+1 ~C nIf it remains connected to GND, assuming it's an ideal binary capacitor array, the voltage at the voltage divider port will always be zero. However, if the current capacitor C... i With low-segment capacitors C1 to C i-1 If there is a capacitance mismatch ΔC, the voltage appearing at the voltage divider port after the switch represents the voltage represented by the capacitance mismatch ΔC. At this point, the current capacitance C can be extracted. i Error voltage V res,i ;
[0025] The multiplexed SAR logic circuit utilizes the compensation capacitor array C of the calibration compensation circuit. comp For error voltage V res,i Quantify;
[0026] Repeat the process to extract the error voltage V from Cn-1 to C1 in sequence. res,n-1 ~V res,1 ;
[0027] The error voltage codeword is stored in a register.
[0028] Normal working status:
[0029] Sample input voltage;
[0030] Switch the current capacitor C i A voltage comparison is performed, and the error voltage codeword stored in the register is used to compensate the current capacitance C using a calibration compensation capacitor array. i Error voltage V res,i ;
[0031] Switch to the next capacitor C based on the comparator result. i-1 Perform the next voltage comparison and voltage compensation, and complete the entire successive approximation logic sequentially from the high bit to the low bit.
[0032] Voltage comparison complete, proceed to the next voltage quantization.
Claims
1. A calibration method for a voltage-compensated SAR-type ADC, characterized in that, The SAR-type ADC includes a CADC circuit module, a comparator, successive approximation logic and calibration logic modules, and a calibration compensation circuit module. The CADC circuit module comprises n branches, each consisting of a capacitor and a switch connected in series. One end of all capacitors is connected to a voltage divider port of the CADC circuit module, which is connected to the power supply and also to the positive input terminals of the calibration compensation circuit module and the comparator. The switch in each branch of the CADC circuit module is connected to a reference voltage or ground under the control of its enable terminal. The negative input terminal of the comparator is connected to the common-mode voltage of the ADC, and the output terminal of the comparator is connected to the input terminals of the successive approximation logic and calibration logic modules. The calibration compensation circuit module includes a bridging capacitor and a compensation capacitor array. One end of the bridging capacitor is connected to a port of the CADC circuit module, and the other end of the bridging capacitor is connected to one end of the compensation capacitor array, with the other end of the compensation capacitor array grounded. The output terminals of the successive approximation logic and calibration logic modules are connected to the enable terminals of all switches in the CADC circuit module and the switches of the compensation capacitor array. The successive approximation logic and calibration logic modules are used to control the calibration compensation circuit module to extract the error voltage; the calibration method includes: To extract the error voltage of all n capacitors in the CADC circuit module, specifically: first, control the ADC to enter the sampling state, and simultaneously adjust the current calibration capacitor C. i Connect to a reference voltage, which is less than the current capacitor C. i The capacitance values C1~C i-1 Grounded, greater than the current capacitance C i Capacitance C i+1 ~C n Ground; then put the ADC into conversion state, while simultaneously setting the current calibration capacitor C. i Grounded, less than the current capacitance C i Capacitors with capacitance values C1~C i-1 Connect to a reference voltage, which is greater than the current capacitor C. i Capacitance C i+1 ~C n Still grounded; if the current capacitor C i With low-segment capacitors C1~C i-1 If there is a capacitance mismatch value ΔC, the voltage appearing at the voltage divider port after the switch represents the voltage represented by the capacitance mismatch value ΔC, thus extracting the current capacitance C. i Error voltage V res,i traverse C1~C n The total error voltage is V. res,1 ~V res,n ; The obtained error voltage is stored in a register; Under normal operating conditions, the input voltage is sampled, and voltage comparison is performed using a compensation capacitor array. When the comparator output is high, the error voltage codeword stored in the register is used to compensate for the negative error voltage -V of the currently used capacitor using the calibration compensation capacitor array. res,i When the comparator output is low, the error voltage codeword stored in the register is used to compensate the positive error voltage V of the currently used capacitor using the calibration compensation capacitor array. res,i .