OOK receiving device and OOK transmitting device

Abstract

An OOK receiving device and an OOK transmitting device, the OOK receiving device comprising: a low noise amplifier, an automatic bias tracking demodulator, a single-to-differential conversion circuit and a continuous time linear equalizer, wherein: the low noise amplifier is configured to receive an OOK modulated signal through a receiving antenna; the automatic bias tracking demodulator is configured to automatically track a bias voltage and demodulate the OOK modulated signal into a baseband signal; the single-to-differential conversion circuit is configured to convert the baseband signal output by the automatic bias tracking demodulator into a differential signal; and the continuous time linear equalizer is configured to perform an equalization operation on the differential signal output by the single-to-differential conversion circuit.

Description

TECHNICAL FIELD

[0001] The embodiment of the present disclosure relates to, but is not limited to, the field of communication, in particular to an OOK receiving device and an OOK transmitting device. BACKGROUND

[0002] Modern wireless communication has higher and higher requirements on data rate. In the frequency band below 10 GHz, such as Bluetooth, wireless local area network (WIFI), 5G frequency 1 (FR1), etc., due to limited spectrum resources, high-order digital modulation is often used to improve communication rate, such as 1024-QAM (Quadrature Amplitude Modulation) modulation used in WIFI 6. These high-order digital modulations can effectively improve the spectral efficiency and achieve high communication rate in a relatively narrow bandwidth. However, high-order digital modulation requires the modulation and demodulation circuit of the load to process the signal. In the analog domain, a quadrature local oscillator generation circuit, a quadrature mixer, a local oscillator leakage calibration, and image rejection are required; in the digital domain, a carrier recovery circuit and a phase recovery circuit are also required, which not only increases the difficulty of implementation, but also increases the system chip development cost and system power consumption.

[0003] However, in the millimeter wave frequency band, the available bandwidth can be as high as tens of gigahertz (GHz), and high communication rate can be obtained without high-order digital modulation. In point-to-point interconnection and other communication scenarios, the communication circuit can use the full bandwidth, and it is better to use a relatively simple modulation format to reduce chip design difficulty and system power consumption, and use large bandwidth to obtain high communication data rate and achieve relatively balanced performance. SUMMARY

[0004] The embodiment of the present disclosure provides an OOK receiving device, comprising a low noise amplifier, an automatic bias tracking demodulator, a single-to-differential conversion circuit and a continuous time linear equalizer, wherein:

[0005] The low noise amplifier is configured to receive an OOK modulated signal through a receiving antenna;

[0006] The automatic bias tracking demodulator is configured to automatically track a bias voltage and demodulate the OOK modulated signal into a baseband signal;

[0007] The single-to-differential conversion circuit is configured to convert the baseband signal output by the automatic bias tracking demodulator into a differential signal;

[0008] The continuous time linear equalizer is configured to perform equalization operation on the differential signal output by the single-to-differential conversion circuit.

[0009] Optionally, the automatic bias tracking demodulator comprises a fourth resistor, a fifth resistor, a first demodulator, a replica demodulator, an operational amplifier and a reference voltage generating circuit, wherein: the fourth resistor and the fifth resistor are connected in series between two differential input terminals of the first demodulator, the series connection point of the fourth resistor and the fifth resistor is connected with two differential input terminals of the replica demodulator and an output terminal of the operational amplifier, an output terminal of the replica demodulator is connected with one input terminal of the operational amplifier, and the reference voltage generating circuit is connected with the other input terminal of the operational amplifier; the first demodulator and the replica demodulator have the same circuit and layout.

[0010] Optionally, the first demodulator comprises a fifth transistor, a sixth transistor and a sixth resistor, and the replica demodulator comprises a seventh transistor, an eighth transistor and a seventh resistor, wherein: a control terminal of the fifth transistor is connected with one differential input terminal of the first demodulator, a control terminal of the sixth transistor is connected with the other differential input terminal of the first demodulator, a first stage of the fifth transistor and a first stage of the sixth transistor are both grounded, a second stage of the fifth transistor and a second stage of the sixth transistor are connected and then connected with an output terminal and one end of the sixth resistor, and the other end of the sixth resistor is connected with a power supply voltage.

[0011] a control terminal of the seventh transistor is connected with a control terminal of the eighth transistor and then connected with the series connection point of the fourth resistor and the fifth resistor, a first stage of the seventh transistor and a first stage of the eighth transistor are both grounded, a second stage of the seventh transistor and a second stage of the eighth transistor are connected and then connected with one input terminal of the operational amplifier and one end of the seventh resistor, and the other end of the seventh resistor is connected with a power supply voltage.

[0012] Optionally, the low noise amplifier comprises an on-chip transformer balun and one or more cascaded amplification networks, each amplification network comprising a pseudo-differential common-source amplifier and a bandwidth matching network connected in sequence, wherein: one input terminal of the on-chip transformer balun is a signal input terminal of the low noise amplifier, the other input terminal of the on-chip transformer balun is grounded, and two output terminals of the on-chip transformer balun are connected with two input terminals of the pseudo-differential common-source amplifier of the first stage.

[0013] The pseudo-differential common source amplifier of each stage comprises a second capacitor, a third capacitor, a ninth transistor and a tenth transistor, one end of the second capacitor is connected with the control end of the tenth transistor and one input end of the pseudo-differential common source amplifier, the other end of the second capacitor is connected with the second electrode of the ninth transistor and one output end of the pseudo-differential common source amplifier; one end of the third capacitor is connected with the control end of the ninth transistor and the other input end of the pseudo-differential common source amplifier, the other end of the third capacitor is connected with the second electrode of the tenth transistor and the other output end of the pseudo-differential common source amplifier; the first electrode of the ninth transistor and the first electrode of the tenth transistor are both grounded.

[0014] Optionally, the single-to-difference conversion circuit comprises a low-pass filter and a differential amplifier circuit of one or more stages, wherein: in the first stage of the differential amplifier circuit, the positive input end of the first stage of the differential amplifier circuit is connected with the signal input end of the single-to-difference conversion circuit, the negative input end of the first stage of the differential amplifier circuit is connected with the signal input end of the single-to-difference conversion circuit through the low-pass filter, the positive output end of each stage of the differential amplifier circuit is connected with the positive input end of the next stage of the differential amplifier circuit, and the negative output end of each stage of the differential amplifier circuit is connected with the negative input end of the next stage of the differential amplifier circuit, and n is the number of stages of the differential amplifier circuit.

[0015] Optionally, the low-pass filter comprises a first resistor and a first capacitor connected in series, wherein: the first end of the first resistor is connected with the signal input end of the single-to-difference conversion circuit, the second end of the first resistor is connected with the first end of the first capacitor and the negative input end of the first stage of the differential amplifier circuit, and the second end of the first capacitor is grounded.

[0016] Optionally, the differential amplifier circuit comprises a differential pair and an active load, wherein: the differential pair comprises a first transistor and a second transistor, the control end of the first transistor is the positive input end, the control end of the second transistor is the negative input end, the first electrode of the first transistor and the first electrode of the second transistor are both connected with a bias current source, and the second electrode of the first transistor and the second electrode of the second transistor are respectively connected with two ends of the active load.

[0017] Optionally, the active load comprises a second resistor, a third transistor and a fourth transistor, wherein: a first electrode of the third transistor and a first electrode of the fourth transistor are connected with a power supply voltage, a second electrode of the third transistor is connected with a first end of the second resistor, a second electrode of the fourth transistor is connected with a first end of the third resistor, and a control electrode of the third transistor and a control electrode of the fourth transistor are connected together and connected with a second end of the second resistor and a second end of the third resistor.

[0018] Optionally, the active load further comprises a differential inductor, the control electrode of the third transistor and the control electrode of the fourth transistor are connected together and connected with the second end of the second resistor and the second end of the third resistor, and the second end of the second resistor is connected with a first end of the differential inductor, the second end of the third resistor is connected with a second end of the differential inductor, and the control electrode of the third transistor and the control electrode of the fourth transistor are connected together and connected with a center tap of the differential inductor.

[0019] The embodiments of the present disclosure further provide an OOK transmitting device, comprising: a continuous-time linear equalizer, a CML-to-CMOS conversion circuit, a modulator, an oscillator and a power amplifier, wherein:

[0020] The continuous-time linear equalizer is configured to receive a signal from a PCB channel and perform equalization operation on the received signal.

[0021] The CML-to-CMOS conversion circuit is configured to receive a signal output by the continuous-time linear equalizer, convert a CML level into a CMOS level, and output the CMOS level to the modulator.

[0022] The oscillator is configured to generate an intrinsic signal and output the intrinsic signal to the modulator.

[0023] The modulator is configured to generate an OOK modulated signal according to the CMOS level output by the CML-to-CMOS conversion circuit and the intrinsic signal.

[0024] The power amplifier is configured to amplify and output the OOK modulated signal output by the modulator.

[0025] The millimeter wave OOK wireless transceiver provided by the embodiments of the present disclosure improves the transmitting power and reduces the noise coefficient by integrating the power amplifier / low noise amplifier on the chip, thereby improving the communication distance; compensates for the baseband signal loss of the transceiver and the bandwidth limitation of the demodulator by integrating the continuous-time linear equalizer on the chip; and improves the robustness of the OOK demodulator by integrating the automatic bias tracking demodulator on the chip.

[0026] Other features and advantages of the present disclosure will be set forth in the description that follows, and in part will be apparent from the description, or can be learned by practice of the present disclosure. Other advantages of the present disclosure will be realized and attained by the solution described in the specification and the accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

[0027] The accompanying drawings are included to provide a further understanding of the technical solution of the present disclosure, and constitute a part of the specification, and are used together with the embodiments of the present disclosure to explain the technical solution of the present disclosure, and do not constitute a limitation on the technical solution of the present disclosure.

[0028] Figure 1 A structure schematic diagram of an OOK receiving device provided by an embodiment of the present disclosure;

[0029] Figure 2 An implementation block diagram of a single slip circuit provided by an embodiment of the present disclosure;

[0030] Figure 3A And Figure 3B Specific implementation circuit diagrams of two single slip circuits provided by an embodiment of the present disclosure;

[0031] Figure 4 An implementation schematic diagram of an automatic bias tracking demodulator provided by an embodiment of the present disclosure;

[0032] Figure 5 An implementation circuit example diagram of a low noise amplifier provided by an embodiment of the present disclosure;

[0033] Figure 6 A structure schematic diagram of an OOK transmitting device provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0034] The present disclosure describes multiple embodiments, but the description is exemplary rather than limiting, and it is obvious to those skilled in the art that there can be more embodiments and implementation solutions within the scope of the embodiments described in the present disclosure. Although many possible combinations of features are shown in the drawings and discussed in the specific embodiments, many other combinations of the disclosed features are also possible. Unless specifically limited, any feature or element of any embodiment can be used with any other feature or element of any other embodiment, or can replace any other feature or element of any other embodiment.

[0035] The present disclosure includes and contemplates combinations of features and elements known to those of ordinary skill in the art. The presently disclosed embodiments, features and elements can also be combined with any conventional feature or element to form a unique application defined by the claims. Any feature or element of any embodiment can also be combined with features or elements from other application to form another unique application defined by the claims. Therefore, it is to be understood that any feature shown and / or discussed in the present disclosure can be realized alone or in any appropriate combination. Thus, unless otherwise restricted by the claims, embodiments are not to be limited by any particular disclosed embodiment. Furthermore, various modifications and changes can be made within the scope of the attached claims.

[0036] Furthermore, in describing representative embodiments, the specification can have presented the method and / or process as a particular sequence of steps. However, to the extent that the method or process depends on more than one step, the method or process should not be limited to the particular sequence of steps described. Other sequences of steps can be possible, depending on the particular application, and the sequence of steps need not be performed in the order presented. The specific order of steps presented in the specification is not to be construed as a limitation, but is presented for illustrative purposes. Further, the claims should not be limited to the steps of the method and / or process presented in the specification. Additionally, persons having ordinary skill in the art can readily devise other methods and / or processes to which the claims can be applicable, without the exercise of inventive capacity.

[0037] On-Off Keying (OOK) is a simple modulation format, which represents data by on and off of the local oscillator signal. When the local oscillator signal is on, it represents data 1; when the local oscillator signal is off, it represents data 0. OOK modulation has two advantages. First, OOK modulation has no requirement on the phase noise of the local oscillator signal, so that an open loop oscillator can be used to generate the local oscillator signal, without the need of a complex phase locked loop, which reduces the design complexity and power consumption. Second, at the receiving end, the OOK signal can be directly envelope detected, i.e., the baseband signal can be extracted, without the need of coherent demodulation, so that there is no need of complex carrier recovery and phase recovery loops. In summary, OOK modulation is of great interest in low power communication and millimeter wave high speed interconnection, due to its simple circuit structure, low implementation cost, low power consumption, and no need of coherent local oscillator demodulation.

[0038] The inventors have found that the application of a traditional OOK transmitter and receiver in a millimeter wave frequency band has the following design difficulties: first, in a millimeter wave frequency band exceeding 100 GHz, the output power of the OOK modulator is small, and the noise coefficient of the OOK demodulator is large, which limits the communication distance. Since the signal carrier frequency is high and the bandwidth is wide, it is difficult to use power amplifiers and low-noise amplifiers outside the chip for signal amplification. Second, when the OOK modulation data rate exceeds 20 Gbps, the communication data rate will be limited by the transmission and reception baseband channel bandwidth and the bandwidth of the OOK demodulator. Third, the performance of the OOK demodulator is related to its bias voltage, and the bias voltage fluctuates with fluctuations in process, temperature and power voltage, which requires individual calibration for each chip, making it difficult to use.

[0039] As shown in Figure 1 The present disclosure provides an OOK receiving device, comprising a low noise amplifier 101, an automatic bias tracking demodulator 102, a single-to-differential conversion circuit 103 and a continuous time linear equalizer 104 connected in sequence, wherein:

[0040] The low noise amplifier 101 is configured to receive an OOK modulated signal through a receiving antenna;

[0041] The automatic bias tracking demodulator 102 is configured to automatically track the bias voltage and demodulate the OOK modulated signal into a baseband signal;

[0042] The single-to-differential conversion circuit 103 is configured to convert the baseband signal output by the automatic bias tracking demodulator 102 into a differential signal;

[0043] The continuous time linear equalizer 104 is configured to perform equalization operation on the differential signal output by the single-to-differential conversion circuit 103.

[0044] In the OOK receiving device provided by the present disclosure, the low noise amplifier 101 receives a millimeter wave OOK modulated signal through a receiving antenna. The automatic bias tracking demodulator 102 demodulates the OOK modulated signal into a baseband signal, which has a bias voltage tracking loop and can automatically track the bias voltage, reducing the disturbance caused by process angle, power voltage and temperature change. The single-to-differential conversion circuit 103 converts the single-ended signal output by the automatic bias tracking demodulator 102 into a differential signal. The continuous time linear equalizer 104 compensates for the limited bandwidth of the demodulator and the insertion loss of the continuous time linear equalizer at the transmitting end in the high frequency band, so as to improve the baseband data rate.

[0045] The OOK receiving device of the embodiments of the present disclosure can be single-chip integrated, the low noise amplifier 101 is integrated on a single chip, the noise figure is reduced, and the communication distance is improved; the continuous time linear equalizer 104 is integrated on a single chip, the baseband signal loss of the transceiver and the bandwidth limitation of the demodulator are compensated; the automatic bias tracking demodulator 102 is integrated on a single chip, the automatic bias tracking loop is arranged in the automatic bias tracking demodulator 102, the robustness of the OOK demodulator is improved, and then the communication distance and the data rate of the millimeter wave OOK circuit are improved.

[0046] In some example embodiments, as shown in Figure 2 The single-to-differential conversion circuit 103 includes a low-pass filter 1031 and one or more cascaded differential amplifier circuits 1032, wherein:

[0047] In the first n-1 differential amplifier circuits 1032, the positive input end of the first differential amplifier circuit 1032 is connected with the signal input end of the single-to-differential conversion circuit, the negative input end of the first differential amplifier circuit 1032 is connected with the signal input end of the single-to-differential conversion circuit through the low-pass filter 1031, the positive output end of each differential amplifier circuit 1032 is connected with the positive input end of the next differential amplifier circuit 1032, the negative output end of each differential amplifier circuit 1032 is connected with the negative input end of the next differential amplifier circuit 1032, and n is the number of cascaded stages of the differential amplifier circuit 1032.

[0048] In some example embodiments, as shown in Figure 3A or Figure 3B The low-pass filter 1031 includes a first resistor R1 and a first capacitor C1 connected in series, wherein:

[0049] The first end of the first resistor R1 is connected with the signal input end of the single-to-differential conversion circuit, the second end of the first resistor R1 is connected with the first end of the first capacitor C1 and the negative input end of the first differential amplifier circuit 1032, and the second end of the first capacitor C1 is grounded.

[0050] In some example embodiments, as shown in Figure 3A or Figure 3B The differential amplifier circuit includes a differential pair and an active load, wherein:

[0051] The differential pair includes a first transistor T1 and a second transistor T2, the control end of the first transistor T1 is the positive input end, the control end of the second transistor T2 is the negative input end, the first pole of the first transistor T1 and the first pole of the second transistor T2 are connected with a bias current source A, and the second pole of the first transistor T1 and the second pole of the second transistor T2 are respectively connected with two ends of the active load.

[0052] In some example embodiments, the active load comprises a second resistor R2, a third resistor R3, a third transistor T3 and a fourth transistor T4, wherein:

[0053] The first pole of the third transistor T3 and the first pole of the fourth transistor T4 are connected with a power supply voltage, the second pole of the third transistor T3 is connected with the first end of the second resistor R2, the second pole of the fourth transistor T4 is connected with the first end of the third resistor R3, and the control end of the third transistor T3 and the control end of the fourth transistor T4 are connected together and connected with the second end of the second resistor R2 and the second end of the third resistor R3.

[0054] In some example embodiments, the at least one stage of active load further comprises a differential inductor L, the control end of the third transistor T3 and the control end of the fourth transistor T4 are connected together and connected with the second end of the second resistor R2 and the second end of the third resistor R3, specifically:

[0055] The second end of the second resistor R2 is connected with the first end of the differential inductor L, the second end of the third resistor R3 is connected with the second end of the differential inductor L, and the control end of the third transistor T3 and the control end of the fourth transistor T4 are connected together and connected with the center tap of the differential inductor L.

[0056] Figure 2 An implementation block diagram of a single conversion circuit is provided for the embodiments of the present disclosure. As shown in the figure, Figure 2 the single conversion circuit can be composed of one or more stages of differential amplifier circuits in cascade. The input signal is input to the positive input end of the first stage of differential amplifier circuit, and the DC component in the input signal is extracted through a low-pass filter and input to the negative input end of the first stage of differential amplifier circuit, thereby playing a role of automatically tracking the DC component. In actual use, one or more stages of differential amplifier circuits in cascade are determined according to the actual demand for gain and bandwidth, as well as the limitation on power consumption and area.

[0057] Figure 3A And Figure 3B Two specific implementation circuit diagrams of the single conversion circuit are provided for the embodiments of the present disclosure (wherein, Figure 3A two stages are included, Figure 3B three stages are included, however, the embodiments of the present disclosure are not limited thereto), as shown in the figures, Figure 3A and 3B the differential amplifier circuit adopts a differential pair circuit with an active resistor and a PMOS transistor as a load. In the active load, the center of the resistor can be connected to a differential inductor, and then the center tap of the differential inductor is connected to the control end of the PMOS transistor, thereby playing a role of expanding the bandwidth. In actual use, one or more stages of differential inductors can be selected according to the requirement for speed and bandwidth, as well as the limitation on chip area.

[0058] In some example embodiments, as shown in FIG. 1, the automatic bias tracking demodulator comprises a fourth resistor R4, a fifth resistor R5, a first demodulator, a replica demodulator, an operational amplifier and a reference voltage generating circuit, wherein: Figure 4

[0059] The fourth resistor R4 and the fifth resistor R5 are connected in series between two differential input terminals of the first demodulator, the series connection point of the fourth resistor R4 and the fifth resistor R5 is connected to two differential input terminals of the replica demodulator and an output terminal of the operational amplifier, an output terminal of the replica demodulator is connected to one input terminal (positive input terminal) of the operational amplifier, and the reference voltage generating circuit is connected to the other input terminal (negative input terminal) of the operational amplifier.

[0060] The circuit and layout of the first demodulator and the replica demodulator are the same.

[0061] In some example embodiments, the first demodulator comprises a fifth transistor T5, a sixth transistor T6 and a sixth resistor R6, and the replica demodulator comprises a seventh transistor T7, an eighth transistor T8 and a seventh resistor R7, wherein:

[0062] The control terminal of the fifth transistor T5 is connected to one differential input terminal (positive input terminal) of the first demodulator, the control terminal of the sixth transistor T6 is connected to the other differential input terminal (negative input terminal) of the first demodulator, the first stage of the fifth transistor T5 and the first stage of the sixth transistor T6 are both grounded, the second stage of the fifth transistor T5 and the second stage of the sixth transistor T6 are connected and then connected to the output terminal and one end of the sixth resistor R6, and the other end of the sixth resistor R6 is connected to a power supply voltage.

[0063] The control terminal of the seventh transistor T7 is connected to the control terminal of the eighth transistor T8 and then connected to the series connection point of the fourth resistor R4 and the fifth resistor R5, the first stage of the seventh transistor T7 and the first stage of the eighth transistor T8 are both grounded, the second stage of the seventh transistor T7 and the second stage of the eighth transistor T8 are connected and then connected to one input terminal (positive input terminal) of the operational amplifier and one end of the seventh resistor R7, and the other end of the seventh resistor R7 is connected to a power supply voltage.

[0064] Figure 4 An implementation schematic diagram of an automatic bias tracking demodulator according to an embodiment of the present disclosure. As shown in FIG. 1, the automatic bias tracking demodulator comprises a fourth resistor R4, a fifth resistor R5, a first demodulator, a replica demodulator, an operational amplifier and a reference voltage generating circuit, wherein: Figure 4 ​As shown, the drains of two NMOS transistors (T5 and T6) are connected together and then connected to the load resistor (R6). The control terminal is connected to the differential input signal, serving as an envelope detector. To automatically track the bias voltage, a copy of the circuit and layout of the first demodulator is created, forming a duplicate demodulator. The output of the duplicate demodulator is connected to the positive input of an operational amplifier. The negative input of the operational amplifier is connected to a reference voltage generation circuit, and its output is connected to both the control terminals of the two transistors in the duplicate demodulator and the bias voltage input of the first demodulator. Due to the operational amplifier feedback loop, regardless of process, power supply voltage, and temperature fluctuations, the loop controls the output DC voltage of the duplicate demodulator to match the output voltage of the reference voltage generation circuit. Since the first demodulator and the duplicate demodulator have the same parameters, circuitry, and layout, the output voltage of the first demodulator is also the output voltage of the reference voltage generation circuit, thus achieving automatic bias tracking.

[0065] In some exemplary implementations, such as Figure 5 As shown, the low-noise amplifier includes an on-chip transformer balun and one or more cascaded amplification networks. Each amplification network includes a pseudo-differential common-source amplifier and a bandwidth matching network connected in sequence, wherein:

[0066] One input terminal of the on-chip transformer balun is the signal input terminal of the low-noise amplifier, the other input terminal of the on-chip transformer balun is grounded, and the two output terminals of the on-chip transformer balun are connected to the two input terminals of the first-stage pseudo-differential common-source amplifier.

[0067] Each stage of the pseudo-differential common-source amplifier includes a second capacitor C2, a third capacitor C3, a ninth transistor T9, and a tenth transistor T10. One end of the second capacitor C2 is connected to the control terminal of the tenth transistor T10 and one input terminal of the pseudo-differential common-source amplifier, while the other end of the second capacitor C2 is connected to the second terminal of the ninth transistor T9 and one output terminal of the pseudo-differential common-source amplifier. One end of the third capacitor C3 is connected to the control terminal of the ninth transistor T9 and the other input terminal of the pseudo-differential common-source amplifier, while the other end of the third capacitor C3 is connected to the second terminal of the tenth transistor T10 and the other output terminal of the pseudo-differential common-source amplifier. The first terminals of both the ninth transistor T9 and the tenth transistor T10 are grounded.

[0068] Figure 5 An example circuit diagram of an implementation of a millimeter-wave low-noise amplifier is provided. Figure 5 As shown, the input terminal uses an on-chip transformer balun to convert the single-ended signal from the antenna into a differential signal, which is then passed through a multi-stage pseudo-differential common-source amplifier. Figure 5 The amplifier is amplified in four stages (4 stages in total). Each stage of the pseudo-differential common-source amplifier has a neutralization capacitor to improve gain and stability. On-chip transformers are used for broadband matching between stages to improve the overall data rate.

[0069] As Figure 6 shown in the figure, the embodiment of the present disclosure further provides an OOK transmitting device, comprising: a continuous-time linear equalizer 601, a CML to CMOS conversion circuit 602, a modulator 603, an oscillator 604 and a power amplifier 605, wherein:

[0070] The continuous-time linear equalizer 601 is configured to receive a signal from a PCB channel and perform equalization operation on the received signal.

[0071] The CML to CMOS conversion circuit 602 is configured to receive a signal output by the continuous-time linear equalizer 601, convert the CML level into a CMOS level, and output to the modulator 603.

[0072] The oscillator 604 is configured to generate an intrinsic signal and output to the modulator 603.

[0073] The modulator 603 is configured to generate an OOK modulated signal according to the CMOS level output by the CML to CMOS conversion circuit 602 and the intrinsic signal generated by the oscillator 604.

[0074] The power amplifier 605 is configured to amplify and output the OOK modulated signal output by the modulator 603.

[0075] In the OOK transmitting device of the embodiment of the present disclosure, the continuous-time linear equalizer 601 compensates for the loss of the PCB channel at high frequencies and improves the baseband data rate. The CML to CMOS conversion circuit 602 converts the CML output level of the continuous-time linear equalizer 601 into a CMOS level and acts on the modulator 603. The oscillator 604 generates a local oscillation signal. The OOK modulated signal generated by the modulator 603 is amplified and output by the power amplifier 605.

[0076] The OOK transmitting device of the embodiment of the present disclosure can be single-chip integrated, by integrating the power amplifier 605 on a single chip, improving the transmitting power and reducing the noise coefficient, thereby improving the communication distance; by integrating the continuous-time linear equalizer 601 on a single chip, compensating for the loss of the transceiver baseband signal and the bandwidth limitation of the demodulator, thereby improving the communication distance and data rate of the millimeter wave OOK circuit.

[0077] In summary, the millimeter wave OOK wireless transceiver device provided by the embodiment of the present disclosure improves the transmitting power, reduces the noise coefficient, and thereby improves the communication distance by integrating the power amplifier / low noise amplifier on the chip; compensates for the loss of the transceiver baseband signal and the bandwidth limitation of the demodulator by integrating the continuous-time linear equalizer on the chip; improves the robustness of the OOK demodulator by integrating the automatic bias tracking demodulator on the chip.

[0078] Those of ordinary skill in the art will realize and understand that all or some of the steps in the methods disclosed above and the functional modules / units in the systems and devices can be implemented as software, firmware, hardware, and appropriate combinations thereof. In hardware implementation, the division between the functional modules / units mentioned in the above description does not necessarily correspond to the division of physical components; for example, one physical component can have multiple functions, or one function or step can be performed by several physical components in cooperation. Some or all of the components can be implemented as software executed by a processor, such as a digital signal processor or a microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit. Such software can be distributed on computer-readable media, which can include computer storage media (or non-transitory media) and communication media (or transitory media). As is well known to those of ordinary skill in the art, the term computer storage media includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data. Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tapes, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to store the desired information and which can be accessed by a computer. Furthermore, it is common and well understood by those of ordinary skill in the art that communication media typically embodies computer readable instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transport mechanism and can include any information delivery media.

Claims

1. An OOK receiving device, characterized in that, It includes, in sequence: a low-noise amplifier, an automatic bias tracking demodulator, a single-to-differential converter, and a continuous-time linear equalizer, wherein: The low-noise amplifier is configured to receive an OOK modulated signal via a receiving antenna. The automatic bias tracking demodulator is configured to automatically track the bias voltage and demodulate the OOK modulated signal into a baseband signal; The single-to-differential conversion circuit is configured to convert the baseband signal output by the automatic bias tracking demodulator into a differential signal. The continuous-time linear equalizer is configured to perform equalization on the differential signal output from the single-to-differential conversion circuit. The automatic bias tracking demodulator includes: a fourth resistor, a fifth resistor, a first demodulator, a replica demodulator, an operational amplifier, and a reference voltage generation circuit, wherein: The fourth resistor and the fifth resistor are connected in series between the two differential input terminals of the first demodulator. The series connection point of the fourth resistor and the fifth resistor is connected to the two differential input terminals of the replica demodulator and the output terminal of the operational amplifier. The output terminal of the replica demodulator is connected to one input terminal of the operational amplifier. The output voltage of the reference voltage generation circuit is connected to the other input terminal of the operational amplifier. The first demodulator and the replica demodulator have the same parameters, circuitry, and layout.

2. The OOK receiving device according to claim 1, characterized in that, The first demodulator includes a fifth transistor, a sixth transistor, and a sixth resistor, and the replica demodulator includes a seventh transistor, an eighth transistor, and a seventh resistor, wherein: The control terminal of the fifth transistor is connected to one differential input terminal of the first demodulator, and the control terminal of the sixth transistor is connected to the other differential input terminal of the first demodulator. The first stage of the fifth transistor and the first stage of the sixth transistor are both grounded. The second stage of the fifth transistor and the second stage of the sixth transistor are connected to the output terminal and one end of the sixth resistor. The other end of the sixth resistor is connected to the power supply voltage. After the control terminal of the seventh transistor is connected to the control terminal of the eighth transistor, it is connected to the series connection point of the fourth resistor and the fifth resistor. The first stage of the seventh transistor and the first stage of the eighth transistor are both grounded. After the second stage of the seventh transistor and the second stage of the eighth transistor are connected, they are connected to one input terminal of the operational amplifier and one end of the seventh resistor. The other end of the seventh resistor is connected to the power supply voltage.

3. The OOK receiving device according to claim 1, characterized in that, The low-noise amplifier includes an on-chip transformer balun and one or more cascaded amplification networks. Each amplification network includes a pseudo-differential common-source amplifier and a bandwidth matching network connected in sequence, wherein: One input terminal of the on-chip transformer balun is the signal input terminal of the low-noise amplifier, the other input terminal of the on-chip transformer balun is grounded, and the two output terminals of the on-chip transformer balun are connected to the two input terminals of the first-stage pseudo-differential common-source amplifier. Each stage of the pseudo-differential common-source amplifier includes a second capacitor, a third capacitor, a ninth transistor, and a tenth transistor. One end of the second capacitor is connected to the control terminal of the tenth transistor and one input terminal of the pseudo-differential common-source amplifier, and the other end of the second capacitor is connected to the second terminal of the ninth transistor and one output terminal of the pseudo-differential common-source amplifier. One end of the third capacitor is connected to the control terminal of the ninth transistor and the other input terminal of the pseudo-differential common-source amplifier, and the other end of the third capacitor is connected to the second terminal of the tenth transistor and the other output terminal of the pseudo-differential common-source amplifier. The first terminals of both the ninth and tenth transistors are grounded.

4. The OOK receiving device according to claim 1, characterized in that, The single-to-differential conversion circuit includes: a low-pass filter and one or more cascaded differential amplifier circuits, wherein: In the first n-1 stages of the differential amplifier circuit, the positive input terminal of the first stage differential amplifier circuit is connected to the signal input terminal of the single-to-differential converter circuit, and the negative input terminal of the first stage differential amplifier circuit is connected to the signal input terminal of the single-to-differential converter circuit through the low-pass filter. The positive output terminal of each stage differential amplifier circuit is connected to the positive input terminal of the next stage differential amplifier circuit, and the negative output terminal of each stage differential amplifier circuit is connected to the negative input terminal of the next stage differential amplifier circuit. n is the number of stages of the differential amplifier circuit.

5. The OOK receiving device according to claim 4, characterized in that, The low-pass filter includes a first resistor and a first capacitor connected in series, wherein: The first end of the first resistor is connected to the signal input terminal of the single-to-differential converter circuit, the second end of the first resistor is connected to the first end of the first capacitor and the negative input terminal of the first stage differential amplifier circuit, and the second end of the first capacitor is grounded.

6. The OOK receiving device according to claim 4, characterized in that, The differential amplifier circuit includes differential pairs and an active load, wherein: The differential pair includes a first transistor and a second transistor. The control terminal of the first transistor is the positive input terminal, and the control terminal of the second transistor is the negative input terminal. The first terminals of the first transistor and the second transistor are both connected to a bias current source, and the second terminals of the first transistor and the second transistor are respectively connected to the two ends of the active load.

7. The OOK receiving device according to claim 6, characterized in that, The active load includes a second resistor, a third resistor, a third transistor, and a fourth transistor, wherein: The first terminals of the third transistor and the fourth transistor are both connected to the power supply voltage. The second terminal of the third transistor is connected to the first end of the second resistor. The second terminal of the fourth transistor is connected to the first end of the third resistor. The control terminals of the third transistor and the fourth transistor are connected together and connected to the second end of the second resistor and the second end of the third resistor.

8. The OOK receiving device according to claim 7, characterized in that, At least one stage of the active load further includes a differential inductor, wherein the control terminals of the third transistor and the fourth transistor are connected together and connected to the second terminal of the second resistor and the second terminal of the third resistor, including: The second end of the second resistor is connected to the first end of the differential inductor, the second end of the third resistor is connected to the second end of the differential inductor, and the control terminal of the third transistor and the control terminal of the fourth transistor are connected together and connected to the center tap of the differential inductor.

9. A millimeter-wave OOK wireless transceiver, comprising: The OOK receiving device and the single-chip integrated OOK transmitting device according to any one of claims 1 to 8 are characterized in that the OOK transmitting device comprises: a continuous-time linear equalizer, a CML to CMOS conversion circuit, a modulator, an oscillator, and a power amplifier integrated on a single chip, wherein: The continuous-time linear equalizer is configured to receive signals from the PCB channel and perform equalization operations on the received signals. The CML to CMOS conversion circuit is configured to receive the signal output by the continuous-time linear equalizer, convert the CML level to the CMOS level, and output it to the modulator. The oscillator is configured to generate an intrinsic signal and output it to the modulator; The modulator is configured to generate an OOK modulated signal based on the CMOS level output from the CML to CMOS conversion circuit and the intrinsic signal. The power amplifier is configured to amplify and output the OOK modulated signal output by the modulator.

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