Current-Mirror-Based Composite Dielectric-Gate Dual-Transistor Pixel Dual-Sampling Readout Circuit

Abstract

The present invention discloses a composite dielectric gate dual-transistor pixel double-sampling readout circuit based on a current mirror. The circuit includes a composite dielectric gate dual-transistor photosensitive detector pixel, a negative feedback driving module, a clamping circuit, a current mirror, switches, a current source, a comparator, and a counter. Among them, the source terminal of the composite dielectric gate dual-transistor photosensitive detector pixel is grounded, the gate terminal is connected to the output terminal of the negative feedback driving module, and the drain terminal is connected to the output of the clamping circuit and the current mirror module. The two current mirrors are respectively connected to switches S1 and S2 to control the charging and discharging of the control capacitor C1. The charging and discharging speed of C1 is the signal current of the composite dielectric gate dual-transistor pixel in the dark field and under light exposure. The two comparators are respectively compared with the first reference voltage and the second reference voltage, and the counter uses the outputs of the two comparators as enable signals. The circuit structure of the present invention is stable, has low noise, and can eliminate the FPN noise caused by the non-uniformity of pixels.

Description

Technical Field

[0001] The present invention relates to a composite dielectric gate dual-transistor pixel double-sampling readout circuit based on a current mirror, and belongs to the field of integrated circuits. Background Art

[0002] Chinese Patent CN201210442007.X proposes a dual-transistor photosensitive detector. The characteristic of this detector is that a single semiconductor device can achieve the complete functions of resetting, photosensing, and readout, forming a complete pixel, which can greatly improve the fill factor of the pixel. As a new generation of imaging device, the MOSFET region of this composite dielectric gate dual-transistor photosensitive detector is an N-type MOSFET with a variable threshold. However, due to the particularity of the process, the thresholds of the dual-transistor photosensitive detectors cannot be made exactly the same, and there will be non-uniformity problems in the devices, which is the FPN (Fixed Pattern Noise) noise in the array image. Therefore, it is necessary to design a more stable double-sampling circuit that can eliminate FPN noise. Summary of the Invention

[0003] In view of this, the present invention provides a composite dielectric gate dual-transistor pixel readout circuit based on a switched capacitor to solve the non-uniformity problem caused by FPN noise.

[0004] The technical solution adopted by the present invention is as follows:

[0005] A composite dielectric gate dual-transistor pixel double-sampling readout circuit based on a current mirror includes a composite dielectric gate dual-transistor photosensitive detector pixel, a negative feedback driving module, a clamping circuit, a current mirror, switches, a first current source, a comparator, and a counter. The source of the composite dielectric gate dual-transistor photosensitive detector pixel is grounded, its control gate is connected to the output end of the negative feedback driving module, and its drain is connected to the output of the clamping circuit and the input of the current mirror. The current mirror includes a first current mirror and a second current mirror. The input of the first current mirror is connected to the drain, and its output is connected to the input of the second current mirror and is connected to the positive end of the capacitor C1 through the second switch S2. The output of the second current mirror is connected to the positive end of the capacitor C1 through the third switch S3.

[0006] The positive end of the first current source is connected to the power supply, and its negative end is connected to the positive end of the capacitor C1 through the first switch S1. The comparator includes a first comparator and a second comparator. The first input reference voltage and the positive end of the capacitor C1 are respectively connected to the positive input interface and the negative input interface of the first comparator. The capacitor C1 and the positive end of the second reference voltage are respectively connected to the positive input interface and the negative input interface of the second comparator. The outputs of the first comparator and the second comparator are commonly connected to the enable signal of the counter.

[0007] Further, the composite dielectric-gate bipolar transistor photosensitive detector pixel includes a MOS-C part and a MOSFET part. During the exposure stage, a depletion region is generated in the MOS-C part under the action of the gate substrate bias voltage to collect photo-generated carriers. During the readout stage, the threshold voltage of the MOSFET part changes correspondingly according to the amount of photo-generated charge collected.

[0008] Further, the negative feedback driving module includes a second current source, a first resistor, and a first operational amplifier. It is characterized in that the output of the second current source is connected to the positive terminal of the first resistor and the positive input terminal of the first operational amplifier. The negative terminal of the first resistor is grounded, and the negative input terminal of the first operational amplifier is connected to the output terminal of the first operational amplifier.

[0009] Further, the clamping circuit module includes a third current source, a second resistor, and a second operational amplifier. It is characterized in that the output of the third current source is connected to the positive terminal of the second resistor and the positive input terminal of the second operational amplifier. The negative terminal of the second resistor is grounded, and the negative input terminal of the second operational amplifier is connected to the output terminal of the second operational amplifier.

[0010] Further, the first current mirror includes a PMOS first transistor and a second transistor. It is characterized in that the width-to-length ratios of the PMOS first transistor and the second transistor are the same or in a proportional relationship. The source terminal and the substrate of the first transistor are connected to the power supply, and its drain terminal is the input of the first current mirror, which is connected to the gate terminals of the first transistor and the second transistor. The source terminal and the substrate of the second transistor are connected to the power supply, its gate terminal is connected to the drain terminal and the gate terminal of the first transistor, and the drain terminal of the second transistor is the output of the first current mirror.

[0011] Further, the second current mirror includes an NMOS first transistor and a second transistor. It is characterized in that the width-to-length ratios of the NMOS first transistor and the second transistor are the same or in a proportional relationship. The source terminal and the substrate of the first transistor are grounded, and its drain terminal is the input of the second current mirror, which is connected to the gate terminals of the first transistor and the second transistor. The source terminal and the substrate of the first transistor are grounded, its gate terminal is connected to the drain terminal and the gate terminal of the first transistor, and the drain terminal of the second transistor is the output of the second current mirror.

[0012] Further, the first switch S1, the second switch S2, and the third switch S3 are all different enable signal switches, and these three types of switches are turned on according to the working timing respectively.

[0013] Further, the positive and negative terminals of the comparator compare the electric potentials. When the positive terminal potential is greater than the negative terminal potential, the comparator output is 1; when the negative terminal potential is greater than the positive terminal potential, the comparator output is 0.

[0014] Further, the counter includes an AND gate, a counting module, a first latching module, and a second latching module. It is characterized in that the outputs of the first comparator and the second comparator serve as the input signals of the AND gate, and the output of the AND gate is connected to the enable signal of the counting module. The counting module has its own internal clock, and the output of the counting module is respectively connected to the first latching module and the second latching module.

[0015] Further, when the output of the AND gate is 1, the counting module starts counting. When the output of the AND gate is 0, the counting module stops counting, waits for data to be transmitted to the first latching module or the second latching module, and clears itself. When one end of the input of the AND gate is 1 and the other end jumps from 1 to 0, the counting module transmits the data to the first latching module or the second latching module and clears itself.

[0016] The circuit structure of the present invention is stable, with low noise. It can eliminate the FPN noise of the photosensitive detector (composite dielectric gate bipolar transistor pixel) array and improve the signal-to-noise ratio of the output picture. The present invention adopts a current mirror module. The photosensitive detector charges or discharges the capacitor during the light-sensing and dark-field (just after reset) stages respectively to achieve correlated double sampling, eliminating the reset noise and the initial threshold deviation of the photosensitive detector, greatly reducing the FPN noise caused by the non-uniformity of the pixels, and greatly improving the consistency of the photosensitive detector array. Description of the Drawings

[0017] Figure 1 is the structural block diagram of the correlated double sampling readout circuit of the composite dielectric gate bipolar transistor pixel based on the current mirror;

[0018] Figure 2 is the basic structure of the counter;

[0019] Figure 3 is the working timing diagram of the present invention. Detailed Embodiments

[0020] The technical solution of the present invention will be described in more detail below with reference to the drawings.

[0021] In the present application, a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) includes a source terminal, a drain terminal, and a gate terminal. In the conducting state of the MOSFET, the majority carriers flow from the source terminal to the drain terminal. The current of a P-type MOSFET flows from the source terminal to the drain terminal, and the current of an N-type MOSFET flows from the drain terminal to the source terminal.

[0022] The dual-sampling readout circuit of a composite dielectric-gate dual-transistor pixel based on a current mirror in this embodiment includes a composite dielectric-gate dual-transistor photosensitive detector pixel, a negative feedback driving module, a clamping circuit, a current mirror, switches, a comparator, and a counter. Among them, the specific structure of the composite dielectric-gate dual-transistor photosensitive detector pixel is as described in Patent CN201210442007.X. The composite dielectric-gate dual-transistor photosensitive detector pixel includes a MOS-C part and a MOSFET part. During the exposure stage, a depletion region is generated in the MOS-C part under the action of the gate substrate bias voltage to collect photo-generated carriers. During the readout stage, the threshold voltage of the MOSFET part changes correspondingly according to the collected photo-generated charge quantity. In this embodiment, the MOSFET part is of N type and includes a source electrode, a drain electrode, and a control gate. As Figure 1 shown, the source electrode of the composite dielectric-gate dual-transistor photosensitive detector pixel is grounded, the control gate is connected to the output end of the negative feedback driving module, and the drain electrode is connected to the output of the clamping circuit and the input of current mirror 1. Among them, both the negative feedback driving module and the clamping circuit adopt built-in biasing and only have output ends. The output of current mirror 1 is connected to the input of current mirror 2. The output of current mirror 1 is connected to the positive end of capacitor C1 through the second switch S2. The input of current mirror 2 is connected to the output end of current mirror 1. The output of current mirror 2 is connected to the positive end of capacitor C1 through the third switch S3. The positive end of current source I3 is connected to power supply VDD, and the negative end of current source I3 is connected to the positive end of capacitor C1 through the first switch S1. The reference voltage Vref1 and the positive end of capacitor C1 are respectively connected to the positive input interface and the negative input interface of comparator 1. The capacitor C1 and the positive end of reference voltage Vref2 are respectively connected to the positive input interface and the negative input interface of comparator 2. The outputs of comparator 1 and comparator 2 are jointly connected to the enable signal of the counter. The positive and negative ends of the comparator compare the electric potentials. When the potential at the positive end is greater than the potential at the negative end, the output of the comparator is 1. When the potential at the negative end is greater than the potential at the positive end, the output of the comparator is 0. Among them, the first switch S1, the second switch S2, and the third switch S3 are all switches with different enable signals, and these three types of switches are not turned on simultaneously.

[0023] According to an example disclosed in the present invention, the negative feedback driving module includes a current source I1, a resistor R1, and an operational amplifier. The output of the current source I1 is connected to the positive end of the resistor R1 and the positive input terminal of the operational amplifier. The negative end of the resistor R1 is connected to GND. The negative input terminal of the operational amplifier is connected to the output terminal of the operational amplifier.

[0024] According to an example disclosed in the present invention, the clamping circuit module includes a current source I2, a resistor R2, and an operational amplifier. The output of the current source I2 is connected to the positive end of the resistor R2 and the positive input terminal of the operational amplifier. The negative end of the resistor R2 is connected to GND. The negative input terminal of the operational amplifier is connected to the output terminal of the operational amplifier.

[0025] According to an example disclosed by the present invention, the current mirror 1 includes PMOS transistors MP1 and MP2. The width-to-length ratios of both the PMOS transistor MP1 and the PMOS transistor MP2 are the same or in a proportional relationship; the source and substrate of MP1 are connected to VDD, the drain of MP1 is the input of the current mirror 1, and is connected to the gates of MP1 and MP2; the source and substrate of MP2 are connected to VDD, the gate of MP2 is connected to the drain and gate of MP1, and the drain of MP2 is the output of the current mirror 1. The current mirror 2 includes NMOS transistors MN1 and MN2. The width-to-length ratios of both the NMOS transistor MN1 and the NMOS transistor MN2 are the same or in a proportional relationship; the source and substrate of MN1 are connected to GND, the drain of MN1 is the input of the current mirror 2, and is connected to the gates of MN1 and MN2; the source and substrate of MN2 are connected to GND, the gate of MN2 is connected to the drain and gate of MN1, and the drain of MN2 is the output of the current mirror 2.

[0026] According to an example disclosed by the present invention, the counter module includes an AND gate, a counting module, and two latch modules. The outputs of comparator 1 and comparator 2 serve as the input signals of the AND gate. The output of the AND gate is connected to the enable signal of the counting module. When the output of the AND gate is 1, the counting module starts counting. When the output of the AND gate is 0, the counting module stops counting, waits for data to be transmitted to latch module 1 or latch module 2, and clears itself; the counting module has its own internal clock and can count by counting the number of its own clock pulses. The output of the counting module is respectively connected to latch module 1 and latch module 2; when one end of the input of the AND gate is 1 and the other end jumps from 1 to 0, the counting module transmits the data to latch module 1 or latch module 2 and clears itself.

[0027] During the operation of the circuit, as Figure 3 shown, it is mainly divided into three time periods. The first switch S1 is open, and the second switch S2 and the third switch S3 are closed for the reset stage; the third switch S3 is open, and the first switch S1 and the second switch S2 are closed for the dark field stage; the second switch S2 is open, and the first switch S1 and the third switch S3 are closed for the photosensitive stage.

[0028] During the reset stage, the first switch S1 is conducting, the second switch S2 and the third switch S3 are closed, the output terminal connected to the current source I3 is connected to the positive terminal of the capacitor C1, and the potential of the positive terminal of the capacitor C1 is charged to the power supply potential VDD.

[0029] In the dark-field reading stage, the third switch S3 is turned on, and the first switch S1 and the second switch S2 are turned off. At this time, the photosensitive detector is in a non-exposed state. In the dark-field reading stage, the photosensitive detector is in the linear region, and the input voltage of the driving module is greater than the threshold voltage of the photosensitive detector. Therefore, the input of the negative feedback driving module, that is, the product of the current of the current source I1 and the resistor R1, I1×R1, should be greater than the input of the clamping module, that is, the product of the current of the current source I2 and the resistor R2 plus the threshold voltage of the photosensitive detector at this time. In the dark-field reading stage, the photosensitive detector is turned on and in the linear region, and the current I flowing through the photosensitive detector dark Through the accurate copying of current mirror 1 and current mirror 2, the charge on the capacitor C1 is discharged. At this time, the output of comparator 1 is 0, and the output of comparator 2 is 1. When the potential on the capacitor drops to the reference voltage Vref1, the output of comparator 1 is 1, and the output of comparator 2 is 1. The AND gate output in the counter is 1, and the counting module in the counter starts counting. When the potential on the capacitor drops to the reference voltage Vref2, the output of comparator 1 remains unchanged, and the output of comparator 2 is 0. The latch in the counter reads the value t1 of the counting module, and the counting module is cleared.

[0030] In the exposure reading stage, the second switch S2 is turned on, and the first switch S1 and the third switch S3 are turned off. At this time, the photosensitive detector is in the exposure-ended state. Since a large number of electrons are accumulated in the MOS-C part of the photosensitive detector during the exposure state, the reading threshold increases. Keeping the input of the current source I1 of the negative feedback driving module and the resistors R1, and the input of the current source I2 of the clamping circuit and the resistor R2 unchanged, the photosensitive detector is still in the linear region in the exposure reading stage, and the current I flowing through the photosensitive detector lig h t Through the accurate copying of current mirror 1 and current mirror 2, the charge on the capacitor C1 is charged. At this time, the output of comparator 1 is 1, and the output of comparator 2 is 0. When the potential on the capacitor rises to the reference voltage Vref2, the output of comparator 1 remains unchanged, and the output of comparator 2 becomes 1. The AND gate output in the counter is 1, and the counting module in the counter starts counting. When the potential on the capacitor rises to the reference voltage Vref1, the output of comparator 1 becomes 0, and the output of comparator 2 remains unchanged. The latch module in the counter reads the value t2 of the counting module, and the counting module is cleared.

[0031] During the exposure process of the composite dielectric-gate dual transistor pixel, photons will induce electrons to accumulate in the MOS-C part. The threshold of the composite dielectric-gate dual transistor pixel increases before and after exposure. Since the composite dielectric-gate dual transistor pixel is in the linear region during both the dark-field readout stage and the exposure readout stage, the current flowing out of the composite dielectric-gate dual transistor pixel is proportional to the negative threshold voltage, and the change in the threshold can be quantified by the current. Since the capacitor discharge model can be simplified as: Q = C×ΔV = I×t, where Q is the total charge number, C is the capacitance, ΔV is the change in the potential difference across the capacitor, I is the discharge current magnitude, and t is the discharge time, the discharge current magnitude is Therefore, by obtaining the values t1 and t2 of the latch module, the current magnitudes of the dark-field and exposure composite dielectric-gate dual transistor pixels can be known, and the gray value can be expressed as:

Claims

1. A compound dielectric gate dual-transistor pixel dual-sampling readout circuit based on a current mirror, comprising a compound dielectric gate dual-transistor photosensitive detector pixel, a negative feedback driving module, a clamping circuit, a current mirror, a switch, a first current source, a comparator, and a counter, characterized in that, The source of the composite dielectric-gate bipolar transistor photosensitive detector pixel is grounded, its control gate is connected to the output terminal of the negative feedback driving module, and its drain is connected to the output of the clamping circuit and the input of the current mirror. The current mirror includes a first current mirror and a second current mirror. The input of the first current mirror is connected to the drain, and its output is connected to the input of the second current mirror and is connected to the positive terminal of the capacitor C1 through the second switch S2. The output of the second current mirror is connected to the positive terminal of the capacitor C1 through the third switch S3. The positive terminal of the first current source is connected to the power supply, and its negative terminal is connected to the positive terminal of the capacitor C1 through the first switch S1. The comparator includes a first comparator and a second comparator. The first input reference voltage and the positive terminal of the capacitor C1 are respectively connected to the positive input interface and the negative input interface of the first comparator. The positive terminal of the capacitor C1 and the second reference voltage are respectively connected to the positive input interface and the negative input interface of the second comparator. The outputs of the first comparator and the second comparator are jointly connected to the enable signal of the counter.

2. The composite dielectric-gate dual-transistor pixel double-sampling readout circuit based on a current mirror according to claim 1, wherein The composite dielectric-gate bipolar transistor photosensitive detector pixel includes a MOS-C part and a MOSFET part. During the exposure stage, the MOS-C part generates a depletion region under the action of the gate substrate bias voltage to collect photo-generated carriers. During the readout stage, the threshold voltage of the MOSFET part changes correspondingly according to the collected photo-generated charge amount.

3. The composite dielectric-gate dual-transistor pixel dual-sampling readout circuit based on a current mirror according to claim 1, wherein the negative feedback driving module includes a second current source, a first resistor, and a first operational amplifier, characterized in that, The output of the second current source is connected to the positive terminal of the first resistor and the positive input terminal of the first operational amplifier. The negative terminal of the first resistor is grounded, and the negative input terminal of the first operational amplifier is connected to the output terminal of the first operational amplifier.

4. The clamping circuit module of the composite dielectric gate dual-transistor pixel double-sampling readout circuit based on a current mirror according to claim 1, wherein the clamping circuit module comprises a third current source, a second resistor, and a second operational amplifier. The output of the third current source is connected to the positive terminal of the second resistor and the positive input terminal of the second operational amplifier. The negative terminal of the second resistor is grounded, and the negative input terminal of the second operational amplifier is connected to the output terminal of the second operational amplifier.

5. The composite dielectric gate dual-transistor pixel dual-sampling readout circuit based on a current mirror according to claim 1, wherein the first current mirror includes a PMOS first transistor and a second transistor, characterized in that, The width-to-length ratios of the PMOS first transistor and the second transistor are the same or in a proportional relationship. The source and substrate of the first transistor are connected to the power supply, and its drain is the input of the first current mirror and is connected to the gate of the first transistor and the gate of the second transistor. The source and substrate of the second transistor are connected to the power supply, its gate is connected to the drain and gate of the first transistor, and the drain of the second transistor is the output of the first current mirror.

6. The compound dielectric gate dual-transistor pixel dual-sampling readout circuit based on a current mirror according to claim 1, wherein the second current mirror comprises an NMOS first transistor and a second transistor. The width-to-length ratios of the NMOS first transistor and the second transistor are the same or in a proportional relationship. The source and substrate of the first transistor are grounded, and its drain is the input of the second current mirror and is connected to the gate of the first transistor and the gate of the second transistor. The source and substrate of the second transistor are grounded, its gate is connected to the drain and the gate of the first transistor, and the drain of the second transistor is the output of the second current mirror.

7. The compound dielectric gate dual-transistor pixel dual-sampling readout circuit based on a current mirror according to claim 1, wherein The first switch S1, the second switch S2, and the third switch S3 are all different enable signal switches, and these three types of switches are turned on according to the working timing.

8. The compound dielectric gate dual-transistor pixel dual-sampling readout circuit based on a current mirror according to claim 1, characterized in that, The comparator compares the positive and negative potential differences. When the positive terminal potential is greater than the negative terminal potential, the comparator output is 1, and when the negative terminal potential is greater than the positive terminal potential, the comparator output is 0.

9. The compound dielectric gate dual-transistor pixel double-sampling readout circuit based on a current mirror according to claim 1, wherein the counter comprises an AND gate, a counting module, a first latching module, and a second latching module. The outputs of the first comparator and the second comparator serve as the input signals of an AND gate, and the output of the AND gate is connected to the enable signal of the counting module; the counting module has its own internal clock, and the output of the counting module is respectively connected to the first latch module and the second latch module.

10. The composite dielectric-gate dual-transistor pixel double-sampling readout circuit based on a current mirror according to claim 9, wherein When the output of the AND gate is 1, the counting module starts counting. When the output of the AND gate is 0, the counting module stops counting, waits for data to be transmitted to the first latch module or the second latch module, and clears itself; when one end of the input of the AND gate is 1 and the other end jumps from 1 to 0, the counting module transmits the data to the first latch module or the second latch module and clears itself.

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