A PWM dimming circuit and dimming chip

Abstract

This application relates to the field of PWM dimming technology, providing a PWM dimming circuit and a dimming chip. The dimming circuit includes a PWM signal sampling module for acquiring the signal value of the PWM signal at both edges of the clock signal, the signal value including a high-level value and a low-level value; a PWM signal edge detection module for detecting the rising edge flag signal and the falling edge flag signal of the PWM signal; and a dimming code determination module, connected to the PWM signal sampling module and the PWM signal edge detection module, for determining the ratio between the count of high-level values ​​and the total count of signal values ​​in each cycle of the PWM signal based on the rising edge flag signal, the falling edge flag signal, and the signal value of the PWM signal, and determining the dimming code based on the ratio. The above dimming circuit and dimming chip can improve detection accuracy, that is, improve the accuracy of adjusting the brightness of the light-emitting diode (LED), save the power consumption required for clock switching, and further improve the performance of the chip.

Description

Technical Field

[0001] This application relates to the field of PWM dimming technology, and in particular to a PWM dimming circuit and dimming chip. Background Technology

[0002] Pulse Width Modulation (PWM) controls the switching of devices in an inverter circuit, producing a series of pulses with equal amplitude but varying widths at the output. These pulses are used to replace a sine wave or the desired waveform. PWM dimming technology uses simple digital pulses to change the current of an LED, thereby adjusting its brightness. Digital PWM dimming technology based on digital sampling is currently one of the most widely used PWM dimming techniques.

[0003] Currently, digital PWM dimming technologies based on digital sampling methods all use single-edge sampling of the clock signal. Their detection accuracy depends on the frequencies of the clock and PWM signals; generally, the higher the clock frequency, the higher the detection accuracy, and thus the more precise the adjustment of the LED brightness. However, due to hardware and other technological limitations, if single-edge sampling of the clock signal is used, existing clock frequencies are insufficient to achieve high-precision sampling of PWM signals with low duty cycles. Furthermore, if sampling of PWM signals with low dimming codes is required, the necessary clock frequency is also higher, resulting in greater power consumption during clock switching, further impacting chip performance. Summary of the Invention

[0004] This application provides a PWM dimming circuit and dimming chip, which improves the detection accuracy of the PWM signal and the brightness adjustment accuracy of the light-emitting diode (LED) by sampling the PWM signal using the rising and falling edges of the clock.

[0005] In a first aspect, this application provides a PWM dimming circuit, comprising: a PWM signal sampling module for acquiring the signal value of a PWM signal at both edges of a clock signal, the signal value including a high level value and a low level value; a PWM signal edge detection module for detecting the rising edge flag signal and the falling edge flag signal of the PWM signal; and a dimming code determination module connected to the PWM signal sampling module and the PWM signal edge detection module for determining, based on the rising edge flag signal and the falling edge flag signal of the PWM signal, and the signal value of the PWM signal, the ratio between the count of high level values ​​and the total count of signal values ​​in each cycle of the PWM signal, and determining the dimming code based on the ratio.

[0006] In conjunction with the first aspect, in some implementations, the PWM signal sampling module includes: a first sampling module for acquiring the signal value of the PWM signal at the rising edge of the clock signal; and a second sampling module for acquiring the signal value of the PWM signal at the falling edge of the clock signal.

[0007] In conjunction with the first aspect, in some implementations, the first sampling module includes a first register, which is used to receive a clock signal and acquire the signal value of the PWM signal at the rising edge of the clock signal; the second sampling module includes a second register, which is used to receive the inverse signal of the clock signal and acquire the signal value of the PWM signal at the rising edge of the inverse signal.

[0008] In conjunction with the first aspect, in some implementations, the dimming code determination module includes: a first counting module, connected to the first sampling module, the second sampling module, and the PWM signal edge detection module, used to determine the count of high-level values ​​in each cycle of the PWM signal; a second counting module, connected to the first sampling module, the second sampling module, and the PWM signal edge detection module, used to determine the count of low-level values ​​in each cycle of the PWM signal; an addition module, connected to the first and second counting modules, used to accumulate the count of high-level values ​​and the count of low-level values ​​to obtain the total count of the signal value; and a division module, connected to the first counting module and the addition module, used to divide the count of high-level values ​​and the count of the signal value to obtain the ratio of the count of high-level values ​​to the total count.

[0009] In conjunction with the first aspect, in some implementations, the first counting module includes: a first adder, the first input terminal of which is connected to the output terminal of the first sampling module, and the second input terminal of which is connected to the output terminal of the second sampling module through a first inverter; a third register, the input terminal of which is connected to the output terminal of the first adder, and a signal control terminal for receiving a clock signal; and the second counting module includes: a second adder, the first input terminal of which is connected to the output terminal of the second sampling module, and the second input terminal of which is connected to the output terminal of the first sampling module through a second inverter; and a fourth register, the input terminal of which is connected to the output terminal of the second adder, and a signal control terminal for receiving a clock signal.

[0010] In conjunction with the first aspect, in some implementations, the addition module includes: a third adder, the first input of which is connected to the first output of the third register, and the second input of which is connected to the output of the fourth register; a fifth register, the input of which is connected to the output of the third adder, and a control signal terminal for receiving a clock signal; and the division module includes: a divider, the divisor input of which is connected to the output of the fifth register, the dividend input of which is connected to the second output of the third register, and a sixth register, the input of which is connected to the output of the divider.

[0011] In conjunction with the first aspect, in some implementations, the PWM signal edge detection module includes: a first edge detection module for detecting the rising edge flag signal of the PWM signal; and a second edge detection module for detecting the falling edge flag signal of the PWM signal; wherein the first counting module, the addition module, and the division module of the dimming code determination module are respectively connected to the first edge detection module, and the second counting module of the dimming code determination module is connected to the second edge detection module.

[0012] In conjunction with the first aspect, in some implementations, the first edge detection module includes a seventh register, an eighth register, a third inverter, a fourth inverter, a first OR gate, a first AND gate, and a second AND gate. The first input of the seventh register is connected to the output of the first sampling module, the control signal input of the seventh register is used to receive a clock signal, and the output of the seventh register is connected to the input of the third inverter. The first input of the eighth register is connected to the output of the second sampling module, the control signal input of the eighth register is used to receive the inverted signal of the clock signal, and the output of the eighth register is connected to the input of the fourth inverter. The outputs of the third and fourth inverters are respectively connected to the two inputs of the first AND gate. The outputs of the first and second sampling modules are respectively connected to the two inputs of the first OR gate, the outputs of the first OR gate and the first AND gate are respectively connected to the two inputs of the second AND gate, and the output of the second AND gate is used to output a rising edge flag signal.

[0013] In conjunction with the first aspect, in some implementations, the second edge detection module includes a ninth register, a tenth register, a fifth inverter, a sixth inverter, a second OR gate, a third AND gate, and a fourth AND gate. The first input of the ninth register is connected to the output of the first sampling module, the control signal input of the ninth register is used to receive a clock signal, and the output of the ninth register is connected to the first input of the third AND gate. The first input of the tenth register is connected to the output of the second sampling module, the control signal input of the tenth register is used to receive the inverted signal of the clock signal, and the output of the tenth register is connected to the second input of the third AND gate. The inputs of the fifth and sixth inverters are respectively connected to the outputs of the first and second sampling modules. The output of the fifth inverter is connected to the first input of the second OR gate, the output of the sixth inverter is connected to the second input of the second OR gate, the outputs of the second OR gate and the third AND gate are respectively connected to the two inputs of the fourth AND gate, and the output of the fourth AND gate is used to output a falling edge flag signal.

[0014] In conjunction with the first aspect, in some implementations, the PWM dimming circuit also includes a frequency switching module, which is used to provide a clock signal and an inverse clock signal of the corresponding frequency to the PWM signal sampling module and the PWM signal edge detection module.

[0015] In conjunction with the first aspect, in some implementations, the frequency switching module includes: a period determination module, used to determine the required clock frequency based on the total count of the received signal values, and then input the enable of the required clock frequency to the clock selection module; the input terminal of the period determination module is connected to the output terminal of the PWM signal sampling module, and the input terminal of the period determination module is connected to the clock selection module; a clock division module, used to divide the initial clock signal into clock signals with frequencies different from the initial clock signal; and a clock selection module, used to select the clock signal of the required clock frequency from the clock division module, and then provide the clock signal of the required clock frequency to the PWM signal sampling module and the PWM signal edge detection module.

[0016] In conjunction with the first aspect, in some implementations, the period determination module includes n gears, where n is a natural number greater than or equal to 1. Each gear corresponds to a PWM signal with a frequency range and a clock signal with a frequency.

[0017] Secondly, this application provides a PWM dimming chip, including a main circuit and a PWM dimming circuit as described above, wherein the main circuit may include a current analog-to-digital converter (IDAC).

[0018] In summary, the PWM dimming circuit and dimming chip provided in this application sample the PWM signal using both edges of the clock (i.e., rising edge and falling edge). Compared with the single-edge sampling method, the sampling frequency can be doubled without increasing the clock frequency (i.e. without increasing the clock inversion power consumption), thereby improving the detection accuracy and dimming accuracy. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1a A schematic diagram of a PWM signal is shown according to some embodiments of this application;

[0021] Figure 1b According to some embodiments of this application, a schematic diagram of a PWM dimming circuit is shown;

[0022] Figure 2 According to some embodiments of this application, a schematic diagram is shown of sampling a PWM signal using the rising edge of a clock signal;

[0023] Figure 3a According to some embodiments of this application, a schematic diagram of another PWM dimming circuit is shown;

[0024] Figure 3b According to some embodiments of this application, a schematic diagram of another PWM dimming circuit is shown;

[0025] Figure 4a According to some embodiments of this application, a schematic diagram of the structure of the first edge detection module is shown;

[0026] Figure 4b According to some embodiments of this application, a schematic diagram of another first edge detection module is shown;

[0027] Figure 5 According to some embodiments of this application, a schematic diagram is shown of sampling a PWM signal using the rising and falling edges of a clock signal. Detailed Implementation

[0028] The illustrative embodiments will now be described using terms commonly used by those skilled in the art.

[0029] It is understood that the illustrative embodiments of this application include, but are not limited to, a PWM dimming circuit and a dimming chip.

[0030] In the embodiments of this application, "one or more" refers to one, two, or more; "and / or" describes the relationship between related objects, indicating that three relationships can exist; for example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone, where A and B can be singular or plural. The character " / " generally indicates that the related objects before and after it have an "or" relationship.

[0031] To facilitate understanding, some of the terms used in this article are explained below.

[0032] (1) PWM duty cycle: The proportion of high level in the entire cycle within a pulse cycle.

[0033] As described in the background section, Pulse Width Modulation (PWM) is a highly effective technique for controlling analog circuits using the digital output of a microprocessor. It modulates the width of a series of pulses to create the desired waveform (including shape and amplitude), digitally encoding the analog signal level. As a control engine, PWM has become crucial for drivers in modern semiconductor electromechanical and electrical equipment. Most power electronic systems are driven and controlled by PWM signals, and PWM is widely used in many fields, from measurement and communication to power control and conversion.

[0034] Figure 1a A schematic diagram of a PWM signal is shown. (Reference) Figure 1a A PWM signal includes high-level values ​​(represented by "1") and low-level values ​​(represented by "0"). The duration of adjacent high-level and low-level values ​​is called one cycle of the PWM signal. The ratio of the duration of the high-level value to the total duration of the cycle within a PWM signal cycle is called the duty cycle of the PWM signal. For ease of explanation, the following embodiments use PWM signal I with a duty cycle of 0.65, PWM signal II with a duty cycle of 0.5, and PWM signal III with a duty cycle of 0.6 as examples to illustrate the technical solution of this application. It is understood that in other embodiments, the duty cycle of the PWM signal can be any value between 0 and 1. Furthermore, in other embodiments, the duty cycle of the PWM signal also changes over time.

[0035] The following is in conjunction with the appendix Figure 1b and Figure 2 The structure and sampling principle of the PWM dimming circuit are explained in some embodiments.

[0036] like Figure 1bAs shown, a PWM dimming circuit includes a synchronization register 110, an adder 120, a high-count register 130, an inverter 140, an adder 150, a low-count register 160, an adder 170, a register 180, a divider 190, a dimming code register 200, and an edge detection circuit. The edge detection circuit includes a register 210, an inverter 220, and an AND gate 230, as well as a register 240, an inverter 250, and an AND gate 260.

[0037] The working principle of the above PWM dimming circuit is as follows:

[0038] The PWM signal is input to the synchronization register 110. The synchronization register 110 is used to synchronize the PWM signal to the clock domain and to sample the PWM signal using the rising edge of the clock signal. The CLK signal in the diagram is the clock signal. After sampling the PWM signal using the rising edge of the clock signal, the synchronization register 110 sequentially inputs the number of high-level samples within one cycle of the PWM signal into the start adder 120 for accumulation, obtaining the count of high-level values ​​within one cycle of the PWM signal, and then stores it in the high-count register 130. Furthermore, after sampling the PWM signal using the rising edge of the clock signal, the synchronization register 110 also samples the number of low-level samples within one cycle of the PWM signal. The counts of low-level values ​​in one cycle of the PWM signal are accumulated by sequentially inputting into inverter 140 and adder 150, and then stored in low-level count register 160. Then, the counts of high-level values ​​in high-level count register 130 and the counts of low-level values ​​in low-level count register 160 are input into adder 170 to obtain the total count of signal values, and then the total count of signal values ​​is stored in cycle count register 180. Then, the counts of high-level values ​​stored in high-level count register 130 and the total count of signal values ​​stored in cycle count register 180 are input into first initial divider 190 to obtain dimming code. Finally, the dimming code is stored in dimming code register 200.

[0039] In the edge detection circuit, register 210, inverter 220, and AND gate 230 are used to detect the rising edge of the PWM signal. When the edge detection circuit detects the first rising edge flag signal, the divider 190 performs a division operation based on the count of the high-level value sent by the high-count register 130 and the total count of the signal value sent by the period count register 180 to obtain the dimming code, and the high-count register 130 is cleared. Register 240, inverter 250, and AND gate 260 are used to detect the falling edge of the PWM signal. When the edge detection circuit detects the first falling edge flag signal, the low-count register 160 is cleared.

[0040] The dimming code output from the aforementioned PWM dimming circuit is used to dim the LED. For example, after the dimming code register 200 inputs the dimming code into the current analog-to-digital converter (IDAC), the IDAC generates an output current, which is the current of the LED. Exemplarily, the relationship between the output current of the IDAC and the dimming code can be expressed as I = I0 base × Dimming code, where I is the output current of the current analog-to-digital converter (IDAC), I base The reference current of the current analog-to-digital converter (IDAC) is used. It can be understood that the current of the LED will change according to the dimming code. Therefore, the dimming code can be used to implement the dimming operation of the LED light-emitting diode.

[0041] Figure 2 It shows the use of Figure 1b The dimming circuit shown is a schematic diagram of sampling PWM signals with different dimming codes based on the rising edge of the clock signal, as follows: Figure 2 As shown, the signal between A and B is PWM signal I (PWM signal of the first cycle), the signal between B and C is PWM signal II (PWM signal of the second cycle), and the signal between C and D is PWM signal III (PWM signal of the third cycle).

[0042] In the synchronization register 110, the rising edge of the clock signal is used to sample the PWM signal I. After sampling the PWM signal I at the rising edges of clock signal 1, clock signal 2, and clock signal 3, the high-level count is obtained by adder 120, which is 3. After sampling the PWM signal I at the rising edge of clock signal 4, the low-level count is obtained by adder 150, which is 1. The high-level count 3 and the low-level count 1 are stored in the high-count register 130 and the low-count register 160, respectively. The high-level count 3 and the low-level count 1 stored in the high-count register 130 and the low-level count register 160 are input into adder 170 to obtain the total signal count 4. Then, the total signal count 4 is stored in the first signal count register 180. The high-level count 3 stored in the high-count register 130 and the total signal count stored in the register 180 are input into divider 190 to obtain the dimming code 0.75, and the dimming code is then stored in dimming code register 200.

[0043] Similarly, after sampling PWM signal II using the rising edge of the clock signal in synchronization register 110, the resulting dimming code 0.43 is stored in dimming code register 200. After sampling PWM signal III using the rising edge of the clock signal in synchronization register 110, the resulting dimming code 0.67 of PWM signal III is stored in dimming code register 200.

[0044] It's understandable that in actual sampling, a large number of rising edges of the clock signal are needed to sample the PWM signal, not just a few. Figure 2 The 14 rising edges of the clock signals shown are used, but the specific number of clock signals used varies depending on the frequency of the clock signals and the frequency of the PWM signals.

[0045] exist Figure 1b In the illustrated scheme, the dimming circuit samples the PWM signal only on the rising edge of the clock signal, thus requiring a high-speed clock to achieve sufficient detection accuracy. However, high-speed clocks consume significant power, which impacts chip performance. Furthermore, when the dimming code of the PWM signal is low (e.g., below 0.2%), Figure 1b The dimming circuit shown is difficult to achieve high-precision detection. Therefore, as... Figure 3a This application proposes another PWM dimming circuit, including: a PWM signal sampling module for acquiring the signal value of the PWM signal at both edges of a clock signal, the signal value including a high level value and a low level value; a PWM signal edge detection module for detecting the rising edge flag signal and the falling edge flag signal of the PWM signal; and a dimming code determination module connected to the PWM signal sampling module and the PWM signal edge detection module for determining the ratio between the number of high level values ​​and the total number of signal values ​​in each cycle of the PWM signal based on the rising edge flag signal, the falling edge flag signal, and the signal value of the PWM signal, and determining the dimming code based on the ratio.

[0046] In this application, the dimming circuit can sample the PWM signal at both edges of the clock signal, namely the rising edge and the falling edge of the clock signal, and output a dimming code, which can be used to dim the LED light-emitting diode.

[0047] Compared to the prior art method of sampling the PWM signal using only the rising edge of the clock, this method samples the PWM signal using both the rising and falling edges of the clock. Figure 1b Compared to single-edge sampling, this method can double the sampling frequency while maintaining the same clock frequency, thereby improving the detection accuracy of the dimming circuit. Alternatively, while maintaining the same detection accuracy, the frequency of the clock signal used in this application can be reduced to [a lower value]. Figure 1b This is half of the method shown, which can reduce the power consumption of clock reversal and improve chip performance.

[0048] Specifically, such as Figure 3bAs shown, the PWM signal sampling module includes: a first sampling module, used to acquire the signal value of the PWM signal at the rising edge of the clock signal; and a second sampling module, used to acquire the signal value of the PWM signal at the falling edge of the clock signal.

[0049] Specifically, the first sampling module includes a first register 310, which is used to receive a clock signal and acquire the signal value of the PWM signal at the rising edge of the clock signal; the second sampling module includes a second register 350, which is used to receive the inverted signal of the clock signal and acquire the signal value of the PWM signal at the rising edge of the inverted signal.

[0050] The first and second sampling modules mentioned above sample the PWM signal using the clock signal and its direction signal through two registers, respectively, which can obtain the sampling counts of the high and low levels of the PWM signal, thus improving the overall detection accuracy.

[0051] Specifically, the dimming code determination module includes: a first counting module, connected to the first sampling module, the second sampling module, and the PWM signal edge detection module, used to determine the number of high-level values ​​in each cycle of the PWM signal; a second counting module, connected to the first sampling module, the second sampling module, and the PWM signal edge detection module, used to determine the number of low-level values ​​in each cycle of the PWM signal; an addition module, connected to the first and second counting modules, used to accumulate the number of high-level values ​​and the number of low-level values ​​to obtain the total number of signal values; and a division module, connected to the first counting module and the addition module, used to divide the number of high-level values ​​and the total number of signal values ​​to obtain the ratio of the number of high-level values ​​to the total number of counts.

[0052] The dimming encoding module described above can obtain a dimming code by receiving high-level and low-level sampling counts collected by the first sampling module and the second sampling module, and then obtain a dimming current by inputting the dimming code into a current analog-to-digital converter. This dimming current is used to adjust the brightness of the LED light-emitting diode.

[0053] Specifically, the first counting module includes: a first adder 330, whose first input terminal is connected to the output terminal of the first sampling module, and whose second input terminal is connected to the output terminal of the second sampling module through a first inverter 320; a third register 340, whose input terminal is connected to the output terminal of the first adder 330, and whose signal control terminal is used to receive a clock signal; and the second counting module includes: a second adder 370, whose first input terminal is connected to the output terminal of the second sampling module, and whose second input terminal is connected to the output terminal of the first sampling module through a second inverter 360; and a fourth register 380, whose input terminal is connected to the output terminal of the second adder 370, and whose signal control terminal is used to receive a clock signal.

[0054] The first counting module receives high-level sampling counts from the first and second sampling modules, uses an adder to obtain the count of high-level values ​​in each sampling period, and stores the high-level counts in a register. Similarly, the second counting module receives low-level sampling counts from the first and second sampling modules, uses an adder to obtain the count of low-level values ​​in each sampling period, and stores the low-level counts in a register. By processing the sampling data from the first and second sampling modules, the counts of high-level and low-level values ​​of the PWM signal in each sampling period can be obtained.

[0055] Specifically, the addition module includes: a third adder 390, whose first input is connected to the first output of the third register 340, and whose second input is connected to the output of the fourth register 380; a fifth register 400, whose input is connected to the output of the third adder 390, and whose control signal terminal is used to receive a clock signal; and the division module includes: a divider 410, whose divisor input is connected to the output of the fifth register 400, whose dividend input is connected to the second output of the third register 340; and a sixth register, whose input is connected to the output of the divider 410.

[0056] The addition module described above calculates the total signal count by combining the counts of high-level values ​​and low-level values ​​acquired by the first and second counting modules in each sampling period. Similarly, the division module calculates the ratio of the received high-level value counts to the total signal count, i.e., the dimming code, using the received high-level value counts and the total signal count. By acquiring the dimming code of the PWM signal in each sampling period, the final dimming code can be determined.

[0057] like Figure 4a and Figure 4b As shown, specifically, the PWM signal edge detection module 430 includes: a first edge detection module for detecting the rising edge flag signal of the PWM signal; and a second edge detection module for detecting the falling edge flag signal of the PWM signal; wherein, the first counting module, the addition module, and the division module in the dimming code determination module are respectively connected to the first edge detection module, and the second counting module in the dimming code determination module is connected to the second edge detection module.

[0058] The first edge detection module and the second edge detection module detect the rising edge flag signal and the falling edge flag signal of the PWM signal and input them into the PWM signal sampling module to control the PWM signal sampling module to perform sampling.

[0059] Specifically, the first edge detection module includes a seventh register 440, an eighth register 450, a third inverter 460, a fourth inverter 470, a first OR gate 480, a first AND gate 490, and a second AND gate 500. The first input of the seventh register 440 is connected to the output of the first sampling module, the control signal input of the seventh register 440 is used to receive the clock signal, and the output of the seventh register 440 is connected to the input of the third inverter 460. The first input of the eighth register 450 is connected to the output of the second sampling module. The control signal input terminal is used to receive the inverted signal of the clock signal. The output terminal of the eighth register 450 is connected to the input terminal of the fourth inverter 470. The output terminals of the third inverter 460 and the fourth inverter 470 are respectively connected to the two input terminals of the first AND gate 490. The output terminals of the first sampling module and the second sampling module are respectively connected to the two input terminals of the first OR gate 480. The output terminals of the first OR gate 480 and the first AND gate 490 are respectively connected to the two input terminals of the second AND gate 500. The output terminal of the second AND gate 500 is used to output the rising edge flag signal.

[0060] The aforementioned first edge detection module receives signals from the first sampling module and the second sampling module, and obtains the rising edge flag signal of the PWM signal through several electronic components, so as to control the PWM signal sampling module to perform sampling.

[0061] Specifically, the second edge detection module includes a ninth register 510, a tenth register 520, a fifth inverter 530, a sixth inverter 540, a second OR gate 550, a third AND gate 560, and a fourth AND gate 570. The first input of the ninth register 510 is connected to the output of the first sampling module, and its control signal input is used to receive a clock signal. The output of the ninth register 510 is connected to the first input of the third AND gate 560. The first input of the tenth register 520 is connected to the output of the second sampling module, and its control signal input is used to receive a clock signal. The inverted clock signal is connected to the output of the tenth register 520 and the second input of the third AND gate 560. The inputs of the fifth inverter 530 and the sixth inverter 540 are respectively connected to the outputs of the first sampling module and the second sampling module. The output of the fifth inverter 530 is connected to the first input of the second OR gate 550. The output of the sixth inverter 540 is connected to the second input of the second OR gate 550. The outputs of the second OR gate 550 and the third AND gate 560 are respectively connected to the two inputs of the fourth AND gate 570. The output of the fourth AND gate 570 is used to output the falling edge flag signal.

[0062] The aforementioned second edge detection module receives signals from the first and second sampling modules and obtains the falling edge flag signal of the PWM signal through several electronic components, thereby controlling the PWM signal sampling module to perform sampling.

[0063] First register 310, first inverter 320, first adder 330, third register 340, second inverter 360, second adder 370, fourth register 380, second register 350, total signal value count, total signal value count, divider 410, encoding, sixth register 420, first adder 330, first inverter 320, total signal value count, total signal value count, second inverter 360, second adder 370, divider 410.

[0064] The first edge detection module acts as a detector for the third inverter (460), the fourth inverter (470), the first AND gate (490), the second AND gate (500), the ninth register (510), the tenth register (520), the fifth inverter (530), the sixth inverter (540), the third AND gate (560), and the fourth AND gate (570). Figure 3b As shown, the PWM dimming circuit also includes a frequency switching module, which provides a clock signal and an inverse clock signal of the corresponding frequency to the PWM signal sampling module and the PWM signal edge detection module.

[0065] The working principle of the PWM dimming circuit 20 is as follows:

[0066] In the PWM sampling circuit, the PWM signal is input to the first register 310 and the second register 350. The first register 310 is used to synchronize the PWM signal to the clock domain and to sample the PWM signal using the rising edge of the clock signal. The second register 350 is used to synchronize the PWM signal to the clock domain and to sample the PWM signal using the falling edge of the clock signal. In the figure, CLK is the clock signal and CLK_N is the inverted clock signal. After the first register 310 samples the PWM signal using the rising edge of the clock signal, it inputs the number of high-level samples within one cycle of the PWM signal into the first adder 330 for accumulation. At the same time, after the second register 350 samples the PWM signal using the falling edge of the clock signal, it inputs the number of high-level samples within one cycle of the PWM signal into the first inverter 320 and the first adder 330 for accumulation, obtaining the count of high-level values ​​in one cycle of the PWM signal, and then storing it in the third register 340. The first register 310 samples the PWM signal using the rising edge of the clock signal, and then inputs the number of low-level samples within one cycle of the PWM signal into the second inverter 360 and the second adder 370 for accumulation. Simultaneously, the second register 350 samples the PWM signal using the falling edge of the clock signal, and then inputs the number of low-level samples within one cycle of the PWM signal into the second adder 370 for accumulation, obtaining the count of low-level values ​​in one cycle of the PWM signal, which is then stored in the fourth register 380. Next, the counts of high-level values ​​in the third register 340 and the counts of low-level values ​​in the fourth register 380 are input into the sixth adder 390 to obtain the total signal value count, which is then stored in the second signal value count register 400. Then, the counts of high-level values ​​stored in the third register 340 and the total signal value count stored in the second signal value count register 400 are input into the divider 410 to obtain the dimming code. Finally, the dimming code is stored in the sixth encoding register 420. The sixth register 420 inputs the dimming code into the current analog-to-digital converter (IDAC). The IDAC outputs the current corresponding to the dimming code, and then inputs the current into the LED, thereby realizing the dimming operation of the LED.

[0067] In the first edge detection module, the third register 440, the fourth register 450, the third inverter 460, the fourth inverter 470, the first OR gate 480, the first AND gate 490, and the second AND gate 500 are used to detect the rising edge of the PWM signal. The first register 310 samples the PWM signal using the rising edge of the clock signal, and then inputs the sampled PWM signal into the first OR gate 480 and the third register 440. The third register 440 samples the PWM signal using the rising edge of the clock signal, and then inverts the sampled PWM signal through the third inverter 460 before inputting it into the first AND gate 490. The second register 350 samples the PWM signal using the falling edge of the clock signal, and then inputs the sampled PWM signal into the first OR gate 480 and the fourth register 450. The fourth register 450 samples the PWM signal using the falling edge of the clock signal, and then inverts the sampled PWM signal through the fourth inverter 470 before inputting it into the first AND gate 490. The first OR gate 480 and the first AND gate 490 input the output signal into the second AND gate 500 to obtain the second rising edge flag signal, which is the rising edge pulse flag of the PWM signal. When the first edge detection module detects the second rising edge flag signal, it inputs the second rising edge flag signal into the third register 340, the sixth adder 390, and the divider 410 respectively. The sixth adder 390 calculates the total count of the signal value based on the count of high-level values ​​sent by the third register 340 and the count of low-level values ​​sent by the fourth register 380, and sends the total count of the signal value to the divider 410. After receiving the second rising edge flag signal, the divider 410 performs a division operation to obtain the dimming code, and the third register 340 is cleared. The sixth register 420 inputs the dimming code into the current analog-to-digital converter (IDAC). The current analog-to-digital converter (IDAC) outputs the current corresponding to the dimming code, and then inputs the current into the LED, thereby realizing the dimming operation of the LED.

[0068] In the second edge detection module, the ninth register 510, the tenth register 520, the fifth inverter 530, the sixth inverter 540, the second OR gate 550, the third AND gate 560, and the fourth AND gate 570 are used to detect the falling edge of the PWM signal. The first register 310 samples the PWM signal using the rising edge of the clock signal, inputs the sampled PWM signal to the fifth inverter 530 and the second OR gate 550, and inputs the sampled PWM signal to the ninth register 510; the ninth register 510 samples the PWM signal using the rising edge of the clock signal, and inputs the sampled PWM signal to the third AND gate 560; the second register 350 samples the PWM signal using the falling edge of the clock signal, inputs the sampled PWM signal to the sixth inverter 540 for inversion, and then inputs it to the second OR gate 550; the tenth register 520 samples the PWM signal using the falling edge of the clock signal, and inputs the sampled PWM signal to the third AND gate 560; the second OR gate 550 and the third AND gate 560 respectively input the signals to the fourth AND gate 570 to obtain the second falling edge flag signal, wherein the second falling edge flag signal is the falling edge pulse flag of the PWM signal. When the first edge detection module detects the second falling edge flag signal, it inputs the second falling edge flag signal into the fourth register 380, which is then cleared. The sixth encoding register 420 inputs the dimming code into the current analog-to-digital converter (IDAC). The IDAC outputs the current corresponding to the dimming code, which is then input into the LED, thus achieving the dimming operation of the LED.

[0069] Similar to the principle described above, dimming codes are used to dim LEDs. After the second dimming code register 410 inputs the dimming code into the current analog-to-digital converter (IDAC), the output current of the IDAC, which is also the current of the LED, will change according to the dimming code. The relationship between the output current of the IDAC and the dimming code can be expressed as I = I base × Dimming code, where I is the output current of the current analog-to-digital converter (IDAC), I base Since the current is the reference current of the current analog-to-digital converter (IDAC), the dimming operation of the LED can be achieved by inputting different dimming codes into the current analog-to-digital converter (IDAC) and then inputting the current into the LED.

[0070] Figure 5 A schematic diagram is shown illustrating the sampling of the PWM signal using the rising and falling edges of the clock signal, as follows: Figure 5As shown, the signal between A and B is PWM signal I (PWM signal of the first cycle), the signal between B and C is PWM signal II (PWM signal of the second cycle), and the signal between C and D is PWM signal III (PWM signal of the third cycle).

[0071] In the first register 310, the rising edge of the clock signal is used to sample the PWM signal I. The rising edges of clock signals 1, 2, and 3 are used to sample the PWM signal I, and the samples are then input to the first adder 330. In the second register 350, the falling edge of the clock signal is used to sample the PWM signal I. The falling edges of clock signals 1 and 2 are used to sample the PWM signal I, and the samples are then input to the first inverter 320 and the first adder 330. Accumulation yields a high-level count of 5. In the first register 310, the rising edge of the clock signal is used to sample the PWM signal I. The rising edge of clock signal 4 is used to sample the PWM signal I, and the samples are then input to the second inverter 360 and the second adder 370. In the second register 350, the falling edge of the clock signal is used to sample the PWM signal I. The falling edges of clock signals 3 and 3 are used to sample the PWM signal I. After sampling the PWM signal I on the falling edge of signal 4, the signal is input to the second adder 370. The accumulation yields a low-level count of 3. The high-level count of 5 and the low-level count of 3 are stored in the third register 340 and the fourth register 380, respectively. The high-level count of 5 and the low-level count of 3 stored in the third register 340 and the fourth register 380 are input to the sixth adder 390 to obtain the total signal count of 8. The total signal count of 8 is then stored in the second total signal count register 400. The high-level count of 5 stored in the third register 340 and the total signal count of 8 stored in the second total signal count register 400 are input to the divider 410 to obtain the dimming code 0.63 of the PWM signal I. The dimming code 0.63 of the PWM signal I is then stored in the sixth encoding register 420.

[0072] Similarly, in the first register 310, the rising edge of the clock signal is used to sample the PWM signal II. The rising edges of clock signals 5, 6, and 7 are used to sample the PWM signal I, which is then input into the first adder 330. In the second register 350, the falling edge of the clock signal is used to sample the PWM signal I. The falling edges of clock signals 5, 6, and 7 are used to sample the PWM signal I, which is then input into the first inverter 320 and the first adder 330 in sequence. The accumulation yields a high-level count of 6. In the first register 310, the rising edge of the clock signal is used to sample the PWM signal II. The rising edges of clock signals 8, 9, 10, and 11 are used to sample the PWM signal II, which is then input into the second inverter 360 and the second adder 370 in sequence. In the second register 350, the falling edge of the clock signal is used to sample the PWM signal I. The PWM signal I is sampled at the falling edges of clock signals 8, 9, and 10, and then input to the second adder 370. Accumulation yields a low-level count of 7. The high-level count of 6 and the low-level count of 7 are stored in the third register 340 and the fourth register 380, respectively. The high-level count of 6 and the low-level count of 7 stored in the third register 340 and the fourth register 380 are input to the sixth adder 390 to obtain a total signal count of 13. This total signal count of 13 is then stored in the second total signal count register 400. The high-level count of 6 stored in the third register 340 and the total signal count of 13 stored in the second total signal count register 400 are input to the divider 410 to obtain the dimming code 0.46 of the PWM signal II. This dimming code 0.46 is then stored in the sixth encoding register 420.

[0073] Similarly, in the first register 310, the rising edge of the clock signal is used to sample the PWM signal III. The rising edges of clock signals 12 and 13 are used to sample the PWM signal III, which is then input to the first adder 330. In the second register 350, the falling edge of the clock signal is used to sample the PWM signal III. The falling edges of clock signals 11 and 12 are used to sample the PWM signal III, which is then input to the first inverter 320 and the first adder 330 sequentially. Accumulation yields a high-level count of 4. In the first register 310, the rising edge of the clock signal is used to sample the PWM signal III. The rising edge of clock signal 14 is used to sample the PWM signal III, which is then input to the second inverter 360 and the second adder 370 sequentially. In the second register 350, the falling edge of the clock signal 13 is used to sample the PWM signal III. The rising edge of clock signal 14 is used to sample the PWM signal III, which is then input to the second inverter 360 and the second adder 370 sequentially. After sampling the PWM signal III at the falling edge of clock signal 14, the signal is input to the second adder 370. The accumulation yields a low-level count of 3. The high-level count of 4 and the low-level count of 3 are stored in the third register 340 and the fourth register 380, respectively. The high-level count of 4 and the low-level count of 3 stored in the third register 340 and the fourth register 380 are input to the sixth adder 390 to obtain the total signal count of 7. The total signal count of 7 is then stored in the second total signal count register 400. The high-level count of 4 stored in the third register 340 and the total signal count of 7 stored in the second total signal count register 400 are input to the divider 410 to obtain the dimming code 0.57 of PWM signal II. The dimming code 0.57 of PWM signal III is then stored in the sixth encoding register 420.

[0074] It's understandable that in actual sampling, a large number of rising edges of the clock signal are needed to sample the PWM signal, not just a few. Figure 5 The rising and falling edges of the 14 clock signals shown are used. The specific number of rising edges of the clock signals used varies depending on the frequency of the clock signals and the frequency of the PWM signals.

[0075] Table 1 below shows Figure 2 and Figure 5 The two sampling methods shown are used to obtain data from sampling PWM signal I, PWM signal II, and PWM signal III.

[0076] Table 1:

[0077]

[0078] As shown in Table 1, the duty cycle of PWM signal I is 0.65, the duty cycle of PWM signal II is 0.5, and the duty cycle of PWM signal III is 0.6. Using... Figure 2 The dimming circuit shown samples PWM signal I, PWM signal II, and PWM signal III, and the resulting dimming codes are 0.75, 0.43, and 0.67, respectively, with errors relative to the duty cycle of the PWM signals of 13%, 14%, and 12%, respectively.

[0079] The dimming circuit provided in this embodiment (for example, ...) is used. Figures 3a to 4b The dimming circuit shown samples PWM signal I, PWM signal II, and PWM signal III, and the resulting dimming codes are 0.63, 0.46, and 0.57, respectively, with errors of 3%, 8%, and 5% relative to the duty cycle of the PWM signal.

[0080] It can be seen that, relative to Figure 2 In contrast to the single-edge sampling method, this embodiment employs dual-edge sampling, which significantly reduces the detection error of the dimming circuit and improves dimming accuracy.

[0081] refer to Figure 3b The PWM dimming circuit 20 may also include a frequency switching module. The frequency switching module can provide the required clock signal or reverse clock signal to several electronic components in the PWM signal sampling module and the PWM signal edge detection module as needed, so as to control the PWM signal sampling module and the PWM signal edge detection module to perform sampling operations.

[0082] Specifically, the frequency switching module includes: a period determination module, used to determine the required clock frequency based on the total count of the received signal values, and then input the enable signal of the required clock frequency to the clock selection module. The input terminal of the period determination module is connected to the output terminal of the PWM signal sampling module, and the input terminal of the period determination module is connected to the clock selection module; a clock division module, used to divide the initial clock signal into clock signals with frequencies different from the initial clock signal; and a clock selection module, used to select the clock signal of the required clock frequency from the clock division module, and then provide the clock signal of the required clock frequency to the PWM signal sampling module and the PWM signal edge detection module.

[0083] In the frequency switching module described above, the period judgment module can determine the frequency of the required clock signal and the frequency of the reverse clock signal under the current sampling period based on the total count of the signal values ​​output by the PWM signal sampling module. Then, the clock frequency division module divides the initial input clock signal to obtain clock signals of various frequencies, and the clock selection module selects the clock signal of the determined required frequency. Finally, the selected signal is provided to the PWM signal sampling module and the PWM signal edge detection module, which can reduce the power consumption of the entire circuit system.

[0084] Specifically, the cycle determination module includes n gears, where n is a natural number greater than or equal to 1. Each gear corresponds to a PWM signal of one frequency and a clock signal of one frequency.

[0085] The aforementioned period determination module can determine the frequency of the clock signal corresponding to the current PWM signal based on the total count of the signal values ​​output by the PWM signal sampling module, so that the clock selection module can input the clock signal of the corresponding frequency into the PWM signal sampling module and the PWM signal edge detection module.

[0086] like Figure 5 As shown, the PWM dimming circuit also includes a frequency switching module, which is used to input the required frequency clock signal and reverse clock signal to the PWM sampling circuit.

[0087] In the frequency switching module, SCLK is the original clock signal. The clock divider module divides the original clock signal into clock signals of other frequencies. The count register 390 of the second signal value in the PWM sampling circuit inputs the total count of the signal value into the period judgment module. The period judgment module can be divided into different levels, each corresponding to a clock frequency. The period judgment module can determine the required clock frequency based on the total count of the signal value and then input the signal of the required clock frequency into the clock selection module. The clock selection module then selects the corresponding frequency clock signal from the clock signal input from the clock divider module and inputs it into the PWM sampling circuit. By selecting a suitable clock frequency for sampling the PWM signal through the frequency switching module, the power consumption of the entire circuit system can be reduced.

[0088] Table 2 shows the results of sampling PWM signals with frequencies between 100Hz and 5kHz using the rising and falling edges of the original clock frequency of 1MHz.

[0089] Table 2:

[0090]

[0091] As shown in Table 2, the PWM signal frequency is 100Hz-5kHz, and the original clock frequency is 1MHz. For different PWM signal frequencies, sampling is performed using the rising and falling edges of the 1MHz operating clock. The number of sampled points is 10000, 2000, 1000, 500, and 250 respectively. Different numbers of sampled points represent different resolutions. When the number of sampled points is 10000, 2... 13 Equal to 8192, the dimming resolution can reach 13 bits, and when the number of sampled points is 2000, 2 11 Equal to 2048, the dimming resolution can reach 11 bits, and when the number of sampled points is 1000, 2 10 Equal to 1024, the dimming resolution can reach 10 bits, and when the number of sampling points is 500, 2 9 Equal to 512, the dimming resolution can reach 9 bits, and when the number of sampling points is 250, 2 8 It equals 256, and the dimming resolution can reach 8 bits.

[0092] If the user requires only 8-bit dimming resolution, the number of sampling points can be controlled to 250, and then the corresponding clock frequency can be selected. Table 3 shows the corresponding clock frequencies selected using the frequency switching module.

[0093] Table 3:

[0094]

[0095] As shown in Table 3, if the user requires an 8-bit dimming resolution, then the required number of sampling points is 250. The clock judgment module can calculate the multiple between the current number of sampling points and the required number of sampling points 250 by using the total count of the signal value input into the second signal value count register 390, which is the current number of sampling points. Then, based on the different multiples corresponding to different levels, the required frequency division number is determined. For example, each level in the period judgment module can be set to correspond to a different multiple range, and different levels correspond to different frequency division numbers. Then, the clock selection module selects the corresponding frequency clock for sampling in the clock frequency division module according to the frequency division number, instead of continuously sampling through the original 1MHz clock signal. For cases where the dimming resolution is not high, a relatively low frequency clock can be used for sampling, effectively reducing the power consumption of clock switching and thus maintaining the performance of the chip.

[0096] By using the PWM dimming circuit described above, sampling the PWM signal using both the rising and falling edges of the clock signal, compared to sampling the PWM signal using only the rising edge of the clock signal, can collect more data points, thus significantly improving detection accuracy and correspondingly improving the dimming accuracy of the LED. The required clock frequency is also lower. Furthermore, by selecting an appropriate clock frequency based on the total count of the sampled PWM signal values, unnecessary higher clock frequencies can be avoided, reducing power consumption during clock switching and better maintaining chip performance.

[0097] On the other hand, this application also proposes a PWM dimming chip, wherein the PWM dimming chip includes the PWM dimming circuit disclosed in the embodiments of this application.

[0098] It is understood that in this application, the PWM dimming chip can sample the PWM signal on both edges of the clock signal, namely the rising edge and the falling edge of the clock signal, and output a dimming code, which can be used to dim the LED light-emitting diode.

[0099] In the embodiments of this application, "one or more" refers to one, two, or more; "and / or" describes the relationship between related objects, indicating that three relationships can exist; for example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects have an "or" relationship. Although this application has been illustrated and described with reference to certain preferred embodiments, those skilled in the art should understand that various changes in form and detail can be made without departing from the scope of this application.

Claims

1. A PWM dimming circuit, characterized by comprising: The application relates to a PWM signal sampling module, a PWM signal edge detection module and a dimming code determination module. The PWM signal sampling module is used for collecting signal values of a PWM signal at double edges of a clock signal, wherein the signal values include high level values and low level values. The PWM signal edge detection module is used for detecting a rising edge flag signal and a falling edge flag signal of the PWM signal. The dimming code determination module is connected with the PWM signal sampling module and the PWM signal edge detection module, and is used for determining a ratio between a count number of the high level values in each cycle of the PWM signal and a total count number of the signal values according to the rising edge flag signal and the falling edge flag signal of the PWM signal and the signal values of the PWM signal, and determining a dimming code according to the ratio. The PWM signal sampling module comprises: A first sampling module used for collecting the signal values of the PWM signal at a rising edge of the clock signal. A second sampling module used for collecting the signal values of the PWM signal at a falling edge of the clock signal. The dimming code determination module comprises: A first counting module connected with the first sampling module, the second sampling module and the PWM signal edge detection module, and used for determining the count number of the high level values in each cycle of the PWM signal. A second counting module connected with the first sampling module, the second sampling module and the PWM signal edge detection module, and used for determining the count number of the low level values in each cycle of the PWM signal. An adding module connected with the first counting module and the second counting module, and used for accumulating the count number of the high level values and the count number of the low level values to obtain the total count number of the signal values. A dividing module connected with the first counting module and the adding module, and used for dividing the count number of the high level values by the total count number of the signal values to obtain the ratio between the count number of the high level values and the total count number.

2. The PWM dimming circuit of claim 1, wherein, The first sampling module comprises a first register used for receiving the clock signal and collecting the signal values of the PWM signal at a rising edge of the clock signal. The second sampling module comprises a second register used for receiving an inverse signal of the clock signal and collecting the signal values of the PWM signal at a rising edge of the inverse signal.

3. The PWM dimming circuit of claim 1, wherein, The first counting module comprises: A first adder, wherein a first input end of the first adder is connected with an output end of the first sampling module, a second input end of the first adder is connected with an output end of the second sampling module through a first inverter, and an output end of the first adder is connected with an input end of a third register. The third register has an input end connected with the output end of the first adder and a signal control end used for receiving a clock signal. The second counting module comprises: A second adder, wherein a first input end of the second adder is connected with an output end of the second sampling module, a second input end of the second adder is connected with an output end of the first sampling module through a second inverter, and an output end of the second adder is connected with an input end of a fourth register. The fourth register has an input end connected with the output end of the second adder and a signal control end used for receiving a clock signal.

4. The PWM dimming circuit of claim 3, wherein, The adding module comprises: a third adder, a first input terminal of the third adder being connected with a first output terminal of the third register, and a second input terminal being connected with an output terminal of the fourth register; a fifth register, an input terminal of the fifth register being connected with an output terminal of the third adder, and a control signal terminal being used for receiving the clock signal; and the division module comprises: a divider, a divisor input terminal of the divider being connected with an output terminal of the fifth register, and a dividend input terminal of the divider being connected with a second output terminal of the third register; a sixth register, an input terminal of the sixth register being connected with an output terminal of the divider.

5. The PWM dimming circuit of claim 1, wherein, the PWM signal edge detection module comprises: a first edge detection module, used for detecting a rising edge flag signal of the PWM signal; a second edge detection module, used for detecting a falling edge flag signal of the PWM signal; wherein the first counting module, the addition module and the division module in the dimming code determination module are connected with the first edge detection module respectively, and the second counting module in the dimming code determination module is connected with the second edge detection module.

6. The PWM dimming circuit of claim 5, wherein, the first edge detection module comprises a seventh register, an eighth register, a third inverter, a fourth inverter, a first OR gate, a first AND gate and a second AND gate, wherein, a first input terminal of the seventh register is connected with an output terminal of the first sampling module, a control signal input terminal of the seventh register is used for receiving the clock signal, and an output terminal of the seventh register is connected with an input terminal of the third inverter; a first input terminal of the eighth register is connected with an output terminal of the second sampling module, a control signal input terminal of the eighth register is used for receiving an inverted signal of the clock signal, and an output terminal of the eighth register is connected with an input terminal of the fourth inverter; output terminals of the third inverter and the fourth inverter are connected with two input terminals of the first AND gate respectively; output terminals of the first sampling module and the second sampling module are connected with two input terminals of the first OR gate respectively, an output terminal of the first OR gate and an output terminal of the first AND gate are connected with two input terminals of the second AND gate respectively, and an output terminal of the second AND gate is used for outputting the rising edge flag signal.

7. The PWM dimming circuit of claim 5, wherein, the second edge detection module comprises a ninth register, a tenth register, a fifth inverter, a sixth inverter, a second OR gate, a third AND gate and a fourth AND gate, wherein, a first input terminal of the ninth register is connected with an output terminal of the first sampling module, a control signal input terminal of the ninth register is used for receiving the clock signal, and an output terminal of the ninth register is connected with a first input terminal of the third AND gate; a first input terminal of the tenth register is connected with an output terminal of the second sampling module, a control signal input terminal of the tenth register is used for receiving an inverted signal of the clock signal, and an output terminal of the tenth register is connected with a second input terminal of the third AND gate; An input end of the fifth inverter and an input end of the sixth inverter are connected to an output end of the first sampling module and an output end of the second sampling module respectively, an output end of the fifth inverter is connected to a first input end of the second or gate, an output end of the sixth inverter is connected to a second input end of the second or gate, an output end of the second or gate and an output end of the third and gate are connected to two input ends of the fourth and gate respectively, and an output end of the fourth and gate is used for outputting a falling edge flag signal.

8. The PWM dimming circuit of claim 1, wherein, The PWM dimming circuit further comprises a frequency switching module, which is used for providing clock signals and reverse clock signals of corresponding frequencies to the PWM signal sampling module and the PWM signal edge detection module.

9. The PWM dimming circuit of claim 8, wherein, In the formula, The frequency switching module comprises: a cycle judgment module, which is used for determining a required clock frequency according to a total count of received signal values, and then inputting an enable signal of the required clock frequency into a clock selection module, an input end of the cycle judgment module being connected to an output end of the PWM signal sampling module, and the input end of the cycle judgment module being connected to the clock selection module; a clock frequency division module, which is used for dividing an initial clock signal into clock signals with different frequencies from that of the initial clock signal; and the clock selection module, which is used for selecting a clock signal of the required clock frequency from the clock frequency division module, and then providing the clock signal of the required clock frequency to the PWM signal sampling module and the PWM signal edge detection module.

10. The PWM dimming circuit of claim 9, wherein, The cycle judgment module comprises n gears, n being a natural number greater than or equal to 1, wherein each gear corresponds to a frequency of PWM signal and a frequency of clock signal.

11. A PWM dimming chip, characterized by, It comprises: a main circuit and the PWM dimming circuit as claimed in any one of claims 1 to 10.

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