Method of forming a semiconductor device

Abstract

The application discloses a method for forming a semiconductor device, comprising: forming a sacrificial layer on a substrate; performing a first etching process to remove part of the sacrificial layer and form a plurality of first grooves; forming a first dielectric layer; performing a second etching process to remove the first dielectric layer outside the plurality of first grooves and form a first isolation structure, wherein a gap exists in the first isolation structure; performing a third etching process to etch the plurality of first isolation structures to remove part of the dielectric material at the top of the plurality of first isolation structures and expose the gap; forming a second dielectric layer to cover the plurality of first isolation structures and the sacrificial layer, wherein the second dielectric layer fills at least part of the space of each gap; and performing a fourth etching process to remove the top of the second dielectric layer until the sacrificial layer is exposed to form a second isolation structure. The application can eliminate or effectively reduce the gap in the isolation structure, and has more stable performance.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, in particular to a forming method of semiconductor device. BACKGROUND

[0002] In the process of forming semiconductor structure, it is often necessary to form a medium layer and other structures in a deep groove by deposition process. The inventors have found that when a corresponding structure is formed in the groove, the medium layer is formed along the sidewall and gradually closes in the middle, so that a gap is easily formed in the middle of the formed structure. For example, in the dynamic random access memory (DRAM) semiconductor device shown in FIGS. 1 and 2, the DRAM is a plan view, and FIG. 2 is a cross-sectional view along the direction of line BB'. Figure 1a and Figure 1b The inventors have found that if a gap is formed in the middle of the formed medium layer in the groove used to form the medium layer, a short circuit of the semiconductor structure is easily caused in the subsequent manufacturing process, thereby affecting the performance of the formed semiconductor device. Figure 1a Figure 1b Figure 1a In the process of forming semiconductor structure, it is often necessary to form a medium layer and other structures in a deep groove by deposition process. The inventors have found that when a corresponding structure is formed in the groove, the medium layer is formed along the sidewall and gradually closes in the middle, so that a gap is easily formed in the middle of the formed structure. For example, in the dynamic random access memory (DRAM) semiconductor device shown in FIGS. 1 and 2, the DRAM is a plan view, and FIG. 2 is a cross-sectional view along the direction of line BB'. SUMMARY

[0003] In view of this, the present application provides a forming method of semiconductor device to solve the problem that a gap is easily formed in the middle of the formed structure when a corresponding structure is deposited along the sidewall of the groove, which easily affects the performance of the formed semiconductor device.

[0004] The present application provides a forming method of semiconductor device, comprising:

[0005] providing a substrate;

[0006] forming a sacrificial layer on the substrate;

[0007] performing a first etching process to remove part of the sacrificial layer to form a plurality of first grooves;

[0008] forming a first medium layer covering the sacrificial layer and filling the plurality of first grooves;

[0009] performing a second etching process to remove the first medium layer outside the plurality of first grooves to form a first isolation structure, wherein a gap exists in the first isolation structure;

[0010] performing a third etching process to etch the plurality of first isolation structures to remove part of the medium material at the top of the plurality of first isolation structures to expose the gap;

[0011] forming a second medium layer covering the plurality of first isolation structures and the sacrificial layer, wherein the second medium layer fills at least part of the space of each gap;

[0012] ​​A fourth etching process is performed to remove a top portion of the second dielectric layer until the sacrificial layer is exposed, forming second isolation structures.

[0013] Optionally, the third etching process includes forming a plurality of recesses in the first isolation structures, the plurality of recesses including upper recesses and lower recesses, wherein the lower recesses are formed between the slits and the upper recesses are formed on top of the first isolation structures.

[0014] Optionally, a width of the lower recesses is less than or equal to a width of the upper recesses.

[0015] Optionally, before forming the second dielectric layer, the forming method further includes forming a first oxide layer conformally covering the recesses such that the recesses are between the first oxide layer.

[0016] Optionally, after the fourth etching process, a second oxide layer is formed on a surface of the second isolation structures.

[0017] Optionally, before forming the sacrificial layer, the forming method further includes forming a plurality of buried word lines in the substrate, the plurality of buried word lines including a top mask layer; and forming a buffer layer covering the substrate and the plurality of buried word lines.

[0018] Optionally, the plurality of first recesses formed by the first etching process are lower than the buffer layer.

[0019] Optionally, the plurality of first isolation structures formed by the second etching process have bottoms directly contacting the mask layer on top of the plurality of buried word lines.

[0020] Optionally, the plurality of second isolation structures formed by the fourth etching process have bottoms directly contacting the mask layer on top of the plurality of buried word lines.

[0021] Optionally, the first dielectric layer and the second dielectric layer include the same material.

[0022] Optionally, the first dielectric layer and the second dielectric layer include silicon nitride.

[0023] The forming method of the semiconductor device, by the second etching process, removes the first dielectric layer outside the plurality of first grooves to form the first isolation structure with the gap, then the third etching process is performed to etch the plurality of first isolation structures to remove part of the dielectric material at the top of the plurality of first isolation structures to expose the gap, form the second dielectric layer filling at least part of the space of each gap to eliminate the gap in the first isolation structure or make the gap in the first isolation structure as small as possible, and then the fourth etching process is performed to remove the top of the second dielectric layer until the sacrificial layer is exposed to form the second isolation structure, at this time, the gap in the second isolation structure is eliminated or effectively reduced, and has more stable performance, thereby improving the performance of the obtained semiconductor device. BRIEF DESCRIPTION OF DRAWINGS

[0024] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative effort.

[0025] Figure 1a and Figure 1b A semiconductor structure diagram in the research process of the inventor;

[0026] Figure 2 A flow chart of the forming method of the semiconductor device in an embodiment of the present application;

[0027] Figure 3a , Figure 3b , Figure 3c , Figure 3d , Figure 3e , Figure 3f , Figure 3g , Figure 3h and Figure 3i A structure diagram obtained in each step in an embodiment of the present application;

[0028] Figure 4 A structure diagram obtained in related steps in an embodiment of the present application;

[0029] Figure 5a and Figure 5b A structure diagram obtained in related steps in an embodiment of the present application;

[0030] Figure 6a , Figure 6b and Figure 6c A structure diagram obtained in related steps in an embodiment of the present application. DETAILED DESCRIPTION

[0031] With reference to the drawings, the technical solutions in the embodiments of the present application will be clearly and completely described. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, any other embodiments obtained by a person of ordinary skill in the art without creative effort should fall within the scope of the present application. In the case of no conflict, each of the described embodiments and the technical features thereof can be combined with each other.

[0032] The present application provides, in a first aspect, a method for forming a semiconductor device, referring to FIG. 1, the method comprises steps S110-S180. Figure 2

[0033] S110, referring to FIG. 1, a substrate 110 is provided. Figure 3a

[0034] The substrate 110 can comprise a semiconductor material, for example, the substrate 110 can be a silicon substrate, a silicon germanium substrate, or a silicon-on-insulator substrate, etc. An isolation region 111a and a plurality of active regions 111b defined by the isolation region 111a are formed in the substrate 110, and the active regions 111b can form various functional regions in the substrate 110. Optionally, a plurality of buried word lines 112 can also be formed in the substrate 110, and the plurality of buried word lines 112 can pass through each active region 111b.

[0035] S120, referring to FIG. 2, a sacrificial layer 121 is formed on the substrate 110. This step can use a deposition process to form the sacrificial layer 121 on the surface of the substrate 110. Figure 3b

[0036] S130, referring to FIG. 3, a first etching process is performed to remove part of the sacrificial layer 121 to form a plurality of first recesses 122. Figure 3c

[0037] S140, referring to FIG. 4, a first dielectric layer 123 is formed to cover the sacrificial layer 121 and fill the plurality of first recesses 122. This step can use a deposition process to form the first dielectric layer 123, and the material of the first dielectric layer 123 can comprise a dielectric material such as silicon oxide and / or silicon nitride. Specifically, the first dielectric layer 123 in the first recess 122 needs to be deposited along the sidewall of the first recess 122, and during the deposition process, a gap 125 is easily formed in the middle of the first dielectric layer 123 in the first recess 122. Figure 3d

[0038] S150, referring to FIG. 5, a second etching process is performed to remove the first dielectric layer outside the plurality of first recesses 122 to form a first isolation structure 124, and the first isolation structure 124 has the gap 125. Figure 3e

[0039] ​​​​​​S160, refer to Figure 3f and Figure 3g As shown in FIG. 12, a third etching process is performed to etch the plurality of first isolation structures 124 to remove part of the medium material on the top of the plurality of first isolation structures 124 to expose the gaps 125.

[0040] Specifically, the gaps 125 can include a plurality of recesses. For example, the third etching process can include forming a plurality of recesses in the first isolation structures 124, the plurality of recesses including upper recesses 125a and lower recesses 125b, wherein the lower recesses 125b are formed between the gaps, and the upper recesses 125a are formed on the top of the first isolation structures 124.

[0041] Optionally, the width of the lower recesses 125b is less than or equal to the width of the upper recesses 125a. The lower recesses 125b can include long and narrow slits; the upper recesses 125a can be triangular (as shown in FIG. 13) or semi-elliptical (as shown in FIG. 14). Figure 3f Figure 3g

[0042] S170, refer to Figure 3h As shown in FIG. 15, a second medium layer 126 is formed to cover the plurality of first isolation structures 124 and the sacrificial layer 121, the second medium layer 126 filling at least part of the space of each of the gaps 125 to make the gaps 125 in the first isolation structures 124 as small as possible or eliminate the gaps 125 in the first isolation structures 124. The second medium layer 126 can be formed by a deposition process, and the material of the second medium layer 126 can include silicon oxide and / or silicon nitride.

[0043] Optionally, the first medium layer 123 and the second medium layer 126 include the same material, so that the second isolation structures 127 formed subsequently have the same material, which can simplify the corresponding formation process and also make the second isolation structures 127 including the first isolation structures 124 have more stable performance.

[0044] Optionally, the first medium layer 123 and the second medium layer 126 include silicon nitride.

[0045] S180, refer to Figure 3i As shown in FIG. 16, a fourth etching process is performed to remove the top of the second medium layer 126 until the sacrificial layer 121 is exposed, forming a new isolation structure 127a on the surface of the first isolation structure 124, the new isolation structure 127a and the first isolation structure 124 thereunder constituting the second isolation structure 127 in the first recess 122, the gaps 125 in the second isolation structure 127 being eliminated or effectively reduced, and having more stable performance. ​​

[0046] The forming method of the semiconductor device, by the second etching process, removes the first dielectric layer outside the plurality of first grooves 122 to form the first isolation structure 124 with the gap 125, and then by the third etching process, etches the plurality of first isolation structures 124 to remove part of the dielectric material at the top of the plurality of first isolation structures 124 to expose the gap 125, form the second dielectric layer 126 to fill at least part of the space of each gap 125, so that the gap 125 in the first isolation structure 124 is as small as possible, or the gap 125 in the first isolation structure 124 is eliminated, and then by the fourth etching process, removes the top of the second dielectric layer 126 until the sacrificial layer 121 is exposed to form the second isolation structure 127, at this time, the gap 125 in the second isolation structure 127 is eliminated or effectively reduced, and has more stable performance, so as to improve the performance of the obtained semiconductor device.

[0047] In one embodiment, before forming the second dielectric layer 126, the forming method further comprises: referring to Figure 4 As shown, the first oxide layer 128 is formed to conformally cover the recess 125, so that the recess 125 is located between the first oxide layer 128, and the surface of the first isolation structure 124, i.e. the bottom of the recess 125, is more flat, which can improve the quality of the second dielectric layer 126 formed by subsequent deposition, so that the second dielectric layer 126 can fill as many gaps 125 as possible to eliminate the gap 125, or make the gap 125 as small as possible. Optionally, the first oxide layer 128 can be made of stable oxide materials such as silicon oxide. Optionally, the first oxide layer 128 can be formed by thermal oxidation process.

[0048] Optionally, after the fourth etching process, the forming method further comprises: referring to Figure 5a and Figure 5b As shown, the second oxide layer 129 is formed on the surface of the second isolation structure 127 to further improve the stability of the isolation structure in the first groove 122. Optionally, the second oxide layer 129 can be made of stable oxide materials such as silicon oxide. Optionally, the second oxide layer 129 can be formed by thermal oxidation process.

[0049] Optionally, as shown in Figure 5b The surface of the second oxide layer 129 can be aligned with the surface of the sacrificial layer 121 to simplify the difficulty of subsequent processes and improve the quality of the structure obtained by subsequent processes.

[0050] In one embodiment, before forming the sacrificial layer 121, the forming method further comprises: referring to Figure 6aAs shown, a plurality of buried word lines 112 are formed in the substrate 110, and the plurality of buried word lines 112 include a top mask cover layer 112a; a buffer layer 131 is formed, covering the substrate 110 and the plurality of buried word lines 112.

[0051] In one example, referring to Figure 6b As shown, the plurality of first grooves 122 formed by the first etching process are lower than the buffer layer 131, so that the first grooves 122 can expose the mask cover layer 112a on the top of the buried word lines 112, and thus the structures subsequently formed in the first grooves 122 can directly contact the mask cover layer 112a on the top of the buried word lines 112.

[0052] In one example, referring to Figure 6c As shown, the plurality of first isolation structures 124 formed by the second etching process have bottoms directly contacting the mask cover layer 112a on the top of the plurality of buried word lines 112.

[0053] In one example, the plurality of second isolation structures 127 formed by the fourth etching process have bottoms directly contacting the mask cover layer 112a on the top of the plurality of buried word lines 112.

[0054] In one example, the sacrificial layer 121 can also be removed to form second grooves between the respective second isolation structures 127, and a contact structure is formed in the second grooves to electrically lead out the corresponding active region 111b.

[0055] The above method for forming a semiconductor device includes, by the second etching process, removing the first dielectric layer outside the plurality of first grooves 122 to form the first isolation structure 124 with the gap 125, then by the third etching process, etching the plurality of first isolation structures 124 to remove part of the dielectric material on the top of the plurality of first isolation structures 124 to expose the gap 125, forming the second dielectric layer 126 to fill at least part of the space of the respective gap 125 to eliminate the gap 125 in the first isolation structure 124 or make the gap 125 in the first isolation structure 124 as small as possible, and then by the fourth etching process, removing the top of the second dielectric layer 126 until the sacrificial layer 121 is exposed to form the second isolation structure 127, at this time, the gap 125 in the second isolation structure 127 is eliminated or effectively reduced, and has more stable performance, so as to improve the performance of the obtained semiconductor device.

[0056] The present application provides, in a second aspect, a semiconductor device which can be formed by the above method for forming a semiconductor device. Referring to Figure 3i As shown, the semiconductor device can include:

[0057] a substrate 110;

[0058] An isolation structure on the substrate surface, the isolation structure comprising a second isolation structure 127, the gap in the second isolation structure 127 being eliminated or reduced.

[0059] Optionally, if a plurality of buried word lines 112 are formed in the substrate 110, the second isolation structure 127 is located above the buried word lines 112, and the bottom of the second isolation structure 127 directly contacts the mask cover layer 112a on the top of the buried word lines 112.

[0060] The semiconductor device can be formed by using the forming method of the semiconductor device according to any one of the above embodiments, and has all the beneficial effects of the forming method of the semiconductor device according to any one of the above embodiments, which will not be repeated here.

[0061] Although the present application has been shown and described with respect to one or more implementations, equivalent alterations and modifications will occur to others skilled in the art based on the foregoing description and accompanying drawings. The present application includes all such modifications and alterations and is limited only by the scope of the following claims. In particular, with respect to the various functions performed by the above described components (assemblies), terms such as "means for" are intended to correspond to any component (or components) which serve to perform the specified function (e.g., that is functionally equivalent), such that in the claims the components are described by the name of their function (instead of by their specific structure), which is then associated with the specific structure (or structures) known from the prior art or of which the claimant is otherwise knowledgeable.

[0062] That is, the above-described embodiments are merely exemplary implementations of the present application, and thus are not intended to limit the scope of the present application, and any equivalent structure or equivalent flow changes made by using the contents of the specification and drawings of the present application, such as the mutual combination of technical features between the embodiments, or direct or indirect application to other related technical fields, are also included in the scope of patent protection of the present application.

[0063] In addition, in the description of the present application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer" and the like indicate the orientation or positional relationship shown in the drawings based on the orientation or positional relationship shown in the drawings, and are only for the purpose of facilitating the description of the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as limiting the present application. In addition, for structural elements with the same or similar properties, the present application can use the same or different reference numerals to identify them. In addition, the terms "first", "second" are only for the purpose of description, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features limited by "first", "second" can explicitly or implicitly include one or more features. In the description of the present application, the meaning of "a plurality of" is two or more, unless otherwise expressly specified.

[0064] In the present application, the word "exemplary" is used to mean "serving as an example, instance, or illustration." Any implementation described as "exemplary" in the present application is not necessarily to be construed as preferred or advantageous over other implementations. The present application is given in the above description to enable any person skilled in the art to practice the present application. In the above description, various details are set forth for the purpose of explanation. It should be appreciated that one of ordinary skill in the art can realize the application without using these specific details. In other implementations, well-known structures and processes are not described in detail to avoid obscuring the description of the present application. Therefore, the present application is not intended to be limited to the embodiments shown, but is to be consistent with the widest scope consistent with the principles and features disclosed.

Claims

1. A method of forming a semiconductor device, characterized by, The forming method comprises: providing a substrate; forming a sacrificial layer on the substrate; performing a first etching process to remove part of the sacrificial layer to form a plurality of first grooves; forming a first dielectric layer covering the sacrificial layer and filling the plurality of first grooves; performing a second etching process to remove the first dielectric layer outside the plurality of first grooves to form a plurality of first isolation structures, wherein gaps exist between the plurality of first isolation structures; performing a third etching process to etch the plurality of first isolation structures to remove part of the dielectric material at the top of the plurality of first isolation structures to expose the gaps; the third etching process comprises: forming a plurality of recesses in the plurality of first isolation structures, the plurality of recesses comprising upper recesses and lower recesses, wherein the lower recesses are formed between the gaps, and the upper recesses are formed at the top of the plurality of first isolation structures; forming a second dielectric layer covering the plurality of first isolation structures and the sacrificial layer, the second dielectric layer filling at least part of the space of each gap; performing a fourth etching process to remove the top of the second dielectric layer until the sacrificial layer is exposed to form a plurality of second isolation structures; Before forming the second dielectric layer, the forming method further comprises: forming a first oxide layer conformally covering the recesses so that the recesses are located between the first oxide layer.

2. The method of forming a semiconductor device according to claim 1, wherein The width of the lower recesses is less than or equal to the width of the upper recesses.

3. The method of forming a semiconductor device according to claim 1, wherein The fourth etching process further comprises: forming a second oxide layer on the surface of the second isolation structure.

4. The method of forming a semiconductor device according to Claim 1, wherein Before forming the sacrificial layer, the forming method further comprises: forming a plurality of buried word lines in the substrate, the plurality of buried word lines comprising a top mask cover layer; forming a buffer layer covering the substrate and the plurality of buried word lines.

5. The method of forming a semiconductor device according to claim 4, wherein Further comprising: the plurality of first grooves formed by the first etching process have bottoms lower than the buffer layer.

6. The method of forming a semiconductor device according to claim 4, wherein Further comprising: the plurality of first isolation structures formed by the second etching process have bottoms directly contacting the mask cover layer at the top of the plurality of buried word lines; the plurality of second isolation structures formed by the fourth etching process have bottoms directly contacting the mask cover layer at the top of the plurality of buried word lines.

7. The method of forming a semiconductor device according to Claim 1, wherein Further comprising: the first dielectric layer and the second dielectric layer comprise the same material.

8. The method of forming a semiconductor device according to claim 7, wherein Further comprising: the first dielectric layer and the second dielectric layer comprise silicon nitride.

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