Contact structures for three-dimensional memory devices and methods of forming the same

Abstract

The present disclosure describes a three-dimensional (3D) memory device including a first memory array and a second memory array disposed on a semiconductor layer. The 3D memory device can also include a staircase structure disposed between the first memory array and the second memory array. The staircase structure includes a first staircase region and a second staircase region. The first staircase region includes a first staircase structure including a first plurality of steps descending in a first direction. The second staircase region includes a second staircase structure including a second plurality of steps descending in a second direction. The 3D memory device can also include a contact region disposed between the first staircase region and the second staircase region. The contact region includes a plurality of contacts extending through an insulating layer and into the semiconductor layer.

Description

[0001] This application is a divisional application of Chinese invention patent application filed on September 15, 2021, entitled "Contact Structure of Three-Dimensional Memory Device and Method for Forming Thereof", with application number 202180004557.0.

[0002] Cross-references to related applications

[0003] This application claims priority to Chinese Patent Application No. 2021101961129, filed on February 22, 2021, the entire contents of which are incorporated herein by reference. Technical Field

[0004] This disclosure generally relates to the field of semiconductor technology, and more specifically, to a method for forming a three-dimensional (3D) memory device. Background Technology

[0005] Planar memory cells can be miniaturized to smaller sizes through improvements in process technology, circuit design, programming algorithms, and manufacturing processes. However, as the feature size of memory cells approaches its lower limit, planar processes and manufacturing technologies become challenging and costly. Consequently, the storage density of planar memory cells is nearing its upper limit. Three-dimensional (3D) memory architectures can address the density limitations of planar memory cells. Summary of the Invention

[0006] This disclosure describes embodiments of a three-dimensional (3D) capacitor structure for a memory device and a method for forming the same.

[0007] In some embodiments, a three-dimensional (3D) memory device may include a first memory array and a second memory array disposed on a semiconductor layer. The 3D memory device may also include a stepped structure disposed between the first memory array and the second memory array. The stepped structure may include a first stepped region and a second stepped region. The first stepped region may include a first stepped structure comprising a first plurality of steps descending in a first direction. The second stepped region may include a second stepped structure comprising a second plurality of steps descending in a second direction. The 3D memory device may also include a contact region disposed between the first stepped region and the second stepped region. The contact region may include a plurality of contacts extending through an insulating layer and into the semiconductor layer.

[0008] In some embodiments, a three-dimensional (3D) memory device may include first and second semiconductor structures. The first semiconductor structure may include a first memory array and a second memory array disposed on a semiconductor layer. The 3D memory device may also include a stepped structure disposed between the first memory array and the second memory array and including a first stepped structure and a second stepped structure. The first stepped structure may include a first plurality of steps descending in a first direction. The second stepped structure may include a second plurality of steps descending in a second direction. The 3D memory device may also include a contact region contacting the first stepped structure and the second stepped structure. The contact region may include a plurality of contacts extending through an insulating layer and into the semiconductor layer. The 3D memory device may also include a first bonding layer on the plurality of contacts. The second semiconductor structure may include peripheral circuitry and a second bonding layer above the peripheral circuitry. The second bonding layer is in contact with the first bonding layer.

[0009] In some embodiments, a method for forming a three-dimensional (3D) memory device may include disposing an alternating layer stack on a semiconductor layer, wherein the alternating layer stack may include contact regions contacting a first step region and a second step region. The method may further include performing a plurality of etch processes on the alternating layer stack in the first and second step regions, wherein each of the plurality of etch processes etches a portion of the alternating layer stack in the contact region. The method may further include disposing an isolation dielectric layer in the contact region and on the first and second step structures. The method may further include forming a plurality of openings in the isolation dielectric layer disposed in the contact region, and disposing a conductive material in the plurality of openings to form a plurality of contacts in the TSC region.

[0010] In some embodiments, a 3D memory device may include a memory chip and peripheral chips. The memory chip may include a first substrate and an alternating layer stack formed on the first substrate. The memory chip may also include a first memory array structure and a second memory array structure, a stepped structure, and a connector for electrically coupling the stepped structure to the first or second memory array structure. The memory chip may also include a through-silicon contact (TSC) formed between the first memory array and the second memory array. The memory chip may also include an interconnect layer formed over the alternating layer stack and a first bonding layer formed over the interconnect layer. Peripheral chips may be formed on the memory chip and bonded to the first bonding layer. The peripheral chips may be electrically coupled to the first substrate via the first bonding layer, the interconnect layer, and the TSC.

[0011] In some embodiments, the stepped structure may include first and second stepped regions formed along a first direction. A step formed in the first stepped region is electrically coupled to the first memory array. A step formed in the second stepped region is electrically coupled to the second memory array.

[0012] In some embodiments, the 3D memory device may further include a connector extending along a first direction. The connector extends along the first direction and electrically connects the first and second memory arrays. In some embodiments, the connector may be formed in a connector region extending in the same direction as the stepped region. At least one step of the stepped structure may be electrically connected to the first and second memory arrays via the connector.

[0013] In some embodiments, the first step structure in the first step region is formed at a different height than the second step structure in the second step region.

[0014] In some embodiments, the TSC is formed between the first stepped region and the second stepped region.

[0015] In some embodiments, the TSC is formed in the TSC region extending along the first and second step regions.

[0016] In some embodiments, the stepped structure includes at least one pair of steps facing each other in a first direction, and each step in the pair of steps may include the same number of steps.

[0017] In some embodiments, the peripheral chip may include a second bonding layer configured to be bonded to the first bonding layer. The peripheral chip may also include peripheral circuitry formed to contact the second bonding layer and electrically connected to the first bonding layer via the second bonding layer. The peripheral chip may further include a second substrate in contact with the peripheral circuitry.

[0018] In some embodiments, a method for forming a 3D memory device may include forming a memory chip and a peripheral chip. Forming the memory chip may include forming an alternating layer stack on a first substrate and forming first and second memory arrays along a first direction. The method may further include forming a stepped region and a TSC region between the first and second memory arrays. The method may further include forming a stepped structure in the stepped region and removing a portion of the alternating layer stack within the TSC region to expose the underlying first substrate. The method may further include forming a TSC in the TSC region and forming an interconnect layer on the TSC, the interconnect layer being electrically coupled to the first substrate. The method may further include forming a first bonding layer on the interconnect layer and bonding the first and second bonding layers using a suitable bonding technique.

[0019] In some embodiments, the method for forming a TSC may include disposing an insulating dielectric material in the TSC region, forming an opening in the TSC region, and disposing a conductive material in the opening.

[0020] In some embodiments, a method for forming a 3D memory device may include forming a connector region between a first memory array and a second memory array, and forming a connector in the connector region. The connector is formed to be electrically connected to first and second step structures in the first and second step regions, respectively.

[0021] In some embodiments, the method for exposing the underlying first substrate may further include forming a plurality of steps of different heights in the first and second step regions. In some embodiments, each etching step for forming the plurality of steps may also etch a portion of the alternating layer stack in the TSC region.

[0022] In some embodiments, the method for forming a plurality of steps may include determining the height of each of the plurality of steps. Each height of a step is equal to the height of a single step multiplied by a multiplication factor. In some embodiments, the multiplication factor is an integer value. In some embodiments, the etching depth for forming the plurality of steps is equal to the height of a single step multiplied by an odd number. In some embodiments, the etching process may include simultaneously etching alternating layer stacks in two or more step regions, and the etching depth of each etching process is equal to the height of a single step multiplied by an even number.

[0023] In some embodiments, a method for forming a stepped structure includes providing a mask layer including openings extending in first and second directions. The method may further include performing an etching process using the mask layer to form at least one step in the stepped region. The mask layer may also include openings in the TSC region, and the etching process may further etch portions of the alternating layer stack in the TSC region. The method may further include trimming the mask layer and etching the alternating layer stack after trimming. The method may further include repeating the trimming and etching processes to form steps of different heights, and removing the alternating layer stack in the TSC region while forming the steps.

[0024] In some embodiments, the stepped region includes a first stepped region and a second stepped region, and the TSC region is formed between the first stepped region and the second stepped region.

[0025] In some embodiments, the TSC region is in contact with and parallel to the first step region and the second step region.

[0026] In some embodiments, the method for forming a 3D memory device may further include forming peripheral circuitry on a second substrate and forming a second bonding layer on the peripheral circuitry. The method may also include bonding the first and second bonding layers using a suitable wafer bonding technique. Attached Figure Description

[0027] The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate embodiments of the present disclosure and, together with the specification, further serve to explain the principles of the present disclosure and enable those skilled in the art to construct and use the present disclosure.

[0028] Figure 1A A schematic top view of an exemplary three-dimensional (3D) memory chip according to some embodiments of the present disclosure is shown.

[0029] Figure 1B A schematic top view of a region of a 3D memory chip according to some embodiments of the present disclosure is shown.

[0030] Figure 1C A perspective view of a portion of an exemplary 3D memory array structure according to some embodiments of the present disclosure is shown.

[0031] Figure 1D A cross-sectional view of an exemplary 3D memory array structure according to some embodiments of the present disclosure is shown.

[0032] Figure 2 and Figure 3 A schematic top view of a region of a 3D memory chip according to some embodiments of the present disclosure is shown.

[0033] Figure 4 and Figure 5 Schematic perspective and top views of memory regions of a 3D memory device according to some embodiments of the present disclosure are shown respectively.

[0034] Figure 6 and Figure 7 Schematic perspective and top views of memory regions of a 3D memory device according to some embodiments of the present disclosure are shown respectively.

[0035] Figure 8 A flowchart illustrating the formation of contact structures in a 3D memory device according to some embodiments of the present disclosure is shown.

[0036] Figure 9-23 Mask patterns and corresponding cross-sectional views of various mask layers of a 3D memory device at various process stages are shown according to some embodiments of the present disclosure.

[0037] The features and advantages of the invention will become more apparent when viewed in conjunction with the accompanying drawings, in which similar reference numerals consistently identify corresponding elements. In the drawings, similar reference numerals generally denote identical, functionally similar, and / or structurally similar elements. The first appearance of an element in the drawing is indicated by the leftmost numeral(s) of the corresponding reference numeral.

[0038] Embodiments of this disclosure will be described with reference to the accompanying drawings. Detailed Implementation

[0039] Although specific configurations and arrangements have been discussed, it should be understood that this is for illustrative purposes only. Those skilled in the art will recognize that other configurations and arrangements can be used without departing from the spirit and scope of this disclosure. It will be apparent to those skilled in the art that this disclosure can also be used in a variety of other applications.

[0040] It should be noted that references to "an embodiment," "an embodiment," "an exemplary embodiment," "some embodiments," etc., in the specification indicate that the described embodiments may include specific features, structures, or characteristics, but each embodiment may not necessarily include that specific feature, structure, or characteristic. Furthermore, such phrases do not necessarily refer to the same embodiment. In addition, when a specific feature, structure, or characteristic is described in connection with an embodiment, whether explicitly described or not, implementing such a feature, structure, or characteristic in conjunction with other embodiments is within the knowledge of those skilled in the art.

[0041] Generally, terms can be understood at least partly from their usage in context. For example, the term "one or more," as used herein, depends at least partly on the context and can be used to describe any feature, structure, or characteristic in a singular sense, or to describe a combination of features, structures, or characteristics in a plural sense. Similarly, terms such as "a," "an," or "the" can also be understood, at least partly on the context, to express either a singular or plural usage. Furthermore, the term "based on" can be understood to not necessarily convey an exclusive set of factors, but rather to allow for the presence of other factors that are not necessarily explicitly described, which also depends at least partly on the context.

[0042] It should be readily understood that the terms "on," "above," and "over" in this disclosure should be interpreted in the broadest possible sense, such that "on" means not only "directly on" something, but also includes "on" something with an intermediate feature or layer in between. Furthermore, "above" or "over" means not only "on" something, but also "above" or "over" something without an intermediate feature or layer in between (i.e., directly on).

[0043] Furthermore, for ease of description, spatially relative terms such as “below,” “under,” “down,” “above,” and “above” may be used herein to describe the relationship between one element or feature as shown in the figures and another element(s) or feature(s). In addition to the orientations shown in the figures, the spatially relative terms are intended to cover different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations) and the spatially relative descriptive terms used herein may be interpreted accordingly.

[0044] As used herein, the term "substrate" refers to the material on which subsequent material layers are added. A substrate includes a "top" surface and a "bottom" surface. The top surface of the substrate is typically where semiconductor devices are formed; therefore, unless otherwise stated, semiconductor devices are formed on the top side of the substrate. The bottom surface is opposite to the top surface, so the bottom side of the substrate is opposite to the top side. The substrate itself may be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. Furthermore, the substrate may include a variety of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of a non-conductive material, such as glass, plastic, or sapphire wafers.

[0045] As used herein, the term "layer" refers to a portion of material comprising a region of thickness. A layer has a top side and a bottom side, wherein the bottom side of the layer is relatively close to the substrate, while the top side is relatively far from the substrate. A layer may extend over the entire lower or upper layer structure, or may have a range smaller than that of the lower or upper layer structure. Furthermore, a layer may be a region of a uniform or non-uniform continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any set of horizontal planes at the top and bottom surfaces. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, which may include one or more layers, and / or may have one or more layers on, above, and / or below it. A layer may include multiple layers. For example, an interconnect layer may include one or more conductive and contact layers (where contacts, interconnects, and / or vertical interconnect accesses (VIAs) are formed) and one or more dielectric layers.

[0046] In this disclosure, for ease of description, the term "tier" is used to refer to elements having substantially the same height along the vertical direction. For example, a word line and the underlying gate dielectric layer may be referred to as "a tier," a word line and the underlying insulating layer may be referred to together as "a tier," word lines having substantially the same height may be referred to as "a tier word line" or similar, and so on.

[0047] As used herein, the term "nominal / nominally" refers to the expected or target value of a characteristic or parameter of a component or process step set during the design phase of a product or process, and the range of values ​​higher and / or lower than the expected value. The range of values ​​may be due to slight variations in manufacturing processes or tolerances. As used herein, the term "about" indicates a value of a given quantity that can vary based on a specific technology node associated with the subject semiconductor device. Based on a specific technology node, the term "about" can indicate a value of a given quantity that varies, for example, within 10-30% of that value (e.g., ±10%, ±20%, or ±30% of the value).

[0048] In this disclosure, the terms “horizontal / horizontally / laterally” refer to a lateral surface that is nominally parallel to the substrate, and the terms “vertical” or “perpendicularly” refer to a lateral surface that is nominally perpendicular to the substrate.

[0049] As used herein, the term “3D memory” refers to a three-dimensional (3D) semiconductor device having vertically oriented strings of memory cell transistors (referred to herein as “memory strings”, such as NAND strings) on a laterally oriented substrate, such that the memory strings extend in the vertical direction relative to the substrate.

[0050] As the development of 3D memories (e.g., 3D NAND flash memory) moves towards high-density and high-capacity memory cells, the number of stepped layers in 3D memory devices continues to increase. Through-silicon contact (TSC) structures extend through the stepped layers and connect to structures in the underlying substrate. With more and more stepped layers stacked on top of each other, high-quality contact structures become increasingly critical for providing reliable electrical connections between memory control circuitry and peripheral devices.

[0051] Various embodiments of this disclosure provide structures and methods for manufacturing contact structures in various regions of a 3D memory structure. For example, through-silicon contacts (TSCs) can be formed in regions extending parallel to a stepped structure or in regions between two opposing sub-stepped structures. A sub-stepped structure can refer to a portion of a stepped structure comprising a specific number of layers and extending in a lateral direction. Adjacent sub-stepped structures can comprise a similar number of layers and extend in opposite lateral directions. To improve device density and real estate efficiency, TSCs can be formed in the stepped regions. Specifically, one or more operations for forming a TSC in a stepped region can be performed simultaneously with the formation process of the stepped structure. For example, the TSC region can be within the stepped region, and the formation of the TSC region includes, for example, removing portions of alternating dielectric layer stacks, providing an isolation dielectric layer in place of the removed portions of the alternating stepped structure, forming an opening through the isolation dielectric layer, and providing a conductive material in the opening. In some embodiments, the stepped structure can be formed during a multi-step trimming etching process, referred to as a "multi-chopping" process. Each step of the trimming etching process removes portions of the alternating dielectric layer stacks within the TSC region, allowing the alternating dielectric layer stacks within the TSC region to be removed once the multi-truncation process is complete. The contact structures and methods for forming the contact structures described in this disclosure offer various benefits, including but not limited to increased device density and reduced manufacturing costs.

[0052] Figure 1A A top view of an exemplary 3D memory device 100 according to some embodiments of this disclosure is shown. The 3D memory device 100 may be a memory chip (package), a memory chip, or any part of a memory chip, and may include one or more memory surfaces 101, each of which may include a plurality of memory blocks 103. The same and concurrent operations may occur at each memory surface 101. The size of a memory block 103 may be megabytes (MB), which may be the minimum size required to perform an erase operation. Figure 1AAs shown, the exemplary 3D memory device 100 includes four memory surfaces 101, and each memory surface 101 includes six memory blocks 103. Each memory block 103 may include a plurality of memory cells, wherein each memory cell can be addressed by interconnections such as bit lines and word lines. The bit lines and word lines may be arranged vertically (e.g., in rows and columns, respectively) to form an array of metal lines. The orientation of the bit lines and word lines is... Figure 1A and Figure 1B The blocks are labeled "BL" and "WL". Storage block 103 may include a memory array, which is the core area of ​​the memory device and performs storage functions.

[0053] The 3D memory device 100 also includes a peripheral region 105, which is the region surrounding the memory surface 101. The peripheral region 105 may include a variety of digital, analog, and / or mixed-signal circuitry to support the functionality of the memory array, such as page buffers, row and column decoders, and sense amplifiers. The peripheral circuitry uses active and / or passive semiconductor devices, such as transistors, diodes, capacitors, resistors, etc., as will be apparent to those skilled in the art.

[0054] Figure 1A The arrangement of the peripheral region 105 and storage surface 101 in the 3D memory device 100 shown, as well as the arrangement of the storage blocks 103 in each storage surface 101, is provided as an example only and does not limit the scope of this disclosure. For example, the peripheral region 105 may be formed below or above the storage surface 101.

[0055] refer to Figure 1B This illustrates some embodiments according to the present disclosure. Figure 1AAn enlarged top view of region 108 in the 3D memory device 100. Region 108 may include a stepped region 210 and a core array region 211. The core array region 211 may include an array of channel structures 212, each channel structure including a plurality of memory cells. The stepped region 210 may include stepped structures and an array of contact structures 214 formed on the stepped structures. In some embodiments, a plurality of slot structures 216 extending in the WL direction across the core array region 211 and the stepped region 210 may divide the memory block into a plurality of memory fingers 218. In some embodiments, the slot structures 216 may also be used to divide between different memory fingers. At least some of the slot structures 216 may serve as common source contacts for the array of channel structures 212 in the core array region 211. A top select gate notch 220 may be disposed in the middle of each memory finger 218 to divide the top select gate (TSG) of the memory finger 218 into two portions, thereby dividing the memory string in the memory finger into two regions. While erase operations on the 3D NAND memory can be performed at the block level, read and write operations can be performed at the page level. Bit lines may be electrically connected to a memory string in one page and another memory string in another page, allowing data operations to be performed in memory cells of one page at a time. In some embodiments, region 108 also includes dummy channel structures for process variation control during manufacturing and / or for additional mechanical support.

[0056] Figure 1C A perspective view of a portion of an exemplary 3D structure 120 according to some embodiments of the present disclosure is shown. Structure 120 includes a substrate 330, an insulating layer 331 above the substrate 330, a bottom select gate (BSG) 332 above the insulating layer 331, and a multilayer control gate 333 (also referred to as a “word line (WL)”) stacked on top of the LSG 332 to form an alternating conductive and dielectric layer stack 335. For clarity, in Figure 1C The dielectric layer adjacent to each control gate is not shown. The exemplary 3D structure 120 is provided by way of example only and does not limit the scope of this disclosure. The memory structure described in this disclosure can be implemented in any suitable memory array structure.

[0057] The control gate of each layer is separated by slot structures 216-1 and 216-2 through the film stack 335. In some embodiments, slot structures 216-1 and 216-2 may be discontinuous between the stepped region 210 and the core array region 211. Structure 120 may include a top selected gate (TSG) 334 located above the stack of control gates 333. The stack of TSG 334, control gates 333, and LSG 332 is also referred to as a “gate electrode”. Structure 120 also includes channel structures 212 and doped source electrode regions 344 in portions of the substrate 330 between adjacent LSGs 332. Each channel structure 212 includes a channel via 336 extending through the film stack 335 of insulating layer 331 and alternating conductive and dielectric layers. The channel structure 212 may further include a storage film 337 on the sidewall of the channel via 336, a channel layer 338 above the storage film 337, and a core-filling film 339 surrounded by the channel layer 338. Storage cells 340 may be formed at the intersection of the control gate 333 and the storage string 212. Structure 120 also includes multiple bit lines (BLs) 341 connected to the channel structure 212 above the TSG 334. Structure 120 also includes multiple metal interconnects 343 connected to the gate electrode via multiple contact structures 214. The edges of the film stack 335 are configured in a stepped shape to allow electrical connections to each layer of the gate electrode.

[0058] exist Figure 1C In this illustration, for illustrative purposes, three layers of control gates 333-1, 333-2, and 333-3 are shown together with a TSG 334 and an LSG 332. In this example, each memory string 212 may include three memory cells 340-1, 340-2, and 340-3 corresponding to control gates 333-1, 333-2, and 333-3, respectively. In some embodiments, the number of control gates and the number of memory cells may be greater than three to increase storage capacity. Structure 120 may also include other structures, such as TSG notches, common source contacts, and dummy channel structures. For simplicity, these structures are not shown. Figure 1C As shown in the image.

[0059] To achieve higher storage density, the number of vertical wave arrays (WLs) in 3D memory, or the number of memory cells per string, has been significantly increased; for example, WLs can exceed 60 or 90 layers or more. Further increasing the number of vertical WLs presents challenges in forming the channel structure extending through them. For example, channel openings with high aspect ratios (e.g., height-to-width ratio) can lead to over-etching of the upper portion of the opening and under-etching of the lower portion. Uneven etching can cause adjacent memory cells (e.g.,…) to… Figure 1C Crosstalk or unwanted coupling between the storage cells 340-1, 340-2 and 340-3 shown.

[0060] Figure 1D An exemplary 3D memory structure according to some embodiments is shown. Figure 1D The memory structure 140 shown includes a first semiconductor structure such as a memory chip 10 and a second semiconductor structure such as a peripheral chip 20. Other suitable structures may be used as the first and second semiconductor structures. In some embodiments, the peripheral chip 20 is formed above and electrically coupled to the memory chip 10.

[0061] The memory chip 10 includes at least a first substrate 102, a layer stack 200, a through-silicon contact (TSC) 300, an interconnect layer 400, and a first bonding layer 500.

[0062] The first substrate 102 may include silicon (e.g., single-crystal silicon), silicon-germanium (SiGe), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), gallium arsenide (GaAs), gallium nitride, silicon carbide, indium phosphide, gallium arsenide, glass, III-V compounds, any other suitable material, or any combination thereof. In some embodiments, the first substrate 102 may be double-sided polished prior to device fabrication. In some embodiments, the first substrate 102 may have a pattern on its back surface, such as... Figure 1D As shown in the image. Figure 1D The first substrate 102 shown is merely an example and does not limit the scope of this disclosure. For example, the first substrate 102 may be a dielectric layer or any suitable material or structure. In some embodiments, the first substrate 102 may include polycrystalline silicon.

[0063] The layer stack 200 includes alternately formed control gates 201 and dielectric layers 202. For example, the layer stack 200 may include pairs of control gates 201 and dielectric layers 202 alternately disposed on a substrate 102. Each pair of control gates 201 and dielectric layers 202 may be considered as a level (e.g., a step) of the 3D memory structure 140. In some embodiments, the layer stack 200 may include any suitable number of levels, such as 60 levels, 90 levels, or more. The layer stack 200 may be formed by alternately disposing two dielectric layers and replacing one of the two dielectric layers with a conductive layer. The control gates 201 and dielectric layers 202 may be disposed using one or more thin-film deposition processes, including but not limited to chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD), plasma-enhanced ALD (PEALD), or any combination thereof. In some embodiments, the control gate 201 further includes at least one of a top-select gate structure and a bottom-select gate structure.

[0064] Along the word line direction (e.g., the x-direction), the layer stack 200 can be divided into various regions, such as a first memory array 11 and a second memory array 12 containing a channel structure. A step structure can be formed between the first memory array 11 and the second memory array 12. The step structure can be electrically coupled to one or more memory arrays. For example, the layer stack 200 also includes a first step region 13 and a second step region 14, respectively coupled to the first memory array 11 and the second memory array 12. A contact region 15 is formed between the first step region 13 and the second step region 14. In some embodiments, the first step region 13 and the second step region 14 surround the contact region 15; in some embodiments, the contact region can be formed within the step region.

[0065] An insulating layer 230 is disposed on the stack 200. For example, the insulating layer 230 may be disposed on the stepped structure in the first stepped region 13 and the second stepped region 14. In some embodiments, the insulating layer 230 may also be disposed in the contact region 15. In some embodiments, the insulating layer 230 may be formed using any suitable insulating material. For example, the insulating layer 230 may be formed using silicon oxide, silicon nitride, silicon oxynitride, any suitable dielectric material, and / or combinations thereof.

[0066] The stack 200 may also include various channel structures. For example, the stack 200 may include channel structure 203 and dummy channel structure 206.

[0067] Channel structures 203 are formed in the first memory array 11 and the second memory array 12. Each channel structure 203 extends through alternating layers of control gate 201 and dielectric layer 202. According to some embodiments, the channel structure 203 may include a tunneling layer, a storage layer, and a barrier layer arranged along a direction from the center of each channel structure 203 toward the layer stack 200. The portion of the channel structure 203 that contacts the top or bottom selective structure may include the barrier layer and the storage layer.

[0068] A dummy channel structure 206 can also be formed through the stacked layers 200. In some embodiments, the structure and composition of the dummy channel structure 206 may be similar to that of the channel structure 203, except that the top portion of the dummy channel structure 206 may not include contact structures for connecting to conductive lines. In some embodiments, the dummy channel structure may be filled with an insulating material.

[0069] Contact region 15 may include TSC 300. In some embodiments, TSC 300 may extend through substrate 102 and contact contact pads such as contact pads 302. TSC 300 may be configured to be electrically coupled to an external electrical connection via contact pads 302. Figure 1D(Not shown in the image). The TSC 300 can be used to transmit signals to external circuitry or devices embedded in the substrate 102. In some embodiments, each TSC 300 may include a conductive structure extending in the vertical direction (e.g., the z-direction) and surrounded by an insulating layer.

[0070] Contact structures 204 may be formed on the layer stack 200. Each contact structure 204 may extend through the insulating layer 230 and the dielectric layer 202, such that the bottom surface of the contact structure contacts and is electrically coupled to the control gate 201. The top surface of the contact structure 204 may be connected to the contact structure of the interconnect layer 400.

[0071] Interconnect layer 400 is formed over layer stack 200 and connects to channel structure 203, contact structure 204, TSC 300, and any other suitable structure of memory structure 140. Interconnect layer 400 may include laterally extending conductors and vias for connecting conductors on different layers. In some embodiments, interconnect layer 400 may contact first bonding layer 500.

[0072] For 3D memory structures with a high number of layers, such as those with 60, 90, or more stacked WL layers, forming stepped regions and TSCs between memory arrays can offer various benefits. For example, compared to structures with TSCs formed between memory regions, the horizontal length of interconnects can be reduced, which in turn reduces resistance and increases device density.

[0073] The peripheral chip 20 includes at least a second bonding layer 700, peripheral circuitry 800, and a second substrate 900. The peripheral chip 20 may include any other suitable structure, which is not shown for simplicity. Figure 1D As shown in the image.

[0074] The second bonding layer 700 can be formed using a material similar to that of the first bonding layer 500. For example, the first bonding layer 500 and the second bonding layer 700 can be formed using dielectric materials such as silicon oxide, silicon nitride, silicon oxynitride, any suitable dielectric material and / or combinations thereof. In some embodiments, the first bonding layer 500 and the second bonding layer 700 can be formed using different materials.

[0075] The peripheral circuitry 800 may include any suitable semiconductor device, such as low-voltage or high-voltage devices, metal-oxide-semiconductor field-effect transistors (MOSFETs), bipolar junction transistors (BJTs), diodes, resistors, capacitors, inductors, etc. The peripheral circuitry 800 also includes interconnect structures. For example, the peripheral circuitry 800 may include vias and wires electrically connected to circuitry formed in the peripheral circuitry 800 and the substrate 900. The interconnect structures can be electrically connected to circuitry formed in the memory chip 10 via bonding pads embedded in the first bonding layer 500 and the second bonding layer 700.

[0076] The second substrate 900 can be formed using a material similar to the first substrate 102. In some embodiments, the peripheral circuitry 800 and the second substrate 900 may include a suitable CMOS device 904. In some embodiments, the second substrate 900 may be any suitable structure, such as a semiconductor layer or a dielectric layer.

[0077] The peripheral chip 20 may be manufactured separately from the memory chip 10 and flipped to be bonded to the memory chip 10. In some embodiments, the first bonding layer 500 and the second bonding layer 700 are pressed together and bonded using a suitable bonding technique, such as a hybrid bonding technique. In some embodiments, the contact pads 501 of the first bonding layer 500 and the contact pads 701 of the second bonding layer 700 are aligned and bonded together.

[0078] Figure 2 A schematic top view of regions of a 3D memory chip according to some embodiments of the present disclosure is shown. The 3D memory device 2000 includes memory regions 200a-200f. Each memory region (e.g., a memory finger or block) is separated from an adjacent memory region by a slot structure 205, such as a gate line slot (GLS). Each slot structure extends laterally along the WL direction in a straight line pattern (parallel to the wafer plane) in a plan view. In some embodiments, the slot structure 205 separates a first memory region 200a from an adjacent second memory region 200b. In some embodiments, the slot structure 205 is optional and may not be formed between adjacent memory regions. For example, the slot structure 205 between the first memory region 200a and the second memory region 200b, between the third memory region 200c and the fourth memory region 200d, and / or between the fifth memory region 200e and the sixth memory region 200f may be omitted. In some embodiments, the slot structure 205 may be discontinuous in stepped regions. The 3D memory device 2000 may also include any other suitable memory regions, and for simplicity, these are not listed here. Figure 2As shown in the figure. In some embodiments, the first memory region 200a includes a first memory array 210a and a second memory array 211a. A stepped structure 220a is formed in the first stepped region 13a and the second stepped region 14a, respectively. The stepped structure 220a is also formed between the first memory array 210a and the second memory array 211a. A connector 212a is used to electrically couple the stepped structure 220a to at least one of the first memory array 210a and the second memory array 211a. In some embodiments, the connector may also be referred to as a bridging structure, and the area forming the connector may be referred to as a bridging region. A first TSC region 15a is formed between the two portions of the stepped structure 220a.

[0079] The third memory region 200c includes a first memory array 210c and a second memory array 211c. A first stepped region 13c and a second stepped region 14c may be formed between the first memory array 210c and the second memory array 211c. A TSC region 15c may be formed between and adjacent to the first stepped region 13c and the second stepped region 14c (e.g., in direct contact). A connector 16c may be formed in the first stepped region 13c, the second stepped region 14c, and the TSC region 15c.

[0080] Other memory regions may also be formed in the 3D memory device 2000. For example, the fifth memory region 200e includes at least a first memory array 210e, a second memory array 211e, a connector 212e, and a stepped structure 220e.

[0081] Figure 3 A schematic top view of the memory region of a 3D memory chip according to some embodiments of the present disclosure is shown. Specifically, Figure 3 yes Figure 2 An enlarged view of the first memory region 200a. (See attached image.) Figure 3 As shown, the first memory region 200a is the portion of the layer stack 200 separated by the slot structure 205. The first memory region 200a includes a channel structure 203, which can be divided into two groups by a top select gate cutout 207. In some embodiments, the top select gate cutout 207 may extend into a stepped region. In some embodiments, the first memory region 200a also includes a contact structure 204 and a dummy channel structure 206. A first TSC region 15a including TSC 300 is formed between the stepped structures 220a.

[0082] Figure 4 and Figure 5 Schematic perspective and top views of memory regions of a 3D memory chip according to some embodiments of the present disclosure are shown respectively. For example, Figure 4 yes Figure 2An enlarged schematic perspective view of the fifth memory region 200e, which includes at least a first memory array 210e, a second memory array 211e, a connector 212e, and a stepped structure 220e. Figure 4 and Figure 5 A portion of the memory array is shown, and for simplicity, additional structures, such as additional memory arrays, are not shown. For example, the fifth memory array 200e may include other suitable structures, which are not shown for simplicity. Figure 4 and Figure 5 As shown in the image. Among other things, Figure 4 and Figure 5 The TSC region, which forms parallel to the stepped structure, is shown.

[0083] The stepped structure 220e may include multiple steps 221e-228e. In some embodiments, steps 221e-228e may also be referred to as sub-steps. In some embodiments, each step in steps 221e-228e may be adjacent to (e.g., in direct contact with) an adjacent step. For example, step 221e may be adjacent to step 222e. Each step includes at least one or more steps, and the bottommost step may be a control gate 201 (…). Figure 4 (Not shown in the image). In some embodiments, the stepped structure 220e includes a plurality of adjacent pairs of steps having steps that descend in opposite directions. For example, step 221e is adjacent to step 222e, the former containing steps that descend in the x-direction, while the latter contains steps that descend in the negative x-direction. Step 222e may also be formed at a horizontal height below step 221e, such as... Figure 4 As shown. Specifically, the top rung of step 222e may be formed below the bottom rung of step 221e. At least one rung of each step in steps 221e-228e is electrically connected to the first memory array 210e or the second memory array 211e via connector 212e. In some embodiments, connector 212e may be divided into two parts, respectively connected to the first memory array 210e and the second memory array 211e.

[0084] Each step of the stepped structure 220e may contain a suitable number of steps. For example, Figure 4 The stairs 226e and 228e shown can each have five steps. For simplicity, Figure 4 A schematic diagram of the steps used for other steps is omitted. In some embodiments, the bottom step 226-1e of step 226e can be electrically coupled to the first memory array 210e and / or the second memory array 211e via connector 212e. Reference Figure 4 and Figure 5The control gate of the fifth memory region 200e may be formed at least in the first memory region 11e, the second memory region 12e, the second step region 14e, and the connector region 212e. Each contact structure 204 extends through the dielectric layer 230 to make physical contact with the hierarchy of the step structure.

[0085] TSC region 15e is formed between the first memory array 210e and the second memory array 211e. In some embodiments, TSC region 15e may be formed to extend in the word line direction (e.g., the x-direction) and parallel to the stepped structure. An isolation dielectric material may then be disposed in TSC region 15e, and a TSC extending through the isolation dielectric material in TSC region 15e may be formed.

[0086] Steps 221e-228e can be formed at different levels along a vertical direction (e.g., the z-direction). In some embodiments, a pair of steps, such as opposing steps 221e and 222e, can be formed at different vertical levels. For example, the bottom step of step 221e can be formed in a horizontal plane above another horizontal plane in which the top step of step 222e is formed. As another example, step 226e can be formed below step 228e. Specifically, the top steps 226-2e of step 226e can be in a horizontal plane below the horizontal plane in which the bottom steps 228-1e of step 228e are formed. Each step in steps 221e-228e can be connected to a corresponding contact 204 (for simplicity, in...). Figure 4 (Not shown in the image).

[0087] Figure 6 and 7 Schematic perspective and top views of memory regions of a 3D memory chip according to some embodiments of the present disclosure are shown respectively. For example, Figure 6 yes Figure 2 An enlarged schematic perspective view of the third memory region 200c, which includes at least a first memory array 210c, a second memory array 211c, a connector 212c, and a stepped structure 220c. The third memory array 200c may include other suitable structures, which are not shown for simplicity. Figure 6 and Figure 7 As shown in the image. Figure 6 and Figure 7 The TSC region formed within the stepped area and between the opposing stepped structures is shown.

[0088] Similar to Figure 4The stepped structure 220e shown may include a plurality of steps 221c-228c formed between the first memory array 210c and the second memory array 211c. In some embodiments, the stepped structure 220c includes a plurality of steps having opposite ramps. A TSC region may be formed between a pair of opposite stepped structures. For example, a TSC region 15c may be formed between opposite steps 223c and 224c. That is, the stepped structure 220c may be divided into two stepped regions by the TSC region 15c. For example, the first stepped region may include steps 221c-223c, while the second stepped region may include steps 224c-228c. Although Figure 6 The diagram shows a TSC region 15c, but additional TSC regions can be formed between other suitable steps in 221c-228c. For example... Figure 6 As shown, step 223c includes steps descending in the x-direction, and step 224c includes steps descending in the negative x-direction. In some embodiments, steps 223c and 224 each include steps descending in the same direction, such as in the x-direction or the negative x-direction. In another example, step structures 221c and 223c may each include steps descending in the positive x-direction, while step structure 222c formed by adjacent step structures 221c and 223c includes steps descending in the negative x-direction. An isolation dielectric material can then be disposed in the TSC region 15c, and a TSC extending through the isolation dielectric material in the TSC region 15c can be formed. In some embodiments, the TSC region 15c may extend in the bit line direction (e.g., the y-direction). In some embodiments, connector region 16 may extend in the word line direction and be formed between the first memory region 11 and the second memory region 12. In some embodiments, connector region 16 may be formed through a region (e.g., the central region) of the third memory region 200c. Specifically, stepped structures such as a first stepped structure 13c and a second stepped structure 14c can be formed on both sides of the connector region 16. The connector 212c can be formed within the connector region 16.

[0089] Figure 8 This is a flowchart of an exemplary method 800 for forming a TSC structure in a 3D memory device according to some embodiments of the present disclosure. The operation of method 800 may be performed in different orders and / or variations, and method 800 may include further operations not described for simplicity. Figure 9-23 These are various views of the mask patterns used to form the TSC structure and exemplary semiconductor structures. Examples of cross-sectional views are provided. Figure 9-23 To facilitate the explanation of method 800. Provided Figure 9-18 To show the formation Figure 2 and Figure 6An exemplary patterning and photolithography process for the third memory region 200c. Provided Figure 19-23 To show the formation Figure 2 and Figure 4 An exemplary patterning and photolithography process for the third memory region 200e. Although a fabrication process for forming a TSC structure within or adjacent to a stepped region is described herein by way of example, this fabrication process can be applied to form a TSC in any suitable region of a 3D memory device. The fabrication process provided herein is exemplary, and alternative processes according to this disclosure, not shown in these figures, can be performed.

[0090] Method 800 includes operations S100, S200, and S300. Specifically, operation S100 includes operations for forming a memory chip containing a TSC region within a stepped region. Operation S200 includes operations for forming a peripheral chip. Operation S300 includes operations for bonding the memory chip and the peripheral chip using a suitable bonding technique.

[0091] refer to Figure 8 In operation S101 of operation S100, according to some embodiments, an alternating layer stack may be disposed on a first substrate. In some embodiments, a dielectric layer and a sacrificial layer may be alternately disposed on the first substrate. Examples of the first substrate and the dielectric layer may be a first substrate 102 and a dielectric layer 202. The sacrificial layer may be formed prior to the formation of the control gate 201. In some embodiments, the sacrificial layer may be formed using silicon nitride.

[0092] refer to Figure 8 In operation S102 of operation S100, according to some embodiments, a stepped structure may be formed on the first substrate. For example, the stepped structure may be formed in different regions of the alternating layer stack formed in operation S101. The stepped structure may be divided into multiple regions, such as first and second stepped regions. In some embodiments, the alternating dielectric layer stack within the TSC region may be removed simultaneously during patterning and etching of the stepped structure. In some embodiments, as referenced... Figure 6 and Figure 9-18 As described, the TSC region is formed within the stepped region and between opposing sub-step structures. In some embodiments, as referenced... Figure 4 and Figure 19-23 As described, the TSC region is formed adjacent to and / or parallel to the stepped region. The TSC region can be formed in any suitable area of ​​the stepped region to reduce device footprint, increase device density, and reduce wire length, which in turn reduces power consumption. For ease of description only, the stepped region or stepped structure may contain multiple sub-stepped structures. The sub-stepped structure may also be referred to as the stepped structure itself and may include multiple ascending or descending steps.

[0093] TSC regions can be formed within the stepped region and between opposing sub-stepped structures, as shown in the reference. Figure 6 and Figure 9-18 As described. Reference Figure 9 The mask layer 600 includes openings corresponding to the stepped regions and the TSC regions. Specifically, the mask layer 600 includes a stepped pattern 610 having a pattern 601 for covering the first memory array 210c and the second memory array 211c. The stepped pattern 610 also includes openings for forming the slot structure 205. In some embodiments, the stepped pattern 610 also includes openings 603 extending in the bit line direction (e.g., the y-direction). The openings 603 can determine the number of stepped pairs facing each other, and therefore the number of openings 603 can depend on the arrangement of the stepped structures in the final product of the memory device. Each opening 603 can have a substantially rectangular shape. The mask layer 610 may also include a pattern 602 for forming connector regions. In some embodiments, the connector regions are electrically coupled to the first memory array 210c and / or the second memory array 211c. In some embodiments, mask layer 600 can be a hard mask formed using any suitable material, such as polysilicon, a high-k dielectric material (e.g., a material having a dielectric constant greater than about 3.9), any suitable material, and / or combinations thereof. Mask layer 600 can be used as an etching mask to etch the lower exposed portions of an alternating dielectric layer stack. An etching process can be used to etch the lower layer material using mask layer 600 as an etching mask. The initial etching process forms a uniform stepped structure (e.g., each step formed on the same horizontal level), such as... Figure 14 As shown.

[0094] After the initial etching process is completed, one or more trimming masks can be used in subsequent trimming etching processes to form steps and other suitable structures. (Reference) Figure 10-13 Describing trimming masks 620-650. Each of trimming masks 620-650 includes at least an opening in a substantially identical region for forming the TSC region 15c, such that each trimming etch process removes a portion of the underlying material in the TSC region 15c until the top surface of the underlying substrate is exposed. In some embodiments, trimming masks 620-650 may be soft masks (e.g., photoresist masks) that can be trimmed in trimming etch processes to form steps. In some embodiments, mask layer 600 may be formed by spin-coating a photoresist layer and patterning the coated photoresist layer using photolithography and development processes.

[0095] Trimming etching processes can create stepped structures with varying heights. (Reference) Figure 6Steps 221c-228c can each be formed at different heights. The height of each step is determined by the corresponding etch depth measured from the top surface of the first memory array 210c and the second memory array 211c to the top surface of the topmost step of each step in steps 221c-228c. In some embodiments, the etch depth of the corresponding structure can be calculated by multiplying the height of the step structure by a multiplication factor. In some embodiments, the multiplication factor is an integer value. As an example, the multiplication factors for steps 221c-223c, TSC region 15c (having a width that is substantially equal to twice the step width), and steps 224c-228c are 0, 4, 5, 8, 8, 7, 6, 2, 3, and 1, respectively.

[0096] The first trimming etching process uses Figure 10 The trimming mask 620 shown is used to perform the first etching process. The trimming mask 620 includes an opening 621 that exposes steps 223c, 224c, 227c, 228c, and the TSC region 15c. Region 623 represents a transparent area on the trimming masks 620-650, such that the TSC region 15c is exposed to multiple etching processes of the trimming etching process. The second, third, and fourth trimming etching processes use trimming masks 630, 640, and 650 as etching masks, respectively, to form... Figure 16 , Figure 17 and Figure 18 The structure shown.

[0097] TSC regions can be formed adjacent to and parallel to stepped regions, as shown in the reference. Figure 4 and Figure 19-23 As described. Reference Figure 19 The mask layer 1000 includes openings corresponding to the stepped region and the TSC region. Specifically, the mask layer 1000 includes a stepped pattern 1010 having a pattern 901 for covering the first memory array 210e and the second memory array 211e. The TSC region 15e may extend laterally in the word line direction (e.g., the x-direction) and be parallel to the stepped region in which the stepped region 220e is formed. Forming a TSC region parallel to the stepped region can provide benefits such as improved device density and reduced manufacturing costs. Trimming masks 1020-1050 may be substantially similar to trimming masks 620-650 and may be labeled with similar reference numerals. Each of trimming masks 1020-1050 includes at least one region 923 in substantially the same area for forming the TSC region 15e, such that each trimming etch process removes portions of the underlying alternating dielectric material in the TSC region 15e until the top surface of the underlying substrate is exposed.

[0098] refer to Figure 8In operation S103 of operation S100, according to some embodiments, the top surface of the underlying substrate can be exposed. For example... Figure 18 As shown, continue. Figure 13 The fourth trimming etching process shown uses trimming mask 650 until the material above TSC region 15c is completely removed. In some embodiments, the top surface of substrate 102 may be exposed. Figure 18 Not shown in the image, but Figure 1D (As shown in the diagram). The exposure of the underlying substrate can be accomplished by a trimming etching process such as the fourth trimming etching process described above, or by a suitable individual etching process.

[0099] refer to Figure 8 In operation S104 of operation S100, according to some embodiments, a TSC can be formed in the TSC region. Examples of TSC and TSC regions can be... Figure 1D The TSC 300 and TSC region 15c shown herein will not be described further for simplicity. A TSC can be formed, for example, by etching an opening through an isolation dielectric layer and placing one or more conductive materials within the opening.

[0100] refer to Figure 8 In operation S105 of operation S100, according to some embodiments, a memory string can be formed. The memory string can extend through alternating layers, and each memory string can include a stack of memory cells. Examples of memory strings could be... Figure 1C The array of channel structures 212 formed in the core array region 211 is shown, and will not be described further for simplicity.

[0101] refer to Figure 8 At operation S106 of operation S100, a control gate may be formed according to some embodiments. In some embodiments, the control gate may be formed by removing the dielectric layer of a stack of alternating dielectric layers and replacing the removed dielectric layer with a conductive material. Examples of control gates may include... Figure 1C The control gate 333 described in the document will not be described further in this document for the sake of simplicity.

[0102] refer to Figure 8 In operation S107 of operation S100, according to some embodiments, an interconnect layer may be formed. The interconnect layer may include conductive pads and lines providing electrical connections between different structures of the 3D memory device. Examples of the interconnect layer could be... Figure 1D The array of interconnect layers 400 shown is not described further here for the sake of simplicity.

[0103] refer to Figure 8In operation S108 of operation S100, according to some embodiments, a first bonding layer may be formed. The first bonding layer may be formed on the top surface of the isolation dielectric material encapsulating the stepped structure, TSC, memory array, etc. Examples of the first bonding layer could be... Figure 1C The first bonding layer 500 described in the previous section will not be described further in this paper for the sake of simplicity.

[0104] refer to Figure 8 Operation S200 includes operations for forming peripheral chips, etc. At operation S201 of operation S200, according to some embodiments, peripheral circuitry is formed. Peripheral circuitry may include any suitable semiconductor device for operating the memory device, such as low-voltage or high-voltage devices, metal-oxide-semiconductor field-effect transistors (MOSFETs), bipolar junction transistors (BJTs), diodes, resistors, capacitors, inductors, etc. Examples of peripheral circuitry may include... Figure 1D The peripheral circuit 800 described herein will not be described further for simplicity. At operation S202 of operation S200, a second bonding layer is formed according to some embodiments. The second bonding layer can be formed using a dielectric material suitable for wafer bonding. In some embodiments, conductive structures (e.g., metal bonding pads) may be formed in the second bonding layer. Examples of the second bonding layer could be... Figure 1D The second bonding layer 700 described in the previous section will not be described further in this paper for the sake of simplicity.

[0105] refer to Figure 8 In operation S300, according to some embodiments, first and second bonding layers are bonded using suitable wafer bonding techniques. The first and second bonding layers can be attached to each other using hybrid bonding techniques, during which dielectric layers and conductive structures from the memory chip and peripheral chip respectively contact and bond to each other face-to-face. In some embodiments, conductive structures such as metal bonding pads from the respective chips are aligned and bonded to achieve electrical connections. Examples of bonded first and second bonding layers could be... Figure 1D The first bonding layer 500 and the second bonding layer 700 shown in the figure will not be described in detail in this article for the sake of simplicity.

[0106] Various embodiments of this disclosure provide structures and methods for manufacturing contact structures in various regions of a 3D memory architecture. For example, through-silicon contacts can be formed in regions extending parallel to a stepped structure or in regions between two opposing stepped structures. Contact structures can be formed in contact regions by removing portions of alternating dielectric layer stacks, providing an isolation dielectric layer to replace the removed portions of the alternating stepped structures, forming openings through the isolation dielectric layer, and providing a conductive material in the openings. In some embodiments, the stepped structure can be formed during a multi-step trimming etching process, referred to as a "multi-truncation" process. The contact structures and methods for forming contact structures described in this disclosure offer various benefits, including but not limited to improved device density and reduced manufacturing costs.

[0107] The foregoing description of specific embodiments will fully reveal the general nature of this disclosure, enabling others to readily modify and / or adapt these specific embodiments to various applications by applying knowledge of the art, without excessive experimentation and without departing from the general concept of this disclosure. Therefore, based on the teachings and guidance provided herein, such adaptations and modifications are intended to fall within the meaning and scope of equivalent variations of the disclosed embodiments. It should be understood that the wording or terminology used herein is for descriptive purposes and not for limiting purposes, and that the terminology or terminology of this specification should be interpreted by those skilled in the art based on this disclosure and guidance.

[0108] Embodiments of this disclosure have been described above using functional building blocks, which illustrate implementations of specific functions and their relationships. For ease of description, the boundaries of these functional building blocks are arbitrarily defined herein. Alternative boundaries may be defined as long as the specific functions and relationships are properly performed.

[0109] The summary and abstract may set forth one or more, but not all, exemplary embodiments of this disclosure conceived by the inventors, and are therefore not intended to limit this disclosure and the appended claims in any way.

[0110] The scope and extent of this disclosure should not be limited by any of the exemplary embodiments described above, but should be defined solely by the appended claims and their equivalents.

Claims

1. A three-dimensional (3D) memory device, comprising: a first memory array and a second memory array disposed on a semiconductor layer; a staircase structure disposed between the first memory array and the second memory array, the staircase structure comprising a first staircase region and a second staircase region; the first staircase region comprising a first staircase structure, wherein the first staircase structure comprises a first plurality of steps descending in a first direction; the second staircase region comprising a second staircase structure, wherein the second staircase structure comprises a second plurality of steps descending in a second direction; a connector structure disposed between the first memory array and the second memory array, at least one step of the staircase structure connected to at least one of the first memory array and second memory array through the connector structure; and a contact region disposed between the first memory array and the second memory array, an extension direction of the contact region being the same as an extension direction of the connector structure; wherein the contact region comprises an insulating layer and a contact; the contact extending through the insulating layer and into the semiconductor layer.

2. The 3D memory device of claim 1, wherein, the insulating layer of the contact region and the first memory array, the second memory array are in contact.

3. The 3D memory device of claim 1, wherein, the first direction is the same as the second direction.

4. The 3D memory device of claim 1, wherein, the first direction is different from the second direction.

5. The 3D memory device of claim 1, wherein, at least one step of the first plurality of steps or the second plurality of steps is connected to the first memory array and the second memory array through the connector structure.

6. The 3D memory device of claim 1, wherein, the first staircase region further comprises a third staircase structure comprising a third plurality of steps descending in the second direction, the second direction being opposite to the first direction.

7. The 3D memory device of claim 6, wherein, the first staircase region further comprises a fourth staircase structure comprising a fourth plurality of steps descending in the first direction, and wherein the third staircase structure is adjacent to the first staircase structure and the fourth staircase structure.

8. The 3D memory device of claim 1, further comprising: a bonding layer over the contact and the staircase structure; and a semiconductor structure in contact with the bonding layer, wherein the semiconductor structure comprises a peripheral chip.

9. A three-dimensional (3D) memory device, comprising: a first semiconductor structure comprising: a first memory array structure and a second memory array structure disposed on a semiconductor layer; a staircase structure disposed between the first memory array structure and the second memory array structure and comprising a first staircase structure and a second staircase structure; the first staircase structure comprising a first plurality of steps descending in a first direction; the second staircase structure comprising a second plurality of steps descending in a second direction; a connector structure disposed between the first memory array structure and the second memory array structure, at least one step of the staircase structure connected to at least one of the first memory array and second memory array through the connector structure. ​ a contact region disposed between the first staircase structure and the second staircase structure, an extension direction of the contact region being perpendicular to an extension direction of the connector structure; wherein the contact region comprises an insulating layer and a contact; the contact extends through the insulating layer and into the semiconductor layer.

10. The 3D memory device of claim 9, wherein, the insulating layer of the contact region and the first staircase structure, the second staircase structure are in contact.

11. The 3D memory device of claim 9, wherein, the first direction is the same as the second direction.

12. The 3D memory device of claim 9, wherein, the first direction is different from the second direction.

13. The 3D memory device of claim 9, wherein, at least one of the first plurality of steps or the second plurality of steps is connected to the first memory array and the second memory array by the connector structure.

14. The 3D memory device of claim 9, further comprising a third staircase structure abutting the second staircase structure, wherein, the third staircase structure comprises a third plurality of steps descending in the first direction.

15. The 3D memory device of claim 14, wherein: the first direction and the second direction are opposite to each other.

16. The 3D memory device of claim 9, further comprising, a first bonding layer disposed above the contact; a second semiconductor structure comprising a peripheral circuit and a second bonding layer disposed above the peripheral circuit; wherein the second bonding layer is in contact with the first bonding layer.

17. A method for forming a three-dimensional (3D) memory device, comprising: forming an alternating layer stack on a semiconductor layer, wherein the alternating layer stack comprises a first memory array and a second memory array, a first staircase region and a second staircase region between the first memory array and the second memory array, and a contact region in contact with the first staircase region and the second staircase region; performing an etching process on the alternating layer stack in the first staircase region and the second staircase region, wherein each of a plurality of etching processes etches a portion of the alternating layer stack in the contact region; forming a connector structure between the first memory array and the second memory array to connect to the first memory array and / or the second memory array structure; wherein an extension direction of the contact region is the same as an extension direction of the connector structure; or, an extension direction of the contact region is perpendicular to an extension direction of the connector structure; forming an insulating dielectric layer in the contact region and on the alternating layer stack; forming a plurality of openings through the insulating dielectric layer disposed in the contact region and into the semiconductor layer; and disposing a conductive material in the plurality of openings to form a contact in the contact region.

18. The method of claim 17, wherein, the etching process exposes a top surface of the semiconductor layer in the contact region.

19. The method of claim 17, wherein, performing the etching process on the alternating layer stack comprises: forming a first staircase structure in the first staircase region, wherein the first staircase structure comprises a first plurality of steps descending in a first direction; and a second staircase structure is formed in the second staircase region, wherein the second staircase structure comprises a second plurality of steps descending in a second direction different from the first direction, and wherein the contact region adjoins the first staircase structure and the second staircase structure.

20. The method of claim 19, further comprising etching the alternating layer stack in the first staircase region to form a third staircase structure in the first staircase region, wherein, the third staircase structure adjoins the first staircase structure and comprises a third plurality of steps descending in the second direction.

21. The method of claim 17, wherein, the etching process comprises etching the alternating layer stack using a mask layer, wherein the mask layer comprises an opening in the contact region.

Images