Semiconductor structure and method of forming a semiconductor structure

Abstract

A semiconductor structure and a method of forming a semiconductor structure, the structure comprising: a substrate; a dielectric layer on the substrate; a gate opening in the dielectric layer, the gate opening comprising a first region and a second region on the first region, the first region having a first projection on the substrate, the second region having a second projection on the substrate, the second projection having an area greater than an area of the first projection, and the first projection being within the second projection; and a gate layer in the first region and in the second region. The second projection area of the second region is greater than the first projection area of the first region, so that the gate layer is more easily formed in the first region, and the performance of the semiconductor structure is improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a semiconductor structure and a method for forming the semiconductor structure. Background Technology

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. In the evolution of ICs, functional density (i.e., the number of interconnect devices per chip area) has generally increased, while geometry (i.e., the smallest component or line that can be produced using manufacturing processes) has decreased. This scaling down process typically provides benefits by increasing production efficiency and reducing associated costs. However, this scaling down also increases the complexity of handling and manufacturing ICs.

[0003] In some IC designs, as technology nodes shrink, one advantage is the ability to replace typical polysilicon gates with metal gates to improve device performance as component sizes decrease. A process for forming a metal gate is called a replacement gate or "post-gate" process, where the metal gate is manufactured "last." This allows for a reduction in the number of subsequent processes, including the high-temperature processing that must be performed after gate formation.

[0004] However, there are still some problems with the existing "post-gate" process for forming metal gates. Summary of the Invention

[0005] The technical problem solved by this invention is to provide a semiconductor structure and a method for forming the semiconductor structure, so as to improve the performance of the semiconductor structure.

[0006] To solve the above-mentioned technical problems, the present invention provides a semiconductor structure, comprising: a substrate; a dielectric layer on the substrate; a gate opening located within the dielectric layer, the gate opening comprising a first region and a second region located on the first region, the first region having a first projection on the substrate, the second region having a second projection on the substrate, the area of ​​the second projection being larger than the area of ​​the first projection, and the first projection being within the range of the second projection; and a gate layer located within the first region and the second region.

[0007] Optionally, the size of the second region in a first direction parallel to the substrate surface is greater than the size of the first region in the first direction parallel to the substrate surface by a range of 1 nanometer to 5 nanometers.

[0008] Optionally, the gate opening further includes a third region located on the second region, the third region having a third projection on the substrate, the area of ​​the third projection being larger than the area of ​​the second projection, and the second projection and the first projection being within the range of the third projection.

[0009] Optionally, the size of the third region in the first direction parallel to the substrate surface is greater than the size of the second region in the first direction parallel to the substrate surface by a range of 1 nanometer to 5 nanometers.

[0010] Optionally, it may also include a barrier layer located in the third zone.

[0011] Optionally, the barrier layer may be made of a dielectric material, which may include silicon nitride.

[0012] Optionally, it may also include: a gate dielectric layer located on the sidewall surface and bottom surface of the first region, and a work function layer located on the gate dielectric layer; the gate layer is located on the work function layer.

[0013] Optionally, it may also include source / drain doped regions located in the substrate on both sides of the gate layer.

[0014] Optionally, the substrate includes a base and a fin structure located on the base; the gate opening exposes a portion of the top surface and sidewall surface of the fin structure, the gate layer spans the fin structure, and the first direction is the extending direction of the fin structure.

[0015] Optionally, the top surface of the first region is higher than or flush with the top surface of the fin structure.

[0016] Optionally, the material of the gate layer includes a metal; the metal includes tungsten.

[0017] Accordingly, the present invention also provides a method for forming a semiconductor structure, comprising: providing a substrate; forming a dummy gate structure on the substrate; forming a dielectric layer on the sidewalls of the dummy gate structure; removing the dummy gate structure to form an initial gate opening within the dielectric layer, the initial gate opening comprising a first region and an initial second region located on the first region, the first region having a first projection on the substrate; removing a portion of the dielectric layer on the sidewalls of the initial second region to form a gate opening, the gate opening comprising a first region and a second region located on the first region, the second region having a second projection on the substrate, the area of ​​the second projection being larger than the area of ​​the first projection, and the first projection being within the range of the second projection; and forming an initial gate layer within the gate opening.

[0018] Optionally, the size of the second region in the first direction parallel to the substrate surface is greater than the size of the first region in the first direction parallel to the substrate surface by a range of 1 nanometer to 5 nanometers.

[0019] Optionally, the method for forming the second region includes: forming a sacrificial layer in the first region; using the sacrificial layer as a mask, etching the dielectric layer of the initial second region sidewall to form the second region; and removing the sacrificial layer after forming the second region.

[0020] Optionally, the method for forming the sacrificial layer includes: forming a sacrificial material layer within an initial gate opening and on a dielectric layer; etching back the sacrificial material layer until an initial second region is exposed, and forming the sacrificial layer within the first region.

[0021] Optionally, the material of the sacrificial layer includes an organic material; the organic material includes amorphous carbon or photoresist.

[0022] Optionally, the process for etching the dielectric layer on the sidewall of the initial second region includes an isotropic dry etching process.

[0023] Optionally, before forming the sacrificial layer in the first region, the method further includes: forming an initial gate dielectric layer and an initial work function layer on the initial gate opening sidewall surface and bottom surface; the sacrificial layer is located on the initial work function layer.

[0024] Optionally, before etching the dielectric layer of the initial second region sidewall using the sacrificial layer as a mask, the method further includes: removing the initial gate dielectric layer and the initial work function layer of the initial second region sidewall using the sacrificial layer as a mask, and forming the gate dielectric layer and the work function layer on the surface and bottom surface of the first region sidewall; the second region exposes the top surface of the gate dielectric layer and the top surface of the work function layer.

[0025] Optionally, the process for removing the initial gate dielectric layer and the initial work function layer from the initial second region sidewall includes a wet etching process.

[0026] Optionally, the aspect ratio of the initial gate opening is in the range of 3 to 6.

[0027] Optionally, the method for forming the initial gate layer includes: forming a gate material layer inside the gate opening and on the dielectric layer; planarizing the gate material layer until the surface of the dielectric layer is exposed to form the initial gate layer.

[0028] Optionally, the process for forming the gate material layer includes a physical vapor deposition process.

[0029] Optionally, the gate opening may further include a third region located on the second region.

[0030] Optionally, the method for forming the third region includes: removing a portion of the initial gate layer to form a gate layer, forming a transition third region within a dielectric layer, wherein the sidewalls of the transition third region expose the dielectric layer; etching the dielectric layer exposed by the transition third region to form the third region, wherein the third region has a third projection on the substrate, the area of ​​the third projection is larger than the area of ​​the second projection, and the second projection and the first projection are within the range of the third projection.

[0031] Optionally, the etching process for the dielectric layer exposed in the transition third region includes an isotropic dry etching process.

[0032] Optionally, the size of the third region in the first direction parallel to the substrate surface is greater than that of the second region in the first direction parallel to the substrate surface by a range of 1 nanometer to 5 nanometers.

[0033] Optionally, before forming a dielectric layer on the sidewalls of the dummy gate structure, the method further includes forming source / drain doped regions in the substrate on both sides of the dummy gate structure.

[0034] Optionally, it also includes: forming a barrier layer in the third region; after forming the barrier layer, forming a conductive plug in the dielectric layer, the conductive plug being located on the source / drain doped region.

[0035] Optionally, the substrate includes a base and a fin structure located on the base; the dummy gate structure spans the fin structure, and the first direction is the extending direction of the fin structure.

[0036] Optionally, the top surface of the first region is higher than or flush with the top surface of the fin structure.

[0037] Optionally, the material of the initial gate layer includes a metal; the metal includes tungsten.

[0038] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0039] The semiconductor structure of the present invention includes a gate opening located within a dielectric layer. The gate opening comprises a first region and a second region located on the first region. The first region has a first projection on the substrate, and the second region has a second projection on the substrate. The area of ​​the second projection is larger than the area of ​​the first projection, and the first projection falls within the range of the second projection. Therefore, when the gate layer is formed within the first region and the second region, the material of the gate layer can easily fill the first region, resulting in a dense gate layer structure, which is beneficial to improving the reliability of the semiconductor structure.

[0040] Furthermore, the gate opening also includes a third region located on the second region. The third region has a third projection on the substrate, the area of ​​which is larger than the area of ​​the second projection, and the second and first projections are within the range of the third projection. The barrier layer is located within the third region, so that when forming conductive plugs located on the source and drain doped regions, the barrier layer can limit the conductive plugs, thereby reducing the possibility of short circuits between the conductive plugs and the gate layers in the first and second regions, thus improving the performance of the semiconductor structure.

[0041] The semiconductor structure formation method of the present invention removes part of the dielectric layer on the sidewall of the initial second region, so that the second projected area of ​​the second region of the formed gate opening is larger than the first projected area of ​​the first region. Therefore, when the initial gate layer is formed in the gate opening, the material of the initial gate layer can easily fill the first region, thereby making the formed initial gate layer structure dense, which is beneficial to improving the reliability of the semiconductor structure.

[0042] Furthermore, the gate opening also includes a third region located on the second region. The third region has a third projection on the substrate, the area of ​​which is larger than the area of ​​the second projection, and the second and first projections are within the range of the third projection. Therefore, after a barrier layer is formed in the third region, when conductive plugs are formed on the source / drain doped regions, the barrier layer can limit the conductive plugs, thereby reducing the possibility of short circuits between the conductive plugs and the gate layers in the first and second regions, thus improving the performance of the semiconductor structure. Attached Figure Description

[0043] Figure 1 This is a schematic cross-sectional view of a semiconductor structure in one embodiment;

[0044] Figures 2 to 8 This is a cross-sectional schematic diagram of the semiconductor structure in an embodiment of the present invention. Detailed Implementation

[0045] As described in the background section, existing "post-gate" processes for forming metal gates still have some problems. These will now be analyzed and explained with reference to specific embodiments.

[0046] Figure 1 This is a schematic cross-sectional view of a semiconductor structure in one embodiment.

[0047] Please refer to Figure 1 The device includes: a substrate 100; a gate structure 101 located on the substrate 100; source and drain doped regions 102 located in the substrate 100 on both sides of the gate structure 101; and a dielectric layer 103 located on the substrate 100, wherein the dielectric layer 103 is located on the sidewall of the gate structure 101.

[0048] The gate structure 101 is a metal gate. A dummy gate needs to be formed first, followed by a dielectric layer 103 formed on the sidewalls of the dummy gate. Then, the dummy gate is removed, and a gate opening is formed within the dielectric layer 103. Finally, the gate structure 101 is formed within the gate opening. The gate structure 101 includes a gate dielectric layer (not shown), a work function layer (not shown) on the gate dielectric layer, and a gate layer (not indicated) on the work function layer. The material of the gate layer includes tungsten. Because the gate opening has a large depth-to-width ratio, when the gate dielectric layer and work function layer are formed first within the gate opening, and then the gate material layer is deposited using physical vapor deposition (PVD), the reactive gas in the PVD process has difficulty reaching the bottom of the gate opening. It preferentially deposits at the top of the gate opening, thus sealing it. This results in a loose and porous gate layer structure, leading to increased resistance and decreased reliability of the gate structure 101, adversely affecting the performance of the semiconductor structure.

[0049] Reducing the aspect ratio of the gate opening can solve the problem of poor material filling effect of the gate layer. However, if the width of the gate opening increases, the spacing between adjacent gate structures 101 will decrease accordingly. When a conductive plug electrically connected to the source / drain doped region 102 is subsequently formed in the dielectric layer 103, the conductive plug is prone to short-circuiting with the gate structure 101, affecting the performance of the semiconductor structure.

[0050] To address the aforementioned problems, the present invention provides a semiconductor structure and a method for forming the semiconductor structure. By removing a portion of the dielectric layer from the sidewall of the initial second region, the second projected area of ​​the second region of the formed gate opening is made larger than the first projected area of ​​the first region. As a result, when the initial gate layer is formed within the gate opening, the material of the initial gate layer can easily fill the first region, thereby making the formed initial gate layer structure dense and improving the reliability of the semiconductor structure.

[0051] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0052] Figures 2 to 8 This is a cross-sectional schematic diagram of the semiconductor structure in an embodiment of the present invention.

[0053] Please refer to Figure 2 Provides a substrate.

[0054] In this embodiment, the substrate includes a base 200 and a fin structure 201 located on the base; the substrate also has an isolation layer located on a portion of the sidewall of the fin structure 201, and the top surface of the isolation layer is lower than the top surface of the fin structure 201.

[0055] In this embodiment, the substrate 200 is made of silicon; the fin structure 201 is also made of silicon.

[0056] In other embodiments, the substrate material includes silicon carbide, silicon germanium, a multi-element semiconductor material composed of group III-V elements, silicon-on-insulator (SOI), or germanium-on-insulator (GOI). The multi-element semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs, or InGaAsP. The fin structure material includes silicon carbide, silicon germanium, a multi-element semiconductor material composed of group III-V elements, silicon-on-insulator (SOI), or germanium-on-insulator (GOI). The multi-element semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs, or InGaAsP.

[0057] In this embodiment, the fin structure 201 extends in a first direction parallel to the substrate surface.

[0058] In other embodiments, the substrate is a planar substrate.

[0059] Please continue to refer to this. Figure 2 A pseudo-gate structure 202 is formed on the substrate; source / drain doped regions 203 are formed in the substrate on both sides of the pseudo-gate structure 202.

[0060] In this embodiment, the dummy gate structure 202 spans the fin structure 201.

[0061] The dummy gate structure 102 includes a dummy gate dielectric layer (not shown) and a dummy gate layer (not labeled) located on the dummy gate dielectric layer.

[0062] The material of the pseudo-gate dielectric layer includes silicon oxide or a low-K (K less than 3.9) material; the material of the pseudo-gate layer includes polysilicon.

[0063] In this embodiment, the formation process of the source / drain doped region 203 includes an epitaxial growth process, and the top surface of the source / drain doped region 203 is higher than the top surface of the fin structure 201.

[0064] In other embodiments, the process for forming the source / drain doped regions includes an ion implantation process, wherein the top surface of the source / drain doped regions is flush with the top surface of the fin structure.

[0065] Please continue to refer to this. Figure 2 A dielectric layer 204 is formed on the sidewall of the pseudo-gate structure 202.

[0066] The dielectric layer 204 is made of a dielectric material, which includes one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbonate, silicon oxynitride, aluminum oxide, aluminum nitride, silicon oxycarbonate, and silicon oxycarbonate.

[0067] In this embodiment, the material of the dielectric layer 204 includes silicon oxide.

[0068] Please refer to Figure 3 Remove the pseudo gate structure 202 and form an initial gate opening 205 in the dielectric layer 204. The initial gate opening 205 includes a first region A and an initial second region B' located on the first region. The first region A has a first projection on the substrate.

[0069] The top surface of the first region A is higher than or flush with the top surface of the fin structure 201.

[0070] In this embodiment, the top surface of the first region A is higher than or flush with the top surface of the source / drain doped region 203. Therefore, when a gate layer is subsequently formed in the second region, the gate layer is less likely to come into contact with the source / drain doped region 203 and the fin structure 201, thus avoiding a short circuit caused by contact between the gate layer and the source / drain doped region 203 and the fin structure 201.

[0071] In this embodiment, the initial gate opening 205 further includes an initial third region C' located on the initial second region B'. The initial third region C' is used to form a barrier layer within the third region after the third region is subsequently formed.

[0072] In other embodiments, the initial third region may be excluded.

[0073] In this embodiment, the aspect ratio of the initial gate opening 205 is in the range of 3 to 6.

[0074] Next, a portion of the dielectric layer 204 on the sidewall of the initial second region B' is removed to form a transition gate opening 211. The transition gate opening 211 includes a first region A, a second region B located on the first region A, and a transition third region C' located on the second region B. The second region B has a second projection on the substrate, the area of ​​which is larger than the area of ​​the first projection, and the first projection falls within the range of the second projection. For the formation process of the second region B, please refer to [reference needed]. Figures 4 to 6 .

[0075] Please refer to Figure 4 An initial gate dielectric layer 206 and an initial work function layer 207 are formed on the sidewall surface and bottom surface of the initial gate opening 205.

[0076] The initial gate dielectric layer 206 provides a material layer for the subsequent formation of a gate dielectric layer on the sidewall surface and bottom surface of the first region A; the initial work function layer 207 provides a material layer for the subsequent formation of a work function layer on the gate dielectric layer.

[0077] The initial gate dielectric layer 206 is made of a high dielectric constant material, the dielectric constant of which is greater than 3.9, and the high dielectric constant material includes aluminum oxide or hafnium oxide; the initial work function layer 207 is made of an N-type work function material or a P-type work function material, the N-type work function material includes titanium aluminum, and the P-type work function material includes titanium nitride or tantalum nitride.

[0078] The process for forming the initial gate dielectric layer 206 includes atomic layer deposition, chemical vapor deposition, or thermal treatment; the process for forming the initial work function layer 207 includes atomic layer deposition, chemical vapor deposition, or thermal treatment.

[0079] In this embodiment, the process for forming the initial gate dielectric layer 206 includes atomic layer deposition; the process for forming the initial work function layer 207 includes atomic layer deposition.

[0080] Please continue to refer to this. Figure 4 A sacrificial layer 208 is formed in the first region A. The top surface of the sacrificial layer 208 is higher than or flush with the top surface of the fin structure 201. The sacrificial layer 208 is located on the initial work function layer 207.

[0081] In this embodiment, the top surface of the sacrificial layer 208 is higher than or flush with the top surface of the source / drain doped region 203. This ensures that the formed second region is higher than or flush with the top surface of the source / drain doped region 203.

[0082] The method for forming the sacrificial layer 208 includes: forming a sacrificial material layer (not shown) within the initial gate opening 205 and on the dielectric layer 204; etching back the sacrificial material layer until the initial second region B' is exposed; and forming the sacrificial layer 208 within the first region A.

[0083] The sacrificial layer 208 is made of an organic material, which includes amorphous carbon or photoresist. The process for forming the sacrificial material layer includes spin coating.

[0084] Please refer to Figure 5 Using the sacrificial layer 208 as a mask, the initial gate dielectric layer 206 and the initial work function layer 207 of the initial second region B' and the initial third region C' are removed, and the gate dielectric layer 209 and the work function layer 210 are formed on the side wall surface and bottom surface of the first region A.

[0085] The process for removing the initial gate dielectric layer 206 and the initial work function layer 207 from the sidewalls of the initial second region B' and the initial third region C' includes a wet etching process or a dry etching process.

[0086] In this embodiment, the process of removing the initial gate dielectric layer 206 and initial work function layer 207 from the sidewalls of the initial second region B' and the initial third region C' includes a wet etching process. The wet etching process can completely remove the initial gate dielectric layer 206 and initial work function layer 207 from the sidewalls of the initial second region B' and the initial third region C', so that when etching the dielectric layer 204 on the sidewalls of the initial second region B', the etching process encounters less obstruction and can form a second region B with a good sidewall morphology.

[0087] Please continue to refer to this. Figure 5 Using the sacrificial layer 208 as a mask, the dielectric layer 204 on the sidewalls of the initial second region B' and the initial third region C' is etched to form a transition gate opening 211. The transition gate opening 211 includes the second region B and the transition third region C' located on the second region B. The second region B exposes the top surface of the gate dielectric layer 209 and the top surface of the work function layer 210.

[0088] In this embodiment, the second region B has a second projection on the substrate, the area of ​​the second projection is larger than the area of ​​the first projection, and the first projection is within the range of the second projection. Therefore, when the initial gate layer is subsequently formed within the transition gate opening 211, the material of the initial gate layer can easily fill the first region A, resulting in a dense initial gate layer structure, which is beneficial for improving the reliability of the semiconductor structure.

[0089] The size of the second region B in the first direction is greater than that of the first region A in the first direction by a range of 1 nanometer to 5 nanometers. Within this range, the size of the second region B is larger than that of the first region A, which makes it easier for the gate material to fill the bottom of the first region A when the gate material is filled in the second region B and the first region A, resulting in a dense gate layer structure with better performance.

[0090] The process for etching the dielectric layer 204 on the sidewall of the initial second region B' includes an isotropic dry etching process. The isotropic dry etching process has good etching direction selectivity, thereby enabling lateral etching of the dielectric layer 204 on the sidewalls of the initial second region B' and the initial third region C', forming a second region with a second projected area larger than the first projected area.

[0091] After forming the second region B, the sacrificial layer 208 is removed.

[0092] The process for removing the sacrificial layer 208 includes a dry etching process or a wet etching process.

[0093] Please refer to Figure 6 An initial gate layer 212 is formed within the transition gate opening 211.

[0094] The method for forming the initial gate layer 212 includes: forming a gate material layer (not shown) inside the transition gate opening 211 and on the dielectric layer 204; planarizing the gate material layer until the surface of the dielectric layer 204 is exposed to form the initial gate layer 212.

[0095] In this embodiment, the process for forming the gate material layer includes physical vapor deposition. The physical vapor deposition process can rapidly form a dense and thick gate material layer.

[0096] The initial gate layer 212 is made of a metal, including tungsten.

[0097] Since the second projected area of ​​the second region B of the transition gate opening 211 is larger than the first projected area of ​​the first region A, when the initial gate layer 212 is formed in the transition gate opening 211, the material of the initial gate layer 212 is easily filled into the first region A, thereby making the structure of the initial gate layer 212 formed dense, which is beneficial to improving the reliability of the semiconductor structure.

[0098] Next, a gate layer is formed within the first region A and the second region B, and a third region C is formed on the second region B. The formation process of the third region C is described in [reference needed]. Figure 7 and Figure 8 .

[0099] Please refer to Figure 7 A portion of the initial gate layer 212 is removed to form a gate opening (not shown). The gate opening includes a first region A, a second region B located on the first region A, and a third region C located on the second region B. A gate layer 213 is formed in the first region A and the second region B. The gate layer 213 exposes the transition third region C”, and the sidewall of the transition third region C” exposes the dielectric layer 204.

[0100] The process for removing part of the initial gate layer 212 includes dry etching or wet etching.

[0101] Please continue to refer to this. Figure 7 The dielectric layer 204 exposed in the transition third region C” is etched to form the third region C. The third region C has a third projection on the substrate. The area of ​​the third projection is larger than the area of ​​the second projection, and the second projection and the first projection are within the range of the third projection.

[0102] The etching process for the dielectric layer exposed in the transition third region C” includes an isotropic dry etching process. The isotropic dry etching process has good selectivity in etching direction, thereby enabling lateral etching of the dielectric layer 204 on the sidewall of the transition third region C” to form a third region C with a third projected area larger than the first projected area and the second projected area.

[0103] The size of the third region C in the first direction is greater than that of the second region B in the first direction by a range of 1 nanometer to 5 nanometers. If the size of the third region C is too small compared to the second region B, the barrier layer formed in the third region C will have a weak blocking effect on the conductive plug when it is subsequently formed on the source / drain doped region 203. The conductive plug will still have the risk of short circuit due to contact with the gate layer 213 in the first region A and the second region B. If the size of the third region C is too large compared to the second region B, it will occupy the space for the conductive plug to be formed on the source / drain doped region 203, thus affecting the performance of the formed conductive plug.

[0104] The area of ​​the third projection is larger than the area of ​​the second projection, and the second and first projections are within the range of the third projection. Therefore, after a barrier layer is formed in the third region C, when a conductive plug is formed on the source / drain doped region 203, the barrier layer can limit the conductive plug, thereby reducing the possibility of short circuits occurring when the conductive plug contacts the gate layer 213 in the first region A and the second region B, thus improving the performance of the semiconductor structure.

[0105] Please refer to Figure 8 A barrier layer 214 is formed in the third region C; after the barrier layer 214 is formed, a conductive plug 215 is formed in the dielectric layer 204, the conductive plug 215 being located on the source / drain doped region 203.

[0106] The barrier layer 214 is made of a dielectric material, which includes one or more combinations of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbide, silicon oxynitride, and silicon oxycarbide. In this embodiment, the barrier layer 214 is made of silicon nitride.

[0107] The method for forming the conductive plug 215 includes: forming a patterned mask layer (not shown) on the dielectric layer 204 and the barrier layer 214; the patterned mask layer exposing the surface of the dielectric layer 204 on the source / drain doped regions 203; etching the dielectric layer 204 with the patterned mask layer as a mask until the surface of the source / drain doped regions 203 is exposed, forming an opening (not shown) in the dielectric layer 204; and forming the conductive plug 215 in the opening.

[0108] The material of the barrier layer 214 has a large etching selectivity ratio with that of the dielectric layer 204. Therefore, when etching the dielectric layer 204 to form an opening, the etching rate of the barrier layer 214 is relatively low, thus the barrier layer 214 can limit the opening. Consequently, when a conductive plug 215 is formed within the opening, the barrier layer 214 can limit the conductive plug 215, thereby reducing the possibility of a short circuit between the conductive plug 215 and the gate layer 213 in the first region A and the second region B, thereby improving the performance of the semiconductor structure.

[0109] Accordingly, embodiments of the present invention also provide a semiconductor structure, please refer to [the relevant documentation]. Figure 8 ,include:

[0110] Substrate;

[0111] Dielectric layer 204 located on the substrate;

[0112] A gate opening (not shown) is located within the dielectric layer 204. The gate opening includes a first region A and a second region B located on the first region A. The first region A has a first projection on the substrate, and the second region B has a second projection on the substrate. The area of ​​the second projection is larger than the area of ​​the first projection, and the first projection is within the range of the second projection.

[0113] Gate layer 213 located in region A and region B.

[0114] In this embodiment, the size of the second region B in the first direction parallel to the substrate surface is greater than the size of the first region A in the first direction parallel to the substrate surface by a range of 1 nanometer to 5 nanometers.

[0115] In this embodiment, the gate opening further includes a third region C located on the second region B. The third region C has a third projection on the substrate. The area of ​​the third projection is larger than the area of ​​the second projection, and the second projection and the first projection are within the range of the third projection.

[0116] In this embodiment, a barrier layer 214 located in the third region C is also included.

[0117] In this embodiment, the size of the third region C in the first direction parallel to the substrate surface is greater than the size of the second region B in the first direction parallel to the substrate surface by a range of 1 nanometer to 5 nanometers.

[0118] In this embodiment, the material of the barrier layer 214 includes a dielectric material, which includes silicon nitride.

[0119] In this embodiment, it further includes: a gate dielectric layer 209 located on the sidewall surface and bottom surface of the first region A, and a work function layer 210 located on the gate dielectric layer 209; the gate layer 213 is located on the work function layer 210.

[0120] In this embodiment, it also includes source / drain doped regions 203 located in the substrate on both sides of the gate layer 213.

[0121] In this embodiment, the substrate includes a substrate 200 and a fin structure 201 located on the substrate 200; the gate opening exposes a portion of the top surface and sidewall surface of the fin structure 201, the gate layer 213 spans the fin structure 201, and the first direction is the extending direction of the fin structure 201.

[0122] In this embodiment, the top surface of the first region A is higher than or flush with the top surface of the fin structure 201.

[0123] In this embodiment, the material of the gate layer 213 includes metal; the metal includes tungsten.

[0124] The semiconductor structure of the present invention includes a gate opening located within a dielectric layer 204. The gate opening comprises a first region A and a second region B located on the first region A. The first region A has a first projection on the substrate, and the second region B has a second projection on the substrate. The area of ​​the second projection is larger than the area of ​​the first projection, and the first projection falls within the range of the second projection. Therefore, when the gate layer 213 is formed within the first region A and the second region B, the material of the gate layer 213 can easily fill the first region A, resulting in a dense gate layer 213 structure, which is beneficial to improving the reliability of the semiconductor structure.

[0125] Furthermore, the gate opening also includes a third region C located on the second region B. The third region C has a third projection on the substrate. The area of ​​the third projection is larger than the area of ​​the second projection, and the second projection and the first projection are within the range of the third projection. The barrier layer 214 is located within the third region C. Thus, when forming the conductive plug 215 located on the source / drain doped region 203, the barrier layer 214 can limit the conductive plug 215, thereby reducing the possibility of short circuits occurring when the conductive plug 215 contacts the gate layer 213 in the first region A and the second region B, thereby improving the performance of the semiconductor structure.

[0126] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that, include: Substrate; Dielectric layer located on the substrate; A gate opening located within a dielectric layer, the gate opening comprising a first region and a second region located on the first region, the first region having a first projection on a substrate, the second region having a second projection on a substrate, the area of ​​the second projection being larger than the area of ​​the first projection, and the first projection being within the range of the second projection, the sidewall of the second region protruding beyond the sidewall of the first region. Gate layers located within the first and second regions; The source and drain doped regions are located in the substrate on both sides of the gate layer, and the second projection of the second region on the substrate coincides with a portion of the source and drain doped regions.

2. The semiconductor structure as described in claim 1, characterized in that, The size of the second region in the first direction parallel to the substrate surface is greater than that of the first region in the first direction parallel to the substrate surface by a range of 1 nanometer to 5 nanometers.

3. The semiconductor structure as described in claim 1, characterized in that, The gate opening further includes a third region located on the second region, the third region having a third projection on the substrate, the area of ​​the third projection being larger than the area of ​​the second projection, and the second projection and the first projection being within the range of the third projection.

4. The semiconductor structure as described in claim 3, characterized in that, The size of the third region in the first direction parallel to the substrate surface is greater than that of the second region in the first direction parallel to the substrate surface by a range of 1 nanometer to 5 nanometers.

5. The semiconductor structure as described in claim 3, characterized in that, Also includes: The barrier layer located in the third zone.

6. The semiconductor structure as described in claim 5, characterized in that, The barrier layer is made of a dielectric material, which includes silicon nitride.

7. The semiconductor structure as described in claim 1, characterized in that, Also includes: A gate dielectric layer located on the sidewall surface and bottom surface of the first region, and a work function layer located on the gate dielectric layer; the gate layer is located on the work function layer.

8. The semiconductor structure as described in claim 2, characterized in that, The substrate includes a base and a fin structure located on the base; the gate opening exposes a portion of the top surface and sidewall surface of the fin structure, the gate layer spans the fin structure, and the first direction is the extension direction of the fin structure.

9. The semiconductor structure as described in claim 8, characterized in that, The top surface of the first region is higher than or flush with the top surface of the fin structure.

10. The semiconductor structure as claimed in claim 1, characterized in that, The gate layer is made of a metal; the metal includes tungsten.

11. A method for forming a semiconductor structure, characterized in that, include: Provide substrate; A pseudo-gate structure is formed on the substrate; Source and drain doped regions are formed in the substrate on both sides of the pseudo-gate structure; A dielectric layer is formed on the sidewall of the pseudo-gate structure; Remove the dummy gate structure and form an initial gate opening in the dielectric layer. The initial gate opening includes a first region and an initial second region located on the first region. The first region has a first projection on the substrate. A portion of the dielectric layer on the sidewall of the initial second region is removed to form a gate opening. The gate opening includes a first region and a second region located on the first region. The second region has a second projection on the substrate. The area of ​​the second projection is larger than the area of ​​the first projection, and the first projection is within the range of the second projection. The sidewall of the second region protrudes from the sidewall of the first region. The second projection of the second region on the substrate coincides with a portion of the source / drain doped regions. An initial gate layer is formed within the gate opening.

12. The method for forming a semiconductor structure as described in claim 11, characterized in that, The size of the second region in the first direction parallel to the substrate surface is greater than that of the first region in the first direction parallel to the substrate surface by a range of 1 nanometer to 5 nanometers.

13. The method for forming a semiconductor structure as described in claim 11, characterized in that, The method for forming the second region includes: forming a sacrificial layer in the first region; using the sacrificial layer as a mask, etching the dielectric layer of the initial second region sidewall to form the second region; and removing the sacrificial layer after forming the second region.

14. The method for forming a semiconductor structure as described in claim 13, characterized in that, The method for forming the sacrificial layer includes: forming a sacrificial material layer in an initial gate opening and on a dielectric layer; etching back the sacrificial material layer until an initial second region is exposed, and forming the sacrificial layer in the first region.

15. The method for forming a semiconductor structure as described in claim 13, characterized in that, The material of the sacrificial layer includes organic materials; the organic materials include amorphous carbon or photoresist.

16. The method for forming a semiconductor structure as described in claim 13, characterized in that, The process for etching the dielectric layer on the sidewall of the initial second region includes an isotropic dry etching process.

17. The method for forming a semiconductor structure as described in claim 13, characterized in that, Before forming the sacrificial layer in the first region, the method further includes: forming an initial gate dielectric layer and an initial work function layer on the initial gate opening sidewall surface and bottom surface; the sacrificial layer is located on the initial work function layer.

18. The method for forming a semiconductor structure as described in claim 17, characterized in that, Before etching the dielectric layer of the initial second region sidewall using the sacrificial layer as a mask, the method further includes: removing the initial gate dielectric layer and the initial work function layer of the initial second region sidewall using the sacrificial layer as a mask, and forming the gate dielectric layer and the work function layer on the surface and bottom surface of the first region sidewall; the second region exposes the top surface of the gate dielectric layer and the top surface of the work function layer.

19. The method for forming a semiconductor structure as described in claim 18, characterized in that, The process for removing the initial gate dielectric layer and initial work function layer from the sidewalls of the initial second region includes wet etching.

20. The method for forming a semiconductor structure as described in claim 11, characterized in that, The aspect ratio of the initial gate opening is in the range of 3 to 6.

21. The method for forming a semiconductor structure as described in claim 11, characterized in that, The method for forming the initial gate layer includes: forming a gate material layer inside the gate opening and on the dielectric layer; planarizing the gate material layer until the surface of the dielectric layer is exposed to form the initial gate layer.

22. The method for forming a semiconductor structure as described in claim 21, characterized in that, The process for forming the gate material layer includes physical vapor deposition.

23. The method for forming a semiconductor structure as described in claim 11, characterized in that, The gate opening also includes a third region located on the second region.

24. The method for forming a semiconductor structure as described in claim 23, characterized in that, The method for forming the third region includes: removing a portion of the initial gate layer to form a gate layer; forming a transition third region within a dielectric layer, wherein the sidewalls of the transition third region expose the dielectric layer; etching the dielectric layer exposed by the transition third region to form the third region, wherein the third region has a third projection on the substrate, the area of ​​the third projection is larger than the area of ​​the second projection, and the second projection and the first projection are within the range of the third projection.

25. The method for forming a semiconductor structure as described in claim 24, characterized in that, The etching process for the dielectric layer exposed in the transition third region includes an isotropic dry etching process.

26. The method for forming a semiconductor structure as described in claim 23, characterized in that, The size of the third region in the first direction parallel to the substrate surface is greater than that of the second region in the first direction parallel to the substrate surface by a range of 1 nanometer to 5 nanometers.

27. The method for forming a semiconductor structure as described in claim 11, characterized in that, Also includes: A barrier layer is formed in the third region; after the barrier layer is formed, a conductive plug is formed in the dielectric layer, the conductive plug being located on the source / drain doped region.

28. The method for forming a semiconductor structure as described in claim 12, characterized in that, The substrate includes a base and a fin structure located on the base; the dummy gate structure spans the fin structure, and the first direction is the extending direction of the fin structure.

29. The method for forming a semiconductor structure as described in claim 28, characterized in that, The top surface of the first region is higher than or flush with the top surface of the fin structure.

30. The method for forming a semiconductor structure as described in claim 11, characterized in that, The material of the initial gate layer includes a metal; the metal includes tungsten.

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