Semiconductor package, semiconductor device, and power conversion device

Abstract

A semiconductor package (100) includes a semiconductor element (1), a first insulating layer (5), a first wiring layer (6), a second insulating layer (7), and a second wiring layer (8). The first insulating layer (5) covers the semiconductor element (1). The first wiring layer (6) includes a first layer portion (61). The first layer portion (61) covers the first insulating layer (5). The second insulating layer (7) covers the first insulating layer (5) and the first wiring layer (6). The second wiring layer (8) is electrically connected to the semiconductor element (1) through a second through hole (TH2) and a third through hole (TH3). The second wiring layer (8) includes a second layer portion (81). The second layer portion (81) covers the second insulating layer (7). A portion of the second layer portion (81) of the second wiring layer (8) overlaps the first layer portion (61) of the first wiring layer (6) with the second insulating layer (7) interposed therebetween.

Description

Technical Field

[0001] The present disclosure relates to semiconductor packages, semiconductor devices, and power conversion devices. Background Art

[0002] Conventionally, there have been semiconductor elements called power semiconductor elements. Power semiconductor elements are semiconductor elements that handle high voltages and large currents. Among power semiconductor elements, there are elements in which the conduction path runs along the longitudinal direction of the power semiconductor element. A power semiconductor package formed by mounting a power semiconductor element on a circuit board and encapsulating it with a sealing resin is connected to a cooler called a heat sink, control components, and the like. The power semiconductor package connected to the heat sink is used as a semiconductor device in a wide range of fields such as industrial machines, automobiles, and railways.

[0003] In recent years, with the miniaturization and weight reduction of machines equipped with semiconductor devices, miniaturization and weight reduction of power semiconductor packages have also been required. For example, the semiconductor device module (semiconductor package) described in Japanese Patent Laid-Open No. 2014-179612 (Patent Document 1) includes a semiconductor device (semiconductor element), a dielectric layer (first insulating layer), and a metallization layer (first wiring layer). The semiconductor device module can be used as a power semiconductor package. The dielectric layer is stacked on the semiconductor device. Through holes overlapping the semiconductor device are provided in the dielectric layer. The metallization layer is electrically connected to the electrodes of the semiconductor device through the through holes. As a result, the wiring of the metallization layer is drawn out to the surface of the dielectric layer. Therefore, the wiring of the metallization layer is stacked on the dielectric layer. Therefore, miniaturization in the width direction of the semiconductor device module can be achieved.

[0004] In addition, the power semiconductor element of the power semiconductor package performs switching operations under high voltage and large current. When the power semiconductor element changes from the off state to the on state during the switching operation, a surge voltage is applied to the power semiconductor element. The magnitude of the surge voltage is proportional to the time change rate of the current and the inductance of the wiring of the power semiconductor package. When the surge voltage is large, the power semiconductor element may deteriorate. Therefore, in the power semiconductor package, in addition to miniaturization, reduction of inductance is also required.

[0005] Prior Art Documents

[0006] Patent Documents

[0007] Patent Document 1: Japanese Patent Laid-Open No. 2014-179612 Summary of the Invention

[0008] However, in the semiconductor package (semiconductor device module) described in the above literature, when wiring the first wiring layer (metallization layer) in such a way as to ensure the insulation distance between adjacent wirings, the wiring becomes complicated. In the case of complicated wiring, it is difficult to consider the direction of the current flowing in adjacent wirings, so sometimes currents in the same direction flow in adjacent wirings. As a result, in the first wiring layer, the influence of the magnetic flux caused by the current is generated. Therefore, it is difficult to reduce the inductance of the semiconductor package.

[0009] The present disclosure has been made in view of the above problems, and an object thereof is to provide a semiconductor package, a semiconductor device, and a power conversion device capable of reducing inductance.

[0010] The semiconductor package of the present disclosure includes a semiconductor element, a first insulating layer, a first wiring layer, a second insulating layer, and a second wiring layer. The first insulating layer covers the semiconductor element. A first through hole and a second through hole are provided in the first insulating layer. The first wiring layer includes a first layer portion. The first layer portion covers the first insulating layer. The first wiring layer is electrically connected to the semiconductor element through the first through hole. The second insulating layer covers the first insulating layer and the first wiring layer. A third through hole is provided in the second insulating layer. The third through hole communicates with the second through hole. The second wiring layer is electrically connected to the semiconductor element through the second through hole and the third through hole. The second wiring layer includes a second layer portion. The second layer portion of the second wiring layer has a portion that overlaps the first layer portion of the first wiring layer with the second insulating layer interposed therebetween.

[0011] According to the semiconductor package of the present disclosure, the second layer portion of the second wiring layer has a portion that overlaps the first layer portion of the first wiring layer. Therefore, it is possible to make the direction of the current flowing in the portion of the second layer portion that overlaps the first layer portion of the first wiring layer opposite to the direction of the current flowing in the first layer portion. As a result, it is possible to cancel out the influence of the magnetic flux caused by the current flowing in the first layer portion and the current flowing in the second layer portion, respectively. Therefore, it is possible to reduce the inductance of the semiconductor package. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 is a cross-sectional view schematically showing the structure of the semiconductor package according to Embodiment 1.

[0013] Figure 2 is a top view schematically showing the structure of the semiconductor package according to Embodiment 1.

[0014] Figure 3 is a top view schematically showing the structures of the semiconductor element, the conductive plate, and the heat spreader of the semiconductor package according to Embodiment 1.

[0015] Figure 4It is a top view schematically showing the structures of a semiconductor element, a conductive plate, a heat dissipation device, a first insulating layer, and a first wiring layer of the semiconductor package according to Embodiment 1.

[0016] Figure 5 It is a top view schematically showing the structures of a semiconductor element, a conductive plate, a heat dissipation device, a first insulating layer, a first wiring layer, a second insulating layer, and a second wiring layer of the semiconductor package according to Embodiment 1.

[0017] Figure 6 It is a cross-sectional view schematically showing the structure of the semiconductor package according to the first comparative example.

[0018] Figure 7 It is a top view schematically showing the structure of the semiconductor package according to the first comparative example.

[0019] Figure 8 It is a cross-sectional view schematically showing the structure of the semiconductor package according to Embodiment 2.

[0020] Figure 9 It is a cross-sectional view schematically showing the structure of the semiconductor package according to Embodiment 3.

[0021] Figure 10 It is a cross-sectional view schematically showing the structure of the semiconductor package according to Embodiment 4.

[0022] Figure 11 It is a cross-sectional view schematically showing the structure of the semiconductor package according to the second comparative example.

[0023] Figure 12 It is a cross-sectional view schematically showing the structure of the semiconductor package according to Embodiment 5.

[0024] Figure 13 It is a cross-sectional view schematically showing the structure of the semiconductor package according to Embodiment 6.

[0025] Figure 14 It is a cross-sectional view schematically showing the structure of the semiconductor device according to Embodiment 7.

[0026] Figure 15 It is a cross-sectional view schematically showing the state of laminating a first insulating layer, a first wiring layer, a second insulating layer, a second wiring layer, and an organic layer of the semiconductor package of the semiconductor device according to Embodiment 7.

[0027] Figure 16 It is a cross-sectional view schematically showing the state where the semiconductor element and the conductive plate of the semiconductor package of the semiconductor device according to Embodiment 7 are joined to the heat dissipation device.

[0028] Figure 17This is a cross-sectional view schematically showing the structure of the semiconductor device according to Embodiment 8.

[0029] Figure 18 This is a cross-sectional view schematically showing the structure of the semiconductor device according to Embodiment 9.

[0030] Figure 19 This is a cross-sectional view schematically showing the state where the semiconductor package and the heat sink of the semiconductor device according to Embodiment 9 are joined.

[0031] Figure 20 This is a block diagram schematically showing the structure of the power conversion device according to Embodiment 10.

[0032] (Symbol Explanation)

[0033] 1: Semiconductor element; 2: Conductive plate; 3: Bonding material; 4: Heat dissipation device; 5: First insulating layer; 6: First wiring layer; 7: Second insulating layer; 8: Second wiring layer; 9: Sealing portion; 46: First metal plate; 47: Insulating substrate; 48: Second metal plate; 61: First layer portion; 81: Second layer portion; 100: Semiconductor package; 110: Power supply; 200: Semiconductor device; 201: Main conversion circuit; 203: Control circuit; 300: Power conversion device; 400: Load; HS: Heat sink; ML: Conductive metal bonding material; OL: Organic layer; OP1: First opening; OP2: Second opening; RL: Insulating resin layer; TH1: First through hole; TH1a: First through portion; TH1b: Second through portion; TH2: Second through hole; TH3: Third through hole; SB: Control substrate; SP: Control part; SP1: First control component; SP2: Second control component. Detailed Embodiment

[0034] Hereinafter, the embodiments will be described with reference to the drawings. In addition, hereinafter, the same or corresponding parts will be given the same reference numerals and repeated explanations will not be provided.

[0035] Embodiment 1.

[0036] Use Figures 1 - 5 to describe the structure of the semiconductor package 100 according to Embodiment 1. Figure 1 is a cross-sectional view along the Figure 2 I-I line. As Figure 1As shown, the semiconductor package 100 includes a semiconductor element 1, a first insulating layer 5, a first wiring layer 6, a second insulating layer 7, and a second wiring layer 8. The semiconductor package 100 according to the present embodiment further includes a conductive plate 2, a bonding material 3, a heat dissipation device 4, a sealing portion 9, and an organic layer OL. The semiconductor package 100 is a power semiconductor package. A power semiconductor package is a semiconductor package 100 including a power semiconductor element described later.

[0037] The semiconductor element 1 according to the present embodiment is a power semiconductor element. In the present embodiment, a power semiconductor element refers to a semiconductor element for dealing with high voltage or large current. A power semiconductor element is, for example, a semiconductor element for electric power. Specifically, the power semiconductor element is a semiconductor element for electric power control such as a metal oxide semiconductor field effect transistor (MOSFET: Metal Oxide Semiconductor Field Effect Transistor) and an insulated gate bipolar transistor (IGBT: Insulated Gate Bipolar Transistor), a freewheeling diode, and the like.

[0038] The semiconductor element 1 according to the present embodiment is a so-called vertical semiconductor element. Therefore, current flows along a direction from the surface of the semiconductor element 1 toward the back surface. The surface of the semiconductor element 1 is configured as an electrode.

[0039] The semiconductor element 1 is bonded to the heat dissipation device 4 through the bonding material 3. The bonding material 3 is, for example, solder, sintered silver (Ag), and a conductive adhesive. In addition, the bonding of the semiconductor element 1 and the heat dissipation device 4 is not limited to using the bonding material 3. The semiconductor element 1 can also be bonded to the heat dissipation device 4 by liquid phase diffusion bonding, for example.

[0040] The conductive plate 2 is bonded to the heat dissipation device 4 through the bonding material 3. Therefore, the current that has passed through the semiconductor element 1 and the heat dissipation device 4 is guided to the first wiring layer 6 through the conductive plate 2. The material of the conductive plate 2 is a conductive metal. The material of the conductive plate 2 is, for example, copper (Cu) and aluminum (Al). The thickness of the conductive plate 2 is on the same level as that of the semiconductor element 1. In addition, the bonding of the conductive plate 2 and the heat dissipation device 4 is not limited to using the bonding material 3. The conductive plate 2 can also be bonded to the heat dissipation device 4 by liquid phase diffusion bonding, for example.

[0041] The heat dissipation device 4 includes a first surface 41, a second surface 42, and a side surface 43. The semiconductor element 1 and the conductive plate 2 are bonded to the first surface 41. The second surface 42 faces the first surface 41. The side surface 43 connects the first surface 41 and the second surface 42. The material of the heat dissipation device 4 is, for example, a metal with excellent heat dissipation such as copper (Cu) and aluminum (Al).

[0042] The first insulating layer 5 covers the semiconductor element 1. The first insulating layer 5 covers the conductive plate 2. The first insulating layer 5 is a polymer-based insulating film using polymer materials such as liquid crystal polymer and polyimide, for example. The first insulating layer 5 is adhered to the surfaces of the semiconductor element 1 and the conductive plate 2 respectively by a resin adhesive (not shown).

[0043] A first through hole TH1 and a second through hole TH2 are provided in the first insulating layer 5. The first through hole TH1 and the second through hole TH2 penetrate the first insulating layer 5. The first through hole TH1 and the second through hole TH2 are configured as vias. In the first insulating layer 5, the first through hole TH1 and the second through hole TH2 are formed by, for example, laser processing. The first through hole TH1 includes a first through portion TH1a and a second through portion TH1b. The first through portion TH1a overlaps with the semiconductor element 1. The second through portion TH1b overlaps with the conductive plate 2. The second through hole TH2 overlaps with the semiconductor element 1.

[0044] The first wiring layer 6 is electrically connected to the semiconductor element 1 through the first through hole TH1. The first wiring layer 6 is configured as a metal wiring layer. The first wiring layer 6 is formed by patterning.

[0045] The first wiring layer 6 is formed by the following process. After adhering the first insulating layer 5 to the semiconductor element 1 and the conductive plate 2, the first through hole TH1 and the second through hole TH2 are formed in the first insulating layer 5. Then, a metal sputtering film is deposited on the first insulating layer 5. In addition, the metal sputtering film is also deposited inside the first through hole TH1 and the second through hole TH2. Next, a plating layer is formed on the metal sputtering film. After the plating layer grows to have a sufficient thickness, the metal sputtering film and the plating layer are etched. Thereby, the wiring pattern of the first wiring layer 6 is formed. In addition, the method of forming the wiring pattern of the first wiring layer 6 is not limited to the above method. For example, after adhering a metal foil to the first insulating layer 5, the metal foil can be etched to form the wiring pattern of the first wiring layer 6.

[0046] The first wiring layer 6 includes a first layer portion 61, a first connection portion 62, and a first terminal portion 63. The first layer portion 61 covers the first insulating layer 5. The first layer portion 61 is electrically connected to the semiconductor element 1 through the first connection portion 62. The shape of the first layer portion 61 is a flat plate. The first connection portion 62 is disposed inside the first through hole TH1. The first terminal portion 63 is exposed from the second insulating layer 7. Therefore, the first terminal portion 63 is configured as a terminal for connecting to an external wiring.

[0047] The first wiring layer 6 includes a first wiring portion 6a and a second wiring portion 6b. In addition, in the present embodiment, the first wiring layer 6 includes a plurality of first wiring portions 6a as described later. The first wiring portion 6a is electrically connected to the semiconductor element 1 through the first through-hole TH1a. The second wiring portion 6b is electrically connected to the conductive plate 2 through the second through-hole TH1b. In Figure 1 the first layer portion 61 is included in the second wiring portion 6b. The first wiring portion 6a and the second wiring portion 6b are connected through the semiconductor element 1, the conductive plate 2, and the heat dissipation device 4.

[0048] The second insulating layer 7 covers the first insulating layer 5 and the first wiring layer 6. A third through-hole TH3 is provided in the second insulating layer 7. The third through-hole TH3 penetrates the second insulating layer 7. The third through-hole TH3 is configured as a via hole. The third through-hole TH3 communicates with the second through-hole TH2.

[0049] The second insulating layer 7 is, for example, a polymer-based insulating film using polymer materials such as liquid crystal polymer and polyimide. The second insulating layer 7 is adhered to the surfaces of the first insulating layer 5 and the first wiring layer 6 respectively through a resin adhesive (not shown).

[0050] The second wiring layer 8 is electrically connected to the semiconductor element 1 through the second through-hole TH2 and the third through-hole TH3. The second wiring layer 8 is formed by the same method as the first wiring layer 6. Therefore, in the second wiring layer 8, a wiring pattern is formed by etching. In addition, in the present embodiment, for example, the first wiring layer 6 is configured as a P terminal, and the second wiring layer 8 is configured as an N terminal.

[0051] The second wiring layer 8 includes a second layer portion 81, a second connection portion 82, and a second terminal portion 83 (refer to Figure 2 ). The second layer portion 81 covers the second insulating layer 7. The shape of the second layer portion 81 is a flat plate. The second layer portion 81 is superposed parallel to the first layer portion 61. That is, the first layer portion 61 and the second layer portion 81 are configured as parallel flat plates. The second layer portion 81 is electrically connected to the semiconductor element 1 through the second connection portion 82. The second connection portion 82 is disposed inside the second through-hole TH2 and the third through-hole TH3. The structure of the second terminal portion 83 will be described later.

[0052] The second layer portion 81 of the second wiring layer 8 has a portion superposed on the first layer portion 61 of the first wiring layer 6 in a state of sandwiching the second insulating layer 7. The second wiring layer 8 is configured such that a current flowing in a direction opposite to the current flowing in the first layer portion 61 flows in the portion of the second layer portion 81 superposed on the first layer portion 61 in a state of sandwiching the second insulating layer 7.

[0053] The sealing portion 9 seals the semiconductor element 1 and the conductive plate 2 between the first surface 41 and the first insulating layer 5. The sealing portion 9 seals the first surface 41 and the side surface 43 of the heat dissipation device 4. The surface of the semiconductor element 1, the surface of the conductive plate 2, and the second surface 42 of the heat dissipation device 4 are exposed from the sealing portion 9. The material of the sealing portion 9 is, for example, epoxy resin or the like. The sealing portion 9 is formed, for example, by transfer molding using a mold.

[0054] The organic layer OL is stacked on the second wiring layer 8. The material of the organic layer OL is, for example, a resist. For example, the organic layer OL is formed by coating a resist on the surface of the second wiring layer 8. The surface of the second wiring layer 8 is protected by the organic layer OL.

[0055] As Figure 2 shown, the first wiring layer 6 and the second wiring layer 8 are partially exposed from the organic layer OL. In addition, in Figure 2 , the outer shapes of the portions of the semiconductor element 1, the conductive plate 2, and the heat dissipation device 4 on which other components are stacked are indicated by dashed lines. In addition, the outer shapes of the portions of the first insulating layer 5 and the first wiring layer 6 on which other components are stacked are indicated by single-dot dashed lines. The outer shapes of the portions of the second insulating layer 7 and the second wiring layer 8 on which other components are stacked are indicated by double-dot dashed lines. The first wiring layer 6 and the second wiring layer 8 are exposed from the outer periphery of the organic layer OL. The second terminal portion 83 of the second wiring layer 8 is exposed from the organic layer OL. Therefore, the second terminal portion 83 is configured as a terminal for external connection.

[0056] Although not shown, the semiconductor package 100 may further include a third insulating layer and a third wiring layer. The third insulating layer covers the second insulating layer 7 and the second wiring layer 8. The third wiring layer is electrically connected to the second wiring layer 8. The third wiring layer includes a third layer portion. The third layer portion covers the second wiring layer 8. The third layer portion has a portion that is stacked on the second layer portion 81 of the second wiring layer 8 with the third insulating layer interposed therebetween. The organic layer OL may also cover the third wiring layer.

[0057] Next, Figures 3 - 5 is used to describe in detail the semiconductor package 100 according to Embodiment 1.

[0058] As Figure 3 shown, the semiconductor element 1 includes a plurality of first semiconductor portions 1a and a plurality of second semiconductor portions 1b. In addition, in Figure 3 , for ease of explanation, the sealing portion 9 is not shown.

[0059] The conductive plate 2 includes a plurality of first conductive portions 2a, a second conductive portion 2b, and a plurality of third conductive portions 2c. The second conductive portion 2b is disposed between the first semiconductor portion 1a and the second semiconductor portion 1b. The plurality of third conductive portions 2c are disposed on the side opposite to the second conductive portion 2b with respect to the first semiconductor portion 1a.

[0060] The heat dissipation device 4 includes a first heat dissipation device portion 4a and a second heat dissipation device portion 4b. The first heat dissipation device portion 4a is arranged at an interval from the first heat dissipation device portion 4a. A plurality of first semiconductor portions 1a, a plurality of first conductive portions 2a, and a second conductive portion 2b are joined to the first heat dissipation device portion 4a. A plurality of second semiconductor portions 1b and a plurality of third conductive portions 2c are joined to the second heat dissipation device portion 4b.

[0061] As Figure 4 shown, the first wiring layer 6 includes a plurality of first wiring portions 6a, a second wiring portion 6b, a plurality of third wiring portions 6c, a plurality of fourth wiring portions 6d, and a plurality of fifth wiring portions 6e. In addition, in Figure 4 , the outer shapes of the portions where the semiconductor element 1, the conductive plate 2, and the heat dissipation device 4 are superimposed with other components are indicated by dashed lines. Each of the plurality of first wiring portions 6a is joined to each of the plurality of first semiconductor portions 1a. The second wiring portion 6b is joined to the second conductive portion 2b and each of the plurality of second semiconductor portions 1b. Each of the plurality of third wiring portions 6c is joined to each of the plurality of first conductive portions 2a. Each of the plurality of fourth wiring portions 6d is joined to each of the plurality of second semiconductor portions 1b. Each of the plurality of fifth wiring portions 6e is joined to each of the plurality of third conductive portions 2c.

[0062] The first wiring layer 6 has an area larger than that of the semiconductor element 1. Specifically, the second wiring portion 6b has an area larger than that of the semiconductor element 1. The first layer portion 61 has an area larger than that of the semiconductor element 1.

[0063] As Figure 5 shown, each of the plurality of first wiring portions 6a, the plurality of third wiring portions 6c, the plurality of fourth wiring portions 6d, and the plurality of fifth wiring portions 6e is partially exposed from the second insulating layer 7. In addition, in Figure 5 , the outer shapes of the portions where the first insulating layer 5 and the first wiring layer 6 are superimposed with other components are indicated by single-dot dashed lines. Each of the plurality of first wiring portions 6a, the plurality of second wiring portions 6b, the plurality of fourth wiring portions 6d, and the plurality of fifth wiring portions 6e can be connected to external terminals. Each of the plurality of first wiring portions 6a, the plurality of third wiring portions 6c, the plurality of fourth wiring portions 6d, and the plurality of fifth wiring portions 6e includes a first terminal portion 63. The second wiring portion 6b is covered by the second insulating layer 7. The second wiring layer 8 overlaps with the second wiring portion 6b. The second wiring layer 8 has an area larger than that of the semiconductor element 1.

[0064] Next, the current flowing through the semiconductor package 100 according to Embodiment 1 will be described.

[0065] The semiconductor package 100 according to the present embodiment performs switching operations under high current and high voltage. As Figure 1 shown, when the semiconductor element 1 changes from the on state to the off state during the switching operation, a surge voltage ΔV is applied to the semiconductor element 1. The surge voltage ΔV is calculated based on the time change rate di / dt of the current when the semiconductor element 1 changes from the on state to the off state and the inductance L of the wiring included in the semiconductor device 200. Specifically, the surge voltage ΔV is as shown in the following formula.

[0066] ΔV = L·di / dt

[0067] When the inductance L and the time change rate di / dt of the current are large, there is a possibility that a surge voltage ΔV exceeding the breakdown voltage of the semiconductor element 1 is generated. As a result, the semiconductor element 1 may deteriorate. Therefore, it is required to reduce the inductance.

[0068] Next, the effects of the present embodiment will be described.

[0069] According to the semiconductor package 100 according to Embodiment 1, as Figure 1 shown, the second layer portion 81 of the second wiring layer 8 has a portion that overlaps the first layer portion 61 of the first wiring layer 6 with the second insulating layer 7 interposed therebetween. Therefore, it is possible to make the direction of the current flowing through the first layer portion 61 of the first wiring layer 6 opposite to the direction of the current flowing through the portion of the second layer portion 81 that overlaps the first layer portion 61 of the first wiring layer 6 with the second insulating layer 7 interposed therebetween. As a result, the sign of the time change of the current flowing through the first layer portion 61 of the first wiring layer 6 is reversed from the sign of the time change of the current flowing through the portion of the second layer portion 81 that overlaps the first layer portion 61 of the first wiring layer 6 with the second insulating layer 7 interposed therebetween. Therefore, the magnetic flux generated due to the time change rate di / dt of the current is canceled out. As a result, the wiring inductance caused by the commutation loop flowing through the first layer portion 61 and the second layer portion 81 can be reduced. In addition, in the present embodiment, the commutation loop is the current generated during the switching operation of the semiconductor element 1. Therefore, the inductance of the semiconductor package 100 can be reduced.

[0070] Since the inductance of the semiconductor package 100 can be reduced, it is possible to suppress the generation of a surge voltage exceeding the breakdown voltage of the semiconductor element 1. Therefore, deterioration of the semiconductor element 1 can be suppressed.

[0071] As Figure 1As shown, the first layer portion 61 of the first wiring layer 6 covers the first insulating layer 5. Therefore, it is possible to suppress the first wiring layer 6 from protruding in the in-plane direction of the first insulating layer 5. Therefore, the semiconductor package 100 can be miniaturized.

[0072] Compared with Figure 6 and Figure 7 the semiconductor package 101 according to the first comparative example shown, the effects obtained by the semiconductor package 100 according to the present embodiment will be described in detail. Figure 6 is a cross-sectional view taken along the VI-VI line of Figure 7 . As Figure 6 and Figure 7 shown, in the semiconductor package 101 according to the first comparative example, the semiconductor element 1 is connected to the insulating substrate 47 via solder or the like. In addition, the lead frame LF is used as a connection terminal for wiring to the outside. The lead frame LF and the semiconductor element 1 are connected by a bonding wire 69 or the like. The bonding wire 69 is formed of, for example, copper (Cu) or aluminum (Al). Generally, the lead frame LF is manufactured by perforating a metal plate such as copper (Cu) or iron (Fe). Therefore, the inner leads IL that are the bonding portions with the bonding wire 69 in the lead frame LF are arranged on the same plane. In addition, the inner leads IL protrude from the outer periphery of the insulating substrate 47. Therefore, due to the lead frame LF, the size of the semiconductor package 100 in the in-plane direction along the insulating substrate 47 becomes large.

[0073] In contrast, according to the present embodiment, since the first layer portion 61 of the first wiring layer 6 covers the first insulating layer 5, the semiconductor package 100 can be miniaturized in the in-plane direction along the first insulating layer 5.

[0074] As Figure 4 and Figure 5 shown, the first wiring layer 6 and the second wiring layer 8 have an area larger than that of the semiconductor element 1. Therefore, the allowable current (capacity) of the first wiring layer 6 and the second wiring layer 8 is large. The allowable current of the first wiring layer 6 and the second wiring layer 8 is, for example, larger than the case where the first wiring layer 6 and the second wiring layer 8 are thin lines. Therefore, a large current can be applied to the semiconductor element 1 via the first wiring layer 6 and the second wiring layer 8.

[0075] As Figure 1As shown, the organic layer OL is stacked on the second wiring layer 8. Therefore, it is possible to suppress discharge due to foreign matter adhering to the second wiring layer 8. In addition, when external wiring is joined to the first wiring layer 6 by solder, it is possible to suppress the flow of solder on the second wiring layer 8. That is, the organic layer OL can be used as a solder resist. Further, for example, the first wiring layer 6, the second wiring layer 8, the semiconductor element 1, etc. are disposed in the internal space of a housing (not shown), and compared with the case where the internal space is sealed with silicone or the like, the semiconductor package 100 can be insulated in a state where the semiconductor package 100 is miniaturized.

[0076] As Figure 1 shown, the first wiring portion 6a and the second wiring portion 6b are connected by the semiconductor element 1, the conductive plate 2, and the heat dissipation device 4. Therefore, even when the semiconductor element 1 is a vertical semiconductor element, current can be supplied to the semiconductor element 1 through the first wiring portion 6a and the second wiring portion 6b.

[0077] As Figure 1 shown, the sealing portion 9 seals the semiconductor element 1 and the conductive plate 2 between the first surface 41 and the first insulating layer 5. Therefore, the sides of the semiconductor element 1 and the conductive plate 2 can be insulated.

[0078] As Figure 1 shown, the first insulating layer 5 and the second insulating layer 7 are polymer-based films. Therefore, compared with the case of using an insulating layer based on a glass epoxy substrate, the insulation property of the semiconductor package 100 can be improved. In addition, compared with the case of using an insulating layer based on a glass epoxy substrate, the semiconductor package 100 can be made thinner. Therefore, the thickness of the semiconductor package 100 can be reduced. Further, although not shown, for example, even when the semiconductor package 100 includes a third insulating film and a third wiring layer, the thickness of the semiconductor package 100 can be reduced. Therefore, the semiconductor package 100 can be miniaturized. In addition, the semiconductor package 100 can be made lighter.

[0079] Embodiment 2.

[0080] Next, Figure 8 is used to describe the structure of the semiconductor package 100 according to Embodiment 2. Unless otherwise specified, Embodiment 2 has the same structure and effects as those of the above-described Embodiment 1. Therefore, the same reference numerals are attached to the same structures as those of the above-described Embodiment 1, and the description is not repeated.

[0081] As Figure 8As shown, in the semiconductor package 100 according to this embodiment, an organic layer side through hole OOP is provided in the organic layer OL. The organic layer side through hole OOP penetrates the organic layer OL. The second terminal portion 83 of the second wiring layer 8 is disposed inside the organic layer side through hole OOP. The second terminal portion 83 is exposed from the organic layer side through hole OOP.

[0082] The semiconductor package 100 according to this embodiment is different from the semiconductor package 100 according to Embodiment 1 in that the positions where the first wiring layer 6 and the second wiring layer 8 are exposed are not on the outer periphery of the second insulating layer 7.

[0083] Next, the effects of this embodiment will be described.

[0084] According to the semiconductor package 100 according to Embodiment 2, as Figure 8 shown, the second terminal portion 83 is exposed from the organic layer side through hole OOP. Therefore, external connection terminals can be disposed on the surface side of the organic layer OL. Thereby, the degree of freedom in the design of the wiring of the semiconductor package 100 is increased.

[0085] Embodiment 3.

[0086] Next, using Figure 9 , the structure of the semiconductor package 100 according to Embodiment 3 will be described. Unless otherwise specified, Embodiment 3 has the same structure and effects as those of the above Embodiment 1. Therefore, the same reference numerals are assigned to the same structures as those of the above Embodiment 1, and the description will not be repeated.

[0087] As Figure 9 shown, in the semiconductor package 100 according to Embodiment 3, a first opening OP1 is provided in the first insulating layer 5. The first opening OP1 penetrates the first insulating layer 5. The first opening OP1 is provided away from the semiconductor element 1 and the conductive plate 2. The sealing portion 9 is filled into the first opening OP1. Therefore, the sealing portion 9 fits into the first insulating layer 5. In addition, although not shown, when a resin adhesive layer is disposed between the first insulating layer 5 and the semiconductor element 1 and the conductive plate 2, the first opening OP1 penetrates the resin adhesive layer.

[0088] A second opening OP2 is provided in the second insulating layer 7. The second opening OP2 penetrates the second insulating layer 7. The second opening OP2 communicates with the first opening OP1. The sealing portion 9 is filled into the first opening OP1 and the second opening OP2. Therefore, the sealing portion 9 fits into the first insulating layer 5 and the second insulating layer 7. In addition, although not shown, when a resin adhesive layer is disposed between the second insulating layer 7 and the first insulating layer 5 and the second wiring layer 8, the second opening OP2 penetrates the resin adhesive layer.

[0089] Next, the effects of this embodiment will be described.

[0090] According to the semiconductor package 100 related to Embodiment 3, as Figure 9 shown, the sealing portion 9 is filled into the first opening OP1. Therefore, the first insulating layer 5 and the sealing portion 9 can be firmly joined. Accordingly, peeling between the first insulating layer 5 and the sealing portion 9 can be suppressed.

[0091] As Figure 9 shown, the sealing portion 9 is filled into the first opening OP1 and the second opening OP2. Therefore, the second insulating layer 7 and the sealing portion 9 can be firmly joined. Accordingly, peeling between the second insulating layer 7 and the sealing portion 9 can be suppressed.

[0092] Embodiment 4.

[0093] Next, the structure of the semiconductor package 100 related to Embodiment 4 will be described using Figure 10 . Unless otherwise specified, Embodiment 4 has the same structure and effects as those of the above-described Embodiment 1. Therefore, the same reference numerals are assigned to the same structures as those in the above-described Embodiment 1, and repeated description thereof will not be given.

[0094] As Figure 10 shown, the semiconductor package 100 related to Embodiment 4 further includes a control substrate SB and control components SP. The control substrate SB is electrically connected to the first wiring layer 6. The control components SP include a first control component SP1 and a second control component SP2. In Figure 10 , the control components SP include two first control components SP1 and a second control component SP2. The first control component SP1 is mounted on the control substrate SB. The second control component SP2 is mounted on the organic layer OL. The second control component SP2 is electrically connected to the second wiring layer 8. The second control component SP2 penetrates the organic layer OL and is connected to the second wiring layer 8.

[0095] The control substrate SB includes a wiring portion SB1, a substrate portion SB2, and a connection portion SB3. The first control component SP1 is electrically connected to the wiring portion SB1. The wiring portion SB1 is electrically connected to the first wiring layer 6 through the connection portion SB3.

[0096] Next, the effects of this embodiment will be described.

[0097] In the semiconductor package 100 related to Embodiment 4, as Figure 10 shown, the second control component SP2 of the control components SP is mounted on the organic layer OL. The second control component SP2 is electrically connected to the second wiring layer 8. Therefore, a part of the second wiring layer 8 can be used as a part of the control circuit. Thereby, the area of the control substrate SB can be reduced. Accordingly, the semiconductor device 200 can be miniaturized.

[0098] Compared with Figure 11 the semiconductor package 102 related to the second comparative example shown, the effects obtained by the semiconductor package 100 according to the present embodiment will be described in detail. As Figure 11 shown, in the semiconductor package 102 related to the second comparative example, the control part SP is mounted on the surface of the control substrate SB. Three first control parts SP1 of the control component are mounted on the control substrate SB. Therefore, the control substrate SB has an area capable of mounting three first control parts SP1.

[0099] In contrast, in the semiconductor package 100 according to the present embodiment, since the second control part SP2 is mounted on the organic layer OL, the control substrate SB only needs to have an area capable of mounting two first control parts SP1. Therefore, the area of the control substrate SB can be reduced.

[0100] Embodiment 5.

[0101] Next, Figure 12 will be used to describe the structure of the semiconductor package 100 according to Embodiment 5. Unless otherwise specified, Embodiment 5 has the same structure and effects as those of the above Embodiment 1. Therefore, the same reference numerals are attached to the same structures as those in the above Embodiment 1, and the description will not be repeated.

[0102] As Figure 12 shown, in the semiconductor package 100 according to Embodiment 5, the first wiring layer 6 extends further outward than the outer periphery of the sealing part 9. Specifically, the first terminal part 63 of the first wiring layer 6 extends further outward than the outer periphery of the sealing part 9. In addition, the first insulating layer 5 extends further outward than the outer periphery of the sealing part 9. The semiconductor package 100 further includes a connecting component CC. The connecting component CC is fixed to the first insulating layer 5 and the first terminal part 63. The connecting component CC penetrates through the first insulating layer 5 and the first terminal part 63. The connecting component CC is, for example, a screw and a nut.

[0103] Next, the effects of the present embodiment will be described.

[0104] According to the semiconductor package 100 according to Embodiment 5, as Figure 12As shown, the first wiring layer 6 extends further outward than the outer periphery of the sealing portion 9. Therefore, the connection component CC can be fixed to the first wiring layer 6. Thereby, the first wiring layer 6 can be connected to an external wiring through the connection component CC. Therefore, compared with the case where an external wiring is directly connected to the first wiring layer 6 or the second wiring layer 8 by soldering, the semiconductor package 100 can be more easily connected to the external wiring. In addition, compared with the case where an external wiring is connected to a socket soldered to the first wiring layer 6 or the second wiring layer 8 through a socket connection, the semiconductor package 100 can be more easily connected to the external wiring.

[0105] Embodiment 6.

[0106] Next, use Figure 13 , to describe the structure of the semiconductor package 100 according to Embodiment 6. Unless otherwise specified, Embodiment 6 has the same structure and effects as Embodiment 1 described above. Therefore, the same reference numerals are attached to the same structures as those in Embodiment 1 described above, and the description will not be repeated.

[0107] As Figure 13 shown, in the semiconductor package 100 according to Embodiment 6, the heat dissipation device 4 includes a first metal plate 46, an insulating substrate 47, and a second metal plate 48. The semiconductor element 1 and the conductive plate 2 are electrically connected to the first metal plate 46. The insulating substrate 47 is sandwiched between the second metal plate 48 and the first metal plate 46. The insulating substrate 47 is adhered to the first metal plate 46 and the second metal plate 48.

[0108] The materials of the first metal plate 46 and the second metal plate 48 are metals with high conductivity such as copper (Cu) and aluminum (Al), for example. The insulating substrate 47 is a ceramic plate, for example. The insulating substrate 47 has a higher thermal conductivity than the resin insulating layer RL (refer to Figure 14 ) described later.

[0109] Next, the effects of this embodiment will be described.

[0110] According to the semiconductor package 100 according to Embodiment 6, as Figure 13 shown, an insulating plate is sandwiched between the second metal plate 48 and the first metal plate 46. Therefore, the first metal plate 46 and the second metal plate 48 are insulated by the insulating substrate 47. Therefore, when the heat sink HS (refer to Figure 14 ) described later is joined to the semiconductor package 100, the semiconductor element 1 and the heat sink HS (refer to Figure 14 ) can be insulated by the insulating substrate 47. Thereby, it is not necessary to insulate between the heat dissipation device 4 and the heat sink HS (refer to Figure 14An insulating layer is disposed therebetween. In addition, the second metal plate 48 of the heat dissipation device 4 and the heat sink HS (see Figure 14 ) can be joined by solder or the like having a high thermal conductivity. Therefore, the heat dissipation performance of the semiconductor package 100 is improved.

[0111] Embodiment 7.

[0112] Next, Figure 14 is used to describe the structures of the semiconductor package 100 and the semiconductor device 200 according to Embodiment 7. Unless otherwise specified, Embodiment 7 has the same structures and functions as those of the above-described Embodiment 4. Therefore, the same reference numerals are assigned to the same structures as those of the above-described Embodiment 4, and repeated descriptions are not provided.

[0113] As Figure 14 shown, the semiconductor device 200 according to Embodiment 7 includes the semiconductor package 100, the heat sink HS, and the resin insulating layer RL described in Embodiments 1 to 6. The resin insulating layer RL is sandwiched between the heat sink HS and the heat dissipation device 4. Therefore, the semiconductor package is joined to the heat sink HS through the resin insulating layer RL. In addition, in Figure 14 , the semiconductor device 200 includes the semiconductor package 100 described in Embodiment 4. The semiconductor package 100 is adhered to the heat sink HS through the resin insulating layer RL. The semiconductor package 100 is insulated from the heat sink HS through the resin insulating layer RL.

[0114] The heat sink HS includes a base portion HS1 and a plurality of fin portions HS2. The base portion HS1 is joined to the heat dissipation device 4. The plurality of fin portions HS2 are sandwiched between the base portion HS1 and the heat dissipation device 4.

[0115] Next, Figures 14 - 16 is used to describe the manufacturing method of the semiconductor device 200 according to Embodiment 7.

[0116] As Figure 15 shown, after the first insulating layer 5 is disposed to cover the semiconductor element 1 and the conductive plate 2, the first wiring layer 6, the second insulating layer 7, the second wiring layer 8, and the organic layer OL are stacked. Next, as Figure 16 shown, the semiconductor element 1 and the conductive plate 2 are joined to the heat dissipation device 4 by the bonding material 3. Next, as Figure 14 shown, after the semiconductor element 1, the conductive plate 2, and the heat dissipation device 4 are sealed by the sealing portion 9, the heat dissipation device 4 is adhered to the heat sink HS through the resin insulating layer RL.

[0117] Next, the effects of the present embodiment are described.

[0118] According to the semiconductor device 200 according to Embodiment 7, as Figure 14As shown, a resin insulating layer RL is sandwiched between the heat sink HS and the heat dissipation device 4. Therefore, the heat generated from the semiconductor element 1 of the semiconductor package 100 is transferred to the heat sink HS through the heat dissipation device 4 and the resin insulating layer RL. Thus, the heat generated from the semiconductor element 1 is dissipated from the heat sink HS. Therefore, the heat dissipation performance of the semiconductor device 200 is improved.

[0119] Embodiment 8.

[0120] Next, use Figure 17 , to describe the structure of the semiconductor device 200 according to Embodiment 8. Unless otherwise specified, Embodiment 8 has the same structure and effects as Embodiment 6 described above. Therefore, the same reference numerals are assigned to the same structures as those in Embodiment 6, and no repeated description will be given.

[0121] As Figure 17 shown, the semiconductor device 200 according to Embodiment 8 includes the semiconductor package 100, the heat sink HS, and the conductive metal bonding material ML described in Embodiment 6. A conductive metal bonding material ML is sandwiched between the heat sink HS and the second metal plate 48 of the heat dissipation device 4. Therefore, the semiconductor package 100 is bonded to the heat sink HS through the conductive metal bonding material ML. The conductive metal bonding material ML includes, for example, solder, silver (Ag), copper (Cu), etc. The conductive metal bonding material ML has conductivity. The conductive metal bonding material ML has a higher conductivity than the resin insulating layer RL (refer to Figure 14 ). In addition, the conductive metal bonding material ML has a higher thermal conductivity than the resin insulating layer RL (refer to Figure 14 ).

[0122] Next, the effects of this embodiment will be described.

[0123] According to the semiconductor device 200 according to Embodiment 8, as Figure 17 shown, a conductive metal bonding material ML is sandwiched between the heat sink HS and the second metal plate 48 of the heat dissipation device 4. Therefore, the heat generated from the semiconductor element 1 of the semiconductor package 100 is transferred to the heat sink HS through the heat dissipation device 4 and the conductive metal bonding material ML. Thus, the heat generated from the semiconductor element 1 is dissipated from the heat sink HS. Therefore, the heat dissipation performance of the semiconductor device 200 is improved. In addition, the conductive metal bonding material ML has a higher thermal conductivity than the resin insulating layer RL (refer to Figure 14 ). Therefore, compared with the case where the heat dissipation device 4 and the heat sink HS are bonded through the resin insulating layer RL, the heat dissipation performance of the semiconductor device 200 is improved.

[0124] Embodiment 9.

[0125] Next, use Figure 18, describe the structure of the semiconductor device 200 according to Embodiment 9. Unless otherwise specified, Embodiment 9 has the same structure and effects as Embodiment 4 described above. Therefore, the same reference numerals are assigned to the same structures as those in Embodiment 4, and the description will not be repeated.

[0126] As Figure 18 and Figure 19 shown, the semiconductor device 200 according to Embodiment 9 includes the semiconductor package 100 described in Embodiments 1 to 6 and the heat sink HS. The heat sink HS is joined to the heat dissipation device 4 on the side opposite to the semiconductor element 1 with respect to the heat dissipation device 4. The heat dissipation device 4 and the heat sink HS are sealed by the sealing portion 9. Therefore, the heat dissipation device 4 and the heat sink HS are sealed together. The sealing portion 9 seals the first surface 41 and the side surface 43 of the heat dissipation device 4.

[0127] In the present embodiment, after joining the heat dissipation device 4 and the heat sink HS, the heat dissipation device 4 and the heat sink HS are sealed by the sealing portion 9. Therefore, in a state where the resin insulation layer RL is sandwiched between the heat dissipation device 4 and the heat sink HS, the heat dissipation device 4 and the heat sink HS are sealed by transfer molding using a mold. In addition, as Figure 19 shown, the heat dissipation device 4 and the heat sink HS may be joined in advance by the resin insulation layer RL. Alternatively, the heat dissipation device 4 and the heat sink HS may be integrated by joining using an insulating plate such as ceramic instead of the resin insulation layer RL.

[0128] Next, describe the effects of the present embodiment.

[0129] According to the semiconductor device 200 according to Embodiment 9, as Figure 18 shown, the heat dissipation device 4 and the heat sink HS are sealed by the sealing portion 9. Therefore, the heat dissipation device 4 and the heat sink HS can be sealed simultaneously by the sealing portion 9. Therefore, it is not necessary to join the heat sink HS to the heat dissipation device 4 after sealing the heat dissipation device 4 by the sealing portion 9 as Figures 14 - 16 shown. Therefore, the manufacturing process of the semiconductor device 200 can be simplified.

[0130] Embodiment 10.

[0131] This embodiment is an example in which the semiconductor devices according to Embodiments 7 to 9 described above are applied to a power conversion device. The present disclosure is not limited to a specific power conversion device, but hereinafter, as Embodiment 10, the case where the present disclosure is applied to a three-phase inverter will be described.

[0132] Figure 20 A block diagram showing the structure of a power conversion system of a power conversion device to which this embodiment is applied.

[0133] Figure 20The power conversion system shown is composed of a power supply 110, a power conversion device 300, and a load 400. The power supply 110 is a DC power supply that supplies DC power to the power conversion device 300. The power supply 110 can be composed of various examples. For example, it can be composed of a DC system, a solar cell, a storage battery, or it can also be composed of a rectifier circuit and an AC / DC converter connected to an AC system. In addition, the power supply 110 can also be composed of a DC / DC converter that converts the DC power output from the DC system into predetermined power.

[0134] The power conversion device 300 is a three-phase inverter connected between the power supply 110 and the load 400. It converts the DC power supplied from the power supply 110 into AC power and supplies the AC power to the load 400. As shown in Figure 20 it, the power conversion device 300 includes: a main conversion circuit 201 that converts DC power into AC power and outputs it; and a control circuit 203 that outputs a control signal for controlling the main conversion circuit 201 to the main conversion circuit 201.

[0135] The load 400 is a three-phase motor driven by the AC power supplied from the power conversion device 300. In addition, the load 400 is not limited to a specific use and is a motor mounted on various electrical appliances. For example, it is used as a motor for hybrid vehicles, electric vehicles, railway vehicles, elevators, or air-conditioning machines.

[0136] Hereinafter, the power conversion device 300 will be described in detail. The main conversion circuit 201 includes switching elements and freewheeling diodes (not shown). By switching the switching elements, the DC power supplied from the power supply 110 is converted into AC power and supplied to the load 400. There are various examples of the specific circuit structure of the main conversion circuit 201, but the main conversion circuit 201 in this embodiment is a two-level three-phase full-bridge circuit and can be composed of six switching elements and six freewheeling diodes connected in anti-parallel with each switching element. At least any one of each switching element and each freewheeling diode of the main conversion circuit 201 is a switching element or a freewheeling diode of the semiconductor device 200 equivalent to any of the semiconductor devices in Embodiments 7 to 9 of the above. Regarding the six switching elements, every two switching elements are connected in series to form upper and lower branches, and each upper and lower branch constitutes each phase (U phase, V phase, W phase) of the full-bridge circuit. Moreover, the output terminals of each upper and lower branch, that is, the three output terminals of the main conversion circuit 201, are connected to the load 400.

[0137] In addition, the main conversion circuit 201 includes a drive circuit (not shown) for driving each switching element. However, the drive circuit may be incorporated in the semiconductor device 200, or may be configured to have a drive circuit independently of the semiconductor device 200. The drive circuit generates a drive signal for driving the switching elements of the main conversion circuit 201 and supplies it to the control electrodes of the switching elements of the main conversion circuit 201. Specifically, in accordance with a control signal from the control circuit 203 described later, a drive signal that makes the switching element conductive and a drive signal that makes the switching element non-conductive are output to the control electrodes of the respective switching elements. When the switching element is maintained in the conductive state, the drive signal is a voltage signal (conductive signal) equal to or higher than the threshold voltage of the switching element. When the switching element is maintained in the non-conductive state, the drive signal becomes a voltage signal (cut-off signal) lower than the threshold voltage of the switching element.

[0138] The control circuit 203 controls the switching elements of the main conversion circuit 201 so as to supply desired power to the load 400. Specifically, based on the power to be supplied to the load 400, the conduction time (on-time) during which each switching element of the main conversion circuit 201 should be in the conductive state is calculated. For example, the main conversion circuit 201 can be controlled by PWM control that modulates the on-time of the switching element according to the voltage to be output. Then, a control command (control signal) is output to the drive circuit included in the main conversion circuit 201 in such a manner that a conductive signal is output to the switching element that should be in the conductive state and a cut-off signal is output to the switching element that should be in the non-conductive state at each time point. The drive circuit outputs a conductive signal or a cut-off signal as a drive signal to the control electrodes of the respective switching elements in accordance with this control signal.

[0139] In the power conversion device according to the present embodiment, since the semiconductor device 200 constituting the main conversion circuit 201 is the semiconductor device according to Embodiments 7 to 9, the inductance can be reduced.

[0140] In the present embodiment, an example in which the present disclosure is applied to a two-level three-phase inverter has been described. However, the present disclosure is not limited thereto, and can be applied to various power conversion devices. In the present embodiment, a two-level power conversion device is assumed, but it may also be a three-level or multi-level power conversion device. When supplying power to a single-phase load, the present disclosure can also be applied to a single-phase inverter. In addition, when supplying power to a DC load or the like, the present disclosure can also be applied to a DC / DC converter or an AC / DC converter.

[0141] In addition, the power conversion device to which the present disclosure is applied is not limited to the case where the load is a motor. For example, it can be used as a power supply device for an electric discharge machine, a laser processing machine, an induction heating cooker, or a non-contact power supply system, and can further be used as a power conditioner for a solar power generation system, a power storage system, or the like.

[0142] The embodiments disclosed herein should be considered illustrative in all respects and not restrictive. The scope of the present disclosure is shown not by the above description but by the claims, and is intended to include all modifications within the meaning and scope equivalent to the claims.

Claims

1. A semiconductor package comprising: Semiconductor components; a first insulating layer covering the semiconductor element and provided with a first through hole and a second through hole; a first wiring layer including a first layer portion covering the first insulating layer and electrically connected to the semiconductor element through the first through hole; a second insulating layer covering the first insulating layer and the first wiring layer and having a third through hole communicating with the second through hole; and a second wiring layer including a second layer portion covering the second insulating layer and electrically connected to the semiconductor element through the second through hole and the third through hole; The second layer portion of the second wiring layer has a portion superimposed on the first layer portion of the first wiring layer in a state of sandwiching the second insulating layer. The first wiring layer includes a first terminal portion, The second wiring layer includes a second terminal portion, The first terminal portion and the second terminal portion have portions exposed on a side of the first insulating layer opposite to the semiconductor element. The direction of the current flowing in the portion of the second layer portion that is superimposed on the first layer portion of the first wiring layer with the second insulating layer interposed therebetween is opposite to the direction of the current flowing in the first layer portion of the first wiring layer. The semiconductor package further comprises an organic layer superimposed on the second wiring layer, wherein the material of the organic layer is a resist. The semiconductor package further comprises: Conductive plate; A heat dissipation device, comprising a first surface; a sealing portion; and Connecting parts, The semiconductor element and the conductive plate are bonded to the first surface. The first wiring layer includes a first wiring portion and a second wiring portion, The first through hole includes a first through portion overlapping the semiconductor element and a second through portion overlapping the conductive plate. The first wiring portion is electrically connected to the semiconductor element through the first through portion. The second wiring portion is electrically connected to the conductive plate through the second through portion. The first wiring portion and the second wiring portion are connected via the semiconductor element, the conductive plate, and the heat sink. The sealing portion seals the semiconductor element and the conductive plate between the first surface and the first insulating layer. The first terminal portion of the first wiring layer extends outwardly beyond the outer periphery of the sealing portion, and the first insulating layer extends outwardly beyond the outer periphery of the sealing portion, and the connecting component is fixed to the first insulating layer extending outwardly and the first terminal portion extending outwardly.

2. The semiconductor package according to claim 1, in, The first wiring layer and the second wiring layer have an area larger than that of the semiconductor element.

3. The semiconductor package according to claim 1, in, The first wiring layer and the second wiring layer are partially exposed from the organic layer.

4. A semiconductor package comprising: Semiconductor components; a first insulating layer covering the semiconductor element and provided with a first through hole and a second through hole; a first wiring layer including a first layer portion covering the first insulating layer and electrically connected to the semiconductor element through the first through hole; a second insulating layer covering the first insulating layer and the first wiring layer and having a third through hole communicating with the second through hole; and a second wiring layer including a second layer portion covering the second insulating layer and electrically connected to the semiconductor element through the second through hole and the third through hole; The second layer portion of the second wiring layer has a portion superimposed on the first layer portion of the first wiring layer in a state of sandwiching the second insulating layer. The semiconductor package further comprises an organic layer superimposed on the second wiring layer, wherein the material of the organic layer is a resist. The first wiring layer and the second wiring layer are partially exposed from the organic layer. The semiconductor package further comprises: A control substrate electrically connected to the first wiring layer ； as well as Control parts, The control parts include a first control component and a second control component. The first control component is mounted on the control substrate. The second control component is mounted on the organic layer and is electrically connected to the second wiring layer. The direction of the current flowing in the portion of the second layer portion that is superimposed on the first layer portion of the first wiring layer with the second insulating layer interposed therebetween is opposite to the direction of the current flowing in the first layer portion of the first wiring layer. The semiconductor package further comprises: Conductive plate; A heat dissipation device, comprising a first surface; Sealing part; as well as Connecting parts, The semiconductor element and the conductive plate are bonded to the first surface. The first wiring layer includes a first wiring portion and a second wiring portion, The first through hole includes a first through portion overlapping the semiconductor element and a second through portion overlapping the conductive plate. The first wiring portion is electrically connected to the semiconductor element through the first through portion. The second wiring portion is electrically connected to the conductive plate through the second through portion. The first wiring portion and the second wiring portion are connected via the semiconductor element, the conductive plate, and the heat sink. The sealing portion seals the semiconductor element and the conductive plate between the first surface and the first insulating layer. The first terminal portion of the first wiring layer extends outwardly beyond the outer periphery of the sealing portion, and the first insulating layer extends outwardly beyond the outer periphery of the sealing portion, and the connecting component is fixed to the first insulating layer extending outwardly and the first terminal portion extending outwardly.

5. The semiconductor package according to any one of claims 1 to 4, in, The heat sink includes a first metal plate electrically connected to the semiconductor element and the conductive plate, an insulating substrate, and a second metal plate. The insulating substrate is sandwiched between the second metal plate and the first metal plate.

6. The semiconductor package according to any one of claims 1 to 4, in, The first insulating layer is provided with a first opening penetrating the first insulating layer, The first opening is arranged away from the semiconductor element and the conductive plate. The sealing portion is filled up to the first opening.

7. The semiconductor package according to claim 6, in, The second insulating layer is provided with a second opening which penetrates the second insulating layer and communicates with the first opening. The sealing portion is filled in the first opening and the second opening.

8. A semiconductor device comprising: The semiconductor package according to any one of claims 1 to 7; Radiator; and Resin insulation layer, The resin insulating layer is sandwiched between the heat sink and the heat dissipation device.

9. A semiconductor device comprising: The semiconductor package according to any one of claims 1 to 7; and heat sink, The heat sink is joined to the heat sink at a side opposite to the semiconductor element relative to the heat sink, The heat dissipation device and the heat sink are sealed by the sealing portion.

10. A semiconductor device comprising: The semiconductor package according to claim 5; Radiator; and Conductive metal bonding materials, The conductive metal bonding material is sandwiched between the heat sink and the second metal plate of the heat dissipation device.

11. A power conversion device comprising: A main conversion circuit, comprising the semiconductor device according to any one of claims 8 to 10, the main conversion circuit converting input power and outputting the converted power; and The control circuit outputs a control signal for controlling the main conversion circuit to the main conversion circuit.

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